JP6865034B2 - Semiconductor device and amplitude detection method - Google Patents

Description

The present invention relates to a semiconductor device, particularly a semiconductor device that detects the amplitude of a high frequency signal, and an amplitude detection method.

At the front end of the receiver used in the wireless communication system, automatic gain control is performed to keep the signal strength of the high frequency signal received via the antenna constant. Such automatic gain control is performed, for example, based on the result of comparison between the envelope signal of the high frequency signal and the reference voltage.

As a circuit for obtaining the comparison result between the envelope signal of the high frequency signal and the reference voltage, the envelope detection circuit for obtaining the envelope signal by detecting the high frequency signal with the first transistor and the second transistor for generating the base point voltage. A high-frequency power detection circuit including a comparer for comparing the envelope signal and the base point voltage has been proposed (see, for example, Patent Document 1). In this high-frequency power detection circuit, the difference between the envelope signal and the base point voltage, which is the output result of the comparator, that is, the signal representing the amplitude of the high-frequency signal is output as the signal representing the power level of the high-frequency signal.

Japanese Unexamined Patent Publication No. 2009-105726

By the way, when the voltage value of the base voltage output from the second transistor described above fluctuates due to manufacturing variation, temperature fluctuation, power supply voltage fluctuation, etc., the voltage value exceeds the input allowable range of the comparator. There is. At this time, the comparator may malfunction, and as a result, the accuracy of the signal representing the difference between the envelope signal and the base point voltage, that is, the amplitude detection signal representing the amplitude value of the high frequency signal is lowered.

Further, for example, when a DC offset is generated in the comparator itself composed of an operational amplifier or the like, the DC offset is removed from the comparator, or the error amount generated in the amplitude detection signal due to the DC offset is calculated. Adjustment processing such as creating a correction table for correction in advance is required.

Therefore, in the present invention, it is possible to reduce the time and effort of the adjustment process before shipping the product and to detect the amplitude value of the high frequency signal without causing a decrease in accuracy due to manufacturing variation, temperature fluctuation, power supply voltage fluctuation, or the like. It is an object of the present invention to provide a suitable semiconductor device and an amplitude detection method.

The semiconductor device according to the present invention is a semiconductor device that detects the amplitude of a high-frequency signal, and obtains a base-point voltage generator that generates a base-point voltage and sends it to a second line, and an envelope detection of the high-frequency signal. Based on the voltage difference between the detection unit, which generates a signal whose level is shifted by the base point voltage by the base point voltage and sends it to the first line, and the base point voltage and a predetermined reference voltage, the second The voltage adjustment unit adjusts the voltage value of the line voltage to be the voltage value of the reference voltage and shifts the level of the envelope signal by the amount corresponding to the voltage difference, and the voltage adjustment unit raises the level. The voltage obtained by adding the reference voltage to the difference between the shifted envelope signal and the voltage of the second line whose voltage value is adjusted by the voltage adjusting unit is used as an amplitude detection signal representing the amplitude of the high frequency signal. It has a difference detection unit to generate.

The amplitude detection method according to the present invention is an amplitude detection method for detecting the amplitude of a high-frequency signal, in which a base point voltage is generated and the signal obtained by envelope detection of the high-frequency signal is level-shifted by the amount of the base point voltage. a first step of generating a signal as follicle絡線signal, based on the voltage difference between the base voltage and a predetermined reference voltage, the voltage value of the base point voltage is adjusted to be a voltage value of the reference voltage At the same time, the voltage value is adjusted in the second step of shifting the level of the envelope signal by the amount corresponding to the voltage difference, the envelope signal level-shifted in the second step, and the second step. It has a third step of generating a voltage obtained by adding the reference voltage to the difference from the base point voltage as an amplitude detection signal representing the amplitude of the high frequency signal.

In the present invention, the following voltage is obtained with respect to the base voltage generated inside the apparatus and the envelope signal obtained by performing envelope detection on a signal obtained by level-shifting the input high frequency signal by the base voltage. Make adjustments. That is, the voltage adjusting unit adjusts the voltage value of the base point voltage to be the voltage value of the reference voltage based on the voltage difference between the base point voltage and the predetermined reference voltage, and adjusts the above-mentioned envelope signal to this voltage difference. Level shift by the amount corresponding to. Then, the difference detection unit generates a voltage obtained by adding the reference voltage to the difference between the envelope signal and the base point voltage whose voltage values have been adjusted as described above, as an amplitude detection signal representing the amplitude value of the high frequency signal. ..

According to this configuration, even if the base point voltage generated inside the device fluctuates significantly due to manufacturing variations, temperature fluctuations, power supply voltage fluctuations, etc., the voltage value of the base point voltage is the voltage of a predetermined reference voltage. Adjusted to be equal to the value. As a result, the voltage value of the base voltage can be kept within the input allowable range of the difference detection unit, so that the malfunction of the difference detection unit due to the input allowable range being exceeded is avoided, and the amplitude detection signal caused by the malfunction is avoided. It is possible to prevent a decrease in the accuracy of.

Further, in the difference detection unit, when generating the amplitude detection signal, the reference voltage is applied to the difference between the envelope signal and the base point voltage, so that the value of the amplitude detection signal in the state where the high frequency signal is not supplied is used as a reference. It is made to be equal to the voltage value of the voltage. As a result, the DC offset in the difference detection unit is removed. Therefore, after the product is manufactured, the DC offset for the difference detection unit can be removed, or a correction table showing the correction value for the DC offset for the amplitude detection signal can be created. It is possible to omit the adjustment process.

Therefore, according to the present invention, the time and effort of the adjustment process before shipping the product is reduced, and the envelope signal and the reference voltage of the high-frequency signal are not caused to cause a decrease in accuracy due to manufacturing variation, temperature fluctuation, power supply voltage fluctuation, or the like. It is possible to detect the difference between.

It is a block diagram which shows the structure of the receiving apparatus 100. It is a circuit diagram which shows an example of the internal structure of the amplitude detection part 11. It is a circuit diagram which shows another example of the internal structure of the amplitude detection part 11.

FIG. 1 is a block diagram showing a configuration of a receiving device 100 that receives a radio transmission wave and acquires information data. In FIG. 1, the antenna 10 supplies the high-frequency signal RF obtained by receiving the radio transmission wave to the constant voltage type amplitude detection unit 11 and the variable gain amplifier 12.

The amplitude detection unit 11 receives the high frequency signal RF, generates an amplitude detection signal VDT corresponding to the amplitude value of the high frequency signal RF, and supplies the amplitude detection signal VDT to the variable gain amplifier 12. The variable gain amplifier 12 supplies a signal obtained by amplifying the amplitude of the high frequency signal RF with a gain corresponding to the voltage value indicated by the amplitude detection signal VDT to the frequency conversion unit 13 as a reception signal RA. The frequency conversion unit 13 supplies the demodulation unit 14 with a signal obtained by converting the frequency band of the reception signal RA into the frequency band of a desired reception channel as an intermediate frequency signal IF. The demodulation unit 14 acquires information data by performing a predetermined demodulation process on the intermediate frequency signal IF and outputs the information data signal DAT.

The amplitude detection unit 11, the variable gain amplifier 12, the frequency conversion unit 13, and the demodulation unit 14 described above are formed on a single semiconductor IC chip. The amplitude detection unit 11, the variable gain amplifier 12, the frequency conversion unit 13, and the demodulation unit 14 may be dispersedly formed on a plurality of semiconductor IC chips, or only the amplitude detection unit 11 is a single semiconductor IC. It may be formed on a chip.

FIG. 2 is a circuit diagram showing an example of the internal configuration of the amplitude detection unit 11. As shown in FIG. 2, the amplitude detection unit 11 includes a detection circuit 110, a base point voltage generation circuit 111, a voltage adjustment circuit 112, and a difference detection circuit 113.

The detection circuit 110 includes a capacitor C1, an n-channel MOS (Metal Oxide Semiconductor) type transistor M3, and resistors R1 and R3.

A power supply voltage VDD is applied to one end of the resistor R1, and the other end is connected to one end of the resistor R3 and the source of the transistor M3. The other end of the resistor R3 is connected to the gate of the transistor M3 and one end of the capacitor C1. The capacitor C1 as a coupling capacitor receives the high frequency signal RF at the other end, and supplies the high frequency signal RF from which the DC component is removed to the gate of the transistor M3. The drain of the transistor M3 is connected to the line L1.

The base voltage generation circuit 111 includes n-channel MOS type transistors M4, resistors R2 and R4. The resistor R2 has the same resistance value as the resistor R1 and is manufactured of the same insulating material as the resistor R1. The resistor R4 has the same resistance value as the resistor R3 and is manufactured of the same insulating material as the resistor R3. Further, the transistor M4 is manufactured by using the same semiconductor material and metal material as the transistor M3 and having the same channel length and channel width as the transistor M3.

A power supply voltage VDD is applied to one end of the resistor R2, and the other end is connected to one end of the resistor R4 and the source of the transistor M4. The other end of the resistor R4 is connected to the gate of the transistor M4. The drain of the transistor M4 is connected to the line L2.

With the above configuration, the base point voltage generation circuit 111 generates a base point voltage V2 based on the power supply voltage VDD and applies it to the line L2. The detection circuit 110 performs envelope detection on the high frequency signal RF. The circuit configuration of the detection circuit 110 excluding the capacitor C1, that is, the transistors M3, the resistors R1 and R3, is the same as the circuit configuration of the base voltage generation circuit 111, that is, the transistors M4, the resistors R2 and R4. As a result, the detection circuit 110 generates a signal obtained by performing envelope detection of the high frequency signal RF and level-shifting the signal by the base voltage V2 as the envelope signal V1.

The voltage adjustment circuit 112 includes an operational amplifier OP1 and n-channel MOS type transistors M1 and M2. A reference voltage VREF with a fixed voltage value is applied to the non-inverting input terminal of the operational amplifier OP1, and the inverting input terminal is connected to the line L2. Further, the output end of the operational amplifier OP1 is connected to the gate of each of the transistors M1 and M2. A ground potential GND is applied to the source of the transistor M1, and its drain is connected to the line L1. A ground potential GND is applied to the source of the transistor M2, and its drain is connected to the line L2. With the above connection, the operational amplifier OP1 generates an adjustment voltage EG corresponding to the voltage difference between the base voltage V2 applied to the inverting input end via the line L2 and the reference voltage VREF, and the gates of the transistors M1 and M2 respectively. Supply to.

With the above configuration, the voltage adjusting circuit 112 adjusts the voltage value of the base point voltage V2 to be the voltage value of the reference voltage VREF based on the voltage difference (EG) between the base point voltage V2 and the reference voltage VREF, and envelops the voltage. The level of the line signal V1 is level-shifted by the amount corresponding to the voltage difference (EG). As a result, the voltage value of the base point voltage V2 becomes a voltage value equal to the reference voltage VREF, so that the voltage values of the envelope signal V1 and the base point voltage V2 in the state where the high frequency signal RF is not input are both the voltages of the reference voltage VREF. Matches the value.

The difference detection circuit 113 includes an inverting amplifier circuit 113a and an addition circuit 113b.

The inverting amplifier circuit 113a includes an operational amplifier OP2 and resistors Ra and Rb having the same resistance value as each other. One end of the resistor Ra is connected to the line L1, and the other end is connected to the inverting input end of the operational amplifier OP2. The inverting input end and the output end of the operational amplifier OP2 are connected via a resistor Rb. A reference voltage VREF is applied to the non-inverting input end of the operational amplifier OP2. With this configuration, the inverting amplifier circuit 113a amplifies the envelope signal V1 supplied via the line L1 with a gain of 1, and supplies the signal whose phase is inverted to the adder circuit 113b as the inverting envelope signal V1B.

The adder circuit 113b includes an operational amplifier OP3 and resistors Rc, Rd and Re having the same resistance value as each other. An inverting envelope signal V1B is supplied to one end of the resistor Rc, and the other end is connected to the inverting input end of the operational amplifier OP3. A base voltage V2 is applied to one end of the resistor Rd, and the other end is connected to the inverting input end of the operational amplifier OP3. The inverting input end and the output end of the operational amplifier OP3 are connected via a resistor Re. A reference voltage VREF is applied to the non-inverting input end of the operational amplifier OP3. With this configuration, the adder circuit 113b generates a signal having a voltage value obtained by adding the base point voltage V2 and the reference voltage VREF to the inverted envelope signal V1B as the amplitude detection signal VDT.

Therefore, the difference detection circuit 113 including the inverting amplifier circuit 113a and the addition circuit 113b generates a signal having a voltage value obtained by adding the reference voltage VREG to the difference between the envelope signal V1 and the base point voltage V2 as the amplitude detection signal VDT. To do.

As described in detail above, in the amplitude detection unit 11 shown in FIG. 2, the voltage values of the envelope signal V1 and the base point voltage V2 are both equal to the reference voltage VREF in the state where the high frequency signal RF is not input. That is, even if the voltage itself output from the transistor M4 fluctuates due to manufacturing variation, temperature fluctuation, or power supply voltage fluctuation, the reference voltage V2 supplied to the difference detection circuit 113 and the amplitude reference of the envelope signal V1. Both values are constant at the reference voltage VREF.

As a result, the voltage value (VREF) of the base point voltage V2 can be kept within the input allowable range of the operational amplifier OP3 regardless of the manufacturing variation, the temperature fluctuation, or the power supply voltage fluctuation. Therefore, since the malfunction of the difference detection circuit 113 due to the input allowable range exceeding is avoided, it is possible to prevent the accuracy of the amplitude detection signal VDT from being lowered due to the malfunction.

Further, in the difference detection circuit 113 shown in FIG. 2, when the amplitude detection signal VDT is generated, the high frequency signal RF is not supplied by adding the reference voltage VREF to the difference between the envelope signal V1 and the base voltage V2. The value of the amplitude detection signal VDT in is matched with the voltage value of the reference voltage VREF.

As a result, the DC offset in the difference detection circuit 113 is removed. Therefore, after the product is manufactured, the correction table for prompting the removal of the DC offset in the difference detection circuit 113 or the correction of the DC offset in the amplitude detection signal VDT. It is possible to omit the adjustment process such as creation.

As described above, according to the amplitude detection unit 11 shown in FIG. 2, the time and effort of the adjustment process after manufacturing is reduced, and the high frequency signal is not caused to decrease in accuracy due to manufacturing variation, temperature fluctuation, power supply voltage fluctuation, or the like. It becomes possible to detect the amplitude value of RF.

In the difference detection circuit 113 in the embodiment shown in FIG. 2, the output signal of the addition circuit 113b is output as the amplitude detection signal VDT, but the signal obtained by amplifying the output signal of the addition circuit 113b is used in order to increase the detection sensitivity. It may be output as an amplitude detection signal VDT.

FIG. 3 is a circuit diagram showing another example of the internal configuration of the amplitude detection unit 11 made in view of this point. The circuit shown in FIG. 3 has the same configuration as that shown in FIG. 2 except that two inverting amplifier circuits 113c and 113d connected in series are provided after the addition circuit 113b.

In FIG. 3, the inverting amplifier circuit 113c includes an operational amplifier OP4, resistors Rf and Rg. One end of the resistor Rf is connected to the output end of the operational amplifier OP3 of the adder circuit 113b, and the other end of the resistor Rf is connected to the inverting input end of the operational amplifier OP4. The inverting input end and the output end of the operational amplifier OP4 are connected via a resistor Rg. A reference voltage VREF is applied to the non-inverting input end of the operational amplifier OP2. The resistance value of the resistor Rg is higher than the resistance value of the resistor Rf.

With this configuration, the inverting amplifier circuit 113c amplifies the signal output from the operational amplifier OP3 of the adder circuit 113b with a gain (Rg / Rf) larger than the gain 1, and inverting and amplifies the phase inverting amplifier signal whose phase is inverted. It is supplied to the circuit 113d.

The inverting amplifier circuit 113d includes an operational amplifier OP5, resistors Rh and Ri. One end of the resistor Rh is connected to the output end of the operational amplifier OP4, and the other end of the resistor Rh is connected to the inverting input end of the operational amplifier OP5. The inverting input end and the output end of the operational amplifier OP5 are connected via a resistor Ri. A reference voltage VREF is applied to the non-inverting input end of the operational amplifier OP5. The resistance value of the resistor Ri is higher than the resistance value of the resistor Rh.

With this configuration, the inverting amplifier circuit 113d amplifies the phase inverting amplifier signal output from the operational amplifier OP4 of the inverting amplifier circuit 113c with a gain (Ri / Rh) larger than the gain 1, and oscillates the signal whose phase is inverted. It is output as a detection signal VDT.

Therefore, if the amplitude detection unit 11 adopts a configuration including the inverting amplifier circuits 113c and 113d as shown in FIG. 3, the sensitivity of the amplitude detection signal VDT is increased as compared with the case where the configuration shown in FIG. 2 is adopted. Is possible.

In the above embodiment, the amplitude detection unit 11 is used to set the gain of the variable gain amplifier 12 that amplifies the high frequency signal RF of the receiving device 100 that receives the radio transmission wave as shown in FIG. , It may be used in a device other than the receiving device. That is, the signal input to the amplitude detection unit 11 may be a high frequency signal other than the high frequency signal corresponding to the wireless transmission wave.

In short, the amplitude detection unit 11 may include the following detection unit, base point voltage generation unit, voltage adjustment unit, and difference detection unit in detecting the amplitude of the radio frequency signal (RF).

The base point voltage generation unit (111) generates the base point voltage (V2). The detection unit (110) generates a signal obtained by performing envelope detection of a high frequency signal (RF) and level-shifting the signal by the amount of the base point voltage as an envelope signal (V1). The voltage adjusting unit (112) adjusts and encloses the voltage value of the base point voltage to be the voltage value of the reference voltage based on the voltage difference (EG) between the base point voltage (V2) and the predetermined reference voltage (VREF). The level of the line signal is level-shifted by the amount corresponding to the voltage difference. The difference detection unit (113) uses a high-frequency signal (RF) to obtain a voltage obtained by adding a reference voltage to the difference between the envelope signal level-shifted by the voltage adjustment unit and the base voltage whose voltage value is adjusted by the voltage adjustment circuit. It is generated as an amplitude detection signal (VDT) representing the amplitude of.

11 Amplitude detection unit 110 Detection circuit 111 Base point voltage generation circuit 112 Voltage adjustment circuit 113 Difference detection circuit M1 to M4 Transistors OP1 to OP5 Operational amplifier

Claims (7)

A semiconductor device that detects the amplitude of high-frequency signals.
A base voltage generator that generates a base voltage and sends it to the second line,
An envelope detector that generates a signal obtained by subjecting the high-frequency signal to envelope detection and level-shifting the signal by the amount of the base point voltage as an envelope signal and transmits the signal to the first line .
Based on the voltage difference between the base point voltage and the predetermined reference voltage, the voltage value of the voltage of the second line is adjusted to be the voltage value of the reference voltage, and the level of the envelope signal is set to the voltage difference. A voltage adjuster that shifts the level by the corresponding amount,
The amplitude of the high-frequency signal is obtained by adding the reference voltage to the difference between the envelope signal level-shifted by the voltage adjusting unit and the voltage of the second line whose voltage value is adjusted by the voltage adjusting unit. A semiconductor device comprising: a difference detection unit generated as an amplitude detection signal representing the above. The detection unit
Receiving said high frequency signal at its control terminal, a first transistor for supplying a signal corresponding to the high frequency signal received by the control terminal in the first line as the envelope signal,
Includes a first resistor that applies a predetermined voltage to the control end of the first transistor.
The base voltage generator
A second transistor to be applied to the second line and generates the base voltage based on the potential of its control terminal,
Includes a second resistor that applies the predetermined voltage to the control end of the second transistor.
The voltage adjusting unit
A first operational amplifier in which the inverting input end is connected to the second line and the reference voltage is applied to the non-inverting input terminal.
A third transistor that receives the output voltage of the first operational amplifier at its own control end and adjusts the voltage value of the first line according to the output voltage received at this control end.
It is characterized by including a fourth transistor that receives the output voltage of the first operational amplifier at its own control end and adjusts the voltage value of the second line according to the output voltage received at the control end. The semiconductor device according to claim 1. The difference detection unit
An inverting amplifier circuit that inverts the phase of the envelope signal supplied to the first line and generates an inverted envelope signal amplified with a gain of 1.
The inverted envelope signal, a semiconductor according to claim 2, characterized in that it comprises a summing circuit for outputting a signal obtained by adding said reference voltage and voltage of the second line as said amplitude detection signal apparatus. The inverting amplifier circuit
With a third resistor whose end is connected to the first line,
A second operational amplifier in which its own inverting input end is connected to the other end of the third resistor and the reference voltage is applied to its non-inverting input end.
Includes a fourth resistor connected between the output end and the inverting input end of the second operational amplifier.
The adder circuit
A fifth resistor with one end connected to the output end of the second operational amplifier,
A sixth resistor with one end connected to the second line,
A third operational amplifier in which the other ends of the fifth and sixth resistors are connected to their own inverting input ends and the reference voltage is applied to their own non-inverting input ends.
The semiconductor device according to claim 3, further comprising a seventh resistor connected between an output end and an inverting input end of the third operational amplifier. The difference detection unit
A first inverting amplifier circuit that inverts the phase of the envelope signal supplied to the first line and generates an inverted envelope signal amplified with a gain of 1.
The inverted envelope signal, an adding circuit for outputting a sum signal obtained by adding said reference voltage and voltage of the second line,
A second inverting amplifier circuit that inverts the phase of the added signal and generates an amplified signal amplified with a gain of 1 or more.
The semiconductor device according to claim 2, further comprising a third inverting amplifier circuit that inverts the phase of the amplified signal and generates a signal amplified with a gain of 1 or more as the amplitude detection signal. The first inverting amplifier circuit
With a third resistor whose end is connected to the first line,
A second operational amplifier in which its own inverting input end is connected to the other end of the third resistor and the reference voltage is applied to its non-inverting input end.
Includes a fourth resistor connected between the output end and the inverting input end of the second operational amplifier.
The adder circuit
A fifth resistor with one end connected to the output end of the second operational amplifier,
A sixth resistor with one end connected to the second line,
A third operational amplifier in which the other ends of the fifth and sixth resistors are connected to their own inverting input ends and the reference voltage is applied to their own non-inverting input ends.
Includes a seventh resistor connected between the output end and the inverting input end of the third operational amplifier.
The second inverting amplifier circuit
An eighth resistor with one end connected to the output end of the third operational amplifier,
A fourth operational amplifier in which its own inverting input end is connected to the other end of the eighth resistor and the reference voltage is applied to its own non-inverting input end.
Includes a ninth resistor connected between the output end and the inverting input end of the fourth operational amplifier.
The third inverting amplifier circuit is
A tenth resistor whose one end is connected to the output end of the third operational amplifier,
A fifth operational amplifier in which its own inverting input end is connected to the other end of the tenth resistor and the reference voltage is applied to its own non-inverting input end.
The semiconductor device according to claim 5, further comprising an eleventh resistor connected between an output end and an inverting input end of the fifth operational amplifier. This is an amplitude detection method that detects the amplitude of high-frequency signals.
A first step of generating the partial level shifted signal of the base point voltage signal of the high frequency signal obtained by envelope detection to generate a base point voltage as follicle絡線signal,
Based on the voltage difference between the base point voltage and the predetermined reference voltage, the voltage value of the base point voltage is adjusted to be the voltage value of the reference voltage, and the level of the envelope signal is adjusted by the amount corresponding to the voltage difference. The second step to level shift and
The voltage obtained by adding the reference voltage to the difference between the envelope signal whose level has been shifted in the second step and the base point voltage whose voltage value has been adjusted in the second step represents the amplitude of the high frequency signal. An amplitude detection method comprising a third step of generating as an amplitude detection signal.

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