JP6845055B2 - Amplifier - Google Patents

Description

The present invention relates to an amplification device.

There is a Doherty type amplifier as an amplifier that efficiently amplifies signals in the microwave band used in mobile phone base stations and the like.

As shown in FIG. 10, the Doherty type amplifier has an input terminal 200, an average amplifier 201, a λ / 4 wavelength line 202, 203, a peak amplifier 204, and a load resistance 205.

Here, the average amplifier 201 is composed of an amplifier circuit that performs class A operation, class B operation, or class AB operation, and amplifies and outputs a high frequency signal input from the input terminal 200. The average amplifier 201 is an amplifier that operates steadily (always operates). The λ / 4 wavelength line 202 is a line having a length of λ / 4 of the signal wavelength output from the average amplifier 201 and having a characteristic impedance of R. The λ / 4 wavelength line 203 has a length of λ / 4 of the signal wavelength input from the input terminal 200, and has a characteristic impedance of R. The peak amplifier 204 is composed of an amplifier circuit that operates in class C, and amplifies and outputs a high-frequency signal output from the λ / 4 wavelength line 203. The peak amplifier 204 is an amplifier that operates (unsteady operation) only when the input signal exceeds a predetermined power. The load resistance 205 is a resistance element having a resistance value of R / 2.

When the instantaneous input power input to the input terminal 200 is small, the average amplifier 201 executes an amplification operation regardless of the power level of the input signal and outputs an output signal. On the other hand, when the instantaneous input power is small, the peak amplifier 204 is turned off and does not perform the amplification operation. Therefore, since the power consumption of the peak amplifier 204 is sufficiently small, the power consumption of the amplification device as a whole is also small, and the amplification efficiency is high.

When the instantaneous input power input to the input terminal 200 is large, the peak amplifier 204 is turned on, and the input signal is amplified and output. The output signal from the peak amplifier 204 is combined with the output signal of the average amplifier 201 and supplied to the load resistor 205. By synthesizing the output signals of the two amplifiers in this way, an amplification device having a large saturation power can be configured.

When the instantaneous input power of the input signal is small, the peak amplifier 204 is in the off state, so that the output impedance becomes very large. Since the characteristic impedance of the 1/4 wavelength line 202 provided on the output side of the average amplifier 201 is R as described above, the load resistance 205 is impedance-converted and the load impedance seen from the output end of the average amplifier 201 is It becomes 2R. The average amplifier 201 is designed to have good efficiency when the load impedance is 2R. Therefore, in such an operating state, the average amplifier 201 operates with maximum efficiency.

When the instantaneous input power of the input signal is large, both the average amplifier 201 and the peak amplifier 204 are in the operating state, so the load impedance seen from the average amplifier 201 and the peak amplifier 204 is R, which is twice the impedance of the load resistance 205. Become. Since the characteristic impedance of the 1/4 wavelength line 202 provided on the output side of the average amplifier 201 is R, the load impedance seen from the output end of the average amplifier 201 without performing impedance conversion by the 1/4 wavelength line 202. Is also R. When the load impedance is R, both the average amplifier 201 and the peak amplifier 204 are designed so that the saturation power becomes large, and a large saturation power can be obtained as a whole of the amplification device. In such an operating state, the amplification device operates in a state close to saturated power, so that the efficiency is high.

In this way, in the Doherty type amplifier, when the power of the input signal is large, the peak amplifier 204 operates, and the two output powers of the average amplifier 201 and the peak amplifier 204 are combined to increase the saturation power. By changing the load impedance of the average amplifier 201 depending on whether the power of the input signal is small or large, it is possible to operate with high efficiency.

By the way, when a Doherty amplifier is used in a plurality of bands, it is known that it is difficult to widen the bandwidth due to the frequency dependence of the λ / 4 line required on the output side of the average amplifier.

In order to solve such a problem, in the technique disclosed in Patent Document 1, a Doherty type amplification device that can be used in a plurality of bands is realized by switching with a switch according to the frequency band in which the λ / 4 line is used. There is.

Japanese Unexamined Patent Publication No. 2006-343541

By the way, in recent years, since carrier aggregation that uses a plurality of lines in parallel and a relay device of a mobile phone need to amplify a plurality of bands in parallel, a plurality of bands can be simultaneously amplified. There is a need to amplify.

However, the technique disclosed in Patent Document 1 has a problem that a plurality of frequencies cannot be amplified at the same time because only a single frequency can be selected by the switch.

Therefore, an object of the present invention is to provide an amplification device capable of simultaneously amplifying a plurality of frequencies.

In order to solve the above problems, the present invention inputs signals having frequencies of 1st to N (N ≧ 2), respectively, and amplifies them by class A operation, class AB operation, or class B operation. The Nth average amplifier, the input synthesizer that synthesizes and outputs the signals of the first to Nth frequencies, and the signals of the first to Nth frequencies synthesized by the input synthesizer are input and output. A peak amplifier amplified by class C operation, a first to Nth input phase shift section arranged in front of the first to Nth average amplifiers to shift the input signal, and the first to Nth input phase shift sections. The first to Nth output phase shift sections that are arranged after the Nth average amplifier and shift the input signal, and the first to Nth frequency signals output from the peak amplifier are It is characterized by having an output synthesizing unit for synthesizing a synthesized signal and a signal output from the first to Nth output phase shifting units.
With such a configuration, it becomes possible to amplify a plurality of frequencies at the same time.

Further, in the present invention, the output synthesizing unit is composed of a signal obtained by synthesizing the signals of the first to Nth frequencies output from the peak amplifier and all of the first to Nth output phase shifting units. It is characterized by synthesizing the output signal.
According to such a configuration, a signal obtained by synthesizing all the output signals can be obtained.

Further, in the present invention, the output synthesizing unit is either a signal obtained by synthesizing a signal of the first to Nth frequencies output from the peak amplifier or the first to Nth output phase shifting unit. It is characterized by synthesizing signals output from one.
According to such a configuration, it is possible to obtain a signal obtained by synthesizing the output signal of the peak amplifier and the output signals of the output phase shift units.

Further, the present invention is characterized in that a third (N + 1) input phase shift unit is arranged in front of the peak amplifier.
According to such a configuration, the phase shift of the signal input to the peak amplifier can be adjusted so that the phases of all the signals can be surely matched.

Further, the present invention is characterized in that an isolator into which signals of the first to Nth frequencies are input is arranged in front of the input synthesis unit.
With such a configuration, for example, it is possible to prevent the signals reflected by the compositing unit from being mixed.

Further, the present invention generates and outputs digital signals corresponding to the signals of the 1st to Nth frequencies, and functions as the input synthesizer, and corresponds to the signals of the 1st to Nth frequencies. The digital signal processing unit that synthesizes and outputs digital signals and the digital signals corresponding to the signals of the first to Nth frequencies output from the digital signal processing unit are converted into analog signals, respectively, and the first to first to Nth frequencies are converted into analog signals. The peak amplifier or the (N + 1) input phase shift unit is supplied to the Nth input phase shift unit, and the digital signal obtained by synthesizing the signals of the first to Nth frequencies is converted into the analog signal. It is characterized by having a digital-analog conversion unit for supplying to.
According to such a configuration, the circuit configuration can be simplified, and changes in the characteristics of the amplification device due to temperature or changes with time can be suppressed.

Further, in the present invention, the digital signal processing unit functions as the first to (N + 1) input phase shift units, and shifts the digital signals corresponding to the signals of the first to Nth frequencies, respectively. And output, the digital signal in which the signals of the first to Nth frequencies are synthesized is phase-shifted and output, and the digital-analog conversion unit outputs the first to Nth signals output from the digital signal processing unit. The digital signal corresponding to the signal having the frequency of 1 to N is converted into the analog signal and supplied to the average amplifiers of the 1st to Nth, and the digital signal obtained by synthesizing the signals of the 1st to Nth frequencies is obtained. It is characterized in that it is converted into the analog signal and supplied to the peak amplifier.
According to such a configuration, the circuit configuration can be simplified, and changes in the characteristics of the amplification device due to temperature or changes with time can be suppressed.

Further, in the present invention, the digital signal processing unit has first to Nth attenuators for adjusting the amplitudes of the digital signals corresponding to the signals of the first to Nth frequencies, and the first to second attenuators. It is characterized by having a (N + 1) th attenuator that adjusts the amplitude of the digital signal in which a signal having a frequency of N is synthesized.
According to such a configuration, it is possible to adjust the signal level by adjusting these attenuators.

According to the present invention, it is possible to provide an amplification device capable of simultaneously amplifying a plurality of frequencies.

It is a figure which shows the structural example of the amplification apparatus which concerns on 1st Embodiment of this invention. It is a figure which shows the structural example of the amplification apparatus which concerns on 2nd Embodiment of this invention. It is a figure which shows the structural example of the amplification apparatus which concerns on 3rd Embodiment of this invention. It is a figure which shows the structural example of the digital signal processing part shown in FIG. It is a figure which shows the structural example of the amplification apparatus which concerns on 3rd Embodiment of this invention. It is a figure which shows the structural example of the amplification apparatus which concerns on 4th Embodiment of this invention. It is a figure which shows the structural example of the amplification apparatus which concerns on 5th Embodiment of this invention. It is a figure which shows the structural example of the amplification apparatus which concerns on 6th Embodiment of this invention. It is a figure which shows the structural example of the amplification apparatus which concerns on 7th Embodiment of this invention. It is a figure which shows the structural example of the conventional amplification apparatus.

Next, an embodiment of the present invention will be described.

(A) Explanation of Configuration Example of First Embodiment FIG. 1 is a diagram showing a configuration example of an amplification device according to the first embodiment of the present invention. As shown in this figure, the amplification device according to the first embodiment includes input terminals 11, 12, distribution units 13, 14, input phase shift units 15, 16, input synthesis unit 17, average amplifiers 18, 19, and peak amplifier. 20, it has an output phase shift unit 21 and 22, an output synthesis unit 23, and an output terminal 24.

For example, a signal having a center frequency of 800 MHz and a predetermined bandwidth (for example, several MHz to several tens of MHz) is input to the input terminal 11. Further, for example, a signal having a center frequency of 900 MHz and a predetermined bandwidth (for example, several MHz to several tens of MHz) is input to the input terminal 12. In the following, the case where 800 MHz and 900 MHz signals are input will be described as an example, but the above-mentioned center frequency and bandwidth are an example, and other center frequencies and bandwidths may be used. Needless to say.

The distribution unit 13 distributes a signal having a center frequency of 800 MHz input from the input terminal 11 and supplies the signal to the input phase shift unit 15 and the input synthesis unit 17. The distribution unit 14 distributes a signal having a center frequency of 900 MHz input from the input terminal 12 and supplies the signal to the input phase shift unit 16 and the input synthesis unit 17.

The input phase shift unit 15 shifts the phase of a signal having a center frequency of 800 MHz supplied from the distribution unit 13 by phase φ1 and supplies the signal to the average amplifier 18. The input phase shift unit 16 shifts the phase of a signal having a center frequency of 900 MHz supplied from the distribution unit 14 by phase φ2 and supplies the signal to the average amplifier 19.

The input synthesis unit 17 synthesizes a signal having a center frequency of 800 MHz supplied from the distribution unit 13 and a signal having a center frequency of 900 MHz supplied from the distribution unit 14, and supplies the signal to the peak amplifier 20.

The average amplifier 18 is an amplifier that operates in class A, class AB, or class B, and amplifies and outputs a signal having a center frequency of 800 MHz supplied from the input phase shift unit 15. Similarly, the average amplifier 19 is an amplifier that operates in class A, class AB, or class B, and amplifies and outputs a signal having a center frequency of 900 MHz supplied from the input phase shift unit 16. Class A refers to a setting that gives a bias that exceeds the operating point of an amplification element such as a transistor in the entire cycle of the input signal, and class B means that only the polarity of one side of the AC input signal is amplified. A setting that gives a bias to the amplification element. Class AB gives a bias between class A and class B, and operates class A when the input signal has a small amplitude, and class B in other cases. A setting that operates. Class C is a setting that sets a bias on the side where the amplification element is turned off rather than the cutoff value, and obtains an output voltage only when the voltage of the input signal is sufficiently high, and performs an operation similar to switching. ..

The peak amplifier 20 is an amplifier that operates in class C, and amplifies and outputs a signal obtained by combining a signal having a center frequency of 800 MHz and a signal having a center frequency of 900 MHz supplied from the input synthesizer 17.

The output phase shift unit 21 shifts the phase of the signal having a center frequency of 800 MHz output from the average amplifier 18 by 90 ° and outputs the phase. The output phase shift unit 22 shifts the phase of the signal having a center frequency of 900 MHz output from the average amplifier 19 by 90 ° and outputs the phase.

The output synthesis unit 23 synthesizes and outputs the signal output from the output phase shift unit 21, the signal output from the output phase shift unit 22, and the signal output from the peak amplifier 20. It should be noted that the output synthesis unit 23 may be configured to combine the signal output from the output phase shift unit 21, the signal output from the output phase shift unit 22, and the signal output from the peak amplifier 20 after adjusting the phases. Good.

The output terminal 24 supplies the signal output from the output synthesis unit 23 to, for example, an antenna (not shown) in the subsequent stage, and outputs signals having center frequencies of 800 MHz and 900 MHz as radio waves.

(B) Description of Operation of First Embodiment Next, the operation of the first embodiment shown in FIG. 1 will be described. For example, a signal having a center frequency of 800 MHz (for example, a signal from a base station of a mobile phone) received by an antenna (not shown) is supplied to the distribution unit 13 via an input terminal 11. Similarly, a signal having a center frequency of 900 MHz (for example, a signal from a base station of a mobile phone) received by an antenna (not shown) is supplied to the distribution unit 14 via the input terminal 12.

The distribution unit 13 distributes a signal having a center frequency of 800 MHz input from the input terminal 11 and supplies the signal to the input phase shift unit 15 and the input synthesis unit 17. The distribution unit 14 distributes a signal having a center frequency of 900 MHz input from the input terminal 12 and supplies the signal to the input phase shift unit 16 and the input synthesis unit 17.

The input phase shift unit 15 shifts the phase of the signal supplied from the distribution unit 13 by φ1 and supplies it to the average amplifier 18. The input phase shift unit 16 shifts the phase of the signal supplied from the distribution unit 14 by φ2 and supplies it to the average amplifier 19. By adjusting the input phase shift units 15 and 16, the phases of the signals output from the peak amplifier 20 and the signals output from the output phase shift units 21 and 22 are matched, and these signals are appropriately in phase. Can be synthesized into.

The average amplifier 18 is an amplifier that operates constantly (always operates), amplifies a signal having a center frequency of 800 MHz output from the input phase shift unit 15, and supplies the signal to the output phase shift unit 21. Similarly, the average amplifier 19 is an amplifier that operates steadily (always operates), amplifies a signal having a center frequency of 900 MHz output from the input phase shift unit 16, and supplies the signal to the output phase shift unit 22.

The output phase shift unit 21 shifts the phase of the signal output from the average amplifier 18 by 90 ° and outputs the phase. The output phase shift unit 22 shifts the phase of the signal output from the average amplifier 19 by 90 ° and outputs the phase.

The input synthesis unit 17 synthesizes a signal having a center frequency of 800 MHz supplied from the distribution unit 13 and a signal having a center frequency of 900 MHz supplied from the distribution unit 14, and supplies the signal to the peak amplifier 20.

The peak amplifier 20 is an amplifier that executes an amplification operation (unsteady operation) when the signal level or power of the signal supplied from the input synthesizer 17 is equal to or higher than a predetermined threshold value, and is the power of the input signal. When is low, the operation is stopped, and when the power exceeds a predetermined threshold value, the operation is started.

The output synthesis unit 23 synthesizes the signals output from the output phase shift units 21 and 22 and the peak amplifier 20 and outputs the signals from the output terminal 24.

For example, when the power of a signal having a center frequency of 800 MHz input from the input terminal 11 increases, the output of the average amplifier 18 increases, and when it reaches a predetermined power, it reaches a saturated output. Then, for example, when the electric power approaches the maximum power efficiency (78% in the class B operation), the peak amplifier 20 starts the operation. When the peak amplifier 20 starts operating, the output impedance of the peak amplifier 20 changes (decreases), so that the slope of the load line of the average amplifier 18 changes, and as a result, highly efficient amplification can be performed. Since the phases of the 800 MHz signal output from the output phase shift unit 21 and the 800 MHz signal output from the peak amplifier 20 are matched by the input phase shift unit 15, the output synthesis unit 23 uses these. The signals can be properly combined in phase.

The same operation is also executed for a signal having a center frequency of 900 MHz input from the input terminal 12. As a result, when the power of the signals input from the input terminal 11 and the input terminal 12 is low, the average amplifier 18 and the average amplifier 19 operate to amplify the power and input from the input terminal 11 and the input terminal 12. When at least one of the powers of the signals to be used exceeds a predetermined power, the peak amplifier 20 starts operating and the output impedance of the peak amplifier 20 changes (decreases). The slope of the load line changes, and as a result, highly efficient amplification can be performed. Since the phases of the 900 MHz signal output from the output phase shift unit 22 and the 900 MHz signal output from the peak amplifier 20 are matched by the input phase shift unit 16, the output synthesis unit 23 uses these. The signals can be properly combined in phase.

As described above, in the first embodiment of the present invention, signals of a plurality of frequencies are amplified by the average amplifier, and the combined signal is amplified by the peak amplifier to obtain the output signals of the average amplifier and the peak amplifier. Since it is combined, it is possible to amplify a plurality of frequencies at the same time.

Further, in the first embodiment, since the signal output from the output phase shift units 21 and 22 and the signal output from the peak amplifier 20 are combined by the output synthesis unit 23, they are individually combined. The circuit configuration can be simplified as compared with the case.

(C) Description of Second Embodiment Next, a second embodiment of the present invention will be described. FIG. 2 is a diagram showing a configuration example of a second embodiment of the present invention. In FIG. 2, the same reference numerals are given to the portions corresponding to those in FIG. 1, and the description thereof will be omitted. In FIG. 2, as compared with FIG. 1, an input phase shift unit 31 is added between the input synthesis unit 17 and the peak amplifier 20. Other configurations are the same as in FIG.

The input phase shift unit 31 shifts the phase of the signal output from the input synthesizer 17, for example, a signal having a center frequency of 800 MHz and 900 MHz by φ3, and outputs the phase.

That is, in the second embodiment, the phases of the signals having center frequencies of 800 MHz and 900 MHz are adjusted by the input phase shift units 15 and 16, and the phase of the signal obtained by synthesizing these signals is adjusted by the input phase shift unit 31. By adjusting with the above, it is possible to appropriately synthesize signals in the output synthesizing unit 23 in the same phase.

As described above, according to the second embodiment of the present invention, the input phase shift unit 31 is arranged between the input synthesizer 17 and the peak amplifier 20, so that the input phase shift unit 31 outputs the signal. By adjusting the phase of the signal, the output synthesis unit 23 can easily adjust the phase with the signal output from the output phase shift units 21 and 22, and as a result, the signal in the output synthesis unit 23 can be adjusted. Can be appropriately synthesized in the same phase.

(D) Description of Third Embodiment Next, a third embodiment of the present invention will be described. FIG. 3 is a diagram showing a configuration example of a third embodiment of the present invention. In FIG. 3, the same reference numerals are given to the portions corresponding to those in FIG. 2, and the description thereof will be omitted. In FIG. 3, as compared with FIG. 2, the input terminals 11 and 12, the distribution units 13 and 14, and the input synthesis unit 17 are excluded, and the digital signal processing unit 50 and the DAC (Digital to Analog Converter) 61 to 63 are added. Has been done.

Here, for example, the digital signal processing unit 50 outputs a digital signal having a center frequency of 800 MHz to the DAC 61 and outputs a digital signal having a center frequency of 900 MHz to the DAC 62. Further, a signal obtained by synthesizing a digital signal having a center frequency of 800 MHz and a digital signal having a center frequency of 900 MHz is output to the DAC 63.

The DAC 61 converts a digital signal having a center frequency of 800 MHz, which is output from the digital signal processing unit 50, into an analog signal and supplies the digital signal to the input phase shift unit 15. The DAC 62 converts a digital signal having a center frequency of 900 MHz, which is output from the digital signal processing unit 50, into an analog signal and supplies the digital signal to the input phase shift unit 16. The DAC 63 converts a digital signal output from the digital signal processing unit 50, for example, a composite of digital signals having center frequencies of 800 MHz and 900 MHz into an analog signal, and supplies the digital signal to the input phase shift unit 31.

FIG. 4 is a diagram showing a configuration example of the digital signal processing unit 50 shown in FIG. 3 and a configuration example thereof in the preceding stage. As shown in FIG. 4, the digital signal processing unit 50 includes a decoding unit 51, filters 52 and 53, and an addition unit 54.

A digital signal processing unit 80 is arranged in front of the digital signal processing unit 50. The digital signal processing unit 80 includes filters 81 and 82, and a coding unit 83. The digital signal processing unit 80 and the digital signal processing unit 50 are connected by a serial transmission line 85. Further, ADCs (Analog to Digital Converters) 71 and 72 are arranged in front of the digital signal processing unit 80.

Here, the ADC 71 converts, for example, a signal having a center frequency of 800 MHz received by an antenna (not shown) into a digital signal and outputs the signal. The ADC 72 converts, for example, a signal having a center frequency of 900 MHz received by an antenna (not shown) into a digital signal and outputs the signal.

The filter 81 attenuates and outputs an unnecessary signal (for example, a signal other than a signal having a center frequency of 800 MHz) included in the signal output from the ADC 71. The filter 82 attenuates and outputs an unnecessary signal (for example, a signal other than a signal having a center frequency of 900 MHz) included in the signal output from the ADC 72.

The coding unit 83 multiplexes the digital signals output from the filter 81 and the filter 82, converts them into serial signals, and sends them to the serial transmission line 85.

The serial transmission line 85 is composed of, for example, a coaxial cable or an optical cable, and transmits a serial signal (electrical signal or optical signal) output from the coding unit 83 to the decoding unit 51.

The decoding unit 51 of the digital signal processing unit 50 receives the serial signal transmitted via the serial transmission line 85, multiplexes and outputs the serial signal. More specifically, the decoding unit 51 separates the signals included in the serial signal, for example, the signals having center frequencies of 800 MHz and 900 MHz, and supplies them to the filters 52 and 53, respectively.

The filter 52 attenuates and outputs an unnecessary signal (for example, a signal other than a signal having a center frequency of 800 MHz) included in the signal output from the decoding unit 51. The filter 53 attenuates and outputs an unnecessary signal (for example, a signal other than a signal having a center frequency of 900 MHz) included in the signal output from the decoding unit 51.

The addition unit 54 adds and outputs a digital signal having a center frequency of 800 MHz output from the filter 52 and a digital signal having a center frequency of 900 MHz output from the filter 53.

Return to FIG. The digital signal output from the filter 52 (for example, a signal having a center frequency of 800 MHz) is supplied to the DAC 61, converted into an analog signal, and then supplied to the input phase shift unit 15. The digital signal output from the filter 53 (for example, a signal having a center frequency of 900 MHz) is supplied to the DAC 62, converted into an analog signal, and then supplied to the input phase shift unit 16. A digital signal output from the adder 54 (for example, a signal obtained by adding a signal having a center frequency of 800 MHz and a center frequency of 900 MHz) is supplied to the DAC 63, converted into an analog signal, and then supplied to the input phase shift unit 31. Will be done.

The configurations of the input phase shift units 15, 16 and 31 and thereafter are the same as in the case of FIG.

Next, the operation of the third embodiment shown in FIGS. 3 and 4 will be described. The ADC 71 converts an analog signal having a center frequency of 800 MHz into a digital signal and outputs it, and the ADC 72 converts an analog signal having a center frequency of 900 MHz into a digital signal and outputs the signal. The filters 81 and 82 output signals having center frequencies other than 800 MHz and 900 MHz after being attenuated by digital processing. The coding unit 83 multiplexes the digital signals output from the filters 81 and 82 and supplies the digital signals to the digital signal processing unit 50 via the serial transmission line 85.

In the digital signal processing unit 50, the decoding unit 51 receives the digital signal transmitted on the serial transmission line 85, multiplexes it, and outputs it to the filters 52 and 53. The filters 52 and 53 attenuate signals having center frequencies other than 800 MHz and 900 MHz output from the decoding unit 51 by digital processing and output them to the DACs 61 and 62, respectively. The addition unit 54 adds the digital signals output from the filters 52 and 53 and outputs the digital signals to the DAC 63.

The DACs 61 and 62 convert the digital signals output from the filters 52 and 53 into analog signals and supply them to the input phase shift units 15 and 16, respectively. The DAC 63 converts the digital signal output from the addition unit 54 into an analog signal and supplies it to the input phase shift unit 31.

The operations after the input phase shift units 15, 16 and 31 are the same as in the case of FIG.

As described above, in the third embodiment shown in FIGS. 3 and 4, a signal having a center frequency of 800 MHz and a center frequency of 900 MHz is converted into a digital signal and then multiplexed to form a serial transmission line 85. After being transmitted, the digital signal processing unit 50 multiplexes and separates signals having a center frequency of 800 MHz and a center frequency of 900 MHz, supplies the signals to DACs 61 and 62, converts them into analog signals, and then supplies the signals to the input phase shift units 15 and 16. Will be done. Further, a digital signal having a center frequency of 800 MHz and a center frequency of 900 MHz is added by the adding unit 54, supplied to the DAC 63, converted into an analog signal, and then supplied to the input phase shifting unit 31.

As described above, in the third embodiment, since the signal having the center frequency of 800 MHz and the center frequency of 900 MHz is transmitted as the digital signal on the serial transmission line 85, the transmission distance of the serial transmission line 85 is long. However, the deterioration of the signal can be reduced.

Further, by configuring the distribution units 13 and 14 and the input synthesis unit 17 with a digital circuit, it is possible to prevent the characteristics of the circuit from changing due to temperature change or aging, and it is possible to reduce the circuit scale.

(E) Description of Fourth Embodiment Next, a fourth embodiment of the present invention will be described. FIG. 5 is a diagram showing a configuration example of a fourth embodiment of the present invention. In FIG. 5, the same reference numerals are given to the portions corresponding to those in FIG. 3, and the description thereof will be omitted. In FIG. 5, as compared with FIG. 3, input phase shift units 15, 16 and 31 are excluded, and digital input phase shift units 55 to 57 corresponding to these input phase shift units 15, 16 and 31 are digital signal processing units. It is implemented within 50. The configuration other than these is the same as in FIG. The configuration of the stage before the digital signal processing unit 50 is the same as that in FIG.

The digital input phase shift unit 55 shifts the phase of the digital signal output from the filter 52 shown in FIG. 4 by φ1 and outputs the phase to the DAC 61. The digital input phase shift unit 56 shifts the phase of the digital signal output from the filter 53 shown in FIG. 4 by φ2 and outputs the phase to the DAC 62. The digital input phase shift unit 57 shifts the phase of the digital signal output from the adder 54 shown in FIG. 4 by φ3 and outputs the phase to the DAC 63.

In the fourth embodiment shown in FIG. 5, as compared with the third embodiment shown in FIG. 3, in the third embodiment, the phase shift processing for the analog signal is executed by the input phase shift units 15, 16 and 31. However, the fourth embodiment shown in FIG. 5 is different in that the phase shift processing is executed by the digital signal processing on the digital signal. The operation other than this is the same as that of the third embodiment shown in FIG.

As described above, in the fourth embodiment, the phase shift processing is executed by the digital signal processing. Therefore, as compared with the third embodiment, the apparatus is downsized and, for example, the environmental temperature and aging. It is possible to prevent the characteristics of the circuit from changing due to the change.

(F) Description of Fifth Embodiment Next, a fifth embodiment of the present invention will be described. FIG. 6 is a diagram showing a configuration example of a fifth embodiment of the present invention. In FIG. 6, the same reference numerals are given to the portions corresponding to those in FIG. 5, and the description thereof will be omitted. In FIG. 6, as compared with FIG. 5, BPFs (Band Pass Filters) 64 and 65 are arranged between the output phase shift units 21 and 22 and the output synthesis unit 23. The configuration other than these is the same as in FIG. The configuration of the stage before the digital signal processing unit 50 is the same as that in FIG.

In the fifth embodiment, since the BPF 64 is arranged after the output phase shift unit 21, an unnecessary signal included in the signal output from the output phase shift unit 21 (for example, the center frequency is other than 800 MHz). The signal) can be attenuated. Similarly, since the BPF 65 is arranged after the output phase shift unit 22, unnecessary signals (for example, signals having a center frequency other than 900 MHz) included in the signal output from the output phase shift unit 22 can be removed. It can be attenuated. As a result, since the output signals of the average amplifiers 18 and 19 do not include signals of different frequencies, the output synthesis unit 23 can easily adjust the phase when synthesizing these signals.

In the fifth embodiment, BPF64 and 65 are used, but LPF (Low Pass Filter) is used instead of BPF64, and HPF (High Pass Filter) is used instead of BPF65. You may.

(G) Description of the Sixth Embodiment Next, the sixth embodiment of the present invention will be described. FIG. 7 is a diagram showing a configuration example of a sixth embodiment of the present invention. In FIG. 7, the same reference numerals are given to the portions corresponding to those in FIG. 2, and the description thereof will be omitted. In FIG. 7, as compared with FIG. 2, the isolator 91 is arranged between the distribution unit 13 and the input synthesis unit 17, and the isolator 92 is arranged between the distribution unit 14 and the input synthesis unit 17. The configuration other than these is the same as in FIG.

The isolator 91 supplies the signal output from the distribution unit 13 to the input synthesis unit 17 with low loss, while the signal returning from the input synthesis unit 17 is attenuated to reduce the return to the distribution unit 13. Similarly, the isolator 92 supplies the signal output from the distribution unit 14 to the input synthesis unit 17 with low loss, while the signal returning from the input composition unit 17 is attenuated to reduce the return to the distribution unit 14. To do.

According to the sixth embodiment shown in FIG. 7, the isolators 91 and 92 are arranged between the distribution units 13 and 14 and the input synthesis unit 17, so that, for example, 800 MHz output from the distribution unit 13 is centered. A signal having a frequency is reflected by an input synthesis unit 17, and is input to a distribution unit 14 and mixed with a signal having a center frequency of 900 MHz, or conversely, a signal having a center frequency of 900 MHz output from the distribution unit 14 is generated. It is possible to prevent the signal from being reflected by the input synthesizing unit 17 and being input to the distribution unit 13 and being mixed with a signal having a center frequency of 800 MHz. As a result, the output synthesizing unit 23 can simplify the phase adjustment when synthesizing these signals, and can appropriately perform the synthesizing in the same phase.

(H) Description of the 7th Embodiment Next, the 7th embodiment of the present invention will be described. FIG. 8 is a diagram showing a configuration example of a seventh embodiment of the present invention. In FIG. 8, the parts corresponding to those in FIG. 5 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 8, as compared with FIG. 5, the output synthesizing unit 23 and the output terminal 24 are excluded, and the distribution unit 101, the output synthesizing units 102 and 103, and the output terminals 104 and 105 are newly added. The configuration other than these is the same as in FIG.

The distribution unit 101 distributes the signal output from the peak amplifier 20 and supplies the signal to the output synthesis unit 102 and the output synthesis unit 103, respectively.

The output synthesis unit 102 synthesizes the signal output from the distribution unit 101 and the signal output from the output phase shift unit 21, and outputs the signal from the output terminal 104. The output synthesis unit 103 synthesizes the signal output from the distribution unit 101 and the signal output from the output phase shift unit 22, and outputs the signal from the output terminal 105.

In the seventh embodiment of the present invention, when the power of both the signal output from the DAC 61 (for example, the signal having the center frequency of 800 MHz) and the signal output from the DAC 62 (for example, the signal having the center frequency of 900 MHz) are small. The output synthesis unit 102 outputs a signal in which the signal output from the DAC 61 is amplified, and the output synthesis unit 103 outputs a signal in which the signal output from the DAC 62 is amplified. Further, when the power of at least one of the signal output from the DAC 61 or the signal output from the DAC 62 exceeds a predetermined threshold value, the signals amplified by the peak amplifier 20 are synthesized from the output synthesizers 102 and 103. Is output.

As described above, in the seventh embodiment of the present invention, the output synthesizer 102 synthesizes the output signal from the average amplifier 18 and the output of the peak amplifier 20, so that the output of the average amplifier 19 is also included. It is possible to simplify the phase adjustment as compared with the case of synthesizing including. Similarly, since the output synthesizer 103 synthesizes the output signal from the average amplifier 19 and the output of the peak amplifier 20, the phase is adjusted as compared with the case where the output of the average amplifier 18 is also combined. Can be simplified.

(I) Description of Eighth Embodiment Next, the eighth embodiment of the present invention will be described. FIG. 9 is a diagram showing a configuration example of an eighth embodiment of the present invention. In FIG. 9, the parts corresponding to those in FIG. 8 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 9, as compared with FIG. 8, an ATT (Attenuator) 151 is added between the digital input phase shift unit 55 and the DAC 61 of the digital signal processing unit 50, and an ATT 152 is added between the digital input phase shift unit 56 and the DAC 62. Then, ATT153 is added between the digital input phase shift unit 57 and the DAC63. Further, the output from the addition unit 54 is input to the digital input phase shift unit 57, and the output of the ATT 151, 152 is input to the addition unit 54. The configuration other than these is the same as in FIG.

The ATT 151 attenuates (or amplifies) the signal output from the digital input phase shift unit 55 by a predetermined amount and outputs the signal to the DAC 61. The ATT 152 attenuates (or amplifies) the signal output from the digital input phase shift unit 56 by a predetermined amount and outputs the signal to the DAC 62. The ATT 153 attenuates (or amplifies) the signal output from the digital input phase shift unit 57 by a predetermined amount and outputs the signal to the DAC 63.

According to the eighth embodiment shown in FIG. 9, since the digital signal processing unit 50 has ATT 151 to 153, for example, even if the signal levels of the digital input phase shifting units 55 to 57 are different, the levels are uniform. Can be adjusted to. Further, since the level of the signal input to the peak amplifier 20 can be adjusted by ATT 151 to 153, the timing at which the peak amplifier 20 starts operating can be set, for example, for each signal of 800 MHz and 900 MHz or the ratio of the power of the signal. It can be set as appropriate according to the above. Further, since the ATT 151 to 153 are realized by software by the digital signal processing unit 50, the signal level can be adjusted without complicating the circuit configuration. By giving the ATT 151 to 153 a frequency characteristic, the frequency characteristic of the signal output from the digital input phase shift units 55 to 57 may be flattened.

(J) Description of Modified Embodiment The above embodiment is an example, and it goes without saying that the present invention is not limited to the above-mentioned cases. For example, in each of the above embodiments, the case of amplifying two types of signals of 800 MHz and 900 MHz has been described as an example, but frequencies other than these may be used. Further, instead of amplifying two types of signals, three or more types of signals may be amplified. Further, the bandwidths of two or three or more types of signals may be arbitrarily set.

Further, in the above embodiment, the case of amplifying two types of signals of 800 MHz and 900 MHz has been described as an example, but the present invention may be applied when amplifying only one type of frequency.
Specifically, for example, depending on the situation, only one of the average amplifiers 18 and 19 may be operated, or the same type of frequency may be input to the average amplifiers 18 and 19.

Further, in the third to fifth and seventh to eighth embodiments, the digital signal output from the digital signal processing unit 50 is supplied to the average amplifiers 18 and 19 and the peak amplifier 20 as they are. The signal before being input to the ADCs 71 and 72 shown in 4 may be down-converted to a low frequency, and the output signals of the DACs 61 to 63 may be up-converted to the original frequency. According to such a configuration, the frequency at which the digital signal processing unit 50 operates can be lowered, so that the manufacturing cost of the device can be reduced.

Further, the isolator shown in FIG. 7 may be provided in, for example, the first to fifth and seventh to eighth embodiments.

Further, the ATTs 151 to 153 shown in FIG. 9 may be provided in the third to fifth and seventh embodiments. Further, the level and phase of the signals output from the output terminals 24, 104, 105 may be detected, and the ATT 151 to 153 and the digital input phase shift units 55 to 57 may be feedback-controlled based on the detection result.

11,12 Input terminal 13,14 Distributor 15,16,31 Input phase shift unit 17 Input synthesizer 18,19 Average amplifier 20 Peak amplifier 21,22 Output phase shift 23,102,103 Output synthesizer 24,104, 105 Output terminal 50, 80 Digital signal processing unit 51 Decoding unit 52, 53 Filter 54 Adder unit 55-57 Digital input phase shift unit 61-63 DAC
64,65 BPF
71,72 ADC
81,82 Filter 83 Coder 91,92 Isolator 151-153 ATT

Claims (6)

The first to Nth average amplifiers that input signals of frequencies of the first to Nth (N ≧ 2) and amplify them by class A operation, class AB operation, or class B operation, respectively.
An input synthesizer that synthesizes and outputs signals of the first to Nth frequencies, and
A peak amplifier that inputs signals of the first to Nth frequencies synthesized by the input synthesizer and amplifies them by class C operation.
The first to Nth input phase shift portions, which are arranged in front of the first to Nth average amplifiers and shift the input signal, and the first to Nth input phase shift portions.
A first to Nth output phase shift section, which is arranged after the first to Nth average amplifiers and shifts the input signal, and a phase shift section.
An output synthesizer that synthesizes a signal obtained by combining signals of the first to Nth frequencies output from the peak amplifier and a signal output from the first to Nth output phase shift units.
Have a,
The output synthesizing unit is output from any one of the signal obtained by synthesizing the signals of the first to Nth frequencies output from the peak amplifier and the first to Nth output phase shifting units. An amplification device characterized by synthesizing signals. The amplification device according to claim 1, wherein a third (N + 1) input phase shift unit is arranged in front of the peak amplifier. The amplification device according to claim 1 or 2 , wherein an isolator into which signals of the first to Nth frequencies are input is arranged in front of the input synthesis unit. It generates and outputs digital signals corresponding to the signals of the first to Nth frequencies, and also functions as the input synthesizer and synthesizes the digital signals corresponding to the signals of the first to Nth frequencies. And the digital signal processing unit that outputs
The digital signals corresponding to the signals of the first to Nth frequencies output from the digital signal processing unit are converted into analog signals and supplied to the first to Nth input phase shift units, and the above. A digital analog conversion unit that converts the digital signal obtained by synthesizing signals of the first to Nth frequencies into the analog signal and supplies the signal to the peak amplifier or the input phase shift unit of the (N + 1) th (N + 1).
The amplification device according to any one of claims 1 to 3 , wherein the amplification device has. The digital signal processing unit functions as the first to (N + 1) input phase shift units, shifts and outputs the digital signals corresponding to the signals of the first to Nth frequencies, and outputs the digital signals. The digital signal obtained by synthesizing the signals of the first to Nth frequencies is phase-shifted and output.
The digital-analog conversion unit converts the digital signals corresponding to the signals of the first to Nth frequencies output from the digital signal processing unit into the analog signals, respectively, and the first to Nth average amplifiers. The digital signal obtained by synthesizing the signals of the first to Nth frequencies is converted into the analog signal and supplied to the peak amplifier.
The amplification device according to claim 4. The digital signal processing unit has first to Nth attenuators that adjust the amplitudes of the digital signals corresponding to the signals of the first to Nth frequencies, and signals of the first to Nth frequencies. The amplification device according to claim 4 or 5 , wherein the amplifier has a (N + 1) th attenuator that adjusts the amplitude of the synthesized digital signal.

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