JP6838951B2 - Coding device and coding method - Google Patents

Description

The present invention relates to a coding device and a coding method.

An image pickup device, a portable communication device, and the like are known as an image processing device that compresses and encodes moving image data. Such an image processing device acquires a moving image signal by an imaging unit, compresses and encodes the acquired moving image signal, and records the compressed moving image file on a recording medium. Conventionally, the image data before compression coding has been expressed by SDR (Standard Dynamic Range) having a brightness level of 100 nits as the upper limit. However, in recent years, there has been provided image data expressed by HDR (High Dynamic Range) in which the upper limit of the luminance level is extended to about 10,000 bits and having a luminance range close to the luminance range perceptible to humans.

When decoding the HDR image, inverse logarithmic conversion is performed. In this inverse logarithmic transformation, the error generated by lossy compression may be amplified and the image quality of the HDR image may be deteriorated. In Patent Document 1, quantization is performed so that the quantization error is concentrated in the luminance region where the error expansion due to logarithmic inverse conversion is relatively small or in the luminance region where the error does not expand, and the index image obtained by the quantization is obtained. The method of encoding is disclosed.

Japanese Unexamined Patent Publication No. 2013-106333

However, in Patent Document 1, the size of a block, which is a unit of coding when performing quantization, is not considered. Therefore, when the block size is large, the deterioration of the image quality due to the coding may spread over a wide range.

An object of the present invention is to provide a coding apparatus and a coding method capable of reducing deterioration of image quality due to coding.

According to one aspect of the present invention, the luminance information acquisition means for acquiring the luminance information based on the pixel values of the plurality of pixels constituting the image and the block size in the block including the plurality of pixels based on the luminance information. possess a block size limit means for generating a block size control information of the upper limit, and encoding means for encoding the image the block units that are set on the basis of the block size restriction information, the block size restrictions The means generates the block size limit information so as to limit the upper limit of the block size to a value smaller than the maximum block size when the transfer function of the image corresponds to the Perceptual Quantizer or the Hybrid Log Gamma. An encoding device is provided.

According to another aspect of the present invention, the step of acquiring the luminance information based on the pixel values of the plurality of pixels constituting the image and the upper limit of the block size in the block including the plurality of pixels based on the luminance information. generating a block size control information, said block have a step of performing encoding of the image in units of the blocks set on the basis of the size limit information, in the step of generating the block size limitation information, When the transfer function of the image corresponds to Pixel Quantizer or Hybrid Log Gamma, the block size limit information is generated so as to limit the upper limit of the block size to a value smaller than the maximum block size. A featured coding method is provided.

According to the present invention, there is provided a coding device and a coding method capable of reducing deterioration of image quality due to coding.

It is a block diagram which shows the image processing apparatus by 1st Embodiment. It is a block diagram which shows the coding processing part provided in the image processing apparatus by 1st Embodiment. It is a figure which shows the structure of the block by 1st Embodiment. It is a flowchart which shows the operation of the coding processing part by 1st Embodiment. It is a flowchart which shows the operation of the luminance information calculation part by 1st Embodiment. It is a flowchart which shows the operation of the block size limiting part by 1st Embodiment. It is a flowchart which shows the operation of the block size limiting part by 2nd Embodiment. It is a flowchart which shows the operation of the coding processing part by 3rd Embodiment. It is a flowchart which shows the operation of the luminance information calculation performed by the CPU according to 3rd Embodiment.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to the following embodiments.

[First Embodiment]
The coding apparatus and coding method according to the first embodiment will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an image processing device 100 according to the present embodiment. As shown in FIG. 1, the image processing apparatus 100 according to the present embodiment includes a CPU 101, a memory 102, a non-volatile memory 103, an operation unit 104, an image pickup unit 112, an image processing unit 113, and a coding processing unit. It has 114, a display control unit 115, and a display unit 116. Further, the image processing device 100 according to the present embodiment includes a communication control unit 117, a communication unit 118, a recording medium control unit 119, and an internal bus 130. The image processing device 100 forms an optical image of a subject on the pixel array of the imaging unit 112 using the photographing lens 111, but the photographing lens 111 is not removable from the body (housing, main body) of the image processing device 100. It may be removable, or it may be removable. Further, the image processing device 100 writes and reads image data to and from the recording medium 120 via the recording medium control unit 119. The recording medium 120 may be detachable from or detachable from the image processing device 100.

The CPU 101 controls the operation of each part (each functional block) of the image processing device 100 via the internal bus 130 by executing a computer program stored in the non-volatile memory 103.

The memory 102 is a rewritable volatile memory. The memory 102 temporarily records a computer program for controlling the operation of each part of the image processing device 100, information such as parameters related to the operation of each part of the image processing device 100, information received by the communication control unit 117, and the like. .. Further, the memory 102 temporarily records the image acquired by the imaging unit 112, the image processed by the image processing unit 113, the coding processing unit 114, and the like, and the information. The memory 102 has a storage capacity sufficient for temporarily recording these.

The non-volatile memory 103 is a memory that can be electrically erased and recorded, and for example, EEPROM or the like is used. The non-volatile memory 103 stores information such as a computer program that controls the operation of each part of the image processing device 100 and parameters related to the operation of each part of the image processing device 100. The computer program realizes various operations performed by the image processing apparatus 100 according to the present embodiment.

The operation unit 104 provides a user interface for operating the image processing device 100. The operation unit 104 includes various buttons such as a power button, a menu button, and a shooting button, and the various buttons are composed of a switch, a touch panel, and the like. The CPU 101 controls the image processing device 100 according to a user's instruction input via the operation unit 104. Although the case where the CPU 101 controls the image processing device 100 based on the operation input via the operation unit 104 has been described here as an example, the present invention is not limited to this. For example, the CPU 101 may control the image processing device 100 based on a request input from a remote controller (not shown), a mobile terminal (not shown), or the like via the communication unit 118.

The photographing lens (lens unit) 111 is composed of a lens group (not shown) including a zoom lens, a focus lens, etc., a lens control unit (not shown), an aperture (not shown), and the like. The photographing lens 111 can function as a zoom means for changing the angle of view. The lens control unit adjusts the focus and controls the aperture value (F value) by the control signal transmitted from the CPU 101. The imaging unit 112 can function as an acquisition means for sequentially acquiring a plurality of images constituting a moving image. As the image pickup unit 112, for example, an area image sensor using a CCD (charge-coupled device), a CMOS (complementary metal oxide semiconductor) device, or the like is used. The imaging unit 112 has a pixel array (not shown) in which photoelectric conversion units (not shown) that convert an optical image of a subject into an electric signal are arranged in a matrix, that is, two-dimensionally. An optical image of the subject is formed on the pixel array by the photographing lens 111. The image capturing unit 112 outputs the captured image to the image processing unit 113 or the memory 102. The imaging unit 112 can also acquire a still image.

The image processing unit 113 performs predetermined image processing on the image data output from the image pickup unit 112 or the image data read from the memory 102. Examples of the image processing include interpolation processing, reduction processing (resizing processing), color conversion processing, and the like. Further, the image processing unit 113 uses the image data acquired by the image capturing unit 112 to perform predetermined arithmetic processing for exposure control, distance measurement control, and the like. The CPU 101 performs exposure control, distance measurement control, and the like based on the calculation result obtained by the calculation process by the image processing unit 113. Specifically, the CPU 101 performs AE (automatic exposure) processing, AWB (auto white balance) processing, AF (autofocus) processing, and the like.

The coding processing unit 114 compresses the size of the image data by performing intra-frame predictive coding (in-screen predictive coding), inter-frame predictive coding (inter-screen predictive coding), and the like on the image data. .. The coding processing unit 114 is, for example, a coding device composed of a semiconductor element or the like. The coding processing unit 114 may be a coding device provided outside the image processing device 100. The coding processing unit 114, for example, H.A. The coding process is performed by the 265 (ITU H.265 or ISO / IEC23801-2) method. The details of the coding processing unit 114 will be described later with reference to FIG.

The display control unit 115 controls the display unit 116. The display unit 116 includes a display screen (not shown). The display control unit 115 generates an image that can be displayed on the display screen of the display unit 116 by performing resizing processing, color conversion processing, and the like on the image data, and transmits the image, that is, the image signal to the display unit 116. Output. The display unit 116 displays an image on the display screen based on the image signal sent from the display control unit 115. The display unit 116 has an OSD (On Screen Display) function, which is a function of displaying a setting screen such as a menu on the display screen. The display control unit 115 may superimpose the OSD image on the image signal and output the image signal to the display unit 116. The display unit 116 is composed of a liquid crystal display, an organic EL display, or the like, and displays an image signal sent from the display control unit 115. The display unit 116 may be, for example, a touch panel. When the display unit 116 is a touch panel, the display unit 116 can also function as an operation unit 104.

The communication control unit 117 is controlled by the CPU 101. The communication control unit 117 generates a modulated signal conforming to a wireless communication standard predetermined by IEEE802.11 or the like, and outputs the modulated signal to the communication unit 118. Further, the communication control unit 117 receives a modulated signal conforming to the wireless communication standard via the communication unit 118, decodes the received modulated signal, and outputs a signal corresponding to the decoded signal to the CPU 101. The communication control unit 117 includes a register for storing communication settings. The communication control unit 117 can adjust the transmission / reception sensitivity during communication by controlling from the CPU 101. The communication control unit 117 can perform transmission / reception by a predetermined modulation method. The communication unit 118 outputs a modulation signal supplied from the communication control unit 117 to an external device 127 such as an information communication device outside the image processing device 100, and also receives an antenna for receiving the modulation signal from the external device 127. I have. Further, the communication unit 118 is provided with a circuit for communication and the like. Although the case where wireless communication is performed by the communication unit 118 has been described here as an example, the communication performed by the communication unit 118 is not limited to wireless communication. For example, the communication unit 118 and the external device 127 may be connected by an electrical connection using wiring or the like.

The recording medium control unit 119 controls the recording medium 120. The recording medium control unit 119 outputs a control signal for controlling the recording medium 120 to the recording medium 120 based on the request from the CPU 101. As the recording medium 120, for example, a non-volatile memory, a magnetic disk, or the like is used. As described above, the recording medium 120 may be removable or non-detachable. The recording medium 120 records encoded image data and the like. Image data and the like are saved as a file in a format suitable for the file system of the recording medium 120. Examples of the file include an MP4 file (ISO / IEC 14496-14: 2003), an MXF (Material eXchange Format) file, and the like. The functional blocks 101 to 104, 112 to 115, 117, and 119 are accessible to each other via the internal bus 130.

<Code processing unit>
FIG. 2 is a block diagram showing a coding processing unit 114 provided in the image processing apparatus 100 according to the present embodiment. In FIG. 2, the coding processing unit 114 and the memory 102 are extracted and shown. The coding processing unit 114 is, for example, H.A., which is one of the moving image compression standards. Coding is performed by the coding method of 265.

The brightness information acquisition unit 201 acquires image data to be encoded from the memory 102, and calculates brightness information corresponding to each pixel or a pixel group including a plurality of pixels based on the pixel value of the image data. Acquires brightness information. That is, the luminance information acquisition unit 201 functions as the luminance information acquisition means. The calculated luminance information may be temporarily stored in the memory 102, or may be directly transmitted from the luminance information acquisition unit 201 to the block size limiting unit 202. The luminance information may include information regarding the luminance of each pixel. Specifically, the brightness information may include the brightness of each pixel, or may include processed values such as an average value, a total value, a maximum value, and a minimum value of brightness calculated from the brightness of a plurality of pixels. ..

The block size limit unit 202 generates block size limit information regarding the limit of the upper limit of the block size (block size) which is a unit of image coding, and sets the block size limit information by storing it in the memory 102. .. Further, the block size limit unit 202 updates the set block size limit information. That is, the block size limiting unit 202 functions as a block size limiting means. Here, as the block, a macro block, a Coding Tree Unit (CTU), a Coding Unit (CU), a Prediction Unit (PU), a Transfer Unit (TU), or the like can be used. A macroblock is a unit of coding in the H.264 standard. CTU, CU, PU, TU are H. It is a unit of coding in the 265 standard. CTU is H.I. It is a unit of a block that performs coding processing of each image in the 265 standard. CU is a block unit for recursively dividing CTU. PU is a block unit for dividing CU for prediction processing. TU is a block unit for dividing CU for conversion processing.

The block size limiting unit 202 defines a limitation on the range of any or all of the blocks based on the luminance information received from the luminance information acquisition unit 201 or the luminance information acquired from the memory 102. Generate block size limit information. Then, the block size limitation unit 202 outputs the block size limitation information to the prediction coding method determination unit 203. Further, the block size limiting unit 202 provides information that defines a range for acquiring the predicted pixel block of the pixel block of interest (encoding target block) when encoding a certain pixel block of interest as the predictive coding condition information. Output to the predictive coding method determination unit 203.

The predictive coding method determination unit 203 determines the predictive coding method for each pixel block in the coding target region based on the predictive coding condition information input from the block size limiting unit 202. The prediction coding method determination unit 203 performs inter-frame prediction processing including simple in-frame prediction or motion detection from the input image signal and the encoded pixel value read from the memory 102. An evaluation value indicating the coding efficiency is calculated. Then, the predictive coding method determination unit 203 determines the predictive coding method having the best coding efficiency. When the pixel block to be encoded is an I slice, the prediction coding method determination unit 203 determines the block size and prediction mode of the prediction pixel in the frame. When the coded pixel block is a P slice or a B slice, the one with the higher coding efficiency is selected from the intra-frame prediction and the inter-frame prediction. A frame in which all slices in the frame are I slices is called an I frame, a frame in which all slices in the frame are P slices is called a P frame, and all slices in the frame are B slices. A frame is called a B frame. In the case of in-frame prediction, the prediction coding method determination unit 203 determines in-frame prediction coding parameters such as the block size of the prediction pixels in the frame and the in-frame prediction mode based on the block size limit information. Further, the prediction coding method determination unit 203 divides the block size of the prediction pixel in the frame so as to be within the limit based on the block size limit information. The prediction coding method determination unit 203 determines the block size of the prediction pixel in the frame when there is no block size limit information. Further, in the case of inter-frame prediction, the prediction coding method determination unit 203 determines inter-frame prediction coding parameters such as a reference frame, a pixel block division pattern, and a motion vector. Further, the prediction coding method determination unit 203 changes the division pattern of the pixel block so as to be within the limit based on the block size limit information. The predictive coding method determination unit 203 outputs the determined predictive coding parameter to the predictive coding processing unit 204.

The predictive coding processing unit 204 operates as follows when coding the pixel block of interest in the frame to be coded. That is, the predictive coding processing unit 204 generates a predictive pixel block from the coded image read from the memory 102 according to the predictive coding parameter determined by the predictive coding method determination unit 203. Then, the prediction coding processing unit 204 outputs the prediction residual block, which is the difference between the pixel block of interest and the prediction pixel block, to the orthogonal conversion / quantization unit 205. The predictive coding processing unit 204 also outputs the predictive pixel block to the local decoding unit 206.

The orthogonal transformation / quantization unit 205 performs orthogonal conversion processing on the predicted residual block supplied from the predictive coding processing unit 204. Further, the orthogonal conversion / quantization unit 205 quantizes the coefficient obtained by the orthogonal conversion process by using the quantization step corresponding to the quantization parameter set by the code amount control unit 207. The orthogonal conversion / quantization unit 205 outputs the coefficient after quantization, that is, the quantization data to the entropy coding unit 208 and the local decoding unit 206.

The local decoding unit 206 generates predicted residual data by performing an inverse quantization process and an inverse orthogonal conversion process on the quantization data input from the orthogonal conversion / quantization unit 205. Then, the local decoding unit 206 adds the predicted image input from the prediction coding processing unit 204 to the generated prediction residual data to perform the decoding process, and the pixel block obtained by the decoding process is used. The indicated image data is stored in the memory 102. The image data after the decoding process stored in the memory 102 is used for the in-frame prediction process. Further, the decrypted data subjected to the deblocking filter processing is held in the memory 102. The decoded data after the deblocking filter processing held in the memory 102 is also used for the inter-frame prediction processing.

The code amount control unit 207 controls the code amount of the coded data so that the coded picture buffer does not overflow or underflow. The code amount control unit 207 generates a quantization parameter for a subsequent frame based on the generated code amount after entropy coding supplied from the entropy coding unit 208, and the generated quantization parameter is orthogonally converted / quantized. It is supplied to the chemical unit 205. The code amount control unit 207 adjusts the quantization parameter based on the quantization priority information set by the block size limiting unit 202, for example, by changing the weighted quantization coefficient.

The entropy coding unit 208 performs entropy coding processing by CABAC (context adaptive binary arithmetic coding) for each slice of the input quantization data. The entropy encoding unit 208 is a binarization unit that converts the input multi-value quantization data into binary data, and a binarization data memory that stores the binarization data generated by the binarization unit. And have. Further, the entropy encoding unit 208 has a context calculation unit that calculates the occurrence probability of the binarized data according to the context and holds the occurrence probability of the binary data obtained by the calculation. Further, the entropy coding unit 208 has an arithmetic coding unit that performs arithmetic coding according to the occurrence probability of binary data supplied from the context calculation unit. The data encoded in this way is output to the multiplexing processing unit 209, and the generated code amount after entropy coding is output to the code amount control unit 207.

As described above, a part or all of the predictive coding method determination unit 203, the predictive coding processing unit 204, the orthogonal conversion / quantization unit 205, the local decoding unit 206, the code amount control unit 207, and the entropy coding unit 208. Functions as a coding means. The coding of the image by this coding means is performed in units of blocks set based on the block size limit information.

At the start of image coding, the multiplexing processing unit 209 generates stream data by adding encoded image data to various syntax information such as the size of the frame to be encoded, and stores the memory. Save to 102.

The CPU 210 of the coding processing unit 114 controls the operation of each part of the coding processing unit 114 by executing a computer program stored in the non-volatile memory 103. The memory 102 temporarily stores information such as a computer program that controls the operation of each part of the coding processing unit 114 and parameters related to the operation of each part.

<Block configuration>
3 (a), 3 (b) and 3 (c) are diagrams showing an example of the block configuration in the present embodiment. As shown in FIG. 3A, the frame 300, which is one image constituting the moving image, can be divided into a plurality of blocks 301 having a maximum block size. The plurality of blocks 301 are shown as A1, A2, A3, A4, ..., B1, B2, ... In FIG. 3A. The maximum block size in various blocks will be described. When the block 301 is a macro block, the block 301 is composed of 16 × 16 pixels 302. When the block 301 is a CTU, CU, or PU, the block 301 is composed of 64 × 64 pixels 302. When the block 301 is a TU, the block 301 is composed of 32 × 32 pixels 302.

3 (b) and 3 (c) are diagrams showing a configuration example of the block 301. As shown in FIG. 3B, the block 301 is divided into a plurality of pixel groups 303, each of which includes a plurality of pixels 302, and the average value, total value, etc. of the brightness of each pixel 302 included in the pixel group 303. May be the brightness of the pixel group 303. In this case, the pixel group 303 can be treated as if it were the pixel 302. As described above, the pixel 302 or the pixel group 303 is the minimum unit for calculating the luminance information in the luminance information acquisition unit 201.

FIG. 3C is a diagram showing an example of division of the block 301 which is the maximum block size. As described above, the predictive coding method determination unit 203 determines the block size. For example, when the block 301 is a CU, at the maximum block size, the block 301 is composed of 64 × 64 pixels 302, and the block 301 is divided into a plurality of blocks having different sizes such as blocks 304a, 304b, 304c. Can be split. Each block 304a, 304b, 304c includes a plurality of pixels 302 or a plurality of pixel groups 303 for calculating luminance information. In the macro block, CTU, PU, and TU, the block 301 can be divided into a plurality of blocks in the same manner.

<Operation of coding processing unit 114>
FIG. 4 is a flowchart showing the operation of the coding processing unit 114 according to the present embodiment. In this operation, when the power of the image processing device 100 is turned on, the program stored in the non-volatile memory 103 is expanded in the memory 102, and the CPU 210 in the coding processing unit 114 reads the program in the memory 102 and executes it. It is realized by doing. The process according to the flowchart of FIG. 4 is executed frame by frame, and the process may be repeatedly executed periodically.

In step S401, the CPU 210 acquires the transfer function information stored in the memory 102 by the image processing unit 113 from the memory 102. After that, the CPU 210 shifts the process from step S401 to step S402.

In step S402, the CPU 210 determines whether or not the transfer function information acquired from the memory 102 in step S401 indicates a predetermined transfer function corresponding to the predetermined HDR system. As an example of a predetermined transfer function, PQ (Perfectual Quantizer) or HLG (Hybrid Log Gamma) can be mentioned. When the CPU 210 determines that the transfer function information corresponds to the predetermined HDR method (YES in step S402), the CPU 210 shifts the process from step S402 to step S403. When the CPU 210 determines that the transfer function information does not correspond to the predetermined HDR method (NO in step S402), the CPU 210 shifts the process from step S402 to step S408.

In step S403, the CPU 210 confirms that the image data has been written to the memory 102 by the image processing unit 113, and acquires address information indicating the address in which the image data in the memory 102 is stored. After that, the CPU 210 shifts the process from step S403 to step S404.

In step S404, the CPU 210 outputs the address information of the image data stored in the memory 102 to the luminance information acquisition unit 201. The luminance information acquisition unit 201 acquires the luminance information by calculating the luminance information corresponding to the pixels 302 or the pixel group 303 from the pixel values included in the image data. The details of the luminance information calculation process will be described later. After that, the CPU 210 shifts the process from step S404 to step S405.

In step S405, the CPU 210 determines whether to determine the block size limit on a pixel-by-pixel basis or on a pixel-by-pixel basis, based on the setting information predetermined in the image processing apparatus 100. The preset setting information in the image processing device 100 is, for example, information about settings such as a shooting mode and a resolution. For example, when the shooting mode is set to a high frame rate mode, the processing can be speeded up by performing the processing in units of pixel groups. Similarly, even when the resolution is set to be high, the processing can be speeded up by performing the processing in units of pixel groups. When the CPU 210 determines that the block size is limited in pixel units (“pixel unit” in step S405), the process shifts from step S405 to step S406. When the CPU 210 determines that the block size is limited for each pixel group (“pixel group unit” in step S405), the processing shifts from step S405 to step S407.

In step S406, the CPU 210 controls the block size limiting unit 202 to determine the block size limit on a pixel-by-pixel basis and generate block size limit information. The details of the processing in the block size limiting unit 202 will be described later. The CPU 210 shifts the process from step S406 to step S408.

In step S407, the CPU 210 controls the block size limiting unit 202 to determine the block size limit for each pixel group, generate block size limit information, and store it in the memory 102. The details of the processing in the block size limiting unit 202 will be described later. The CPU 210 shifts the process from step S407 to step S408.

In step S408, the CPU 210 sets the priority for the allocation of the quantization parameter of each block at the time of quantization based on the block size limit information stored in the memory 102. The priority of the quantization parameter allocation is set high for the block whose upper limit of the block size is limited by the block size limit information, and the priority is set low for the other blocks. Further, the CPU 210 may weight the priority according to the degree of limitation of the upper limit of the block size. For example, in a TU block, the priority is given so that the assignment of the quantization parameter of the block whose upper limit is limited to 8 × 8 is prioritized over the block whose upper limit is limited to 16 × 16. Weighting can be set. After that, the CPU 210 shifts the process from step S408 to step S409.

In step S409, the CPU 210 controls the predictive coding method determination unit 203, the predictive coding processing unit 204, the orthogonal conversion / quantization unit 205, the local decoding unit 206, the code amount control unit 207, and the entropy coding unit 208. And execute the coding process. The predictive coding method determination unit 203 determines the size of each block based on the block size limit information. The coding process is performed in units of this block. After that, the CPU 210 shifts the process from step S409 to step S410.

In step S410, the CPU 210 controls the multiplexing processing unit 209, adds various syntax information to the encoded image data to generate stream data, and saves the generated stream data in the memory 102. After that, the CPU 210 ends the process in this flowchart. The syntax information includes Maximum Content Light Level (MaxCLL) and Maximum Frame-Average Light Level (MaxFALL) defined in the CEA-861.3 standard.

The processing in the flowchart shown in FIG. 4 may be realized by executing each block without the intervention of the CPU 210. In addition, each block may perform a part of the above-mentioned processing in parallel.

<Operation of brightness information acquisition unit 201>
FIG. 5 is a flowchart showing the operation of the luminance information acquisition unit 201 according to the present embodiment. This processing is described in more detail with respect to the processing of the luminance information acquisition unit 201 of the coding processing unit 114 in step S404 of FIG.

In step S501, the luminance information acquisition unit 201 reads the image data from the memory 102. When the pixel value of the read image data is in the YUV format, YCbCr format, or the like, the brightness information acquisition unit 201 is gamma-corrected RGB data (hereinafter, gamma-corrected RGB) from the pixel value of the image data. The data is called R'G'B'data). After that, the luminance information acquisition unit 201 saves the calculated R'G'B'data in the memory 102. The luminance information acquisition unit 201 reads R'G'B'data from the memory 102, performs degamma processing on the R'G'B' data, calculates linear RGB data, and stores it in the memory 102. The luminance information acquisition unit 201 reads RGB data from the memory 102, calculates the maximum value in the RGB data, and acquires it as a MaxCLL value. Further, the luminance information acquisition unit 201 calculates an average value in the RGB data and acquires it as a MaxFALL value. The luminance information acquisition unit 201 transmits the calculated MaxCLL and MaxFALL as luminance information to the block size limiting unit 202, or stores the calculated MaxCLL and MaxFALL in the memory 102. After that, the luminance information acquisition unit 201 shifts the process from step S501 to step S502.

In step S502, the luminance information acquisition unit 201 acquires the luminance of each pixel 302 from the pixel value of each pixel 302 of the image data read from the memory 102. In the process of step S502, when the brightness is acquired from the RGB data, the pixel value such as the RGB data calculated in the process of calculating MaxCLL or the process of calculating MaxFALL in step S501 is used. You may be broken. After that, the luminance information acquisition unit 201 shifts the process from step S502 to step S503.

In step S503, the luminance information acquisition unit 201 reads the image data from the memory 102 and calculates the average value, total value, maximum value, minimum value, etc. of the luminance of each pixel group 303 in units of predetermined pixel groups 303. In the process of step S503, when the brightness of each pixel group 303 is calculated from the RGB data, the pixels of the RGB data or the like calculated in the process of calculating MaxCLL or the process of calculating MaxFALL in step S501. It may be done using a value. After that, the luminance information acquisition unit 201 ends the process in this flowchart. The processing of each step of the flowchart shown in FIG. 5 may be performed by the CPU 210 instead of the luminance information acquisition unit 201.

<Operation of block size limiting unit 202>
FIG. 6 is a flowchart showing the operation of the block size limiting unit 202 according to the present embodiment. This processing has been described in detail with respect to the processing of the block size limiting unit 202 of the coding processing unit 114 in step S406 or step S407 of FIG. When the processing is performed in pixel units, it is the processing in step S406, and when the processing is performed in pixel group units, it is the processing in step S407.

In step S601, the block size limiting unit 202 tentatively determines the block size. As an example, the block size tentatively determined in this step may be the maximum block size of CTU, CU, PU, TU, or the like. After that, the block size limiting unit 202 shifts the process from step S601 to step S602.

In step S602, the block size limiting unit 202 selects a block to be processed. In this flowchart, different blocks are sequentially selected each time step S602 is repeatedly executed by the loop process. The order of block selection can be, for example, the so-called raster order. The raster order is, for example, the first time the block on the upper left in the frame is selected, the next time the block on the right side of the previously selected block is selected, and the block on the right end is selected and then one down. The block at the left end of the line is selected, and so on. After the block selection is completed, the block size limiting unit 202 shifts the process from step S602 to step S603.

In step S603, the block size limiting unit 202 determines whether or not the luminance indicated by the luminance information is within the first range in the pixels 302 or the pixel group 303 in the selected block. When the brightness in the pixel 302 or the pixel group 303 is within the first range (YES in step S603), the block size limiting unit 202 shifts the process from step S603 to step S604. When the brightness in the pixel 302 or the pixel group 303 is out of the first range (NO in step S603), the block size limiting unit 202 shifts the process from step S603 to step S605.

In step S604, the block size limiting unit 202 updates the block size limiting information so as to limit the upper limit of the block size in the selected block to a predetermined first size, and stores the block size limiting information in the memory 102. After that, the block size limiting unit 202 shifts the process from step S604 to step S607.

In step S605, the block size limiting unit 202 has a second range in which the brightness indicated by the brightness information in the pixels 302 or the pixel group 303 in the selected block is lower than the first range. Judge whether or not. When the block size limiting unit 202 determines that the brightness in the pixel 302 or the pixel group 303 is within the second range (YES in step S605), the block size limiting unit 202 shifts the process from step S605 to step S606. When the block size limiting unit 202 determines that the brightness of the pixel 302 or the pixel group 303 is out of the second range (NO in step S605), the block size limiting unit 202 shifts the process from step S605 to step S607.

In step S606, the block size limiting unit 202 updates the block size limiting information so as to limit the upper limit of the block size in the selected block to a predetermined second size, and stores the block size limiting information in the memory 102. After that, the block size limiting unit 202 shifts the process from step S606 to step S607. It is preferable that the second size is larger than the first size, and the block size limit set in step S606 is looser than the block size limit set in step S604. In this case, the upper limit of the block size can be set in two stages according to the brightness.

The block size limit information may be indicated by a raster order number of pixels 302 or pixel group 303 whose brightness is within the first range or the second range for each block. In this case, the block size limit information includes the block number, the number of the pixel 302 or the pixel group 303 whose brightness is within the first range, and the number of the pixel 302 or the pixel group 303 whose brightness is within the second range. It is composed of a character string enumerating. Further, the first range and the second range may be a range defined by the upper limit and the lower limit of the brightness, or may be a range defined only by the lower limit such as a brightness exceeding a predetermined threshold value. ..

In step S607, the block size limiting unit 202 determines whether or not the processes from step S603 to step S606 have been executed for all the pixels 302 or all the pixel groups 303 in the selected block. When the block size limiting unit 202 determines that the processing has been executed for all the pixels 302 or all the pixel groups 303 in the selected block (YES in step S607), the processing shifts from step S607 to step S608. Let me. When the block size limiting unit 202 determines that there are pixels 302 or pixel group 303 for which processing has not been executed in the selected block (NO in step S607), the block size limiting unit 202 shifts the processing from step S607 to step S603.

In step S608, the block size limiting unit 202 determines whether or not the processes from step S602 to step S607 have been executed for all the blocks in the frame. When the block size limiting unit 202 determines that the processing has been executed for all the blocks in the frame (YES in step S608), the block size limiting unit 202 shifts the processing from step S608 to step S609. When the block size limiting unit 202 determines that there is a block in the frame for which processing has not been executed (NO in step S608), the block size limiting unit 202 shifts the processing from step S608 to step S602.

In step S609, the block size limiting unit 202 adds a frame number to the block size limiting information in the frame, stores it in the memory 102, and ends the process in this flowchart.

In the flowchart of FIG. 6, the case where the brightness is determined by the first range and the second range is shown, but the brightness may be determined by the range of 3 or more in the same manner. Further, the brightness may be determined only in the first range, that is, steps S605 and S606 may be omitted. Further, the process in the flowchart of FIG. 6 may be executed for each block of CTU, CU, PU, and TU, and block size limit information may be generated for each block type. Further, the processing of each step of the flowchart shown in FIG. 6 may be performed by the CPU 210 instead of the block size limiting unit 202.

In the present embodiment, the block size can be reduced by limiting the upper limit of the block size in a pixel whose brightness is within a predetermined range, typically which is relatively high in brightness. As a result, it is possible to narrow the range in which the deterioration of the image quality due to the quantization at the time of coding, which is particularly remarkable in the pixel having high brightness. Therefore, according to the present embodiment, there is provided a coding device and a coding method capable of reducing deterioration of image quality due to coding.

[Second Embodiment]
The coding apparatus and coding method according to the second embodiment will be described in detail with reference to the drawings. The difference between the present embodiment and the first embodiment is the operation of the block size limiting unit 202. In the present embodiment, the configuration of the image processing device 100 is the same as that in FIG. 1, and thus the description thereof will be omitted. Further, in the present embodiment, the configuration of the coding processing unit 114 is the same as that in FIG. 2, and thus the description thereof will be omitted. Further, in the present embodiment, the operations of the coding processing unit 114 and the luminance information acquisition unit 201 are the same as those in FIGS. 4 and 5, respectively, and thus the description thereof will be omitted.

<Operation of block size limiting unit 202>
FIG. 7 is a flowchart showing the operation of the block size limiting unit 202 according to the present embodiment. This operation has been described in detail with respect to the processing of the block size limiting unit 202 of the coding processing unit 114 in step S406 or step S407 of FIG. When the processing is performed in pixel units, it is the processing in step S406, and when the processing is performed in pixel group units, it is the processing in step S407. In the following description, the description may be omitted or simplified for the parts common to the description of FIG.

In step S701, the block size limiting unit 202 tentatively determines the block size. The process is the same as in step S601 of FIG. After that, the block size limiting unit 202 shifts the process from step S701 to step S702.

In step S702, the block size limiting unit 202 selects a block to be processed. The process is the same as in step S602 of FIG. After the block selection is completed, the block size limiting unit 202 shifts the process from step S702 to step S703.

In step S703, the block size limiting unit 202 determines whether or not the luminance indicated by the luminance information is within the first range in the pixels 302 or the pixel group 303 in the selected block. When the brightness in the pixel 302 or the pixel group 303 is within the first range (YES in step S703), the block size limiting unit 202 shifts the process from step S703 to step S704. When the brightness in the pixel 302 or the pixel group 303 is out of the first range (NO in step S703), the block size limiting unit 202 shifts the process from step S703 to step S705.

In step S704, the block size limiting unit 202 sets the value of the register flag FLG_A to 1. When the value is 1, the flag FLG_A indicates that there is a region (hereinafter, referred to as a first luminance region) including the pixel 302 or the pixel group 303 whose luminance is within the first range in the block, and the value is When it is 0, it is information indicating that the first luminance region does not exist in the block. After that, the block size limiting unit 202 shifts the process from step S704 to step S707. It should be noted that the position information of the first luminance region in the block is also added to the flag FLG_A.

In step S705, the block size limiting unit 202 has a second range in which the brightness indicated by the brightness information in the pixels 302 or the pixel group 303 in the selected block is lower than the first range. Judge whether or not. When the block size limiting unit 202 determines that the brightness in the pixel 302 or the pixel group 303 is within the second range (YES in step S705), the block size limiting unit 202 shifts the process from step S705 to step S706. When the block size limiting unit 202 determines that the brightness of the pixel 302 or the pixel group 303 is out of the second range (NO in step S705), the block size limiting unit 202 shifts the process from step S705 to step S707.

In step S706, the block size limiting unit 202 sets the value of the register flag FLG_B to 1. When the value is 1, the flag FLG_B indicates that there is a region (hereinafter, referred to as a second luminance region) including the pixel 302 or the pixel group 303 whose brightness is within the second range in the block, and the value is When it is 0, it is information indicating that the second luminance region does not exist in the block. After that, the block size limiting unit 202 shifts the process from step S706 to step S707. It should be noted that the position information of the second luminance region in the block is also added to the flag FLG_B.

In step S707, the block size limiting unit 202 determines whether or not the value of the flag FLG_A is 1 and the value of the flag FLG_B is also 1. In this process, the block size limiting unit 202 determines whether or not both the first luminance region and the second luminance region exist in the selected block based on the flags FLG_A and the flag FLG_B. When the block size limiting unit 202 determines that the value of the flag FLG_A is 1 and the value of the flag FLG_B is also 1 (YES in step S707), the block size limiting unit 202 shifts the process from step S707 to step S708. When the block size limiting unit 202 determines that at least one of the value of the flag FLG_A and the value of the flag FLG_B is 0 (NO in step S707), the block size limiting unit 202 shifts the process from step S707 to step S710.

In step S708, the block size limiting unit 202 determines whether or not the adjacent first luminance region and second luminance region exist in the selected block. Specifically, the block size limiting unit 202 makes the determination based on the position information of the pixels 302 or the pixel group 303 added to the flags FLG_A and the flag FLG_B. When the block size limiting unit 202 determines that the first and second luminance regions adjacent to each other exist (YES in step S708), the block size limiting unit 202 shifts the process from step S708 to step S709. When the block size limiting unit 202 determines that the adjacent first luminance region and second luminance region do not exist (NO in step S708), the block size limiting unit 202 shifts the process from step S708 to step S710.

In step S709, the block size limiting unit 202 updates the block size limiting information so that the boundary between the adjacent first luminance region and the second luminance region is the same block, and saves the block size limiting information in the memory 102. Step S709 may be repeatedly executed for each pixel 302 or pixel group 303, and in that case, the block size limit information is updated every time the adjacent first luminance region and second luminance region are found, and the memory 102. Save to. After that, the block size limiting unit 202 shifts the process from step S709 to step S710.

In step S710, the block size limiting unit 202 determines whether or not the processes of steps S703 to S709 have been executed for all the pixels 302 or the pixel group 303 in the selected block. When the block size limiting unit 202 determines that the processing has been executed for all the pixels 302 or the pixel group 303 in the selected block (YES in step S710), the block size limiting unit 202 shifts the processing from step S710 to step S711. When the block size limiting unit 202 determines that there are pixels 302 or pixel group 303 for which processing has not been executed in the selected block (NO in step S710), the block size limiting unit 202 shifts the processing from step S710 to step S703.

In step S711, the block size limiting unit 202 again determines whether or not the value of the flag FLG_A is 1 and the value of the flag FLG_B is also 1. When the block size limiting unit 202 determines that the value of the flag FLG_A is 1 and the value of the flag FLG_B is also 1 (YES in S711), the block size limiting unit 202 shifts the process from step S711 to step S712. When the block size limiting unit 202 determines that at least one of the value of the flag FLG_A and the value of FLG_B is 0 (NO in S711), the block size limiting unit 202 shifts the process from step S711 to step S713.

In step S712, the block size limiting unit 202 acquires the flatness of the brightness in the block by calculating the dispersion value of the brightness of the pixels 302 or the pixel group 303 in the block. The variance value is the difference between the average of the squares of the brightness of the pixels 302 or the pixel group 303 in the block and the square of the average. The block size limiting unit 202 updates the block size limiting information according to the dispersion value of the brightness and stores it in the memory 102. For example, when the variance value of the luminance is small, the block size limiting unit 202 tightens the block size limitation by setting the upper limit of the block size defined by the block size limiting information to be low. After that, the block size limiting unit 202 shifts the process from step S712 to step S713.

In step S713, the block size limiting unit 202 determines whether or not the processes from step S702 to step S712 have been executed for all the blocks in the frame. When the block size limiting unit 202 determines that the processing has been executed for all the blocks in the frame (YES in step S713), the block size limiting unit 202 shifts the processing from step S713 to step S714. When the block size limiting unit 202 determines that there is a block in the frame for which processing has not been executed (NO in step S713), the block size limiting unit 202 shifts the processing from step S713 to step S702.

In step S714, the block size limiting unit 202 adds a frame number to the block size limiting information in the frame, stores it in the memory 102, and ends the process in this flowchart.

In the flowchart of FIG. 7, the case where the brightness is determined by the first range and the second range is shown, but the brightness may be determined by the range of 3 or more in the same manner. Further, the brightness may be determined only in the first range, that is, steps S705 and S706 may be omitted. Further, the process in the flowchart of FIG. 7 may be executed for each block of CTU, CU, PU, and TU, and block size limit information may be generated for each block type. Further, the processing of each step of the flowchart shown in FIG. 7 may be performed by the CPU 210 instead of the block size limiting unit 202.

In the present embodiment, a first luminance region (typically a pixel having a relatively high luminance) in which the luminance is within the first range and a second luminance region (typically, a pixel having a relatively high luminance) in which the luminance is within the second range. The processing when (pixels with relatively low brightness) are mixed has been described. When the first luminance region and the second luminance region are adjacent to each other, by making these boundaries the same block, it is possible to consider the influence of the luminance boundary and reduce the deterioration of image quality due to quantization near the boundary. can do. Further, when the first luminance region and the second luminance region exist and the dispersion value is small, the high-luminance region and the low-luminance region coexist by setting the block size limit according to the dispersion value. In the image, the block size can be set in consideration of the flatness of the image.

As described above, according to the present embodiment, in addition to the effect of the first embodiment, in an image in which a high-luminance region and a low-luminance region coexist, the influence of the luminance boundary and the flatness of the image are taken into consideration. The block size is limited, and the deterioration of image quality due to encoding can be further reduced.

[Third Embodiment]
The coding apparatus and coding method according to the third embodiment will be described in detail with reference to the drawings. The difference between this embodiment and the first embodiment or the second embodiment is that in this embodiment, the calculation of the luminance information is performed by an external device of the coding processing unit 114. That is, in the present embodiment, the luminance information acquisition unit 201 acquires the luminance information calculated by using the pixel values by an external device of the coding processing unit 114. Since the configuration of the image processing device 100 is the same as that in FIG. 1, the description thereof will be omitted. Further, in the present embodiment, the configuration of the coding processing unit 114 is the same as that in FIG. 2, and thus the description thereof will be omitted. Further, in the present embodiment, the operation of the block size limiting unit 202 is the same as that in FIG. 6 or FIG. 7, and thus the description thereof will be omitted.

<Operation of coding processing unit 114>
FIG. 8 is a flowchart showing the operation of the coding processing unit 114 according to the present embodiment. In this operation, when the power of the image processing device 100 is turned on, the program stored in the non-volatile memory 103 is expanded in the memory 102, and the CPU 210 in the coding processing unit 114 reads the program in the memory 102 and executes it. It is realized by doing. The process according to the flowchart of FIG. 8 is executed frame by frame, and the process may be repeatedly executed periodically.

Since the operations of step S801 and step S802 are the same as those of step S401 and step S402 of FIG. 4, the description thereof will be omitted. In step S803, the CPU 210 acquires the luminance information stored in the memory 102 by the CPU 101. After that, the CPU 210 shifts the process from step S803 to step S804. It is not essential that the CPU 101 acquire the luminance information stored in the memory 102, and it may be performed by another method. For example, the acquisition of the luminance information by the CPU 210 may be performed by being transmitted from the image processing unit 113 to the coding processing unit 114, and is transmitted from an external device 127 other than the image processing device 100 to the coding processing unit 114. It may be done by.

In step S804, the CPU 210 acquires the address information of the image data by the same operation as in S403. After that, the CPU 210 shifts the process from step S804 to step S805. Subsequent operations of steps S805 to S810 are the same as the operations of steps S405 to S410 of FIG. 4, and thus the description thereof will be omitted.

<Operation of calculating brightness information by CPU 101>
FIG. 9 is a flowchart showing the operation of calculating the luminance information in the CPU 101 according to the present embodiment. This operation is realized by expanding the program stored in the non-volatile memory 103 to the memory 102 and having the CPU 101 read and execute the program in the memory 102 while the power of the image processing device 100 is on. .. The process according to the flowchart of FIG. 9 is executed frame by frame, and the process may be repeatedly executed periodically.

In step S901, the CPU 101 determines whether or not the transfer function information acquired from the image processing unit 113 indicates a predetermined transfer function corresponding to the predetermined HDR method. An example of a predetermined transfer function is PQ or HLG. When the CPU 101 determines that the transfer function information corresponds to the predetermined HDR method (YES in step S901), the CPU 101 shifts the process from step S901 to step S902. When the CPU 101 determines that the transfer function information does not correspond to the predetermined HDR method (NO in step S901), the CPU 101 shifts the process from step S901 to step S906.

In step S902, the CPU 101 reads the image data from the memory 102. When the pixel value of the read image data is in the YUV format, YCbCr format, or the like, the CPU 101 calculates R'G'B'data from the pixel value of the image data and stores it in the memory 102. The CPU 101 reads R'G'B'data from the memory 102, performs degamma processing on the R'G'B' data, calculates linear RGB data, and stores it in the memory 102. The CPU 101 reads RGB data from the memory 102, calculates the maximum value in the RGB data, and acquires it as a MaxCLL value. Further, the CPU 101 calculates an average value in the RGB data and acquires it as a MaxFALL value. The CPU 101 transmits the calculated MaxCLL and MaxFALL as luminance information to the block size limiting unit 202, or stores the calculated MaxCLL and MaxFALL in the memory 102. After that, the CPU 101 shifts the process from step S902 to step S903.

In step S903, the CPU 101 acquires the brightness of each pixel 302 from the pixel value of the image data read from the memory 102. In the process of step S903, when the brightness is acquired from the RGB data, the pixel value such as the RGB data calculated in the process of calculating MaxCLL or the process of calculating MaxFALL in step S902 is used. You may be broken. After that, the CPU 101 shifts the process from step S903 to step S904.

In step S904, the CPU 101 reads the image data from the memory 102 and calculates the average value, the total value, the maximum value, the minimum value, and the like of the brightness of each pixel group 303 in a predetermined pixel group 303 unit. When the brightness of each pixel group 303 is calculated from the RGB data, the process of step S904 may be performed together with the process of calculating MaxCLL or the process of calculating MaxFALL in step S902. After that, the CPU 101 shifts the process from step S904 to step S905.

In step S905, the CPU 101 outputs the luminance information generated in the processes from step S902 to step S904 to the coding processing unit 114. The output method may be such that the CPU 101 writes the luminance information to the memory 102 so that the coding processing unit 114 can read the luminance information, and the CPU 101 directly sends the luminance information to the register of the coding processing unit 114 or the like. It may be something to write. After that, the CPU 101 shifts the process from step S905 to step S906.

In step S906, the CPU 101 outputs the transfer function information acquired in step S901 to the coding processing unit 114. The output method may be such that the CPU 101 writes the transfer function information to the memory 102 so that the coding processing unit 114 can read it, and the CPU 101 directly writes the transfer function information to the register of the coding processing unit 114. Etc. may be written. After that, the CPU 101 shifts the process from step S906 to step S907.

In step S907, the CPU 101 outputs the address information of the image data stored in the memory 102 to the coding processing unit 114. When the coding processing unit 114 exists outside the image processing device 100, the image data is output to the coding processing unit 114 via the communication control unit 117. After that, the CPU 101 shifts the process from step S906 to step S907.

In step S908, the CPU 101 receives the stream data output from the coding processing unit 114 and stores it in the memory 102. After that, the CPU 101 containerizes the stream data into an MP4 file, an MXF file, or the like, controls the recording medium control unit 119, and stores the containerized file in the recording medium 120. After that, the CPU 101 ends the process in this flowchart.

The processing in the flowchart shown in FIG. 9 may be realized by executing the image processing unit 113 instead of the CPU 101.

As shown above, also in the configuration of the present embodiment in which the luminance information is not calculated inside the coding processing unit 114, but the luminance information calculated by an external device is acquired and the coding process is performed. The same effect as that of the first or second embodiment can be obtained. For example, when an external dedicated codec is used as the coding processing unit 114, it can be carried out even when there is no function of calculating the luminance information.

[Modification Embodiment]
Although the present invention has been described in detail based on the preferred embodiments, the present invention is not limited to these embodiments, and various embodiments are also included in the present invention without departing from the gist.

The object to which the present invention can be applied is not limited to the image processing apparatus 100, the coding processing unit 114, and the like described in the above-described embodiment. For example, even when the image processing device or the coding device is a system composed of a plurality of devices, it is possible to realize the same functions as those in the above-described embodiment.

The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by processing. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

100 Image processing device 114 Coding processing unit 201 Brightness information acquisition unit 202 Block size limiting unit 203 Predictive coding method determination unit 204 Predictive coding processing unit 205 Orthogonal conversion quantization unit 206 Local decoding unit 207 Code amount control unit 208 Entropy Coding unit 209 Multiplexing processing unit 210 CPU

Claims (15)

Luminance information acquisition means for acquiring luminance information based on pixel values of a plurality of pixels constituting an image,
A block size limiting means for generating block size limiting information regarding the upper limit of the block size in the block including the plurality of pixels based on the luminance information.
Have a coding means for coding the image the blocks set on the basis of the block size limitation information units,
The block size limiting means limits the block size so as to limit the upper limit of the block size to a value smaller than the maximum block size when the transfer function of the image corresponds to Perceptual Quantizer or Hybrid Log Gamma. A coding device characterized by generating information. The coding device according to claim 1, wherein the luminance information acquisition means acquires the luminance information by calculating the luminance information using the pixel values. The coding device according to claim 1, wherein the luminance information acquisition means acquires the luminance information calculated by using the pixel values by an external device. The reference numeral according to claim 2 or 3, wherein the calculation of the luminance information is performed using the pixel value calculated in the process of calculating the Maximum Content Light Level or the Maximum Frame-Average Light Level. Chemical device. Any of claims 1 to 4, wherein the block size limiting means sets an upper limit of the block size to the first size when the brightness indicated by the brightness information is within the first range. The coding apparatus according to item 1. The block size limiting means further features setting the upper limit of the block size to the second size when it is determined that the brightness is within the second range lower than the first range. The coding apparatus according to claim 5. The coding apparatus according to claim 6, wherein the second size is larger than the first size. The block size limiting means is the first luminance region when the first luminance region in which the luminance is within the first range and the second luminance region in which the luminance is within the second range are adjacent to each other. The coding apparatus according to claim 6 or 7, wherein the block size limit information is updated so that the boundary between the second luminance region and the second luminance region is included in the same block. The coding device according to any one of claims 6 to 8, wherein the block size limiting means updates the block size limiting information according to the dispersion value of the brightness. The block size limiting means is characterized in that the block size limiting information is generated by making a determination on a pixel-by-pixel basis based on the luminance information calculated from the pixel value of each of the pixels. 9. The encoding device according to any one of 9. The claim is characterized in that the block size limiting means generates the block size limiting information by making a determination on a pixel group basis based on the luminance information calculated for each pixel group including the plurality of pixels. Item 2. The coding apparatus according to any one of Items 1 to 9. The coding apparatus according to any one of claims 1 to 11 , wherein the block is any one of a macro block, a coding tree unit, a coding unit, a prediction unit, and a transfer unit. The coding device according to any one of claims 1 to 12 , wherein the coding means sets a priority for assigning a quantization parameter of the block based on the block size limitation information. A step of acquiring luminance information based on the pixel values of a plurality of pixels constituting the image, and
Based on the luminance information, a step of generating block size limit information regarding the upper limit of the block size in the block including the plurality of pixels, and
Possess and performing coding of the image the blocks set on the basis of the block size limitation information units,
In the step of generating the block size limit information, when the transfer function of the image corresponds to Perceptual Quantizer or Hybrid Log Gamma, the upper limit of the block size is limited to a value smaller than the maximum block size. A coding method characterized in that the block size limit information is generated. On the computer
A step of acquiring luminance information based on the pixel values of a plurality of pixels constituting the image, and
Based on the luminance information, a step of generating block size limit information regarding the upper limit of the block size in the block including the plurality of pixels, and
A program that executes a step of encoding the image in units of the blocks set based on the block size limit information.
In the step of generating the block size limit information, when the transfer function of the image corresponds to the Perceptual Quantizer or Hybrid Log Gamma, the upper limit of the block size is limited to a value smaller than the maximum block size. A program characterized in that the block size limit information is generated.

Images