JP6830990B2 - Display device - Google Patents

Description

Embodiments of the present invention relate to display devices.

A display device such as a liquid crystal display device in which a memory is arranged for each pixel in a display area is known. In this type of display device, a digital signal corresponding to the image to be displayed is written in each memory, and the drive potential of each pixel is set to a potential corresponding to the digital signal stored in each memory, so that the image is displayed in the display area. Is displayed. The method of driving the pixels based on the digital signal stored in the memory in this way is called, for example, a digital mode or a digital drive method.

In a display device, it is desired to make the peripheral area around the display area as small as possible (narrowing the frame). In the digital mode display device, it is necessary to arrange various wirings and circuits for controlling the memory in the peripheral area. Therefore, in order to achieve a narrow frame, it is necessary to devise a circuit layout in the peripheral region.

JP-A-2009-1223636

An object of one aspect of the present disclosure is to provide a digital mode display device capable of narrowing the frame.

The display device according to one embodiment includes a pair of substrates, an optical element layer, a pixel electrode, a switching element, a plurality of wirings, and a first driver unit. The pair of substrates has a display area in which a plurality of pixels are arranged. The optical element layer is arranged between the pair of substrates. The pixel electrodes are arranged in the pixels. The switching element is connected to the pixel electrode. The plurality of wirings are connected to the switching element. The first driver unit is arranged in a peripheral area around the display area, and supplies a signal to each of the plurality of wirings. The first driver unit includes a plurality of first circuit units, and the corresponding wiring is connected to each of the plurality of first circuit units. Further, the first circuit unit includes a first circuit, a second circuit, and a first connection line connecting the first circuit and the second circuit. The wiring extends in the second direction in the display area. The first circuit and the second circuit are arranged in the second direction and offset from each other in the first direction intersecting the second direction.

FIG. 1 is a diagram showing an example of the overall configuration of the display device according to the embodiment. FIG. 2 is a diagram showing an example of the circuit configuration of the display device. FIG. 3 is a diagram showing an example of an equivalent circuit of sub-pixels included in the display device. FIG. 4 is a timing chart showing an example of the operation of the display device during the storage period. FIG. 5 is a timing chart showing an example of the operation of the display device during the display period. FIG. 6 is a diagram showing a schematic configuration of a first circuit unit included in the display device. FIG. 7 is a diagram showing a schematic configuration of a second circuit unit included in the display device. FIG. 8 is a diagram showing an example of a circuit layout applicable to the first and second driver units included in the display device in the first region included in the peripheral region. FIG. 9 is a diagram showing another example of the circuit layout applicable to the first and second driver units in the first region. FIG. 10 is a diagram showing an example of a circuit layout applicable to the second driver unit in the second region included in the peripheral region. FIG. 11 is a diagram showing a specific example of a circuit layout that can be applied to the first region. FIG. 12 is an enlarged view of the first circuit unit of FIG. FIG. 13 is an enlarged view showing the second circuit unit of FIG.

One embodiment will be described with reference to the drawings.
It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be represented schematically as compared with actual embodiments in order to clarify the description, but the drawings are merely examples and do not limit the interpretation of the present invention. In each figure, reference numerals may be omitted for the same or similar elements arranged consecutively. Further, in the present specification and each figure, components exhibiting the same or similar functions as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and duplicate detailed description may be omitted.

In the present embodiment, as an example of the display device, a liquid crystal display device having the above-mentioned digital mode function will be disclosed. However, this embodiment does not prevent the application of the individual technical ideas disclosed in this embodiment to other types of display devices. As the other type of display device, a self-luminous display device such as an organic electroluminescence (organic EL) display device, an electronic paper type display device having an electrophoresis element or the like, or the like is assumed.

First, the basic configuration and operation of the display device will be described with reference to FIGS. 1 to 5.
FIG. 1 is a plan view showing an example of a schematic configuration of the display device 1. The display device 1 includes a first substrate SUB1 and a second substrate SUB2. The first substrate SUB1 and the second substrate SUB2 are bonded to each other in a state of facing each other. A liquid crystal layer (liquid crystal layer LC described later) is enclosed between the first substrate SUB1 and the second substrate SUB2. This liquid crystal layer is an example of an optical element layer. Examples of other optical element layers include the above-mentioned organic EL element, electrophoresis element, and MEMS (Micro Electro Mechanical Systems) shutter element.

The display device 1 has a display area DA and a peripheral area SA surrounding the display area DA. The display area DA corresponds to the area where the image is displayed in the area where the first substrate SUB1 and the second substrate SUB2 overlap. Pixels PX are arranged in the display area DA. Specifically, in the display area DA, a large number of pixels PX are arranged in a matrix along the first direction X and the second direction Y. The first direction X and the second direction Y are, for example, orthogonal to each other. The peripheral region SA corresponds to the region outside the display region DA in the region where the first substrate SUB1 and the second substrate SUB2 overlap.

In the example of FIG. 1, the display area DA has a perfect circular shape. However, the display area DA may have another shape such as an elliptical shape, a polygonal shape, or a shape including at least a curved contour. Further, in the example of FIG. 1, the first substrate SUB1, the second substrate SUB2, and the peripheral region SA are also circular. However, the first substrate SUB1, the second substrate SUB2, and the peripheral region SA may have other shapes as in the display region DA.

The display device 1 further includes a control device 2, a first driver unit 3, and a second driver unit 4. The control device 2 is, for example, an integrated circuit mounted on the first substrate SUB1 and functions as a signal supply source that outputs various signals necessary for image display based on image data input from the outside. The control device 2 may be connected to these boards via a flexible wiring board or the like without being mounted on the first board SUB1 or the second board SUB2.

The first driver unit 3 and the second driver unit 4 are formed on, for example, the first substrate SUB1 in the peripheral region SA. In the example of FIG. 1, the first driver unit 3 has an arc shape along the lower edge portion (edge portion on the control device 2 side) of the display area DA. Further, the second driver unit 4 has an arc shape along the left edge portion of the display area DA. The first driver unit 3 can be rephrased as a horizontal driver, a signal line drive circuit, a source driver, or the like. The second driver unit 4 can be rephrased as a vertical driver, a scanning line drive circuit, a gate driver, or the like.

The peripheral region SA is shielded from light by, for example, a light-shielding layer formed on the second substrate SUB2. By providing such a light-shielding layer, it is possible to prevent light leakage from the peripheral region SA and reflection of light by the circuit and wiring formed in the peripheral region SA.

The first driver unit 3 includes a plurality of first circuit units 30. The second driver unit 4 includes a plurality of second circuit units 40.
The peripheral region SA has a first region A1 and a second region A2. In the first region A1, a part of the first driver unit 3 (at least one first circuit unit 30) is located between the second driver unit 4 and the display area DA. On the other hand, in the second area A2, the first driver unit 3 is not located between the second driver unit 4 and the display area DA. From another point of view, both the first circuit unit 30 and the second circuit unit 40 are formed in the first region A1, the second circuit unit 40 is formed in the second region A2, and the first circuit is formed. The unit 30 is not formed.

FIG. 2 is a diagram showing a schematic circuit configuration of the display device 1. Here, for simplification of the illustration, the display area DA is rectangular and the driver units 3 and 4 are linear. In the present embodiment, the pixel PX includes sub-pixel SPs of red (R), green (G), and blue (B). Hereinafter, the red, green, and blue sub-pixel SPs are referred to as sub-pixels SPR, SPG, and SPB, respectively. In the present disclosure, the sub-pixel SP may be simply referred to as a "pixel".

In the example of FIG. 2, the sub-pixels SPR, SPG, and SPB included in one pixel PX are arranged in the first direction X. However, the layout of the pixel PX is not limited to the example of FIG. For example, the pixel PX may further include sub-pixel SPs of other colors such as white (W). Further, at least a part of the sub-pixel SP included in one pixel PX may be arranged in the second direction Y. Further, the pixel PX may include a plurality of sub-pixels SP corresponding to the same color.

The display device 1 includes a plurality of signal lines S and a plurality of scanning lines GD. Each signal line S and each scanning line GD are formed on the first substrate SUB1. Each signal line S is connected to the corresponding first circuit unit 30. Each scan line GD is connected to a corresponding second circuit unit 40. Each signal line S extends to the display area DA along the second direction Y and is lined up in the first direction X. Each scanning line GD extends to the display area DA along the first direction X and is arranged in the second direction Y.

Each of the sub-pixels SP includes a memory 10 and a pixel electrode PE formed on the first substrate SUB1. The memory 10 stores a digital signal supplied via the signal line S. The pixel electrode PE faces the common electrode CE formed on the second substrate SUB2. The common electrode CE may be formed on the first substrate SUB1. The pixel electrode PE and the common electrode CE can be formed of a transparent conductive material such as indium tin oxide (ITO). The common electrode CE is formed over a plurality of sub-pixels SP, and is connected to an AC drive circuit 20 included in the control device 2 via a common electrode line LCM.

The display device 1 includes a color filter facing each sub-pixel SP. These color filters have colors corresponding to the display colors of the opposing sub-pixels SP, and are formed on, for example, the second substrate SUB2.

The display device 1 can be, for example, a reflection type display device. In this case, a reflective layer that reflects external light is formed in the display area DA, and an image is displayed using the light reflected by this reflective layer. A front light may be provided on the outer surface side of the second substrate SUB2, and an image may be displayed by using the light from the front light.

Further, the display device 1 can be a transmissive display device. In this case, a backlight is provided on the back surface side of the first substrate SUB1, and the light from the backlight is used to display an image. The display device 1 may have both reflective and transmissive functions.

FIG. 3 is a diagram showing an example of an equivalent circuit of the sub-pixel SP. The pixel electrode PE, the memory 10, the selection control circuit 11, and the storage control circuit 12 are arranged in each of the sub-pixels SP.

The selection control circuit 11 includes a switching element Q1 whose input end is connected to the first drive line DL1 and a switching element Q2 whose input end is connected to the second drive line DL2. For example, the control device 2 supplies the first drive line DL1 with a first drive signal xFRP, which is an image display signal. The second drive signal FRP, which is a non-display signal of the image, is supplied from the AC drive circuit 20 to the second drive line DL2.

Further, the selection control circuit 11 includes a selection signal line 12a that connects the output ends of the switching elements Q1 and Q2 and the pixel electrode PE.

In FIG. 3, the wiring extending from the AC drive circuit 20 is branched into the second drive line DL2 and the common electrode line LCM. That is, in this example, each signal FRP and VCOM have the same potential.

The memory 10 includes switching elements Q3 to Q6. The first power supply line LP1 is connected to the input ends of the switching elements Q3 and Q5. A power supply voltage VRAM is supplied to the first power supply line LP1 from the second circuit unit 40. A second power supply line LP2 to which voltage VSS is supplied is connected to the input terminals of the switching elements Q4 and Q6. The switching elements Q3 and Q4 form a first inverter whose output end is connected to the control end of the switching element Q2, and the switching elements Q5 and Q6 form a second inverter whose output end is connected to the control end of the switching element Q1. To do. These inverters are connected in parallel in the opposite direction, and one of the switching elements Q1 and Q2 is selectively turned on.

The first circuit unit 30 supplies the digital signal SIG to the signal line S. The storage control circuit 12 is a circuit that stores the digital signal SIG supplied to the signal line S in the memory 10, and includes a switching element Q7. The input end of the switching element Q7 is connected to the signal line S, and the output end is connected to the control ends of the switching elements Q3 and Q4. A scanning line GD is connected to the control end of the switching element Q7. A scanning signal GATED is supplied to the scanning line GD from the second circuit unit 40.

The switching elements Q1 to Q7 are, for example, all thin film transistors and are formed on the first substrate SUB1. The first drive line DL1, the second drive line DL2, the first power supply line LP1, the second power supply line LP2, and the scanning line GD are also formed on the first substrate SUB1, and are formed on a plurality of sub-pixel SPs arranged in the first direction X. It is connected.

The display device 1 having the above configuration can drive each sub-pixel SP in the digital mode. The digital mode is a method of simply controlling the brightness of the sub-pixel SP in monochrome on / off based on the digital signal stored in the memory 10. In the following description, when the display device 1 is in the normal black mode and the memory 10 is set to the H level (high potential level), the sub-pixel SP is turned on (displayed in white) and the memory 10 is set to the L level. It is assumed that the sub-pixel SP is turned off (displayed in black) when it is set to (low potential level).

In the digital mode, the storage period for storing the digital signal SIG supplied to the signal line S in the memory 10 and the digital signal (H level or H level or) stored in the memory 10 among the first drive signal xFRP and the second drive signal FRP. The display period in which one corresponding to the L level) is selectively supplied to the pixel electrode PE is repeated.

In the following description, a group of sub-pixels SP arranged in the first direction X in the display area DA is referred to as a horizontal line. During the storage period, the scanning pulse is sequentially supplied to the scanning line GD, and the digital signal SIG of the horizontal line corresponding to the scanning line GD to which the scanning pulse is supplied is sequentially supplied to each signal line S. As a result, the digital signal SIG corresponding to the image data is sequentially written to the memory 10 for each horizontal line.

FIG. 4 is a timing chart showing an example of the operation of the display device 1 during the storage period. In this timing chart, focusing on one sub-pixel SP shown in FIG. 3, it is stored in the digital signal SIG, the pixel potential PIX of the pixel electrode PE, the common signal VCOM, the scanning signal GATED, the power supply voltage VRAM, and the memory 10. It shows the change of the memory potential RAM.

In the following description, the period for writing the digital signal SIG to one horizontal line is defined as the horizontal period TH. In the horizontal period TH, the digital signal SIG of the signal line S is set to the potential to be written in the memory 10. Here, it is assumed that the voltage VDD, which is the H level, corresponds to the white display, and the voltage VSS, which is the L level, corresponds to the black display. The power supply voltage VRAM of the first power supply line LP1 is lowered from VDD2 to VDD1. After that, when the scanning signal GATED of the scanning line GD is raised from VSS2 to VDD2, the switching element Q7 is turned on and the memory 10 is connected to the signal line S. At this time, as shown by an arrow in the figure, the level of the digital signal SIG supplied to the signal line S is written to the memory 10. FIG. 4 illustrates a case where the H level is written to the memory 10.

After that, by lowering the scanning signal GATED to VSS2, the switching element Q7 is turned off, and the power supply voltage VRAM is raised to VDD2, which is the voltage that turns on the switching elements Q1 and Q2. At this time, the voltage of the memory 10 is also raised from VDD1 to VDD2. As a result, the memory 10 connects the first power supply line LP1 and the switching element Q1, and turns on the switching element Q1 by the power supply voltage VRAM. On the other hand, the memory 10 connects the second power supply line LP2 and the switching element Q2, and turns off the switching element Q2 by the voltage VSS. When the switching element Q1 is turned on, the first drive signal xFRP of the first drive line DL1 is supplied to the selection signal line 12a.

If the potential supplied to the memory 10 is at the L level corresponding to the black display, the memory 10 connects the second power supply line LP2 and the switching element Q1, and turns off the switching element Q1 by the voltage VSS. On the other hand, the memory 10 connects the first power supply line LP1 and the switching element Q2, and turns on the switching element Q2 by the power supply voltage VRAM. When the switching element Q2 is turned on, the second drive signal FRP of the second drive line DL2 is supplied to the selection signal line 12a. That is, the memory 10 exclusively turns on one of the switching elements Q1 and Q2 according to the stored voltage, and uses either one of the first drive line DL1 and the second drive line DL2 as the connection destination of the selection signal line 12a. select.

FIG. 5 is a timing chart showing an example of the operation of the display device 1 during the display period. In this timing chart, as in the case of FIG. 4, one sub-pixel SP is focused on. In the examples of FIGS. 4 and 5, the polarities of the potentials between the pixel electrode PE and the common electrode CE are periodically inverted for each frame period TF in all the sub-pixel SPs arranged in the display area DA. A case using inversion control is shown. The rewriting of the memory 10 of each horizontal line constituting one frame is executed, for example, during one frame period TF. That is, the series of horizontal period TH shown in FIG. 4 is included in one frame period TF, and the signal VCOM is constant. On the other hand, as shown in FIG. 5, the display period is composed of a plurality of frame period TFs, and the potentials of the respective signals VCOM and FRP change between VSS and VDD for each frame period TF. The first drive signal xFRP is an AC signal having a phase opposite to that of the second drive signal FRP, and changes between the voltages VDD and VSS for each frame period TF.

During the display period, the first drive line DL1 is connected to the pixel electrode PE when the switching element Q1 is turned on by the memory 10, and the second drive line when the switching element Q2 is turned on by the memory 10. DL2 is connected to the pixel electrode PE. FIG. 5 illustrates a case where the pixel potential PIX is set to the first drive signal xFRP by connecting the first drive line DL1 to the pixel electrode PE. In this case, a potential difference is generated between the pixel electrode PE and the common electrode CE, and the sub-pixel SP is displayed in white. On the other hand, when the second drive line DL2 is connected to the pixel electrode PE, no potential difference is generated between the pixel electrode PE and the common electrode CE, and the sub-pixel SP is displayed in black.
By the above operation, each sub-pixel SP is displayed in white or black, and an image is displayed in the display area DA.

Subsequently, the first circuit unit 30 and the second circuit unit 40 will be described with reference to FIGS. 6 and 7.
FIG. 6 is a diagram showing a schematic configuration of the first circuit unit 30. The first circuit unit 30 shown in this figure is digitally assigned to each of two sub-pixels SPR1 and SPR2 corresponding to red, two sub-pixels SPG1 and SPG2 corresponding to green, and two sub-pixels SPB1 and SPB2 corresponding to blue. It supplies the signal SIG. For example, the sub-pixels SPR1, SPG1, and SPB1 are included in one pixel PX, and the sub-pixels SPR2, SPG2, and SPB2 are included in the pixel PX and another pixel PX adjacent to the first direction X.

The first circuit unit 30 includes a first shift register 31, a first latch circuit 32, a second latch circuit 33, and a first buffer circuit 34. The first latch circuit 32 includes memory elements MA1 to MA6. The second latch circuit 33 includes memory elements MB1 to MB6. The first buffer circuit 34 includes buffer elements BA1 to BA6.

The first shift register 31 and the first latch circuit 32 are connected by two first connection lines CL1. The memory elements MA1 to MA6 are connected to the memory elements MB1 to MB6 via the second connection line CL2, respectively. The memory elements MB1 to MB6 are connected to the buffer elements BA1 to BA6 via the third connection line CL3, respectively. Signal lines S extending to the sub-pixels SPR1, SPG1, SPB1, SPR2, SPG2, and SPB2 are connected to the buffer elements BA1 to BA6, respectively.

The first shift register 31, the first latch circuit 32, the second latch circuit 33, and the first buffer circuit 34 operate using the voltages VDD1 and VSS as a drive power source. When the reset signal xRST is input, the first shift register 31 clears the outputs OUT and xOUT to the off potential. When the clock HCK is input, the first shift register 31 takes in the output data DI of the first shift register 31 (hereinafter, referred to as the previous stage register) of the first circuit unit 30 in the previous stage, and latches the output data DI. At this time, if the output data DI of the previous stage register is H level, the output OUT of the first shift register 31 is H level, and the output xOUT is L level. On the contrary, if the output data of the previous stage register is L level, the output OUT of the first shift register 31 is L level, and the output xOUT is H level.

The output OUT of the first shift register 31 is output to the first shift register 31 of the first circuit unit 30 in the next stage. Further, the outputs OUT and xOUT of the first shift register 31 are supplied to the memory elements MA1 to MA6 as latch pulses.

In the example of FIG. 6, the data bus DBL extends between the first shift register 31 and the first latch circuit 32. The data bus DBL may extend between the first latch circuit 32 and the second latch circuit 33. The data bus DBL includes six wires to which the video data R1, G1, B1, R2, G2, and B2 are supplied. The video data R1, G1, B1, R2, G2, and B2 are data representing digital signal SIGs supplied to the sub-pixels SPR1, SPG1, SPB1, SPR2, SPG2, and SPB2, respectively.

When the H-level output data DI is input to the first shift register 31, for example, the video data R1, G1, B1, R2, G2, B2 supplied to the data bus DBL are latched by the memory elements MA1 to MA6.

Timing pulses Ds and xDs are input to the memory elements MB1 to MB6. The memory elements MB1 to MB6 simultaneously latch the video data latched by the memory elements MA1 to MA6 by the timing pulses Ds and xDs. In this way, the timing at which the video data is transferred from the first latch circuit 32 to the second latch circuit 33 is the same for all the first circuit units 30, for example. As a result, the video data of each sub-pixel SP (horizontal line) arranged in the first direction X is aligned with the second latch circuit 33 of each first circuit unit 30.

The buffer elements BA1 to BA6 output a digital signal SIG corresponding to the video data latched by the memory elements MB1 to MB6 to the signal line S, respectively. As a result, the digital signal SIG corresponding to the video data latched by the second latch circuit 33 of each first circuit unit 30 is simultaneously supplied to each signal line S, and the data is written to the memory 10 of each sub-pixel SP. Will be done. While the digital signal SIG is being supplied in this way, the video data R1, G1, B1, R2, G2, and B2 of the next horizontal line are latched in the first latch circuit 32.

According to the above configuration, the video data of the two pixels PX can be processed by one first circuit unit 30. Therefore, the drive frequency of the first driver unit 3 can be reduced. Further, since the video data of the next horizontal line can be latched by the first latch circuit 32 while the video data of the second latch circuit 33 is supplied to the signal line S, the processing efficiency can be improved.

The first circuit unit 30 may be configured to include only one latch circuit. Further, the first circuit unit 30 may be configured to supply the digital signal SIG only to the sub-pixel SP included in one pixel PX, or to the sub-pixel SP included in three or more pixel PX. On the other hand, the configuration may be such that a digital signal SIG is supplied.

FIG. 7 is a diagram showing a schematic configuration of the second circuit unit 40. The second circuit unit 40 includes a second shift register 41, two second buffer circuits 42A and 42B, and a power supply circuit 43. The second shift register 41, the second buffer circuits 42A and 42B, and the power supply circuit 43 are connected by the fourth connection line CL4.

The second shift register 41 and the second buffer circuits 42A and 42B operate using the voltages VDD2 and VSS as a drive power source. The power supply circuit 43 operates using the voltages VDD1 and VDD2 as a drive power source. When the reset signal xRST is input, the second shift register 41 clears the outputs OUT and xOUT to, for example, an off potential. When the clock VCK is input, the second shift register 41 takes in the output data DI of the second shift register 41 (hereinafter, referred to as the previous stage register) of the second circuit unit 40 in the previous stage, and latches the output data DI. For example, if the output data DI of the previous register is H level, the output OUT of the second shift register 41 is H level, and the output xOUT is L level. On the other hand, if the output data DI of the previous stage register is L level, the output OUT of the second shift register 41 is L level, and the output xOUT is H level.

The outputs OUT and xOUT of the second shift register 41 are supplied to the second buffer circuits 42A and 42B, and are also output to the second shift register 41 of the second circuit unit 40 in the next stage. Further, the outputs OUT and xOUT are supplied to the power supply circuit 43. The power supply circuit 43 sets the above-mentioned power supply voltage VRAM to H level or L level according to the states of the outputs OUT and xOUT.

The enable signal xENB1 is supplied to the second buffer circuit 42A. The enable signal xENB2 is supplied to the second buffer circuit 42B. The second buffer circuit 42A has an H level on the scanning line GD connected to the second buffer circuit 42A, for example, when the output OUT is H level, the output xOUT is L level, and the enable signal xENB1 is input. Scanning signal GATED is supplied. The second buffer circuit 42B has an H level on the scanning line GD connected to the second buffer circuit 42B, for example, when the output OUT is H level, the output xOUT is L level, and the enable signal xENB2 is supplied. Scanning signal GATED is supplied. In the sub-pixel SP connected to the scanning line GD to which the H-level scanning signal GATED is supplied, the switching element Q7 is turned on. Therefore, in these sub-pixels SP, the digital signal SIG supplied to the signal line S can be written to the memory 10.

In the second circuit unit 40 having the above configuration, when the first-stage second shift register 41 latches the driving data, the two scanning lines GD can be sequentially driven by the enable signals xENB1 and xENB2. it can. That is, it is not necessary to prepare the second shift register 41 for each scanning line GD, and the drive frequency of the second shift register 41 can be relaxed.

In a general display device, the display area DA has a rectangular shape having a side portion along the first direction X and a side portion along the second direction Y. In this case, it is usual that the first driver unit 3 is arranged linearly along the first direction X and the second driver unit 4 is arranged linearly along the second direction Y. Since the driver units 3 and 4 are along the display area DA, the driver units 3 and 4 and the display area DA can be brought close to each other over the entire length.

On the other hand, when the display area DA is circular as shown in FIG. 1, if the driver units 3 and 4 are arranged in a straight line, a wasted space is created between the display area DA and each driver unit 3 and 4. Occurs. Therefore, in the present embodiment, as shown in FIG. 1, each driver unit 3 and 4 has an arc shape along the display area DA. Further, by arranging at least a part of the first driver unit 3 between the second driver unit 4 and the display area DA as in the first area A1, it is possible to prevent the generation of wasted space in the peripheral area SA and narrow the space. We are trying to make a frame.

However, in the first area A1, it is necessary to pass the wiring such as the scanning line GD extending from the second driver unit 4 to the display area DA through the area of the first driver unit 3. Further, when each of the driver units 3 and 4 is formed into an arc shape, it is necessary to appropriately bend the wiring in these driver units. In view of these, it is necessary to improve the efficiency of the circuit layout of each driver unit 3 and 4.

FIG. 8 is a diagram showing an example of a circuit layout that can be applied to each of the driver units 3 and 4. In this figure, the schematic configuration of the peripheral region SA and the display region DA in the vicinity of the first region A1 is shown.

The first driver unit 3 includes a plurality of first circuit units 30 arranged in an arc along the display area DA. In FIG. 8, one signal line S is connected to one first circuit unit 30, but more signal lines S (for example, six signal lines S as shown in FIG. 6) are connected. Is also good.

The second driver unit 4 includes a first driver unit 3 and a plurality of second circuit units 40 arranged in an arc along the display area DA. In FIG. 8, one scanning line GD is connected to one second circuit unit 40, but more scanning lines GD (for example, two scanning lines GD as shown in FIG. 7) are connected. Is also good.

The first circuit unit 30 is divided into two circuits. In the following description, one of these two circuits will be referred to as a horizontal circuit H1 and the other will be referred to as a horizontal circuit H2. For example, the horizontal circuit H1 includes at least one of the first shift register 31, the first latch circuit 32, the second latch circuit 33, and the first buffer circuit 34 shown in FIG. 6, and the horizontal circuit H2 leaves the rest. Including. Further, the horizontal circuits H1 and H2 may be defined by circuit elements of more subdivided units such that the horizontal circuit H1 includes the memory elements MA1 to MA3 and the horizontal circuit H2 includes the memory elements MA4 to MA6. In addition, the method of dividing the first circuit unit 30 is arbitrary, and various aspects can be applied depending on the configuration of the first circuit unit 30. Further, the first circuit unit 30 may be divided into three or more horizontal circuits.

In the example of FIG. 8, the horizontal circuits H1 and H2 are linearly arranged in the second direction Y. Further, a scanning line GD extending in the first direction X extends between the horizontal circuits H1 and H2. The horizontal circuits H1 and H2 are electrically connected to each other by a connecting line provided in a layer different from the scanning line GD.

When the first circuit unit 30 is not divided into a plurality of horizontal circuits, it is necessary to bend the scanning line GD so as to avoid the first circuit unit 30. Therefore, a space for routing the scanning line GD is required around the first circuit unit 30. On the other hand, in the example of FIG. 8, the scanning line GD can be extended toward the display area DA without bending the first circuit unit 30. Therefore, the space for the scanning line GD can be minimized, so that the layout of the peripheral region SA can be made more efficient.

FIG. 9 is a diagram showing another example of the circuit layout applicable to each of the driver units 3 and 4. In the example of this figure, the second circuit unit 40 is further divided into two circuits. In the following description, one of these two circuits will be referred to as a vertical circuit V1 and the other will be referred to as a vertical circuit V2. The vertical circuits V1 and V2 are electrically connected to each other by one or more connecting lines.

For example, the vertical circuit V1 includes at least one of the second shift register 41, the second buffer circuits 42A and 42B, and the power supply circuit 43 shown in FIG. 7, and the vertical circuit V2 includes the rest. In addition, the method of dividing the second circuit unit 40 is arbitrary, and various aspects can be applied depending on the configuration of the second circuit unit 40. The second circuit unit 40 may be divided into three or more vertical circuits.

In the example of FIG. 9, the horizontal circuits H1 and H2 are arranged in the second direction Y as in the case of FIG. However, the horizontal circuits H1 and H2 are arranged so as to be offset from each other in the first direction X. Specifically, the horizontal circuit H2 is deviated from the horizontal circuit H1 in the left direction (direction away from the display area DA) in the drawing. Here, "the two circuits are offset from each other in the first direction X" means that, for example, a line segment connecting the center of one circuit in the first direction X and the center of the other circuit in the first direction X is defined as a line segment. It means that it is not parallel to the second direction Y.

By shifting the horizontal circuits H1 and H2 in this way, the layout of the peripheral region SA can be further made more efficient. For example, in the example of FIG. 8, a space such as a region 50 may be generated around the first circuit unit 30, but in the example of FIG. 9, this region can be effectively utilized to lay out the first circuit unit 30.

The vertical circuits V1 and V2 are arranged in the first direction X. Further, the vertical circuits V1 and V2 are arranged so as to be offset from each other in the second direction Y. Specifically, the vertical circuit V1 is shifted downward in the drawing from the vertical circuit V2. Here, "the two circuits are offset from each other in the second direction Y" means that, for example, a line segment connecting the center of one circuit in the second direction Y and the center of the other circuit in the second direction Y is defined as a line segment. It means that it is not parallel to the first direction X.

Subsequently, the circuit layout in the second region A2 will be described. FIG. 10 is a diagram showing an example of a circuit layout applicable to the second driver unit 4 in the second region A2. The second driver unit 4 corresponds to the second driver unit 4 of FIG. That is, the second circuit unit 40 is not divided into a plurality of vertical circuits. However, the second circuit unit 40 may be divided into a plurality of vertical circuits as in FIG. 9. For example, even if the second circuit unit 40 is divided into the vertical circuits V1 and V2 in the first region A1 as shown in FIG. 9, the second circuit unit 40 is not divided in the second region A2. Is also good.

In the second region A2, the first driver unit 3 does not exist between the second driver unit 4 and the display area DA. Therefore, from FIGS. 1 and 10, the second driver unit 4 can be brought closer to the display area DA. For example, the distance between the second circuit unit 40 and the display area DA in the first region A1 is defined as the first distance, and the distance between the second circuit unit 40 and the display region DA in the second region A2 is defined as the second distance. .. In this case, the second distance can be made smaller than the first distance.

Here, a specific example of the circuit layout applicable to the first region A1 will be described with reference to FIG. In this figure, in addition to the first region A1 (peripheral region SA), a part of the sub-pixel SP arranged in the display region DA is also shown.

In FIG. 11, four first circuit units 30 and three second circuit units 40 are shown. Between the first circuit unit 30 and the display area DA, a first wiring WL1 to which the first drive signal xFRP is supplied and a second wiring WL2 to which the second drive signal FRP is supplied extend. For example, the first drive line DL1 shown in FIG. 3 is connected to the first wiring WL1. For example, the second drive line DL2 shown in FIG. 3 is connected to the second wiring WL2. In the example of FIG. 11, between the first circuit unit 30 and the display area DA, the third wiring WL3 to which the voltage VSS is supplied and the fourth wiring WL4 to which the voltage VDD1 is supplied are further extended. The voltages VSS and VDD1 of the wirings WL3 and WL4 are also supplied to the sub-pixel SP and used to drive the memory 10. Wiring WL1 to WL4 are bent along the display area DA. In FIG. 11, the wirings WL1 to WL4 are bent in a stepped manner, and the number of first circuit units 30 corresponding to one stage is not the same. Specifically, the number of the first circuit units 30 corresponding to the stages of the wirings WL1 to WL4 located in the center of FIG. 11 is two (HU1 and HU2). On the other hand, the number of first circuit units 30 corresponding to the stages adjacent to the stage is one. By making the number of the first circuit units 30 corresponding to each stage different, space efficiency is realized.

In the peripheral region SA, guard rings 60 to which the common signal VCOM is supplied are arranged in an annular shape along the outer peripheral edge of the peripheral region SA, for example. The guard ring 60 plays a role of preventing static electricity supplied from the outside from affecting each circuit of the peripheral region SA. The circuit units 30 and 40 are arranged between the guard ring 60 and the display area DA.

A dummy pixel DSP is arranged between the first wiring WL1 and the display area DA along the contour of the display area DA. The dummy pixel DSP has the same shape as the sub-pixel SP in a plan view, and is arranged at the same pitch as the sub-pixel SP. For example, the dummy pixel DSP includes a pixel electrode PE and a gate circuit 11, but does not include at least a memory 10. A second drive signal FRP, which is a non-display signal, is always supplied to the pixel electrode PE of the dummy pixel DSP. That is, the dummy pixel DSP is a pixel that is always displayed in black and does not display an image.

There are a plurality of pixel sequences (signal lines) driven by one first circuit unit 30, and there are six in FIG. In these six signal lines S, the number of dummy pixel DSPs connected to each signal line S is different. Further, when comparing the adjacent first circuit units 30, the average number of dummy pixel DSPs connected to each signal line S is different. Specifically, in FIG. 11, the number of average dummy pixel DSPs in the first region A1 connected to the HU1 corresponding to the first circuit unit 30 and the corresponding signal line S is 1.6 (8/5). ). On the other hand, the number of average dummy pixel DSPs in the first region A1 connected to the HU2 corresponding to the first circuit unit 30 and the corresponding signal line S is 0.6 (3/5). Dummy pixel DSPs are irregularly arranged over the entire edge of the display area DA to fill the space between the first wiring W1 and the display area DA.

FIG. 12 is an enlarged view of the first circuit unit 30 of FIG. Further, FIG. 13 is an enlarged view showing the second circuit unit 40 of FIG. The first circuit unit 30 shown in FIG. 12 includes a horizontal circuit H1 (first circuit), a horizontal circuit H2 (second circuit), and a horizontal circuit H3 (third circuit). The horizontal circuit H1 includes a first shift register 31. The horizontal circuit H2 includes a first latch circuit 32. The horizontal circuit H3 includes a second latch circuit 33 and a first buffer circuit 34. The horizontal circuits H1 and H2 are connected by the above-mentioned first connection line CL1, and the horizontal circuits H2 and H3 are connected by the above-mentioned second connection line CL2. Further, in the horizontal circuit H3, the second latch circuit 33 and the first buffer circuit 34 are connected by the above-mentioned third connection line CL3.

The horizontal circuit H1 is connected to wiring that supplies the voltage VSS, VDD1, the clock HCK, and the reset signal xRST to the first shift register 31. The horizontal circuit H2 is connected to a wiring that supplies the voltages VSS and VDD1 to the first latch circuit 32. The horizontal circuit H3 is connected to wiring that supplies the voltages VSS, VDD1 and timing pulses Ds, xDs to the second latch circuit 33 and the first buffer circuit 34. In FIGS. 11 and 12, for simplification, a plurality of wirings connected to the horizontal circuits H1 to H3 are appropriately represented by one line segment.

The second circuit unit 40 shown in FIG. 13 includes a vertical circuit V1 (fourth circuit) and a vertical circuit V2 (fifth circuit). The vertical circuit V1 includes a second shift register 41. The vertical circuit V2 includes the second buffer circuits 42A and 42B and the power supply circuit 43. The vertical circuits V1 and V2 are connected by the above-mentioned fourth connection line CL4. A scanning line GD is connected to the second buffer circuits 42A and 42B, respectively, and a first power supply line LP1 for supplying a power supply voltage VRAM is connected to the power supply circuit 43.

The vertical circuit V1 is connected to a wiring that supplies the voltage VSS, VDD2, the clock VCK, and the reset signal xRST to the second shift register 41. The vertical circuit V2 is connected to wiring that supplies the voltages VSS, VDD1, VDD2 and the enable signals ENB1 and ENB2 to the second buffer circuits 42A and 42B and the power supply circuit 43. In FIGS. 11 and 13, for simplification, a plurality of wirings connected to the vertical circuits V1 and V2 are appropriately represented by one line segment.

As shown in FIG. 12, between the horizontal circuits H1 and H2, two scanning lines GD (first scanning line) and a first power supply line LP1 connected to the second circuit unit 40 are in the first direction X. It is postponed. Between the horizontal circuits H2 and H3, two scanning lines GD (second scanning line) and a first power supply line LP1 connected to the other second circuit unit 40 extend in the first direction X. .. Between the horizontal circuit H3 and the fourth wiring WL4, two scanning lines GD and a first power supply line LP1 connected to another second circuit unit 40 extend in the first direction X. Further, a data bus DBL extends in the first direction X between the horizontal circuits H1 and H2.

The scanning line GD, the first power supply line LP1, and the data bus DBL extending between the horizontal circuits H1 and H2 intersect with the first connecting line CL1 in a plan view. The scanning line GD and the first power supply line LP1 extending between the horizontal circuits H2 and H3 intersect with the second connecting line CL2 in a plan view.

In the example of FIG. 12, the signal line S and the first buffer circuit 34 are connected to each other via a lead wire Sa connected to the first buffer circuit 34. The scanning line GD and the first power supply line LP1 extending between the horizontal circuit H3 and the fourth wiring WL4 intersect with the leader line Sa in a plan view. Further, the wirings WL1 to WL4 also intersect the leader line Sa in a plan view.

The horizontal circuits H1 to H3 are arranged in the second direction Y. Further, the horizontal circuits H1 to H3 are displaced from each other in the first direction X. Specifically, the horizontal circuit H2 is located to the left of the horizontal circuit H3 in the drawing, and the horizontal circuit H1 is located further to the left of the horizontal circuit H2. In the region generated by shifting the horizontal circuits H1 to H3 in this way, each wiring is bent from the first direction X to the second direction Y.

In the example of FIG. 12, the positions of the signal line S and the horizontal circuit H3 (first buffer circuit 34) are deviated in the first direction X. The leader line Sa extends in a direction that intersects both the first direction X and the second direction Y. By shifting the position of the signal line S and the horizontal circuit H3 in this way, the degree of freedom in the circuit layout in the peripheral region SA is further increased. That is, the first circuit unit 30 does not necessarily have to be arranged on the extension line of the signal line S to be connected. Further, in the example of FIG. 12, the second connecting line CL2 also extends in a direction in which it intersects both the first direction X and the second direction Y. If the wiring is tilted like the lead wire Sa or the second connection line CL2, the length of these wirings can be shortened as compared with the case where these wirings are bent along the first direction X and the second direction Y. .. As a result, the space of the peripheral region SA can be utilized more effectively.

In the example of FIG. 13, the vertical circuits V1 and V2 are aligned in the first direction X and deviated from each other in the second direction Y. In the region generated by shifting the vertical circuits V1 and V2 in this way, each wiring is bent from the first direction X to the second direction Y.

The wirings shown in FIGS. 11 to 13 are formed of, for example, a metal material or a conductive material such as ITO on the first layer and the second layer of the first substrate SUB1. An insulating layer is arranged between the first layer and the second layer. One of the two wirings intersecting in FIGS. 11 to 13 is formed in the first layer and the other is formed in the second layer. Therefore, these wires are not electrically connected.

For example, the scanning line GD and the first power supply line LP1 are formed in the first layer. Further, the signal line S, the wirings WL1 to WL4, and other wirings such as the data bus DBL are formed in the second layer. For example, the first connection line CL1 needs to avoid the scanning line GD and the first power supply line LP1 formed in the first layer and the data bus DBL formed in the second layer. In such a case, the portion of the first connection line CL1 that intersects the scanning line GD and the first power supply line LP1 is formed in the second layer, and the portion that intersects the data bus DBL is formed in the first layer. The two parts may be connected by a contact hole provided in the insulating layer.
In addition to the two layers of the first layer and the second layer, more layers may be provided on the first substrate SUB1 and dispersed in these layers to form each wiring.

The leader line Sa includes a first portion Sa1 that intersects the scanning line GD and the first power supply line LP1 extending between the horizontal circuit H3 and the fourth wiring WL4, and a second portion Sa2 that intersects the wirings WL1 to WL4. have. The first portion Sa1 extends from the horizontal circuit H3 to the contact position between the scanning line GD and the fourth wiring WL4. The second portion Sa2 extends from the contact position to the signal line S. The first portion Sa1 is formed in the second layer in order to avoid the scanning line GD and the first power supply line LP1 formed in the first layer. The second portion Sa2 is formed in the first layer in order to avoid the wirings WL1 to WL4 formed in the second layer. The first portion Sa1 and the second portion Sa2 are connected at the above contact positions.

As can be seen from FIG. 12, if a configuration is adopted in which the leader line Sa extends parallel to the second direction Y and is connected to the signal line S at the end, the leader line Sa is the scanning line GD and the first power supply. It passes through the region where the line LP1 and the wirings WL1 to WL4 intersect. The scanning line GD and the first power supply line LP1 and the wirings WL1 to WL4 are formed in different layers in order to avoid electrical contact with each other. Therefore, in order to further pass the leader line Sa through this region, a new layer for forming the leader line Sa is required. On the other hand, if the leader line Sa is inclined as shown in FIG. 12 to avoid the region where the scanning line GD and the first power supply line LP1 intersect with the wirings WL1 to WL4, it is not necessary to provide a new layer. ..

By arranging at least a part of the first driver unit 3 between the second driver unit 4 and the display area DA as in the present embodiment described above, it is possible to prevent the generation of wasted space in the peripheral area SA and narrow the space. It is possible to make a frame.

Further, by dividing the first circuit unit 30 into a plurality of horizontal circuits and passing a scanning line GD, a data bus DBL, or the like between the horizontal circuits, the circuit layout of the peripheral region SA can be made more efficient.

Further, by arranging the horizontal circuits in a staggered manner, the circuit layout of the peripheral region SA can be further made more efficient. The same effect can be obtained by dividing the second circuit unit 40 into a plurality of vertical circuits and arranging the vertical circuits in a staggered manner.
In addition to these, various effects described above can be obtained from the present embodiment.

Although one embodiment of the present invention has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. This novel embodiment can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

For example, in the above embodiment, a digital mode display device is disclosed. However, the circuit layout of the peripheral region SA in the above embodiment can also be applied to an analog mode display device that supplies an analog video signal to the pixel electrode PE via the signal line S to obtain a multi-tone display image. Further, the circuit layout of the peripheral region SA in the above embodiment can be applied to a display device having both digital mode and analog mode functions.

Further, the configurations of the circuit units 30 and 40 disclosed in FIGS. 6 and 7 and the circuit layout of the peripheral region SA disclosed in FIGS. 11 to 13 are merely examples. The circuit elements and wirings shown in these figures can be appropriately reduced, and new circuit elements and wirings can be added.

1 ... Display device, 3 ... 1st driver unit, 4 ... 2nd driver unit, 10 ... Memory, 30 ... 1st circuit unit, 40 ... 2nd circuit unit, DA ... Display area, SA ... Peripheral area, PX ... Pixel , A1 ... 1st region, A2 ... 2nd region, S ... signal line, GD ... scanning line, H1 to H3 ... horizontal circuit, V1, V2 ... vertical circuit, DSP ... dummy pixel, Sa ... leader line.

Claims (15)

A pair of substrates having a display area in which multiple pixels are arranged,
The optical element layer between the pair of substrates and
Pixel electrodes arranged on the pixels and
A switching element connected to the pixel electrode and
A plurality of wirings connected to the switching element and
A first driver unit arranged in a peripheral area around the display area and supplying a signal to each of the plurality of wirings, and a first driver unit.
With
The first driver unit includes a plurality of first circuit units.
The corresponding wiring is connected to each of the plurality of first circuit units.
The first circuit unit includes a first circuit, a second circuit, and a first connection line connecting the first circuit and the second circuit.
The wiring extends in the second direction in the display area.
Said first circuit and said second circuit is arranged in the second direction, are arranged offset from each other in a first direction crossing the second direction,
The plurality of wirings are a plurality of signal lines to which a digital signal is supplied.
Display device. The first circuit includes a first shift register.
The second circuit includes a first latch circuit that stores a digital signal supplied to the signal line.
The display device according to claim 1 . Further, it includes a plurality of scanning lines to which scanning signals for controlling the switching element are supplied.
The scanning line extends in the first direction in the display area.
The display device according to claim 1 or 2 . Further, a second driver unit arranged in the peripheral region and supplying the scanning signal to each of the plurality of scanning lines is provided.
The display device according to claim 3 . In a plan view, the scanning line extends between the first circuit and the second circuit so as to intersect the first connecting line.
The display device according to claim 4 . A memory arranged in the pixel and storing the digital signal,
A data bus for sequentially supplying data indicating the digital signal to be stored in the memory of the plurality of pixels is further provided.
In a plan view, the data bus further extends between the first circuit and the second circuit, intersecting the first connecting line.
The display device according to claim 5 . The first circuit unit further includes a third circuit and a second connection line connecting the first circuit or the second circuit and the third circuit.
The first circuit, the second circuit, and the third circuit are arranged in the second direction and offset from each other in the first direction.
The display device according to any one of claims 1 to 6 . The first circuit includes a first shift register.
The second circuit includes a first latch circuit that stores a digital signal supplied to the signal line.
The third circuit includes a second latch circuit that stores the digital signal output from the first latch circuit.
The display device according to claim 7 . The third circuit further includes a first buffer circuit and a third connection line connecting the second latch circuit and the first buffer circuit.
The first buffer circuit supplies the digital signal stored in the second latch circuit to the signal line.
The display device according to claim 8 . The second driver unit includes a plurality of second circuit units.
The corresponding scanning line is connected to each of the plurality of second circuit units.
The second circuit unit includes a fourth circuit, a fifth circuit, and a fourth connection line connecting the fourth circuit and the fifth circuit.
The signal line extends in the second direction in the display area.
The fourth circuit and the fifth circuit are arranged so as to be offset from each other in the second direction.
The display device according to claim 4 . Further provided with a lead wire connecting the wiring and the first circuit unit,
The wiring extends in the second direction in the display area.
The leader line extends in a direction that intersects both the first direction and the second direction in the peripheral region.
The display device according to any one of claims 1 to 10 . The second driver unit includes a plurality of second circuit units.
The peripheral region includes a first region in which the first circuit unit and the second circuit unit are formed, and a second region in which the second circuit unit is formed and the first circuit unit is not formed. And
The distance between the second circuit unit and the display region in the first region is the first distance.
The distance between the second circuit unit and the display area in the second region is the second distance.
The second distance is smaller than the first distance.
The display device according to any one of claims 4 to 6 . With more dummy pixels that do not display images
The first circuit unit is connected to the plurality of wirings, and the number of dummy pixels connected to each wiring is different.
The display device according to any one of claims 1 to 12 . A pair of substrates having a display area in which multiple pixels are arranged,
The optical element layer between the pair of substrates and
Pixel electrodes arranged on the pixels and
A switching element connected to the pixel electrode and
A plurality of wirings connected to the switching element and
A first driver unit arranged in a peripheral area around the display area and supplying a signal to each of the plurality of wirings, and a first driver unit.
With
The first driver unit includes a plurality of first circuit units.
The corresponding wiring is connected to each of the plurality of first circuit units.
The first circuit unit includes a first circuit, a second circuit, and a first connection line connecting the first circuit and the second circuit.
The wiring extends in the second direction in the display area.
The first circuit and the second circuit are arranged in the second direction and offset from each other in the first direction intersecting the second direction.
Further provided with a lead wire connecting the wiring and the first circuit unit,
The leader line extends in a direction that intersects both the first direction and the second direction in the peripheral region.
Display device. A pair of substrates having a display area in which multiple pixels are arranged,
The optical element layer between the pair of substrates and
Pixel electrodes arranged on the pixels and
A switching element connected to the pixel electrode and
A plurality of wirings connected to the switching element and
A first driver unit arranged in a peripheral area around the display area and supplying a signal to each of the plurality of wirings, and a first driver unit.
With
The first driver unit includes a plurality of first circuit units.
The corresponding wiring is connected to each of the plurality of first circuit units.
The first circuit unit includes a first circuit, a second circuit, and a first connection line connecting the first circuit and the second circuit.
The wiring extends in the second direction in the display area.
The first circuit and the second circuit are arranged in the second direction and offset from each other in the first direction intersecting the second direction.
With more dummy pixels that do not display images
The first circuit unit is connected to the plurality of wirings, and the number of dummy pixels connected to each wiring is different.
Display device.

Images