JP6829879B2 - Linear amplifier and power converter - Google Patents

Description

The present invention relates to a linear amplifier that linearly amplifies an input signal and outputs it from an output end, and a power conversion device that converts a voltage of a DC power supply into an AC voltage or a DC voltage according to the input signal.

In the technical field of power electronics that converts voltage, current, frequency, DC AC, etc. using a semiconductor power device, power conversion using a switching operation of a semiconductor power device is known. Power conversion using this switching has a problem that, for example, a high efficiency of 95% conversion efficiency can be obtained, but the output voltage waveform becomes pulsed, and electromagnetic noise and harmonics are generated.

A linear amplifier circuit that outputs an arbitrary voltage waveform by a linear operation such as a class B amplifier is known for power conversion by a switching operation. Since the amplification of the linear amplifier circuit is based on linear operation, the output voltage waveform can be any linear waveform, but the loss generated in the element of the semiconductor power device is large, the theoretical efficiency is only 78.5%, and the conversion efficiency is high. There is a problem that is low.

A diode clamp type linear amplifier circuit (DCLA) has been proposed as a device for improving the conversion efficiency of the linear amplifier circuit. This diode clamp type linear amplifier circuit basically operates in the same manner as the linear amplifier circuit such as the class B amplifier described above, but by using multiple semiconductor power devices in series, the voltage applied to each element is applied. Efficiency is improved by reducing.

The diode clamp type linear amplifier circuit reduces power loss by using only some of the elements of the semiconductor power device in series in the linear region and switching the other elements in the saturation region. In this configuration, as the number of devices in series is increased, the power loss can be further reduced (for example, Patent Document 1 and Non-Patent Document 1).

FIG. 21 shows a configuration example of a diode clamp type linear amplifier circuit. In FIG. 21, the diode clamp type linear amplifier circuit 101 is a series circuit 102 in which a plurality of semiconductor power devices (Q1 to Q4, Q5 to Q8) are connected in series, and each semiconductor power device (Q1 to Q4, Q5 to Q8). A plurality of diode clamp circuits 103 connected to the above are provided.

A DC voltage is applied to the series circuit 102 by the DC power supply 111, and a stepwise voltage is applied to each semiconductor power device (Q1 to Q4, Q5 to Q8) by each diode clamp circuit 103. Each semiconductor power device (Q1 to Q4, Q5 to Q8) linearly amplifies the input signal in each linear region defined according to the voltage applied by each diode clamp circuit 103, and outputs the output current to the load 112.

International release WO2012 / 066839

"High-efficiency linear amplifier circuit using diode clamp circuit" IEEJ Trans.IA, Vol.127, No.1, 2007, p9-16

Since the diode clamp type linear amplifier circuit performs linear operation, the output voltage waveform can be formed into an arbitrary waveform, and high efficiency can be achieved by increasing the number of elements in series of the semiconductor power device. On the other hand, when the output current flows through the clamp diode, power loss occurs in this clamp diode. Therefore, there is a limit to the efficiency improvement due to the power loss generated in the clamp diode other than the power loss generated in the linear operation.

FIG. 22 is a diagram for explaining the power loss generated in the clamp diode. FIG. 22A shows an example of the output voltage of the diode clamp type linear amplifier circuit, and FIG. 22B is a diagram for explaining the voltage state of the diode clamp type linear amplifier circuit. In FIG. 22B, in the power supply voltage E of the DC power supply, the applied voltage on the positive electrode side is E / 2, and the applied voltage on the negative electrode side is −E / 2.

In FIG. 22B, since a voltage obtained by subtracting the voltage drop due to the diode from the applied voltage E / 2 is applied to each element of the semiconductor power device, the voltage used for the output voltage is larger than the applied voltage E / 2. It becomes a low voltage. Therefore, the voltage drop due to the diode causes a power loss.

Therefore, since the diode clamp type linear amplifier circuit (DCLA) conventionally proposed operates by using the clamp diode, there is a problem that the loss is large and the efficiency improvement is limited.

Further, a plurality of DC voltages are required at the source end of the element of each semiconductor power device because a different DC voltage is applied to each element via the clamp diode. Therefore, since the number of DC voltages corresponding to the number of elements in series of the semiconductor power device is required, there is a problem that the configuration of the DC power supply becomes complicated, and there is only one operation mode that can be taken to output an arbitrary voltage. Therefore, there is a problem that the expandability of the gate control is poor.

The present invention includes a mode of a linear amplifier that linearly amplifies an input signal and outputs it from an output end, and a mode of a power conversion device that converts direct current into alternating current or direct current, including a linear amplifier.

(Aspect of linear amplifier)
In the linear amplifier of the present invention, a flying capacitor is used instead of the clamp diode provided in the diode clamp type linear amplifier circuit (DCLA) as a configuration for setting the reference voltage of each element of a plurality of semiconductor power devices constituting the series circuit. It is a configuration.

The linear amplifier (FCLA: Flying-Capacitor Linear Amplifier) provided with the flying capacitor of the present invention sets a reference voltage for each element of a plurality of semiconductor power devices constituting a series circuit by setting the charging voltage of the flying capacitor. It eliminates the power loss caused by the diode generated in the diode clamp type linear amplifier circuit and improves the conversion efficiency.

The linear amplifier of the present invention
(A) A series circuit in which two or more MOSFETs are connected in series on at least one pole side with respect to the output end of the linear amplifier.
(B) A plurality of flying capacitors that hold the potentials at the source ends of each MOSFET in the series circuit at different potentials, and
(C) An input circuit for inputting an input signal is provided at the gate end of each MOSFET.

In the linear amplifier, the series circuit is connected between the power supply side input end connected to the DC power supply and the output end of the linear amplifier, and is a flying capacitor for the source end of each MOSFET connected in series to form the series circuit. Is connected, and an input circuit is connected to the gate end of each MOSFET.

In each MOSFET of the series circuit, a reference voltage is set by applying a respective voltage from each flying capacitor and a power source to the source end of the MOSFET, and the gate potential or drain potential of each MOSFET is determined. The operating state (operating area) of each MOSFET changes depending on the state of the voltage of the input signal with respect to the potential of each source terminal determined by the flying capacitor and the power supply voltage, and the MOSFET is located at the gate end. It operates in the linear region, saturation region, and cutoff region based on the relationship with the voltage of the applied input signal. In the operating state in the saturation region or cutoff region of the MOSFET in the series circuit, the current path flowing through the series circuit of the linear amplifier is switched by the MOSFET that switches to the on state or the off state depending on the voltage of the input signal, and in the linear region in the current path. Linear amplification is performed by the operating MOSFET.

In the MOSFET in the current path, the MOSFET that performs linear operation is a MOSFET in which the drain potential of the MOSFET is the power supply voltage, or the reference voltage set by the flying capacitor is the upper limit of each division when the input signal is divided into a plurality of regions. And a MOSFET that falls within the lower limit. In the MOSFET of the series circuit, only one MOSFET performs linear operation for one input signal, and the other MOSFET operates in the saturation region or the cutoff region.

Further, among the plurality of MOSFETs in the series circuit, the drain-source voltage of the MOSFET that is turned off in the cutoff region is divided by the flying capacitor.

The reference voltage set at the source end of each MOSFET in the series circuit is set in the direction of applying the voltage in the positive direction from the ground voltage in the series circuit or in the direction of decreasing the voltage in the negative direction, and a plurality of MOSFETs constituting the series circuit. Of these, only one MOSFET operates in the linear region and the other MOSFET operates in the saturation region or cutoff region. The MOSFETs operating in the linear region are sequentially switched according to the change in the voltage of the input signal based on the relationship between the voltage of the input signal and the reference voltage of each MOSFET. By sequentially switching the MOSFETs operating in the linear region, the range of linear amplification in the input signal is sequentially switched, and linear amplification is performed for the entire range of the input signal.

Therefore, in the series circuit of the linear amplifier, among the plurality of MOSFETs constituting the series circuit, the MOSFETs operating in the linear region are sequentially switched according to the voltage change of the input signal, so that each voltage of the input signal divided into a plurality of voltages is sequentially switched. Perform linear amplification in the range.

The number of voltage ranges for linear amplification is determined by the number of reference voltages and is determined by the number of flying capacitors connected to the source end of the MOSFET. Therefore, by increasing the number of flying capacitors and the number of reference voltages, the voltage range of the linear amplification performed by division can be set to a small voltage range.

In the linear amplifier of the present invention, the MOSFET that operates linearly operates as a source follower and operates as a current amplifier circuit having a voltage amplification factor of 1.

(Flying capacitor)
Flying capacitors
(1) A function of setting the voltage at the source end of the MOSFET to each reference voltage for each MOSFET (2) A function of setting the voltage between the drain and source of the MOSFET is performed.

(1: Voltage setting at the source end)
Depending on the voltage setting at the source end, the MOSFET that is in the amplification operation or conduction state (on state) and the MOSFET that is in the non-conduction state (off state) are operated separately from the plurality of MOSFETs included in the series circuit. When the voltage set at the source end is low with respect to the voltage range of the input signal, the MOSFET is in a linear amplification or conducting state, and when the voltage set at the source end is high, the MOSFET is in a non-conducting state. ..

The reference voltage set at the source end of each MOSFET in the series circuit is set in the direction in which the voltage is applied in the positive direction from the ground voltage in the series circuit or in the direction in which the voltage is decreased in the negative direction. The setting of this reference voltage is determined by the holding voltage of each connected flying capacitor and the power supply voltage. The holding voltage of this flying capacitor can be held at a predetermined voltage by an insulated power supply or a voltage balance circuit provided in each flying capacitor.

(2: Voltage setting between drain and source)
By setting the voltage between the drain and source of the MOSFET, the DC voltage is linearly amplified according to the voltage change of the input signal based on the gate / output voltage characteristics in the linear region of the MOSFET. When the gate potential of the MOSFET is higher than the source potential of the MOSFET, it operates in the saturation region or the linear region, and when the gate potential is lower than the source potential of the MOSFET, it operates in the cutoff region.

One MOSFET operating in the linear region is selected from a plurality of MOSFETs in the series circuit based on the relationship with the voltage range of the input signal, and the selected MOSFETs are sequentially transferred according to the voltage change of the input signal.

(Series circuit)
The first aspect of the series circuit of the present invention includes a positive side series circuit on the positive electrode side and a negative side series circuit on the negative electrode side with respect to the output end of the linear amplifier.

The MOSFET included in the positive series circuit is an n-MOSFET, and the MOSFET included in the negative series circuit is a p-MOSFET. In this first embodiment, the voltage of each flying capacitor is a set voltage within the voltage of the DC power supply, and each flying capacitor is between the ends of both sources between the n-MOSFET and the p-MOSFET applied by the flying capacitor. The voltage between the source ends of the MOSFET is held at the set voltage. The output of the positive series circuit is a positive voltage, and the output of the negative series circuit is a negative voltage.

A third form of the series circuit of the present invention includes a MOSFET series circuit on the positive side series circuit and a diode series circuit in which a diode is connected in series on the negative side with respect to the output end of the linear amplifier, or the positive side. A diode series circuit formed by connecting a diode in series to the series circuit, and a MOSFET series circuit on the negative side. In each of the series circuits, the MOSFET included in the positive series circuit is an n-MOSFET, and the MOSFET included in the negative series circuit is a p-MOSFET. The MOSFET series circuit on the positive electrode side outputs a positive voltage, and the MOSFET series circuit on the negative electrode side outputs a negative voltage.

(Input circuit)
In the first form of the series circuit, the first form of the input circuit includes a connection circuit for connecting the gate ends of the plurality of MOSFETs, and inputs a common gate voltage to all the gate ends.

Further, the connection circuit of the input circuit includes a gate resistor for overcurrent prevention connected between the gate end and a Zener diode for overvoltage prevention between the gate and source connected between the gate end and the source end. It can be configured.

Further, in the first form of the series circuit, in the second form of the input circuit, a gate drive circuit is individually connected to each gate end of the plurality of MOSFETs, and an individual gate voltage is input to each gate end.

(Aspect of power converter)
The mode of the power conversion device of the present invention includes the linear amplifier and the DC power supply of the present invention, and outputs the DC voltage by converting the DC voltage into an AC voltage or a DC voltage by using the output end of the linear amplifier as the output end of the power conversion device. ..

The DC power supply is connected between the high voltage side of the positive series circuit of the linear amplifier and the ground potential, and the low voltage side of the negative series circuit of the linear amplifier and the ground potential. A configuration provided with two DC power supplies of the negative side DC power supply, or the low voltage side of the negative side series circuit of the linear amplifier is the ground potential, and this ground potential and the high voltage side of the positive side series circuit of the linear amplifier It is a configuration including one DC power supply connected between.

A mode of the power converter of the present invention comprises a full bridge inverter connected between the output end of a linear amplifier and the output end of a power converter. The full bridge inverter inverts either the output of the MOSFET series circuit on the positive electrode side or the output of the MOSFET series circuit on the negative electrode side to output alternating current.

According to the embodiment of the present application, the expandability of the gate control can be enhanced with respect to the change in the number of series elements.

According to the embodiment of the present application, by using a flying capacitor instead of a clamp diode as an element for applying a different DC voltage to each MOSFET, a complicated DC power supply for supplying a DC voltage according to the number of MOSFETs can be obtained. It becomes unnecessary, the requirement for the configuration of the DC power supply can be reduced, the operation can be performed with the DC power supply having a simple configuration, and the expandability of the gate control with respect to the increase or decrease in the number of elements of the MOSFET can be enhanced.

According to the embodiment of the present application, the voltage balance of the flying capacitor can be realized and the power loss of each MOSFET can be equalized by providing the gate drive circuit individually for the gate of each MOSFET.

As described above, according to the present invention, it is possible to reduce the power loss caused by using the clamp diode.

It is a figure for demonstrating the configuration example of the linear amplifier including the n series circuit which connected n MOSFETs of this invention in series. It is a figure for demonstrating another configuration example of the n series circuit which connected n MOSFETs of this invention in series. It is a figure for demonstrating the improvement of conversion efficiency by the linear amplifier of this invention. It is a figure for demonstrating one configuration example of the 2 series circuit of this invention. It is a figure for demonstrating the operation example of the linear amplifier of the 2 series circuit of this invention. It is a signal diagram for demonstrating the operation example of the linear amplifier of the 2 series circuit of this invention. It is a figure for demonstrating the operation example of the linear amplifier of the 2 series circuit of this invention. It is a figure for demonstrating one configuration example of the 4 series circuit of this invention. It is a figure for demonstrating the operation example of the linear amplifier of 4 series circuit of this invention. It is a signal diagram for demonstrating the operation example of the linear amplifier of 4 series circuit of this invention. It is a figure for demonstrating the operation example of the linear amplifier of 4 series circuit of this invention. It is a figure for demonstrating the operation example of the linear amplifier of 4 series circuit of this invention. It is a figure for demonstrating the structural example of the 3 series circuit of this invention. It is a figure for demonstrating one configuration example of the 6 series circuit of this invention. It is a signal diagram for demonstrating the operation example of the linear amplifier of the 6 series circuit of this invention. It is a figure for demonstrating the operation example of the linear amplifier of the 6 series circuit of this invention. It is a figure for demonstrating the structural example of the 5 series circuit of this invention. It is a figure for demonstrating another structural example of the linear amplifier of this invention. It is a figure for demonstrating the conversion efficiency by an Example of the linear amplifier of this invention. It is a graph which shows the difference of the theoretical conversion efficiency of a linear amplifier FCLA and a linear amplifier DCLA with respect to the series number n. It is a figure for demonstrating one configuration example of a diode clamp type linear amplifier circuit. It is a figure for demonstrating the power loss which occurs in a clamp diode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In a power conversion device including a linear amplifier and a linear amplifier, a configuration example of a linear amplifier including an n-series circuit in which n MOSFETs are connected in series will be described with reference to FIGS. 1 to 3, and FIGS. 4 to 7 are shown. A configuration example of a linear amplifier including a two-series circuit in which two MOSFETs are connected in series will be described, and a three-series circuit and a four-series circuit in which three or four MOSFETs are connected in series will be described with reference to FIGS. 8 to 13. A configuration example of a linear amplifier including the above will be described, and FIGS. 14 to 17 will be used to describe a configuration example of a linear amplifier including a 5-series circuit and a 6-series circuit in which 5 or 6 MOSFETs are connected in series. Will be described with reference to a configuration example in which a series circuit of MOSFETs is provided only on one side of the positive electrode side or the negative electrode side. In addition, the conversion efficiency according to the embodiment of the linear amplifier of the present invention will be described with reference to FIGS. 19 and 20.

(Composition with n series circuit)
FIG. 1 is a diagram for explaining a configuration example of a linear amplifier including an n-series circuit in which n MOSFETs are connected in series, FIG. 1 (a) shows a circuit configuration example, and FIG. 1 (b) shows an output voltage. The relationship between and a MOSFET that operates linearly is shown.

The linear amplifier 1 shown in FIG. 1A includes a series circuit 2 (2A, 2B) in which a plurality of MOSFETs (Q1, Q2, ..., Qk, ..., Qn, Qnp, ..., Q2p, Q1p) are connected in series. A plurality of flying capacitors 3 (C1, C2, ..., Cn-1) that hold the potential at the source end of each MOSFET at different potentials, and an input circuit 4 that inputs an input signal bin to the gate end of each MOSFET are provided. .. When the ground potential is used as a reference, the reference voltage at the source end is determined by the voltage generated by the flying capacitor and the power supply voltage. The input circuit 4 shown in FIG. 1A is a configuration example in which a common input signal bin is input to each MOSFET (Q1, Q2, ..., Qk, ..., Qn, Qnp, ..., Q2p, Q1p). .. The input circuit 4 is not limited to this configuration, and may be configured to individually input an input signal to the gate end of each MOSFET.

The series circuit 2 (2A, 2B) is connected between the DC power supply 11 (11A, 11B) and the output terminal 9out of the linear amplifier 1.

The series circuit 2 (2A, 2B) includes a positive side series circuit 2A on the positive electrode side and a negative side series circuit 2B on the negative strong side with respect to the output terminal 9out of the linear amplifier 1. The MOSFETs (Q1, Q2, ..., Qk, ..., Qn) included in the positive series circuit 2A are n-MOSFETs, and the MOSFETs (Qnp, ..., Qkp, Q2p, Q1p) included in the negative series circuit 2B are p- It is a MOSFET. The number n of n-MOSFETs (Q1, Q2, ..., Qk, ..., Qn) included in the positive series circuit 2A, and the p-MOSFETs (Qnp, ..., Qkp, Q2p, Q1p) included in the negative series circuit 2B. The number n can be any number of two or more, and in the same linear amplifier 1, the number n of each MOSFET included in the positive side series circuit 2A and the negative side series circuit 2B is the same number.

In the positive side series circuit 2A, the drain end of the n-MOSFET (Q1) is connected to the positive electrode side of the DC power supply E1, and the source end of the n-MOSFET (Q1) is connected to the drain end of the adjacent n-MOSFET (Q2). Will be done. Similarly, in two adjacent n-MOSFETs, the source end of the n-MOSFET on the positive electrode side of the DC power supply is connected to the drain end of the n-MOSFET on the output end 9out side. The source end of the n-MOSFET (Qn) closest to the output end 9out side is connected to the output end 9out, and the output end 9out is connected to the load 12.

Similarly, in the negative side series circuit 2B, the drain end of the p-MOSFET (Q1p) is connected to the negative electrode side of the DC power supply E2, and the source end of the p-MOSFET (Q1p) is the drain of the adjacent p-MOSFET (Q2p). Connected to the end. Similarly, in two adjacent p-MOSFETs, the source end of the p-MOSFET on the negative electrode side of the DC power supply is connected to the drain end of the p-MOSFET on the output end 9out side. The p-MOSFET (Qnp) closest to the output end 9out side is connected to the output end 9out, and the output end 9out is connected to the load 12. The positive side series circuit 2A outputs a positive voltage, and the negative side series circuit 2B outputs a negative voltage. Note that p-MOSFET (Qkp) is not shown in FIG.

The flying capacitors 3 (C1, C2, ..., Cn-1) are connected between the source ends of both MOSFETs between the n-MOSFET and the p-MOSFET applied by each flying capacitor 3, and between the source ends of each MOSFET. Holds the voltage of.

The flying capacitor 3 (C1) is connected between the source end of the n-MOSFET (Q1) and the source end of the p-MOSFET (Q1p), and the flying capacitor 3 (C2) is connected to the source end of the n-MOSFET (Q2). It is connected between the source ends of the p-MOSFET (Q2p). The other flying capacitors 3 (C3 to Cn-1) are also connected between the source end of the n-MOSFET (Q3 to Qn-1) and the source end of the p-MOSFET (Q3p to Qn-1p). The source end of the n-MOSFET (Qn) is connected to the output end 9out, and the source end of the p-MOSFET (Qnp) is connected to the output end 9out.

The flying capacitor 3 (C1, C2, ..., Cn-1) is held at a specified voltage by charging with an isolated power supply or a voltage balance circuit. For example, in a series circuit composed of n MOSFETs connected in series, when the voltage of the DC power supply is voltage E, the kth flying capacitor 3 (Ck) is set to (nk) E / n. The voltage (n-k) E / n is held at the source ends of the n-MOSFET (Qk) and the p-MOSFET (Qk). In this example, the voltage E of the DC power supply is used as the reference voltage, and the voltage width obtained by dividing this voltage into 1 / n is used as the holding voltage width of each flying capacitor 3, but the holding voltage width of each flying capacitor 3 is used. Is not limited to the same voltage width, and can be any voltage width.

An insulated power supply 5 or a voltage balance circuit (not shown) is connected to each of the flying capacitors 3 (C1, C2, ..., Cn-1), and each flying capacitor 3 (C1, C2) is connected by this insulated power supply or voltage balance circuit. , ..., Cn-1) voltage is held at the set voltage. The voltage balance circuit is an additional circuit that holds the voltage of the flying capacitor at a predetermined voltage, and has a circuit configuration that does not require insulation.

In the configuration shown in FIG. 1, the DC power supply 11 has a configuration in which a positive DC power supply 11A having a voltage E1 and a negative DC power supply 11B having a voltage E2 are connected in series, and the connection points of both DC power supplies are grounded. According to this configuration, the voltage E1 of the positive DC power supply 11A is applied to the positive series circuit 2A, and the voltage E2 of the negative DC power supply 11B is applied to the negative series circuit 2B. The voltage E1 and the voltage E2 can be arbitrary voltages, and can be different or the same voltage from each other.

Each voltage E11, E12, ..., E1n-2, E1n-1 of each C1, C2, ..., Cn-2, Cn-1 of the flying capacitor 3 is a voltage obtained by dividing the voltage 2E1 which is twice the power supply voltage E1. Yes, these voltages are set with the relationship of E11> E12>, ... E1n-2> E1n-1.

In each n-MOSFET of the positive series circuit 2A, the potential at the source end of each n-MOSFET (Q) is set by the voltage of the flying capacitor 3 and the power supply voltage, and the drain-source end voltage is the power supply voltage and flying. It is set by the voltage difference from the voltage of the capacitor or the voltage difference of the adjacent flying capacitor. Further, when the ground potential is used as a reference, the potential at the source end is determined not only by the voltage value held by the flying capacitor but also by the voltage value of the DC power supply. For example, the voltage value of the negative DC power supply is related to the source potential of the MOSFET of the positive series circuit, and the voltage value of the positive DC power supply is related to the source potential of the MOSFET of the negative series circuit.

In the circuit configuration of FIG. 1, the voltage at the source end of the n-MOSFET (Q1) is set by the flying capacitor 3 (C1) based on the voltage E11 and the negative DC power supply E2, and the drain-source voltage is the positive DC. (E1- (E11-E2)) is applied by the voltage E1 of the power supply 11A, the voltage E11 of the flying capacitor 3 (C1), and the voltage E2 of the negative DC power supply 11B. The reference voltage at the source end of the n-MOSFET (Q2) is set by the flying capacitor 3 (C2) based on the voltage E12 and the negative DC power supply E2, and the drain-source voltage is the voltage E11 of the flying capacitor 3 (C1). And the voltage difference (E11-E12) from the voltage E12 of the flying capacitor 3 (C2) is applied. The reference voltage at the source end of the n-MOSFET (Q3) to n-MOSFET (Qn-1) and the drain-source voltage are also set in the same manner.

Since the source end of the n-MOSFET (Qn) is an output terminal, when the output voltage is the ground voltage "0" and no current flows through the load, the drain-source voltage is the flying capacitor 3 (Cn-1). The voltage difference E1n-1 between the voltage E1n-1 and the ground voltage is applied.

On the other hand, in each p-MOSFET of the negative side series circuit 2B, the voltage at the source end of each p-MOSFET (Q) is on the positive side with the voltage of the flying capacitor 3 as in each n-MOSFET of the positive side series circuit 2A. It is set based on the DC power supply, and the drain-source end-to-end voltage is set by the voltage difference between the power supply voltage and the voltage of the flying capacitor, or the voltage difference of the adjacent flying capacitor.

The input circuit 4 is a gate end of each n-MOSFET (Q1, Q2, ..., Qk, ..., Qn) of the positive series circuit 2A, and each p-MOSFET (Q1p, Q2p, ...) Of the negative series circuit 2B. , Qkp, ..., Qnp) The input signal input from the input end 9in, which is configured by connecting each gate end to the input end 9in via the gate resistor 6, is on the positive side via each gate resistor 6. It is input in common to each MOSFET of the series circuit 2A and the series circuit 2B on the negative side. The gate resistor 6 prevents an overcurrent to the gate end. Further, in each MOSFET, a Zener diode 7 for preventing overvoltage between the gate and the source is provided between the gate end and the source end.

Each n-MOSFET (Q1, Q2, ..., Qk, ..., Qn) of the positive series circuit 2A and each p-MOSFET (Q1p, Q2p, ..., Qkp, ..., Qnp) of the negative series circuit 2B are It operates in a conductive or non-conducting state based on the relationship between the voltage set at the source end of the MOSFET and the voltage change of the input signal Vin input to the input terminal 9in, and the voltage between the drain and source of each MOSFET and the voltage between the drain and source of each MOSFET. It operates in a linear region, a saturation region, or a cutoff region based on the relationship with the voltage change of the input signal Vin input to the input terminal 9in.

In the operation of this MOSFET, only one MOSFET among the MOSFETs included in the series circuit 2 operates in the linear region to linearly amplify the input signal vin, and the remaining MOSFETs operate in the saturation region or the cutoff region in the on-state or It is turned off and a current path is formed between the DC power supply 11 and the load 12.

For example, when the voltage of the input signal Vin is in the voltage range higher than the voltage set at the source end of the n-MOSFET (Q1), the n-MOSFET (Q1) is the power supply voltage in the linear region or the saturation region. The n-MOSFET (Q2, ..., Qk, ..., Qn) and p-MOSFET (Q1p, Q2p, ..., Qkp, ..., Qnp) operate in the saturation region or the cutoff region, and operate in the operation mode to output. The n-MOSFETs (Q2, ..., Qk, ..., Qn) are turned on, and the p-MOSFETs (Q1p, Q2p, ..., Qkp, ..., Qnp) are turned off. In this operating state, a current path is formed from the positive DC power supply 11A to the load 12 via the positive series circuit 2A.

In this current path, the n-MOSFET (Q1) operates in the linear region to linearly amplify the input signal bin. The region A1 in FIG. 1B shows the state of linear amplification by this n-MOSFET (Q1).

The voltage of the input signal Vin is higher than the voltage set at the source end of the n-MOSFET (Qk), and is lower than the voltage set at the source end of the n-MOSFET (Qk-1) or n-. When in the voltage range lower than the turn-on threshold of the gate end of the MOSFET (Qk), the n-MOSFET (Qk) operates in the linear region and the n-MOSFET (Qk + 1, ..., Qn) ) And p-MOSFET (Q1p, Q2p, ..., Qkp, ..., Qnp) operate in the saturation region or cutoff region, n-MOSFET (Qk + 1, ..., Qn) is turned on, and p-MOSFET (Q1p) , Q2p, ..., Qnp) are turned off. In this operating state, a current path is formed from the negative DC power supply 11B to the load 12 via a part of the negative side series circuit 2B and a part of the positive side series circuit 2A. In this current path, the n-MOSFET (Qk) operates in the linear region to linearly amplify the input signal bin. The region Ak in FIG. 1B shows the state of linear amplification by this n-MOSFET (Qk).

Here, when the voltage held by the flying capacitor is (n-k) E / n and the MOSFET to which (n-k) E / n is applied to the source end performs linear operation, the MOSFET that performs this linear operation A current path is formed in which the drain potential of is kE / n. In this current path, the maximum value of the voltage drop between the drain and source of each MOSFET is E / n.

Further, as the MOSFET in the off state, since the drain-source voltage is divided into 1 / n of the power supply voltage E by the flying capacitor, a MOSFET having a withstand voltage of 1 / n can be used.

FIG. 2 is a diagram for explaining another configuration example of an n-series circuit in which n MOSFETs are connected in series. The configuration example shown in FIG. 2 includes an input circuit 4B instead of the input circuit 4A of the configuration example shown in FIG. The input circuit 4B is provided for each gate end of the n-MOSFET (Q1, Q2, ..., Qk, ..., Qn) and p-MOSFET (Q1p, Q2p, ..., Qkp, ..., Qnp) of the positive series circuit 2A. A separate gate drive circuit (G, D) 8 is provided. Each gate drive circuit 8 inputs a different input signal bin to the gate end of each connected MOSFET. Each gate drive circuit (G, D) 8 inputs to each MOSFET an input signal bin that differs depending on each individual control signal sent from an external control controller (not shown).

By connecting the gate drive circuit 8 to the gate end of each MOSFET, it is possible to control the voltage balance of the flying capacitor and control to equalize the loss in each MOSFET.

FIG. 3 is a diagram for explaining the improvement of conversion efficiency by the linear amplifier of the present invention. FIG. 3 illustrates the output voltage between a diode-clamped linear amplifier (DCLA) using a conventional diode and a linear amplifier (FCLA: Flying-Capacitor Linear Amplifier) equipped with a flying capacitor of the present invention. Is shown.

In the case of DCLA, since a diode exists in the current path of the output, the voltage drops due to the on-voltage drop of this diode. On the other hand, according to the linear amplifier (FCLA) provided with the flying capacitor of the present invention, the loss due to the diode does not occur, so that high conversion efficiency can be obtained as compared with DCLA.

(Composition with 2 series circuits)
Next, a configuration example and an operation example of the two series circuit in which the series circuit of one polarity is composed of two MOSFETs will be described with reference to FIGS. 4 to 7. FIG. 4 shows a configuration example of a two-series circuit.

In the configuration example shown in FIG. 4, the linear amplifier 1A is a positive series circuit 2A in which two n-MOSFETs (Q1 and Q2) are connected in series, and two p-MOSFETs (Q3 and Q4) are connected in series. The negative side series circuit 2B is provided, and the flying capacitor 3 (C0) is connected between the source end of the n-MOSFET (Q1) and the source end of the p-MOSFET (Q4), and the n-MOSFET (Q1, Q2) is connected. ) And p-MOSFET (Q3, Q4), an input circuit 4A is connected to the gate end, and a common input signal bin is input.

Further, the positive electrode of the positive DC power supply 11A is connected to the drain end of the n-MOSFET (Q1) and a voltage E / 2 is applied, and the negative electrode of the negative DC power supply 11B is applied to the drain end of the p-MOSFET (Q4). Is connected and the voltage E / 2 is applied in the negative direction.

5 (a) and 5 (b) show an operation example of the linear amplifier 1A of the two series circuit shown in FIG. 4, and FIG. 5 (c) shows the input signal bin. In this operation example, the power supply voltage is set to E / 2 on the positive electrode side and the negative electrode side, respectively, and the holding voltage of the flying capacitor C0 is set to E / 2. Further, FIG. 6 (a) shows an input signal vin, FIG. 6 (b) shows an output voltage vout, and FIGS. 6 (c) and 6 (d) show n-MOSFET (Q1) and p-MOSFET (Q4). The drain-source voltages VQ1 and VQ4 are shown, and FIGS. 6 (e) and 6 (f) show the drain-source voltages VQ2 and VQ3 of the n-MOSFET (Q2) and p-MOSFET (Q3).

The operation example shown in FIG. 5 (a) shows the operation when the input signal bin is in the range of the reference numeral A in FIGS. 5 (c) and 6 (a), and the positive series circuit 2A serves as the current path. Indicates the state. In the range where the input signal bin is 0 <vin <E / 2, the n-MOSFET (Q2) is in the on state (FIG. 6 (e)), the p-MOSFET (Q3, Q4) is in the off state, and the n-MOSFET (Q1) is in the off state. ) Operates in the linear region (FIG. 6 (c)). As a result, a current path is formed from the DC power supply to the load via the positive series circuit 2A, and the input signal bin (FIG. 6 (a)) is linearly amplified by the n-MOSFET (Q1) (FIG. 6 (b). )).

On the other hand, in the operation example shown in FIG. 5 (b), the input signal bin is the operation in the range of the reference numeral B in FIGS. 5 (c) and 6 (a), and the negative series circuit 2B serves as the current path. Is shown. When the input signal bin is in the range of -E / 2 <vin <0, the n-MOSFET (Q1, Q2) is in the off state (FIGS. 6 (c) and 6 (e)), and the p-MOSFET (Q3) is on. In the state (FIG. 6 (f)), the p-MOSFET (Q4) operates in the linear region (FIG. 6 (d)). As a result, a current path is formed from the load to the DC power supply from the negative electrode side via the negative side series circuit 2B, and the input signal bin is linearly amplified by the p-MOSFET (Q4).

The above operation example shows a case where the load is a pure resistance, and the direction of the current flowing through the current path is such that when the input signal bin is a positive voltage, a positive current flowing through the positive series circuit 2A as the current path. When the input signal bin is a negative voltage, a negative current flows through the negative series circuit 2B as the current path. FIG. 5D schematically shows the current state when the load is a pure resistance.

On the other hand, when the load has an inductance component or a capacitance component instead of a pure resistance, the path is via a flying capacitor. FIG. 7B shows a current path that becomes a positive current output at the negative voltage input via the negative side series circuit 2B, the flying capacitor Cc, and the positive side series circuit 2A. Note that FIG. 7B shows a case where the voltage value of the flying capacitor is different from the example shown in FIG. 5, and is given here as an example of a current path passing through the flying capacitor.

A load having an inductance component or a capacitance component operates in a different current path due to a phase difference between the voltage and the current, and when the input signal bin is a positive voltage, the negative current with the negative series circuit 2B as the current path. Is flowing, and the current path is not limited to the operation in which the positive current flows through the positive series circuit 2A as the current path when the input signal bin is a negative voltage, but the current path is passed through the positive series circuit 2A when the input signal bin is a positive voltage. In some cases, a positive current flows and a negative current flows through the negative series circuit 2B as a current path when the input signal bin is a negative voltage.

FIG. 5 (e) shows the current state when the load is inductive. Since a delayed current is generated by the inductive load, the negative current is switched to the positive current with a delay from the time when the input signal bin becomes a positive voltage, and the positive current is changed to a negative current with a delay from the time when the input signal bin becomes a negative voltage. Switch.

7 (a) and 7 (b) show another operation example of the linear amplifier 1A of the two series circuit shown in FIG. 4 (a), and FIG. 7 (c) shows the input signal bin. In this operation example, the power supply voltage is set to E / 2 on the positive electrode side and the negative electrode side, respectively, and the holding voltage of the flying capacitor C0 is set to E / 4.

The operation example shown in FIG. 7A shows a state in which the input signal bin is in the range of the symbol C in FIG. 7C, the operation of the positive current is shown, and the positive series circuit 2A serves as the current path. ing. When the input signal vin is in the range of E / 2 <vin <E, the n-MOSFET (Q2) is in the on state, the p-MOSFET (Q3, Q4) is in the off state, and the n-MOSFET (Q1) is in the linear region. Works with. As a result, a current path flowing from the DC power supply to the load via the positive series circuit 2A is formed, and the input signal bin is linearly amplified by the n-MOSFET (Q1).

On the other hand, in the operation example shown in FIG. 7 (b), the input signal bin is the operation in the range of the symbol D in FIG. 7 (c) and shows the operation of the negative current, and the negative side series circuit 2B is the current path. Indicates the state of When the input signal win is in the range of 0 <vin <E / 2, the n-MOSFET (Q1) and p-MOSFET (Q3) are in the off state, the p-MOSFET (Q4) is in the on state, and the n-MOSFET (n-MOSFET) Q2) operates in the linear region. As a result, a current path is formed from the DC power supply to the load via the negative side series circuit 2B and the positive side series circuit 2A, and the input signal bin is linearly amplified by the n-MOSFET (Q2).

In the range of the code D in FIG. 7 (c), which of the operation modes of FIGS. 7 (a) and 7 (b) is used depends on the load condition. When the load is a pure resistance, the operation mode shown in FIG. 7A is used when the load is positive, and the operation mode shown in FIG. 7B is used when the load is negative voltage. On the other hand, when the load contains an inductance component and a capacitance component, it operates in different current paths due to the phase difference between the voltage and the current, so that both operation modes of FIGS. 7A and 7B can be taken.

(Composition of 3 series circuit and 4 series circuit)
Next, a configuration example and an operation example of the three-series circuit and the four-series circuit in which the series circuit of one polarity is composed of three MOSFETs or four MOSFETs will be described with reference to FIGS. 8 to 13. FIG. 8 shows a configuration example of a four-series circuit, FIGS. 9 and 10 show an operation example of the four-series circuit, FIGS. 11 and 12 show an operation example of the four-series circuit separately, and FIG. 13 shows three series. A configuration example of the circuit is shown.

In the configuration example shown in FIG. 8, the linear amplifier 1B has a positive series circuit 2A in which four n-MOSFETs (Q1 to Q4) are connected in series, and four p-MOSFETs (Q5 to Q8) in series. The negative-side series circuit 2B is provided, and the flying capacitor 3 (C1) is connected between the source end of the n-MOSFET (Q1) and the source end of the p-MOSFET (Q8). The flying capacitor 3 (C2) is connected between the source end and the source end of the p-MOSFET (Q7), and flying between the source end of the n-MOSFET (Q3) and the source end of the p-MOSFET (Q6). The capacitor 3 (C3) is connected, the input circuit 4A is connected to the gate end of the n-MOSFET (Q1 to Q4) and the p-MOSFET (Q5 to Q8), and a common input signal bin is input.

The positive electrode of the positive DC power supply 11A is connected to the drain end of the n-MOSFET (Q1) and a voltage E / 2 is applied, and the negative electrode of the negative DC power supply 11B is applied to the drain end of the p-MOSFET (Q8). Is connected and the voltage E / 2 is applied in the negative direction.

9 (a) to 9 (d) show an operation example of the linear amplifier 1B of the four series circuit shown in FIG. This operation example is an example in which the input signal bin is divided into two voltage ranges on the positive electrode side and the negative electrode side, and linearly amplified in the linear region corresponding to each voltage range.

The power supply voltage is E / 2 on the positive electrode side and the negative electrode side, respectively, the holding voltage of the flying capacitor C1 is 3E / 4, the holding voltage of the flying capacitor C2 is 2E / 4, and the holding voltage of the flying capacitor C3 is E / 4. .. Further, FIG. 10A shows an input signal vin, FIG. 10B shows an output voltage vout, FIG. 10C shows a drain-source voltage VQ1 of the n-MOSFET (Q1), and FIG. (D) shows the drain-source voltage VQ2 of the n-MOSFET (Q2), FIG. 10 (e) shows the drain-source voltage VQ3 of the n-MOSFET (Q3), and FIG. 10 (f) shows the n- The drain-source voltage VQ4 of the MOSFET (Q4) is shown.

Hereinafter, the input signal bin is in the range of E / 4 <vin <E / 2 (hereinafter referred to as voltage range A), 0 <vin <E / 4 (hereinafter referred to as voltage range B), and −E / 4 <. The case where it is in each voltage range of vin <0 range (hereinafter referred to as voltage range C) and -E / 2 <vin <-E / 4 (hereinafter referred to as voltage range D) is shown.

Voltage range A:
The operating state shown in FIG. 9A shows the operation when the input signal Vin is in the range of E / 4 <vin <E / 2, and shows the state in which the positive series circuit 2A serves as the current path. When the input signal vin is in the range of E / 4 <vin <E / 2, the n-MOSFET (Q2 to Q4) is in the ON state (FIGS. 10 (d) to 10 (f)), and the p-MOSFET (Q5). ~ Q8) is turned off, and the n-MOSFET (Q1) operates in the linear region (FIG. 10 (c)). As a result, a current path is formed from the DC power supply to the load via the positive series circuit 2A, and the input signal bin (FIG. 10 (a)) is linearly amplified by the n-MOSFET (Q1) (FIG. 10 (b). )).

Voltage range B:
The operating state shown in FIG. 9B shows the operation when the input signal bin is in the range of 0 <vin <E / 4, and the state in which the positive side series circuit 2A and the negative side series circuit 2B serve as the current path is defined. Shown. When the input signal vin is in the range of 0 <vin <E / 4, the n-MOSFET (Q3, Q4) is in the ON state (FIGS. 10 (e) and 10 (f)), and the p-MOSFET (Q8) is in the on state. On state, n-MOSFET (Q1) is off state (FIG. 10 (c)), p-MOSFET (Q5 to Q7) is off state, and n-MOSFET (Q2) operates in the linear region (FIG. 10 (d)). )). As a result, a current path is formed from the DC power supply to the load via the negative side series circuit 2B and the positive side series circuit 2A, and the input signal bin (FIG. 10 (a)) is linearly amplified by the n-MOSFET (Q2). (Fig. 10 (b)).

Voltage range C:
The operating state shown in FIG. 9C shows the operation when the input signal bin is in the range of −E / 4 <vin <0, and the positive side series circuit 2A and the negative side series circuit 2B serve as the current path. Is shown. The operation when the input signal bin is in the range of −E / 4 <vin <0 corresponds to the operation in which the polarity of the operation shown in the voltage range B is reversed. The p-MOSFET (Q5, Q6) is in the on state, the n-MOSFET (Q1) is in the on state (FIG. 10 (c)), the p-MOSFET (Q8) is in the off state, and the n-MOSFET (Q2 to Q4) is in the off state. (FIGS. 10 (d) to (f)), and the p-MOSFET (Q7) operates in the linear region. As a result, a current path is formed from the load to the DC power supply via the negative side series circuit 2B and the positive side series circuit 2A, and the input signal bin (FIG. 10A) is linearly amplified by the p-MOSFET (Q7). To.

Voltage range D:
The operating state shown in FIG. 9D shows an operation when the input signal bin is in the range of −E / 2 <vin <−E / 4, and shows a state in which the negative series circuit 2B serves as a current path. There is. The operation when the input signal bin is in the range of −E / 2 <vin <−E / 4 corresponds to the operation in which the polarity of the operation shown in the voltage range A is reversed. The p-MOSFETs (Q5 to Q7) are in the on state, the n-MOSFETs (Q1 to Q4) are in the off state (FIGS. 10 (c) to (f)), and the p-MOSFET (Q8) operates in the linear region. As a result, a current path is formed from the load to the DC power supply via the negative series circuit 2B, and the input signal bin (FIG. 10A) is linearly amplified by the p-MOSFET (Q8).

11 and 12 show another operation example of the linear amplifier 1B of the four series circuit. The four-series circuit shown in FIG. 11 has the same circuit configuration as the four-series circuit shown in FIG. 8, and the operation shown in FIG. 9 is performed by making the voltage held by the flying capacitors 3 (C1, C2, C3) different. The linear amplification is performed in the linear region corresponding to the voltage range of the input signal win different from the example.

The operation example shown in FIG. 9 is a case where the input signal bin is divided into two voltage ranges on the positive electrode side and the negative electrode side to perform linear amplification, whereas the operation examples shown in FIGS. 11 and 12 are The case where the input signal bin is divided into three voltage ranges on the positive electrode side and the negative electrode side and linear amplification is performed is shown.

In this operation example, regarding the voltage to be held by the flying capacitors 3 (C1 to C3), the holding voltage of C1 is (5E1 / 3), the holding voltage of C2 is the voltage (4E1 / 3), and the holding voltage of C3 is (E1). As a result, the range of the input signal bin is divided into three voltage ranges to perform linear amplification.

12 (a) to 12 (c) show the operating state in the section where the input signal vin is a positive voltage, and FIG. 12 (d) shows the input signal vin and three voltage ranges (A to C) for linear amplification. Shown.

Hereinafter, the input signal bin is in the range of 2E1 / 3 <vin <E1 (hereinafter referred to as voltage range A), E1 / 3 <vin <2E1 / 3 (hereinafter referred to as voltage range B), and 0 <vin <. Each voltage range in the range of E1 / 3 (hereinafter referred to as voltage range C) is shown.

Voltage range A:
The operating state shown in FIG. 12A shows an operation when the input signal bin is in the range of 2E1 / 3 <vin <E1, and shows a state in which the positive series circuit 2A serves as a current path. When the input signal win is in the range of 2E1 / 3 <vin <E1, the n-MOSFET (Q2 to Q4) is in the on state, the p-MOSFET (Q5 to Q8) is in the off state, and the n-MOSFET (Q1) is in the off state. Operates in the linear region. As a result, a current path flowing from the DC power supply to the load via the positive series circuit 2A is formed, and the input signal bin is linearly amplified by the n-MOSFET (Q1).

Voltage range B:
The operating state shown in FIG. 12B shows an operation when the input signal bin is in the range of E1 / 3 <vin <2E1 / 3, and the positive series circuit 2A and the negative series circuit 2B serve as the current path. Indicates the state. When the input signal win is in the range of E1 / 3 <vin <2E1 / 3, n-MOSFET (Q3, Q4) is on, p-MOSFET (Q8) is on, and n-MOSFET (Q1) is off. In the state, p-MOSFETs (Q5 to Q7) are turned off, and n-MOSFETs (Q2) operate in the linear region. As a result, a current path is formed from the DC power supply to the load via the negative side series circuit 2B and the positive side series circuit 2A, and the input signal bin is linearly amplified by the n-MOSFET (Q2).

Voltage range C:
The operation example shown in FIG. 12C shows an operation when the input signal bin is in the range of 0 <vin <E1 / 3, and shows a state in which the positive side series circuit 2A and the negative side series circuit 2B serve as a current path. Shown. When the input signal bin is in the range of 0 <vin <E1 / 3, the n-MOSFET (Q4) is on, the p-MOSFET (Q7, Q8) is on, and the n-MOSFET (Q1, Q2) is off. In the state, the p-MOSFETs (Q5 and Q6) are turned off, and the n-MOSFETs (Q3) operate in the linear region. As a result, a current path is formed from the DC power supply to the load via the negative side series circuit 2B and the positive side series circuit 2A, and the input signal bin is linearly amplified by the n-MOSFET (Q3).

Next, a configuration example of the three series circuit is shown. FIG. 13 (b) shows a configuration example of the three series circuit, and FIG. 13 (a) shows a configuration example of the four series circuit for comparison with the three series circuit of FIG. 13 (b).

In the configuration example of the linear amplifier 1C of the three series circuit shown in FIG. 13B, the positive series circuit 2A in which three n-MOSFETs (Q1 to Q3) are connected in series and the three p-MOSFETs (Q4). ~ Q6) is provided with a negative series circuit 2B connected in series, and a flying capacitor 3 (C1) is connected between the source end of the n-MOSFET (Q1) and the source end of the p-MOSFET (Q6). A flying capacitor 3 (C2) is connected between the source end of the −MOSFET (Q2) and the source end of the p-MOSFET (Q5), and the n-MOSFET (Q1 to Q3) and the p-MOSFET (Q4 to Q6) are connected. A common input signal bin is input to the gate end.

When the voltage of the DC power supply is E1, the holding voltage of the flying capacitor 3 is, for example, 3E1 / 4 for the flying capacitor 3 (C1) and 2E1 / 4 for the flying capacitor 3 (C2). The input signal vin of the peak value E1 can be linearly amplified in two voltage ranges of 0 <vin <E1 / 2 and E1 / 2 <vin <E1.

In the configuration example of the linear amplifier 1B of the four series circuit shown in FIG. 13 (a), the n-MOSFET (Q4) and the p-MOSFET (Q5) connected to the output end side of the series circuits 2A and 2B are The maximum voltage applied between the drain and source is E1 / 4. On the other hand, in the configuration example of the linear amplifier 1C of the three series circuit shown in FIG. 13B, the n-MOSFET (Q3) and p-MOSFET (Q4) connected to the output end side of each series circuit 2A and 2B. ), The maximum voltage applied between the drain and source is 2E1 / 4 (= E1 / 2). Therefore, the MOSFET of the configuration example of the linear amplifier 1C of the 3-series circuit is the configuration of the linear amplifier 1B of the 4-series circuit. A withstand voltage twice that of the example is required.

(Composition of 5 series circuit and 6 series circuit)
Next, a five-series circuit in which one polarity series circuit is composed of five MOSFETs or six MOSFETs, a configuration example of the six-series circuit, and an operation example will be described with reference to FIGS. 14 to 17. FIG. 14 shows a configuration example of a 6-series circuit, FIGS. 15 and 16 show an operation example of the 6-series circuit, and FIG. 17 shows a configuration example of the 5-series circuit.

In the configuration example shown in FIG. 14, the linear amplifier 1D has a positive series circuit 2A in which six n-MOSFETs (Q1 to Q6) are connected in series, and six p-MOSFETs (Q7 to Q12) in series. The negative-side series circuit 2B is provided, and the flying capacitor 3 (C1) is connected between the source end of the n-MOSFET (Q1) and the source end of the p-MOSFET (Q12). The flying capacitor 3 (C2) is connected between the source end and the source end of the p-MOSFET (Q11), and flying between the source end of the n-MOSFET (Q3) and the source end of the p-MOSFET (Q10). The capacitor 3 (C3) is connected, the flying capacitor 3 (C4) is connected between the source end of the n-MOSFET (Q4) and the source end of the p-MOSFET (Q9), and the source of the n-MOSFET (Q5). A flying capacitor 3 (C5) is connected between the end and the source end of the p-MOSFET (Q8), and a common input is applied to the gate ends of the n-MOSFET (Q1 to Q6) and p-MOSFET (Q7 to Q12). The signal Vin is input.

Further, the positive electrode of the positive DC power supply 11A is connected to the drain end of the n-MOSFET (Q1) and the voltage E1 is applied, and the negative electrode of the negative DC power supply 11B is connected to the drain end of the p-MOSFET (Q12). Then, the voltage E2 is applied in the negative direction.

15 (a) to 15 (c) show an operation example of the linear amplifier 1D of the 6-series circuit shown in FIG. This operation example is an example in which the input signal bin is divided into three voltage ranges on the positive electrode side and the negative electrode side, and linearly amplified in the linear region corresponding to each voltage range. FIG. 16 shows the input signal bin (FIG. 16 (a)), the output voltage vout (FIG. 16 (b)), and the drain-source voltage VQ1 to VQ6 (FIG. 16) of the n-MOSFETs (Q1 to Q6) in this operation example. (C) to (f)) are shown. 15 (a) to 15 (c) show an operation example in which the range in which the input signal Vin is a positive voltage is divided into three voltage ranges, and FIG. 16 shows the magnitudes of the DC power supply voltages E1 and E2. The case where E / 2 is set and the peak value of the input voltage is E / 2 is shown.

Hereinafter, in the linear amplifier 1D shown in FIG. 14, the voltage of the DC power supply is set to E / 2 on the positive side and the negative side, respectively, the holding voltage of the flying capacitor C1 is 5E / 6, and the holding voltage of the flying capacitor C2 is 4E / 6. The holding voltage of the flying capacitor C3 is 3E / 6, the holding voltage of the flying capacitor C4 is 2E / 6, the holding voltage of the flying capacitor C5 is E/6, and the input signal bin is E / 3 <vin <E / 2. Range (hereinafter referred to as voltage range A), E / 6 <vin <E / 3 range (hereinafter referred to as voltage range B), 0 <vin <E / 6 range (hereinafter referred to as voltage range C) The voltage range is shown.

Voltage range A:
The operating state shown in FIG. 15A shows an operation when the input signal bin is in the range of E / 3 <vin <E / 2, and shows a state in which the positive series circuit 2A serves as a current path. When the input signal vin is in the range of E / 3 <vin <E / 2, the n-MOSFET (Q2 to Q6) is in the ON state (FIGS. 16 (d) to 16 (f)) and the p-MOSFET (Q7). ~ Q12) is turned off, and the n-MOSFET (Q1) operates in the linear region (FIG. 16 (c)). As a result, a current path is formed from the DC power supply to the load via the positive series circuit 2A, and the input signal bin (FIG. 16 (a)) is linearly amplified by the n-MOSFET (Q1) (FIG. 16 (b). )).

Voltage range B:
The operating state shown in FIG. 15B shows an operation when the input signal bin is in the range of E / 6 <vin <E / 3, and the positive side series circuit 2A and the negative side series circuit 2B serve as the current path. Indicates the state. When the input signal win is in the range of E / 6vin <E / 3, the n-MOSFET (Q3 to Q6) is in the on state (FIGS. 16 (e) and (f)), and the p-MOSFET (Q12) is in the on state. , N-MOSFET (Q1) is in the off state (FIG. 16 (c)), p-MOSFET (Q7 to Q12) is in the off state, and n-MOSFET (Q2) operates in the linear region (FIG. 16 (d)). .. As a result, a current path that flows from the DC power supply to the load via the negative side series circuit 2B and the positive side series circuit 2A is formed, and the input signal bin (FIG. 16A) is linearly amplified by the n-MOSFET (Q2). (Fig. 16 (b)).

Voltage range C:
The operating state shown in FIG. 15C shows the operation when the input signal bin is in the range of 0 <vin <E / 6, and the state in which the positive side series circuit 2A and the negative side series circuit 2B serve as the current path is defined. Shown. When the input signal vin is in the range of 0 <vin <E / 6, the n-MOSFET (Q4 to Q6) is in the on state (FIG. 16 (f)), the p-MOSFET (Q11, Q12) is in the on state, and n. -MOSFETs (Q1, Q2) are in the off state (FIGS. 16 (c) and (d)), p-MOSFETs (Q7 to Q10) are in the off state, and n-MOSFET (Q3) operates in the linear region (FIG. 16). (E)). As a result, a current path flowing from the DC power supply to the load via the negative side series circuit 2B and the positive side series circuit 2A is formed, and the input signal bin (FIG. 16A) is linearly amplified by the n-MOSFET (Q3). (Fig. 16 (b)).

In the operation example of the 6-series circuit shown in FIGS. 15 and 16, the input signal bin is divided into three voltage ranges on one pole side for linear amplification, but the number of divisions in the voltage range is not limited to three. Linear amplification can be performed by the number of divisions of 2, 4, and 5.

Next, a configuration example of the 5-series circuit is shown with reference to FIG. In the configuration example of the linear amplifier 1E of the 5-series circuit shown in FIG. 17, the positive series circuit 2A in which five n-MOSFETs (Q1 to Q5) are connected in series, and five p-MOSFETs (Q6 to Q10) The negative-side series circuit 2B is connected in series, and the flying capacitor 3 (C1) is connected between the source end of the n-MOSFET (Q1) and the source end of the p-MOSFET (Q10). The flying capacitor 3 (C2) is connected between the source end of Q2) and the source end of p-MOSFET (Q9), and the source end of n-MOSFET (Q3) and the source end of p-MOSFET (Q8) are connected. The flying capacitor 3 (C3) is connected between them, and the flying capacitor 3 (C4) is connected between the source end of the n-MOSFET (Q4) and the source end of the p-MOSFET (Q7), and the n-MOSFET (Q1) is connected. A common input signal bin is input to the gate ends of ~ Q5) and p-MOSFETs (Q6 to Q10).

When the voltage of the DC power supply is E1, for example, the voltage of the flying capacitor 3 (C1) is 7E1 / 4, and the voltage of the flying capacitor 3 (C2) is 6E1 / 4 (= 3E1 /). 2) By setting the voltage of the flying capacitor 3 (C3) to 5E1 / 4 and the voltage of the flying capacitor 3 (C4) to 4E1 / 4 (= E1), the input signal vin of the peak value E1 is set to 0 <vin <. In four voltage ranges: E1 / 4 voltage range, E1 / 4 <vin <E1 / 2 voltage range, E1 / 2 <vin <3E1 / 4 voltage range, and 3E1 / 4 <vin <E1 voltage range. It can be linearly amplified.

(Other configuration examples of linear amplifier)
Next, another configuration example of the linear amplifier will be described with reference to FIG. The linear amplifier 1F has a MOSFET series circuit on only one side of the positive electrode side or the negative electrode side, and a diode series circuit on the other side. The example shown in FIGS. 18A to 18C shows an example in which the series circuit on the positive electrode side is composed of MOSFETs and the series circuit on the negative electrode side is composed of diodes. FIG. 18D shows a configuration example of a power conversion device that outputs alternating current.

In the operating state shown in FIG. 18A, the n-MOSFETs (Q2, Q3, Q4) are operated in the saturated state to be turned on, and are operated in the linear region of the n-MOSFET (Q1) to linearize the input signal bin. Amplify.

In the operating state shown in FIG. 18 (b), the n-MOSFET (Q1, Q3, Q4) is operated in the saturated state or the cutoff region, the n-MOSFET (Q3, Q4) is turned on, and the n-MOSFET (Q1) is turned on. Is turned off, and the input signal Vin is linearly amplified by operating in the linear region of the n-MOSFET (Q2).

In the operating state shown in FIG. 18C, the n-MOSFET (Q1, Q2, Q4) is operated in the saturated state or the cutoff region, the n-MOSFET (Q4) is turned on, and the n-MOSFET (Q1, Q2) is turned on. Is turned off, and the input signal Vin is linearly amplified by operating in the linear region of the n-MOSFET (Q3). In each of the above operating states, the series circuit of the diode on the negative electrode side forms a part of the current path. By inverting the relationship between the MOSFET and the diode in the configuration of the linear amplifier 1F, it is possible to linearly amplify only the input signal on the negative electrode side.

The linear amplifier 1F has a configuration in which only the input signal on the positive electrode side is linearly amplified, the output voltage is only a positive voltage, and no negative voltage is output. FIG. 18 (d) shows a configuration example of outputting positive and negative voltage output voltages using the linear amplifier 1F.

The power conversion device 10 shown in FIG. 18D is configured by connecting the full bridge inverter 13 to the linear amplifier 1F. According to the power conversion device 10, the output voltage of the linear amplifier 1F can be inverted every half cycle by the full bridge inverter 13 to output the output voltage of the positive voltage and the negative voltage.

(Conversion efficiency)
Next, the conversion efficiency between the linear amplifier (FCLA) using the flying capacitor of the present invention and the linear amplifier (DCLA) using the conventionally proposed clamp diode, and the number of series elements and theoretical conversion in the linear amplifier of the present invention. The relationship with efficiency is shown.

Theoretical conversion efficiency of n-series linear amplifier FCLA and n-series linear amplifier DCLA when the output voltage vout and output current iout are sinusoidal as shown in the following equations (1) and (2). ηDCLA is represented by the following equations (3) and (4). Note that "n" is the number of series and & "k" is the ordinal number of a plurality of MOSFETs constituting the series circuit.

vout = (E / 2) ・ sinθ… (1)
iout ＝ Imax ・ sinθ… (2)
… (3)
… (4)

Here, θk is the phase of the boundary between the off state and the active state of MOSFET Qk, and is represented by θ = sin ^-1 {(n-2k) / n}. Further, E is the DC power supply voltage value, Imax is the maximum value of the current, Ron is the on-resistance of the MOSFET, RESR is the equivalent series resistance of the flying capacitor, and VF is the forward voltage of the clamp diode.

The above equation is derived under the following conditions.
(a) The voltage of the flying capacitor Ck of the linear amplifier FCLA is maintained at (n−k) E / n, and the voltage of the DC power supply Ek of the linear amplifier DCLA is maintained at E / n.
(b) The gate threshold of each MOSFET is 0V.
(c) In order to maintain the symmetry of the circuit configuration, the number of series n is an even number.
(d) The loss of the gate circuit is ignored as it is small enough.

FIG. 19 shows the relationship of the theoretical conversion efficiency with respect to the series number n using the equations (3) and (4). The theoretical conversion efficiencies of Theory, FCLA, and DCLA in FIG. 19 are calculated values based on theoretical formulas, and Theory (indicated by +) is under ideal conditions (ideal theory) that do not consider the loss caused by Ron, RESR, and VF. , It is a value calculated based on the loss generated only in the linear operation of the MOSFET of the main circuit.

Table 1 below shows the circuit parameters.

However, in the above circuit parameters, for Ron, it is assumed that an element with a withstand voltage of 200 V and an on-resistance of 0.1 [Ω] is used when 100 V is applied to the element, and the withstand voltage is 1 / n when the number of series is n. Since the element of can be used, Ron is set to 0.1 / n [Ω] which is directly proportional to the withstand voltage. Under the parameter conditions shown in Table 1, the conversion efficiency of the linear amplifier FCLA using the flying capacitor of the present invention exceeds the conversion efficiency of the linear amplifier DCLA using the clamp diode.

FIG. 20 is a graph showing the difference in theoretical conversion efficiency between the linear amplifier FCLA and the linear amplifier DCLA with respect to the number n in series. The circuit parameters in Table 1 are used except for the DC power supply voltage E and the maximum current Imax. When the DC power supply voltage is 200V, the withstand voltage of each MOSFET is assumed to be 400V, and the on-resistance is 0.2 / n [Ω].

FIG. 20 shows that the smaller the maximum current value and the lower the voltage value of the DC power supply, the higher the conversion efficiency of the linear amplifier FCLA than that of the linear amplifier DCLA. This means that the loss of the clamp diode is proportional to the current, whereas the loss of the flying capacitor is proportional to the square of the current, so that the linear amplifier FCLA is superior in conversion efficiency when the current value is small. It suggests that.

On the other hand, when the DC power supply voltage is large, the on-resistance of each MOSFET increases, suggesting that the linear amplifier DCLA, which can reduce the number of passing elements of the MOSFET in the on state by passing through the clamp diode, is advantageous. Will be done. Therefore, the linear amplifier FCLA can obtain higher conversion efficiency than the linear amplifier DCLA in the conversion of a small capacity.

Moreover, since power electronics equipment handles a relatively large amount of electric power, improvement of conversion efficiency greatly contributes to the electric power environment.

In addition, a relatively small capacity (for example, about 100 kW or less) inverter is a linear amplifier FCLA of the present invention suitable for small capacity conversion in consideration of the demand environment, which is an important application that occupies more than half of the market on a power basis. The availability of is very high.

The present invention is not limited to each of the above embodiments. Various modifications can be made based on the gist of the present invention, and these are not excluded from the scope of the present invention.

The linear amplifier and power conversion device of the present invention can be applied to all power electronics devices that convert power, such as power conditioners for photovoltaic power generation and inverters for driving motors having a relatively small capacity.

1 Linear amplifier 1A to 1F Linear amplifier 2 Series circuit 2A Positive side series circuit 2B Negative side series circuit 3 Flying capacitor 4,4A, 4B Input circuit 5 Insulated power supply 6 Gate resistance 7 Zener diode 8 Gate drive circuit 9in Input end 9out Output end 10 Power converter 11 DC power supply 11A Positive side DC power supply 11B Negative side DC power supply 12 Load 13 Full bridge inverter 101 Diode clamp type linear amplification circuit 102 Series circuit 103 Diode clamp circuit 111 DC power supply 112 Load C0 to C5, Ck Flying capacitor D2 ~ D7 diode

Claims (9)

It is a linear amplifier that linearly amplifies the input signal and outputs it from the output end.
(A) A series circuit in which two or more MOSFETs are connected in series on at least one pole side with respect to the output end of the linear amplifier.
(B) A plurality of flying capacitors that hold the potential at the source end of each MOSFET of the series circuit at different potentials, and
(C) An input circuit that inputs an input signal to the gate end of each MOSFET and
With
The series circuit is connected between the power input end on the DC power supply side and the output end of the linear amplifier.
Each flying capacitor is connected to the source end of each MOSFET,
The input circuit is connected to the gate end of each MOSFET,
Each MOSFET is a linear amplifier that linearly amplifies the input signal and outputs it from the output end in the linear region of the MOSFET determined by the potential at the source end to which the voltage of each flying capacitor is applied and the voltage of the input signal. An isolated power supply or voltage balance circuit that holds the voltage of each flying capacitor at a predetermined voltage is provided.
The linearity according to claim 1, wherein the predetermined voltage is a voltage that adjusts the reference voltage set at the source end of each MOSFET of the series circuit from the ground voltage to the positive or negative direction in the series circuit. amplifier. The series circuit includes a positive side series circuit on the positive electrode side and a negative side series circuit on the negative electrode side with respect to the output end of the linear amplifier.
The MOSFET included in the positive series circuit is an n-MOSFET.
The MOSFET included in the negative series circuit is a p-MOSFET.
The voltage of each of the flying capacitors is a set voltage within the voltage of the DC power supply.
Each of the flying capacitors is connected between both source ends between the n-MOSFET and the p-MOSFET applied by the flying capacitor, and holds the voltage between the source ends of the MOSFET at the set voltage.
The linear amplifier according to claim 1 or 2, wherein the positive series circuit outputs a positive voltage and the negative series circuit outputs a negative voltage. The linear amplifier according to any one of claims 1 to 3, wherein the input circuit includes a connection circuit for connecting the gate ends of the plurality of MOSFETs and inputs a common gate voltage to all the gate ends. The connection circuit of the input circuit is an overcurrent prevention gate resistor connected between the gate end and / or an overvoltage prevention Zener diode between the gate and source connected between the gate end and the source end. The linear amplifier according to claim 4. The linear amplifier according to any one of claims 1 to 3, wherein the input circuit individually connects a gate drive circuit to each gate end of the plurality of MOSFETs and inputs an individual gate voltage to each gate end. The series circuit is relative to the output end of the linear amplifier.
A MOSFET series circuit is provided on the positive side series circuit, and a diode series circuit is provided by connecting a diode in series on the negative electrode side.
Or
A diode series circuit consisting of a diode connected in series to the positive side series circuit, and a MOSFET series circuit on the negative electrode side.
The MOSFET included in the positive series circuit is an n-MOSFET.
The MOSFET included in the negative series circuit is a p-MOSFET.
The linear amplifier according to claim 1 or 2, wherein the MOSFET series circuit on the positive electrode side outputs a positive voltage, and the MOSFET series circuit on the negative electrode side outputs a negative voltage. DC power supply and
The linear amplifier according to any one of claims 1 to 7.
With
The DC power supply
A positive DC power supply connected between the high voltage side of the positive series circuit of the linear amplifier and the ground potential, and a connection between the low voltage side of the negative series circuit of the linear amplifier and the ground potential. Two DC power supplies on the negative side DC power supply,
Or
One DC power supply connected between the ground potential and the high voltage side of the positive series circuit of the linear amplifier, with the low voltage side of the negative series circuit of the linear amplifier as the ground potential.
A power conversion device that converts DC voltage into power by using the output end of the linear amplifier as the output end of the power conversion device. A full-bridge inverter connected between the output end of the linear amplifier and the output end of the power converter is provided.
The power conversion device according to claim 8, wherein the full bridge inverter inverts and outputs either the output of the MOSFET series circuit on the positive electrode side or the output of the MOSFET series circuit on the negative electrode side.