JP6821763B2 - Image forming apparatus and its control method - Google Patents

Description

The present invention relates to an image forming apparatus and a control method thereof .

Conventionally, an image having a plurality of power modes for reducing power consumption, for example, a normal mode in which power is supplied to all components and a power saving mode in which power is not supplied to at least a part or all of the components. A forming device is known (see, for example, Patent Document 1). The image forming apparatus of Patent Document 1 switches the power mode to the power saving mode when nothing is operated in the normal mode for a certain period of time, and switches the power mode when some operation is performed in the power saving mode. Switch to normal mode. Further, the image forming apparatus of Patent Document 1 includes a main CPU, a sub CPU, an engine controller, an operation display unit, and the like.

By the way, when the power mode of an image forming apparatus including components such as a main CPU, a sub CPU, an engine controller, and an operation display unit is switched from a power saving mode to a normal mode, a return process for supplying power to each component (FIG. 7. Fig. 8) is executed. The process of FIG. 7 is executed by the main CPU, the sub CPU, and the engine controller, and the process of FIG. 8 is executed by the sub CPU.

In FIGS. 7 and 8, first, the main CPU executes the start-up process (steps S701 to S703). Specifically, when power is supplied to the main CPU (step S701), the power-supplied main CPU transmits binary data of the sub CPU to the sub CPU to release the reset state of the sub CPU (step S702). .. As a result, the sub CPU starts the startup process based on the binary data. Then, the main CPU executes a communication preparation process for communicating with the sub CPU (step S703).

Further, when the reset state is released, the sub CPU executes the start-up process (steps S711 to S713, S801 to S803). Specifically, the sub CPU boots the kernel, which is the core part of the OS of the sub CPU (steps S711 and S801), and a plurality of devices that are booted when the power mode of the image forming apparatus is switched from the power saving mode to the normal mode. A plurality of device drivers for driving are sequentially started from, for example, device drivers corresponding to devices arranged around the sub CPU (steps S712 and S802), and virtual communication between the main CPU and the engine controller is established (step). S713, S803). After that, communication is executed between the main CPU and the sub CPU using a predetermined application, and the sub CPU is information necessary for communicating with the engine controller and is a device controlled by the engine controller, for example, a printer. And information about the scanner (hereinafter referred to as "various device information") is received from the main CPU (steps S704, S714, S804).

The engine controller executes the start-up process independently of the main CPU and the sub CPU (step S721). Since the start process of the engine controller is completed in a short time, the engine controller waits from the end of the start process until the communication between the main CPU and the sub CPU is completed (step S722).

Next, the sub CPU communicates with the engine controller, transfers various device information to the engine controller, acquires the status information of the engine controller, and determines whether or not the job can be executed (steps S715 and S723). S805). The main CPU waits from the end of communication with the sub CPU until the end of communication between the sub CPU and the engine controller (step S705). When the sub CPU determines that the job can be executed, the sub CPU notifies the main CPU that the job can be executed, and the main CPU controls the operation display unit to be supplied with power. The main CPU, the sub CPU, and the engine controller wait for the job to be submitted (steps S706, S716, S724, S806) and end this process.

Japanese Unexamined Patent Publication No. 2009-223866

However, as described above, since the engine controller communicates with the sub CPU after the communication between the main CPU and the sub CPU is completed, it is necessary to wait until the engine controller communicates with the sub CPU after the start processing of the engine controller is completed. Must be. As a result, there is a problem that the switching of the power mode of the image forming apparatus with a short standby time of the engine controller is hindered, and the power mode cannot be quickly switched from the power saving mode to the normal mode.

An object of the present invention is to provide an image forming apparatus capable of rapidly switching a power mode from a power saving mode to a normal mode, and a control method thereof .

To achieve the above object, an image forming apparatus of the present invention includes a first processor, a first storage unit, a first substrate having a second processor, second storage means, An image forming apparatus having a second substrate and an engine controller for controlling a device, wherein the first storage means stores a start program of the second processor and information on the device . according to what power supply to the first processor is started, said before starting processing of the second processor is started, the first of said second processor startup program stored in the storage means further comprising a transmission means for transmitting by the DMA transfer information of the device to the second storage means, said second processor, before Symbol said second processor startup program transmitted to the second storage means According to this, before the communication with the first processor is established , the communication with the engine controller is started by using the received information of the device .

According to the present invention, the power mode can be quickly switched from the power saving mode to the normal mode.

It is a block diagram which shows the structure of the image formation system including the MFP as the image formation apparatus which concerns on embodiment of this invention. It is a block diagram which shows schematic the internal structure of the controller in FIG. It is a sequence diagram which shows the 1st return processing which returns the power mode of the MFP in FIG. 1 from a power saving mode to a normal mode. It is a sequence diagram which shows the 2nd return processing which returns the power mode of the MFP in FIG. 1 from a power saving mode to a normal mode. It is a flowchart which shows the procedure of the 2nd return processing of FIG. 4, FIG. 5 (A) is the flowchart which is executed by the main CPU in FIG. 2, and FIG. 5 (B) is execution by the sub CPU in FIG. It is a flowchart. It is a figure used for demonstrating the start-up process which starts a plurality of device drivers in steps S421, S413 of FIG. 4, FIG. 6 (A) shows the conventional start-up process, and FIG. 6 (B) is the 2nd The start processing in the return processing is shown. It is a sequence diagram which shows the return process which returns the power mode of the conventional image forming apparatus from a power saving mode to a normal mode. It is a flowchart which shows the procedure of the return processing of FIG. 7 executed by a sub CPU.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram schematically showing a configuration of an image forming system 100 including an MFP 101 as an image forming apparatus according to an embodiment of the present invention.

The image forming system 100 of FIG. 1 includes an MFP 101 and a PC 102 as an information processing device, and the MFP 101 and the PC 102 are connected to each other via a network, for example, a LAN 103. The MFP 101 includes an operation display unit 104, a controller 105, a printer 106 (printer engine), a scanner 107, a FAX 108, and an HDD 109, and the operation display unit 104, the printer 106, the scanner 107, the FAX 108, and the HDD 109 are connected to each other via the controller 105. Has been done. Further, the printer 106 has a paper feeding unit 106a, a marking unit 106b, and a paper ejection unit 106c, and the paper feeding unit 106a and the paper ejection unit 106c are connected to each other via the marking unit 106b. Further, the scanner 107 has a scanner unit 107a and a document feeding unit 107b, and the scanner unit 107a and the document feeding unit 107b are connected to each other.

The operation display unit 104 includes a hard key and an operation panel, and the user operates the hard key and the operation panel to input an instruction to the MFP 101. The controller 105, for example, accepts a job from the PC 102 and controls each component of the MFP 101 when the accepted job is executed. The printer 106 prints image data stored in the HDD 109 on a recording medium, for example, a recording paper. Specifically, the marking unit 106b prints image data on the recording paper fed from the paper feeding unit 106a, and the recording paper on which the image data is printed is discharged to the paper ejection unit 106c.

The scanner 107 reads the document, generates image data corresponding to the scanned document, and stores the generated image data in the HDD 109. Specifically, the scanner unit 107a reads the document fed from the document feeding unit 107b and generates image data corresponding to the scanned document. FAX 108 receives FAX data from an external device connected via a telephone line 110, or transmits FAX data to an external device connected via a telephone line 110. The HDD 109 is a non-volatile storage device and stores various programs, various data, and the like.

FIG. 2 is a block diagram schematically showing the internal configuration of the controller 105 in FIG.

The controller 105 of FIG. 2 includes a main board 201 (main system) and a sub board 202 (subsystem). The main board 201 has a main CPU 203, a boot ROM 204, a non-volatile memory 205, a memory 206, an RTC 207, a USB controller 208, a disk controller 209, a flash disk 210, a network I / F 211, and a bus controller 212, and has a boot ROM 204 and non-volatile. The memory 205, memory 206, RTC207, USB controller 208, disk controller 209, network I / F211 and bus controller 212 are connected to each other via the main CPU 203, and the flash disk 210 is connected to the main CPU 203 via the disk controller 209. ing. Further, the PC 102 is connected to the network I / F 211 via the LAN 103, the USB memory 219 as an external device is connected to the USB controller 208, the operation display unit 104 is connected to the main CPU 203, and the HDD 109 is connected to the disk controller 209. ing.

The sub board 202 has a sub CPU 213, a non-volatile sub memory 214, a sub memory 215, an image processing processor 216, an engine controller 217, and a bus controller 218, and has a non-volatile sub memory 214, a sub memory 215, an image processing processor 216, and an image processing processor 216. The bus controllers 218 are connected to each other via the sub CPU 213. Further, the engine controller 217 is connected to the image processor 216, the printer 106 and the scanner 107 are connected to the engine controller 217, and the FAX 108 is connected to the sub CPU 213. Further, the bus controllers 212 and 218 are connected to each other for communication between the main board 201 and the sub board 202.

The main CPU 203 executes a boot program stored in the boot ROM 204 to control each component of the main board 201. The non-volatile memory 205 stores various data and the like, and even when the power of the MFP 101 is turned off, the various data and the like stored in the non-volatile memory 205 are not erased. The memory 206 is the work memory of the main CPU 203. The RTC 207 clocks the date and time even when the controller 105 is not powered. The USB controller 208 controls the connected USB memory 219. The disk controller 209 controls the connected flash disk 210, for example SSD.

The sub CPU 213 controls each component of the sub board 202. The non-volatile sub-memory 214 stores various data and the like, and even when the power of the MFP 101 is turned off, the various data and the like stored in the non-volatile sub-memory 214 are not erased. The sub memory 215 is a work memory of the sub CPU 213. The image processor 216, for example, converts image data described in an image description language into bitmap image data. The engine controller 217 controls the printer 106 and the scanner 107.

FIG. 3 is a sequence diagram showing a first return process for returning the power mode of the MFP 101 in FIG. 1 from the power saving mode to the normal mode. The process of FIG. 3 is executed by the main CPU 203, the sub CPU 213, and the engine controller 217.

In FIG. 3, first, the main CPU 203 executes startup processes (steps S301 to S303) that require a certain amount of time. Specifically, when power is supplied to the main CPU (step S301), the power-supplied main board 201 transmits binary data of the sub CPU 213 (starting program of the sub CPU 213) to the sub CPU 213 to reset the sub CPU 213. Release the state. As a result, the sub CPU 213 starts the startup process based on the binary data (step S302). The binary data is DMA-transferred from the non-volatile memory 205 of the main board 201 or the flash disk 210 to the sub memory 215 of the sub board 202. Various device information is added to the binary data. After that, the communication preparation process for communicating with the sub CPU 213 is executed (step S303).

Further, when the main CPU 203 executes the start processing of the main CPU 203 itself, the engine controller 217 also executes the start process of the engine controller 217 itself (step S321). The start processing of the engine controller is completed in a short time, and the engine controller 217 waits after the start processing is completed until communication with the sub CPU 213 described later is executed in steps S313 and S323 (step S322).

The sub CPU 213 executes the startup process (steps S311 to S313) based on the instruction of the main CPU 203. Specifically, the sub CPU 213 boots the kernel which is the core part of the OS of the sub CPU 203 (step S311), and the printer 106, the scanner 107, etc. which are started when the power mode of the MFP 101 is switched from the power saving mode to the normal mode. A plurality of device drivers (software) for driving a plurality of devices are started (step S312).

After all the device drivers are started, the sub CPU 213 executes communication with the engine controller 217 to transfer various device information added to the binary data DMA-transferred from the non-volatile memory 205 to the engine controller 217 and the engine. The status information of the controller 217 is acquired to determine whether or not the job can be executed (steps S313 and S323). Further, when the sub CPU 213 executes communication with the engine controller 217, the virtual communication of the main CPU 203 and the engine controller 217 is established at the same time (step S314), and after the virtual communication of the main CPU 203 and the engine controller 217 is established, the sub CPU 213 is sub. The CPU 213 executes communication with the main CPU 203 (steps S304 and S315).

As a result of the determination in steps S313 and S323, when the job can be executed, the sub CPU 213 notifies the main CPU 203 that the job can be executed, and the main CPU 203 controls the supply of power to the operation display unit 104. Then, the main CPU 203, the sub CPU 213, and the engine controller 217 wait for the job to be submitted (steps S305, S316, S324) and end this process.

According to the process of FIG. 3, various device information which is information required by the engine controller 217 is added to the binary data DMA-transferred from the non-volatile memory 205 to the sub memory 215 when the sub CPU 213 is started (step). Since S302), various device information can be immediately transferred to the engine controller 217 as soon as communication between the sub CPU 213 and the engine controller 217 is established after all the device drivers are started. As a result, the engine controller 217 can receive various device information faster, and thus can switch the power mode from the power saving mode to the normal mode more quickly.

FIG. 4 is a sequence diagram showing a second return process for returning the power mode of the MFP 101 in FIG. 1 from the power saving mode to the normal mode. The process of FIG. 4 is executed by the main CPU 203, the sub CPU 213, and the engine controller 217. 5A and 5B are flowcharts showing the procedure of the second return processing of FIG. 4, FIG. 5A is executed by the main CPU 203 in FIG. 2, and FIG. 5B is executed by the sub CPU 213 in FIG. Will be done.

In FIGS. 4 and 5, first, the main CPU 203 executes startup processing (steps S401 to S403, S501 to S503) that requires a certain period of time. Specifically, when power is supplied to the main CPU 203 (steps S401 and S501), the power-supplied main CPU 203 transmits binary data of the sub CPU 213 (starting program of the sub CPU 213) to the sub CPU 213 to cause the sub CPU 213. Release the reset state. As a result, the sub CPU 213 starts the startup process based on the binary data (steps S402 and S502). Even in the second recovery process, various device information is added to the binary data to be DMA-transferred to the sub-memory 215 . After that, the communication preparation process for communicating with the sub CPU 213 is executed (steps S403 and S503).

Further, when the main CPU 203 executes the start processing of the main CPU 203 itself, the engine controller 217 also executes the start process of the engine controller 217 itself (step S421). The start processing of the engine controller is completed in a short time, and the engine controller 217 waits after the start processing is completed until communication with the sub CPU 213 described later is executed in steps S415 and S423 (step S422).

The sub CPU 213 executes the startup process (steps S411 to S414, S511 to S512, S514 to S515) based on the instruction of the main CPU 203. Specifically, the sub CPU 213 boots the kernel which is the core part of the OS of the sub CPU 203 (steps S411 and S511), and the printer 106 and the scanner 107 are activated when the power mode of the MFP 101 is switched from the power saving mode to the normal mode. Among a plurality of device drivers for driving a plurality of devices such as the above, the device driver required for communication between the sub CPU 213 and the engine controller 217 (hereinafter, referred to as “essential device driver”) is preferentially started (step S412). , S512).

Normally, as shown in FIG. 6, when a plurality of device drivers are composed of device drivers other than the essential device drivers 601-603 and the essential device drivers 601-603 (hereinafter, referred to as "other device drivers") 604, when The required device drivers 601 to 603 and other device drivers 604 are randomly started. Therefore, any of the required device drivers 601 to 603 may be started last among all the device drivers (see FIG. 6A). The sub CPU 213 cannot communicate with the engine controller 217 unless the essential device drivers 601 to 603 are started. However, in the second recovery process, the essential device drivers 601 to 601 are required to execute the communication between the sub CPU 213 and the engine controller 217 at an early stage. The 603 is started in preference to the other device driver 604 (see FIG. 6B). Therefore, the activation of the essential device drivers 601 to 603 is completed before the other device drivers 604 are activated. The other device drivers include, for example, a device driver required for communication between the main CPU 203 and the sub CPU 213, a device driver that identifies and manages each component of the MFP 101, a device driver that controls the image processing processor 216, and the like. included.

Returning to FIGS. 4 and 5, when the essential device drivers 601 to 603 were started in preference to the other device drivers 604, the sub CPU 213 immediately executed communication with the engine controller 217 and was transferred by DMA from the main CPU 203. Various device information added to the binary data is transferred to the engine controller 217, and the status information of the engine controller 217 is acquired to determine whether or not the job can be executed (steps S415, S423, S513).

Next, the sub CPU 213 starts the essential device drivers 601 to 603, then starts the other device drivers 604 (steps S413 and S514), starts all the device drivers, and then performs virtual communication between the main CPU and the engine controller. Establish (steps S414, S515).

After that, the sub CPU 213 executes communication with the main CPU 203 using a predetermined application (steps S404, S416, S504, S516), and as a result of the determination in steps S415, S423, S513, when the job can be executed. , The sub CPU 213 notifies the main CPU 203 that the job can be executed. The main CPU 203 controls the supply of electric power to the operation display unit 104, and the main CPU 203, the sub CPU 213, and the engine controller 217 wait for a job to be input (steps S405, S417, S424, S505, S517). End the process.

According to the processes of FIGS. 4 and 5, among the plurality of device drivers for driving the plurality of devices activated when the power mode of the MFP 101 is switched from the power saving mode to the normal mode, the sub CPU 213 and the engine controller 217 Device drivers 601 to 603, which are indispensable for the communication of the above, are started in preference to the other device drivers 604 (steps S421 and S512). As a result, communication between the sub CPU 213 and the engine controller 217 is executed at an early stage, so that the engine controller 217 is required when switching the power mode from the power saving mode to the normal mode after the engine controller 217 finishes the start processing. The waiting time until receiving various device information which is information can be shortened, and thus the power mode can be quickly switched from the power saving mode to the normal mode.

The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device read the program. It can also be realized by the process to be executed. The present invention can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

101 MFP
213 sub CPU
217 Engine controller 601 to 603 Required device driver 604 Other device dry

Claims (15)

A first processor, a first storage means, a first substrate having a
A second substrate having a second processor and a second storage means,
Has an engine controller, which controls the device,
The first storage means is an image forming apparatus that stores the start program of the second processor and the information of the device .
According to what power supply to the first processor is started, said before starting processing of the second processor is started, the first of said second processor startup program stored in the storage means Further having a transmission means for transmitting the device information to the second storage means by DMA transfer .
The second processor according to the previous SL said second processor startup program transmitted to the second storage means, before the communication with the first processor is established, using the information of the device that received image forming apparatus characterized by initiating communication with the engine controller Te. The first processor releases the reset state of the second processor after the transmitting means transmits the start program of the second processor to the second storage means.
The image forming according to claim 1, wherein the second processor executes a start program of the second processor stored in the second storage means according to the release of the reset state. apparatus. The transmission unit, an image forming apparatus according to claim 1 or 2, characterized in that sending binary data of the startup program of the second processor including information of the device to the second storage means. The image forming apparatus according to any one of claims 1 to 3, wherein the second processor transmits the received information of the device to the engine controller. The transmission means is a normal state in which the image forming apparatus supplies power to the first processor and the second processor from a power saving state in which the image forming apparatus does not supply power to the first processor and the second processor. The image forming apparatus according to any one of claims 1 to 4, wherein the start program of the second processor and information on the device are transmitted to the second processor in accordance with the transition to. The claim is characterized in that the second processor activates a driver used for communication with the engine controller according to the activation program, and then activates another driver used for communication with the first processor. Item 2. The image forming apparatus according to any one of Items 1 to 5. The image forming apparatus according to claim 6, wherein the second processor starts communication with the engine controller using the driver before the activation process of the other driver is completed. A first processor, a first storage means, a first substrate having a
A second substrate having a second processor and a second storage means,
Has an engine controller, which controls the device,
The first storage means is an image forming apparatus that stores the start program of the second processor and the information of the device .
Before the start processing of the second processor is started , the start program of the second processor and the information of the device stored in the first storage means are transmitted to the second storage means by DMA transfer. Further has a means of transmission to
Before Stories second processor, the thus second start program of the second processor sent to the storage means, after starting the communication with the engine controller using information of the device which received the An image forming apparatus characterized by initiating communication with a first processor . Before SL first processor, after it said transmission means has transmitted a start program of the second processor in said second storage means, cancels the reset state of the second processor,
The image forming according to claim 8, wherein the second processor executes a start program of the second processor stored in the second storage means according to the release of the reset state. apparatus. The second processor is a device stored in the second storage means after the reset state is released and before communication between the second processor and the first processor is established . The image forming apparatus according to claim 9 , wherein the information is transmitted to the engine controller. The method according to any one of claims 8 to 10, wherein the transmitting means transmits binary data of a startup program of the second processor including information on the device to the second storage means. Image forming device. The transmission means is a normal state in which the image forming apparatus supplies power to the first processor and the second processor from a power saving state in which the image forming apparatus does not supply power to the first processor and the second processor. The image forming apparatus according to any one of claims 8 to 11, wherein the start program of the second processor and information on the device are transmitted to the second processor in accordance with the transition to. The claim is characterized in that the second processor activates a driver used for communication with the engine controller according to the activation program, and then activates another driver used for communication with the first processor. Item 2. The image forming apparatus according to any one of Items 8 to 12. A first processor, a first storage means, a first substrate having a
A second substrate having a second processor and a second storage means,
Has an engine controller, which controls the device,
The first storage means is a control method of an image forming apparatus that stores an activation program of the second processor and information of the device .
According to what power supply to the first processor is started, said before starting processing of the second processor is started, the first of said second processor startup program stored in the storage means A transmission step of transmitting the device information to the second storage means by DMA transfer , and
According to the previous SL said second processor startup program transmitted to the second storage means, a step of initiating communication with the engine controller by using the information of the device which second processor has received,
A method for controlling an image forming apparatus , which comprises a step of establishing communication with the first processor after the second processor starts communication with the engine controller . A first processor, a first storage means, a first substrate having a
A second substrate having a second processor and a second storage means,
Has an engine controller, which controls the device,
The first storage means is a control method of an image forming apparatus that stores an activation program of the second processor and information of the device .
Before the start processing of the second processor is started , the start program of the second processor and the information of the device stored in the first storage means are transmitted to the second storage means by DMA transfer. Transmission process and
A step in which the second processor starts communication with the engine controller using the received information of the device according to a start program of the second processor transmitted to the second storage means.
A control method for an image forming apparatus , comprising: a step of starting communication with the first processor after communication with the engine controller is started .

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