JP6802072B2 - Data input / output control device and control method - Google Patents

Description

The present invention relates to a data input / output control device and a control method, and more particularly to a data input / output control device and a control method in an environment in which a host and a plurality of terminals communicate serially.

In general, serial communication methods such as I2C (Inter-Integrated Circuit) communication method and SPI (Serial Peripheral Interface) communication method are widely used as signal communication methods within and between devices mounted on electronic devices. Has been done. In addition, such a serial communication method is also used in master-slave communication, and in this case, it is composed of a combination of at least one or more terminals and one or more hosts. For example, multiple DSPs (Digital Signal Processors), which are terminals-side devices mounted on a board that handles a large-scale system, are from multiple ROMs (Read Only Memory), which are host-side devices and hold the same data. A communication form for reading startup data is conceivable.

When there are multiple combinations of devices that perform serial communication between devices and each communicates the same data on a one-to-one basis, the device on the host side is used from the viewpoints of low power consumption, reduction of circuit scale, and reduction of the number of parts. It is desirable to reduce the number of.

Usually, as a method of reducing the number of devices in the serial communication method, the serial connection between the devices is realized by the bus connection method. In the bus connection method, a plurality of terminals are connected to one host on one transmission path, and the host communicates with each terminal in turn.

A communication system using such serial communication is disclosed in Patent Documents 1 to 3.

Patent Document 1 is a technology related to a communication system constructed so that communication between a sensor and a microprocessor can be performed not only by I2C communication but also by SPI communication. In a communication system using both an I2C device and an SPI device as a master, since the I2C communication and the SPI communication operate asynchronously, there is a possibility that the I2C communication signal and the SPI communication signal collide with each other. Therefore, Patent Document 1 is a communication system in which a selection circuit is provided in a communication system using both an I2C device and an SPI device as a master so that the I2C communication signal and the SPI communication signal do not collide with each other. To disclose.

Patent Document 2 discloses a serial communication system in which a plurality of slaves can be simultaneously controlled by a command issued by a master to a plurality of slaves for simultaneous multiple control by serial communication using an I2C bus. According to the technique disclosed in Patent Document 2, a control program composed of a plurality of functions is stored in each slave in advance, and a program step corresponding to the function of the control program to be executed by the master for the plurality of slaves is provided. , Specified via serial communication. Then, by simultaneously executing the designated program steps for each of the plurality of slaves, it is possible to simultaneously control the functions to be executed by the master for the plurality of slaves.

Patent Document 3 discloses a technique in which a parent node and a plurality of child nodes that are multi-drop-connected to the parent node via a communication line and receive a command signal perform serial communication by a polling / selection method. Patent Document 3 realizes a communication system in which a parent node and a plurality of child nodes having different communication speeds can efficiently communicate with each other. In the technique disclosed in Patent Document 3, the parent node stores information on the communication speed of each child node, and sets a higher priority in advance in order from the signal addressed to the child node having the faster communication speed. Then, the parent node transmits a signal to the transmission waiting signal stored in the buffer according to the transmission order set based on the priority, so that the signal addressed to the child node having a high communication speed is preferentially transmitted. Efficient communication is performed.

Japanese Unexamined Patent Publication No. 2016-4388 Japanese Unexamined Patent Publication No. 2008-217757 Japanese Unexamined Patent Publication No. 2010-258811

In the bus connection method in which multiple terminals are connected to one host on one transmission path, when the host performs serial communication with multiple terminals, the communication between the host and each terminal is a sequential process. .. Therefore, the host must wait for the completion of communication processing with the terminal being communicated, and a waiting time occurs before starting communication with the next terminal, and communication as the number of terminals connected to the host increases. There was a problem that the time required for the operation increased.

FIG. 1 is a block diagram showing a configuration example of a serial communication environment for explaining the subject of the present invention. For example, in the case of performing serial communication in a configuration in which a plurality of terminals 101 to 10n are connected to one host 200 by a bus as shown in FIG. 1, while the host 200 is communicating with the terminal 101, the other Terminals 102 to 10n cannot communicate with the host 200. Then, after waiting for the communication processing of the terminal 101 to be completed, the next terminal communicates with the host 200. Therefore, when the number of terminals connected to the host 200 increases, the processing time as a whole increases by the time required for the host 200 to communicate with one terminal as the number of terminals increases. This also applies to an environment in which a plurality of terminals transmit terminal data having the same content to one host and perform serial communication in which the host returns the host data having the same content to each terminal.

Patent Document 1 discloses a communication system in which both an I2C device and an SPI device are used as masters so that the I2C communication signal and the SPI communication signal do not collide with each other. However, Patent Document 1 does not mention shortening the processing time when a plurality of terminals and one host perform serial communication.

Patent Document 2 discloses a serial communication system that enables simultaneous control of a plurality of slaves from a master to shorten processing time. In Patent Document 2, the master instructs each slave in which the control program is stored in advance a program step corresponding to the function of the control program to be executed. Then, each of the plurality of slaves is configured to execute the instructed program step at the same time. However, the communication system disclosed in Patent Document 2 does not mention simultaneous communication from a plurality of slaves to one master direction, which is communication in the reverse direction.

Patent Document 3 transmits a transmission waiting signal stored in a buffer of a parent node with a priority according to the communication speed of the child node when communicating with a plurality of child nodes having different communication speeds from the parent node. Disclose the communication system. However, the communication system disclosed in Patent Document 3 does not mention simultaneous communication from a plurality of child nodes to one parent node and shortening of processing time, which is communication in the reverse direction.

According to the present invention, in an environment in which a plurality of terminals and one host perform serial communication with the same data, the overall processing time in communication between the host and each terminal is minimized. A data input / output control device and a control method that enable the above are provided.

In order to realize the above object, the data input / output control device according to one embodiment of the present invention includes a plurality of terminals that communicate with the outside using a serial communication method, and each of the terminals and data. One host that transmits and receives is connected, and only the terminal data that arrives first among the terminal data of the same content transmitted simultaneously by each of the terminals is transmitted to the host, and the terminal data is transmitted according to the terminal data. Data relay means that receives host data returned by the host, duplicates the received host data and distributes and outputs it, and the host data that is deployed corresponding to each of the terminals and is distributed and output by the data relay means. When the data is stored and a transmission instruction is received, the stored host data is transmitted to the connected terminal including a buffer memory means, and the data relay means distributes and outputs the host data to the respective terminals. It is characterized in that when it is stored in the corresponding buffer memory means and it is identified that the terminal data has arrived from all the terminals, the transmission instruction is output to the buffer memory means.

Further, the data input / output control method, which is another embodiment of the present invention, is the first of the terminal data having the same content transmitted simultaneously by each terminal of a plurality of terminals that communicate with the outside using the serial communication method. Only the terminal data arriving at is transmitted to the host, the host data returned by the host is received according to the terminal data, the received host data is duplicated and distributed and output, and corresponding to each of the terminals. The distributed and output host data is stored in the distributed buffer memory, the distributed and output host data is stored in the buffer memory corresponding to each terminal, and the terminal data is all the terminals. When it is identified that the data has arrived from, the host data stored in the buffer memory is transmitted to the connected terminal.

According to the present invention, in an environment in which a plurality of terminals and one host perform serial communication with the same data, the overall processing time in communication between the host and each terminal can be minimized.

It is a block diagram which shows the structural example of the serial communication environment for demonstrating the subject of this invention. It is a block diagram which shows the structural example of the data input / output control device of 1st Embodiment of this invention. It is a flow diagram explaining operation of the data input / output control method of 1st Embodiment of this invention. It is a block diagram which shows the structural example of the data input / output control device of the 2nd Embodiment of this invention. It is a block diagram which shows the structural example of the terminal data control circuit of the data input / output control device of 2nd Embodiment. It is a block diagram which shows the structural example of the host data control circuit of the data input / output control device of 2nd Embodiment. It is a flowchart which shows the operation which the terminal data control circuit transmits terminal data transmitted from a plurality of terminals to one host. It is a flowchart which shows the operation which the host data control circuit transmits the host data received from one host to a plurality of terminals. It is a block diagram which shows the structural example of the data input / output control device of the 3rd Embodiment of this invention.

The outline of the embodiment for carrying out the present invention will be described.

In a mode for carrying out the present invention, a data input / output control device as a data relay device is arranged between a plurality of terminals and one host that communicate with the outside using the same serial communication method. , Perform communication between those terminals and hosts. As the serial communication method, the case of the SPI method having two data lines, a transmission line and a reception line, will be described.

Further, in the communication applied in the embodiment of the present invention, the same content data is sent from all terminals to the host, and the response data from the host is also returned to all terminals with the same content data. To. For example, it is assumed that a plurality of terminals request startup data (data with the same contents) from the host when the power is started.

The embodiment is an example, and the disclosed device and method are not limited to the configuration of the following embodiment. In addition, the reference symbols attached to the figures are added for convenience as an example to assist understanding, and are not intended to be limited in any way. Further, the direction of the arrow in the drawing shows an example and does not limit the direction of the signal between blocks. The alternate long and short dash line in the figure indicates the control signal transmitted in the device.

(First Embodiment)
The configuration of the data input / output control device of the first embodiment will be described with reference to FIG.

The data input / output control device 30 of the present embodiment is a plurality of terminals 10 that communicate with the outside using a serial communication method, and one host that transmits / receives data to and from each terminal of the plurality of terminals 10. Connect with 20. When it is necessary to distinguish each of the plurality of terminals 10, the terminals 11, 12 to 1n will be described.

The data input / output control device 30 includes a data relay means 31 and a buffer memory means 32.

The data relay means 31 is connected to the respective terminals 11, 12 to 1n of the plurality of terminals 10 by a serial communication line. Further, the data relay means 31 is connected to the host 20 by a serial communication line.

The data relay means 31 transmits only the first arriving terminal data of the terminal data having the same contents transmitted simultaneously by the terminals 11, 12 to 1n of the plurality of terminals 10 to the host 20. Here, the terminals 11, 12 to 1n simultaneously transmit the terminal data, but the time for the terminal data to arrive at the data relay means 31 is slightly different depending on the variation of the transmission processing for each terminal and the position where the terminals are mounted. different. Of the terminal data whose arrival times are slightly different in this way, only the terminal data that arrives first is transmitted to the host 20.

Then, the data relay means 31 receives the host data returned by the host 20 in response to the terminal data, duplicates the received host data, and distributes and outputs the received host data.

The buffer memory means 32 is deployed corresponding to the respective terminals 11, 12 to 1n of the plurality of terminals 10, and stores the host data distributed and output by the data relay means 31. Further, when the buffer memory means 32 receives a transmission instruction, the buffer memory means 32 transmits the accumulated host data to the connected terminals 11, 12 to 1n.

Here, in the data relay means 31, the distributed output host data is stored in the buffer memory means 32 corresponding to each terminal 11, 12 to 1n, and the terminal data is stored in all the terminals 11 of the plurality of terminals 10. When it is identified that the arrival is from 12 to 1n, a transmission instruction is output to the buffer memory means 32.

Next, the operation of the data input / output control method of the first embodiment will be described with reference to FIG.

The data input / output control method of the first embodiment is realized by the data input / output control device 30 of the first embodiment executing each operation step of FIG.

Only the first terminal data of the terminal data of the same content transmitted by each terminal of a plurality of terminals communicating with the outside using the serial communication method is transmitted to the host (S101).

The host data returned by the host according to the terminal data is received, and the received host data is duplicated and distributed and output (S102).

The distributed and output host data is stored in the buffer memory deployed corresponding to each terminal (S103).

When the distributed output host data is stored in the buffer memory corresponding to each terminal and it is identified that the terminal data has arrived from all the terminals of a plurality of terminals, the host data stored in the buffer memory is stored. It is transmitted to the connected terminal (S104).

The data input / output control device of the present embodiment transmits to the host any one terminal data that arrives first from the terminal data transmitted simultaneously by each terminal of a plurality of terminals. Then, the host data returned by the host according to the terminal data is received, duplicated, and stored in the buffer memory deployed corresponding to each terminal. Then, the buffer memory is released by confirming the timing of transmitting the host data to each terminal. The timing at which the host data is transmitted to each terminal is the timing at which the host data is stored in each buffer memory and it is identified that the terminal data having slightly different arrival times has arrived from all the terminals.

As described above, in the present embodiment, in an environment in which a plurality of terminals and one host perform serial communication with the same data, the communication between the host and each terminal is performed without performing sequential processing by each terminal. The processing time as a whole can be minimized.

(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS. 4 to 8.

FIG. 4 is a block diagram showing a configuration example of the data input / output control device according to the second embodiment of the present invention.

The data input / output control device 40 of the second embodiment is the same as the data input / output control device 30 of the first embodiment, with a plurality of terminals 10 communicating with the outside using a serial communication method, respectively. Connects to one host 20 that sends and receives data to and from the terminal. When it is necessary to distinguish each of the plurality of terminals 10, the terminals 11, 12 to 1n will be described.

The data input / output control device 40 includes a terminal data control circuit 41, a host data control circuit 42, and a buffer memory circuit 43. Here, the terminal data control circuit 41 and the host data control circuit 42 have a configuration corresponding to the data relay means 31 in the first embodiment.

The terminal data control circuit 41 is connected to each of the terminals 11, 12 to 1n of the plurality of terminals 10 by a reception data line of a serial communication line, and is connected to the host 20 by a transmission data line of the serial communication line. The terminal data control circuit 41 asynchronously receives terminal data having the same contents from the terminals 11, 12 to 1n of the plurality of terminals 10, and transmits the first-come-first-served terminal data to the host 20. Here, "asynchronously receiving" means that the terminals 11, 12 to 1n simultaneously transmit terminal data, but the time of arrival at the terminal data control circuit 41 varies. This is because, as described above, the arrival time of the terminal data is slightly different depending on the variation of the transmission processing for each terminal and the position where the terminal is mounted.

Further, the terminal data control circuit 41 identifies the arrival status of the terminal data transmitted by the respective terminals 11, 12 to 1n, and confirms the completion of reception of the terminal data from all the terminals 11, 12 to 1n to notify the reception completion. Is output to the host data control circuit 42.

The host data control circuit 42 is connected to the host 20 by a reception data line of a serial communication line, and receives host data returned by the host 20 according to the terminal data.

The host data control circuit 42 duplicates the host data received from the host 20 according to the number of a plurality of terminals 10, and distributes and outputs the host data having the same contents.

The buffer memory circuit 43 includes a FIFO (First In First Out) buffer deployed corresponding to each of the terminals 11, 12 to 1n of the plurality of terminals 10. Each FIFO buffer is connected to the host data control circuit 42, and the host data distributed and output by the host data control circuit 42 is stored and stored in individual FIFO buffers.

The host data control circuit 42 outputs a transmission instruction to the buffer memory circuit 43 on condition that the distributed and output host data is stored in the respective FIFO buffers and the reception completion notification of the terminal data is received. .. The host data control circuit 42 may determine that the host data has been accumulated in the respective FIFO buffers by distributing and outputting the host data. Alternatively, the buffer memory circuit 43 may be configured to check the accumulation status of each FIFO buffer and issue an accumulation completion notification to the host data control circuit 42 when the accumulated data amount of all the FIFO buffers has increased by the same amount. It doesn't matter.

The buffer memory circuit 43 that has received the transmission instruction transmits the host data stored in the individual FIFO buffers to the respective terminals 11, 12 to 1n connected by the transmission data line of the serial communication line.

In this way, the data input / output control device 40 transmits the terminal data first arrived at the terminal data control circuit 41 to the host 20, and when it receives the host data which is the return data for the terminal data, it generates a copy thereof. Distribute output. The distributed and output host data is temporarily stored in the FIFO buffer corresponding to each terminal. Then, when it is confirmed that the terminal data has been received from all the terminals 11, 12 to 1n of the plurality of terminals 10, the FIFO buffer is released and the stored host data is transmitted to each terminal all at once.

An example of using the data input / output control device 40 described above will be briefly described.

When the power is turned on, the terminals 11, 12 to 1n of the plurality of terminals 10 start communication at the same time, and the memory addresses 100 to 101, 102, etc. of the memory provided by the host 20 with respect to the host 20 are in order. The case of reading data will be described as an example.

After activation, each terminal transmits terminal data including a read flag and address information (address 100) to the host 20. The terminal data control circuit 41 transmits the first terminal data among the terminal data received from each terminal to the host 20 as it is. Further, the terminal data control circuit 41 counts until the number of arrivals of terminal data transmitted by each terminal reaches the total number of connected terminals, and when the number of arrivals = the number of terminals, the terminal is sent to the host data control circuit 42. Output data reception completion notification. In addition, terminal data other than the first-come-first-served basis is discarded.

The host 20 executes a process based on the terminal data received on a first-come-first-served basis, reads the data stored in the designated memory address (address 100), and returns the data as host data to the terminal side.

The host data control circuit 42 duplicates the host data received from the host 20 according to the number of a plurality of terminals 10 and distributes and outputs the host data. The distributed output host data is stored in each FIFO buffer of the buffer memory circuit 43 connected to the host data control circuit 42. The host data control circuit 42 outputs a transmission instruction and releases all the FIFO buffers when the accumulation of host data in all the FIFO buffers is completed and the terminal data reception completion notification is received from the terminal data control circuit 41. As a result, the host data stored in the FIFO buffer is transmitted to each terminal.

From the viewpoint of each of the plurality of terminals 10 and the host 20, the above operation is the same as that of normal synchronous serial communication. Then, each terminal sequentially repeats the operation of transmitting the terminal data including the read flag and the address information (address 101) to be read next to the host 20 until the reading of the necessary data is completed.

As described above, in the present embodiment, the host 20 uses the data input / output control device 40 to control the data of one terminal among the plurality of terminals 10 without depending on the number of connected terminals. You just have to do the processing. Therefore, by configuring as in the present embodiment, the communication processing time between the plurality of terminals 10 and one host 20 is taken into consideration in consideration of the time for duplicating the host data and adjusting the timing for releasing the FIFO buffer. Can be significantly shortened.

Subsequently, the terminal data control circuit 41 and the host data control circuit 42 will be described.

FIG. 5 is a block diagram showing a configuration example of the terminal data control circuit 41 of the data input / output control device 40.

The terminal data control circuit 41 is configured to include a terminal data interface unit 411, a host data interface unit 412, a terminal data selection unit 413, and a terminal data reception completion notification unit 414.

The terminal data interface unit 411 is provided corresponding to each terminal 11, 12 to 1n of a plurality of terminals 10, and is connected to each terminal by a reception data line of a serial communication line. The terminal data interface unit 411 outputs the terminal data received from the corresponding terminal to the terminal data selection unit 413. Further, when the terminal data interface unit 411 receives the terminal data from the corresponding terminal, it outputs a terminal data reception notification indicating that the terminal data transmitted by the terminal has arrived to the terminal data reception completion notification unit 414. ..

As described above, the arrival time of the terminal data transmitted by each terminal varies depending on the variation of the startup time for each terminal and the mounting position of the terminal.

The host data interface unit 412 is connected to the host 20 by the transmission data line of the serial communication line.

The terminal data selection unit 413 inputs terminal data received from terminals 11, 12 to 1n of each of the plurality of terminals 10, selects one of them, and outputs the terminal data to the host 20 via the host data interface unit 412. To do. As described above, since all the terminal data transmitted by each terminal has the same content, any one terminal data may be transmitted to the host 20. The terminal data selection unit 413 selects and outputs the first-come-first-served terminal data from the terminal data transmitted by the terminals 11, 12 to 1n of the plurality of terminals 10. Note that other terminal data that arrives after selecting and outputting the first-come-first-served terminal data is discarded.

The terminal data reception completion notification unit 414 can know the arrival of terminal data transmitted by the terminals 11, 12 to 1n of the plurality of terminals 10 by the terminal data reception notification output by the corresponding terminal data interface unit 411. it can. Then, by receiving the terminal data reception notification from all the terminals 11, 12 to 1n connected to the terminal data interface unit 411, it is identified that the terminal data from all the terminals 11, 12 to 1n has arrived. .. The terminal data reception completion notification unit 414 that has identified that the terminal data from all the terminals 11, 12 to 1n has arrived outputs the terminal data reception completion notification to the host data control circuit 42 to notify the fact. The terminal data reception completion notification unit 414 grasps the number of terminals connected to the terminal data interface unit 411, and compares the number of terminals that have received the terminal data with the number of terminals 11, 12 to 1n. Identifies that the terminal data of is arrived.

Further, the terminal data reception completion notification unit 414 receives the reset notification from the host data control circuit 42. As will be described later, this reset notification is a related circuit in preparation for the next communication after the host data control circuit 42 outputs a transmission instruction to the buffer memory circuit 43 described with reference to FIG. 4 to release all the FIFO buffers. Is to reset. Therefore, the terminal data reception completion notification unit 414 resets the count of the terminal data reception notification, and also sends a reset notification to the terminal data selection unit 413. Upon receiving the reset notification, the terminal data selection unit 413 resets the information regarding the first-come-first-served terminal data selection and prepares for the selection of the terminal data to be transmitted next.

Next, the host data control circuit 42 will be described.

FIG. 6 is a block diagram showing a configuration example of the host data control circuit 42 of the data input / output control device 40.

The host data control circuit is configured to include a host data interface unit 421, a host data duplication unit 422, and a host data transmission control unit 423.

The host data interface unit 421 is connected to the host 20 by the reception data line of the serial communication line.

The host data duplication unit 422 duplicates the host data received from the host 20 via the host data interface unit 421 by the number of all connected terminals and distributes and outputs the host data. Here, the host data received from the host 20 is the return data for the terminal data selected by the terminal data control circuit 41 and transmitted to the host 20.

The host data distributed and output by the host data duplication unit 422 is stored and stored in the FIFO buffer corresponding to each terminal of the buffer memory circuit 43 described with reference to FIG.

The host data duplication unit 422 outputs a distribution output completion notification when the distribution output of the duplicated host data is completed. Here, it is considered that the host data is accumulated in each FIFO buffer by distributing and outputting the host data. Of course, as described above, when the buffer memory circuit 43 is configured to receive the storage completion notification of the FIFO buffer, the distribution output completion notification may be output by receiving the storage completion notification from the buffer memory circuit 43. ..

The host data transmission control unit 423 receives the terminal data reception completion notification from the terminal data reception completion notification unit 414 of the terminal data control circuit 41 described with reference to FIG. Further, the host data transmission control unit 423 receives a distribution output completion notification from the host data duplication unit 422 indicating that the distribution output of the duplicated host data has been completed.

When the host data transmission control unit 423 receives the distribution output completion notification and receives the terminal data reception completion notification, the host data transmission control unit 423 outputs a transmission instruction to the buffer memory circuit 43 described with reference to FIG. 4 to output all the FIFO buffers. To release. As a result, the host data stored in the FIFO buffer is transmitted to each terminal.

After outputting the transmission instruction and releasing all the FIFO buffers, the host data transmission control unit 423 deletes the received terminal data reception completion notification and distribution output completion notification, and sends a reset notification to the terminal data control circuit 41. .. This resets the related circuit in preparation for the next communication, as described above.

The operations of the terminal data control circuit 41 and the host data control circuit 42 described above will be described with reference to FIGS. 7 and 8, respectively.

FIG. 7 is a flowchart showing an operation in which the terminal data control circuit 41 transmits terminal data transmitted from a plurality of terminals to one host.

Each of the terminals 11, 12 to 1n of the plurality of terminals 10 starts communication asynchronously and transmits terminal data to the host 20. For example, assuming that data reading processing is performed in order from address 100 to address 101, address 102, etc. of the memory provided in the host 20 when the power is turned on, the read flag and address information (address 100) are included as terminal data. Send the data.

Each terminal starts communication at the same time, but the time for each terminal data to arrive at the terminal data control circuit 41 is slightly different depending on the variation of the startup time for each terminal and the mounting position of the terminal. The terminal data control circuit 41 receives the terminal data transmitted by the terminals 11, 12 to 1n of the plurality of terminals 10 in the order of arrival (S201).

The terminal data control circuit 41 confirms whether or not the received terminal data is first-come-first-served (S202).

When the received terminal data is the first-come-first-served one (S202, Yes), the terminal data control circuit 41 transmits the first-come-first-served terminal data to the host 20 as it is (S203). Then, the process returns to step S201, and subsequent terminal data is sequentially received.

If the received terminal data is not the first-come-first-served one in the process of step S202 (S202, No), the terminal data control circuit 41 confirms whether or not the received terminal data is the last-arrival (S204). That is, the terminal data control circuit 41 counts until the number of arrivals of terminal data transmitted by each terminal reaches the total number of connected terminals, and when the number of arrivals = the number of terminals, the last terminal data arrives. Identifies that the was received.

If the received terminal data is not the last one in the process of step S204 (S204, No), the terminal data control circuit 41 discards the received terminal data (S205), returns to step S201, and succeeds the terminal. Receive data sequentially.

In the process of step S204, when the received terminal data is the last one (S204, Yes), the terminal data control circuit 41 inputs the terminal data from all the terminals 11, 12 to 1n of the plurality of terminals 10. A terminal data reception completion notification indicating that the data has been received is output (S206). The last received terminal data is discarded in step S206.

Subsequently, the operation of the host data control circuit 42 will be described.

FIG. 8 is a flowchart showing an operation in which the host data control circuit 42 transmits the host data received from one host 20 to the respective terminals 11, 12 to 1n of the plurality of terminals 10.

The host 20 executes processing based on the first-come-first-served terminal data received from the terminal data control circuit 41, reads the data stored in the designated memory address (address 100), and controls the host data as host data. It transmits to the circuit 42.

The host data control circuit 42 receives the host data returned from the host 20 (S301).

Then, the host data control circuit 42 duplicates the received host data and transmits it to each FIFO buffer of the buffer memory circuit 43 (S302). The host data is duplicated for each of the terminals 11, 12 to 1n of the plurality of terminals 10, and is distributed and output to the corresponding FIFO buffer. In step S303, it is confirmed whether or not the host data has been accumulated in all the FIFO buffers.

The processes of steps S302 and S303 are executed by the host data duplication unit 422, and when the distribution output of the duplicated host data is completed, a distribution output completion notification is output. As described above, it is considered that the host data has been accumulated in each FIFO buffer when the distribution output of the host data is completed. Of course, when the buffer memory circuit 43 is configured to receive the storage completion notification of the FIFO buffer, it can be confirmed by the storage completion notification from the buffer memory circuit 43.

After confirming that the host data has been accumulated in all the FIFO buffers (S303, Yes), the host data control circuit 42 confirms whether or not the terminal data reception completion notification has been received from the terminal data control circuit 41 (S304).

If the terminal data reception completion notification has not yet been received in step S304 (S304, No), the terminal data reception completion notification from the terminal data control circuit 41 is awaited.

When the terminal data reception completion notification is received (S304, Yes), the host data control circuit 42 outputs a transmission instruction and releases all the FIFO buffers (S305). As a result, the host data stored in the FIFO buffer is transmitted to each terminal. Further, in step S305, after outputting the transmission instruction to release all the FIFO buffers, the received terminal data reception completion notification and distribution output completion notification are deleted, and the reset notification is sent to the terminal data control circuit 41. As described above, the reset notification resets the related circuit in preparation for the next communication.

A series of communication is completed when all of the terminals 11, 12 to 1n of the plurality of terminals 10 receive the host data from the corresponding FIFO buffers.

That is, each terminal reads and returns the host data, which is the data read and returned by the host 20 from the specified memory address (address 100), with respect to the terminal data including the transmitted read flag and address information (address 100). Receive. Then, each terminal transmits the terminal data including the read flag and the address information (address 101) to be read next to the host 20, and sequentially repeats until the reading of the necessary data is completed to execute the next and subsequent communications. ..

In the above description, it is confirmed in step S303 whether or not the host data is accumulated in all the FIFO buffers, and in step S304, the reception of the terminal data reception completion notification from the terminal data control circuit 41 is confirmed. However, the order of these steps can be reversed. That is, the reception of the terminal data reception completion notification from the terminal data control circuit 41 may be confirmed, and then it may be confirmed whether or not the host data has been accumulated in all the FIFO buffers. The host data control circuit 42 outputs a transmission instruction when the storage of the host data in all the FIFO buffers is completed and the reception completion notification is received from the terminal data control circuit 41.

As described above, when serial communication is performed between a plurality of terminals and one host, sequential processing is performed between each terminal and the host, and the communication time as a whole increases as the number of terminals increases. It increased by the number of terminals. For example, assuming that the total communication time between a plurality of terminals and one host is T, the time for the host to communicate with one terminal is S, and the number of terminals is N, sequential processing is performed. , T = S × N communication time was required.

On the other hand, by using the data input / output control device of the present embodiment, the host may process the terminal data of one terminal among the plurality of terminals. Therefore, the required communication time can be expressed as T = S × 1 + (data processing time in the data input / output control device).

That is, when the number N of terminals increases, the communication time T as a whole increases in proportion to the number of terminals when performing sequential processing, whereas in the present embodiment, it does not depend on the number N of terminals. It can be said that the communication time T as a whole is constant. Further, since each terminal can perform communication without worrying about the timing regardless of the communication status of other terminals, it can contribute to the simplification of the control circuit and the like in the terminal. Further, since the host only needs to process the data of one terminal among the plurality of terminals, it can contribute to the reduction of the host load.

As described above, in the present embodiment, in an environment in which a plurality of terminals and one host perform serial communication with the same data, the communication between the host and each terminal is performed without performing sequential processing by each terminal. The processing time as a whole can be minimized.

(Third Embodiment)
Next, a third embodiment will be described with reference to FIG.

FIG. 9 is a block diagram showing a configuration example of the data input / output control device according to the third embodiment of the present invention.

The data input / output control device 50 of the third embodiment has a configuration including an operation clock supply circuit 54 in addition to the data input / output control device 40 of the second embodiment shown in FIG.

Further, the operating speeds of the terminals 11, 12 to 1n of the plurality of terminals 10 connected to the data input / output control device 50 by the serial communication line are configured to be different. Then, it is assumed that the operating speed between the data input / output control device 50 and the host 20 is set to the slowest operating speed in accordance with the operating speed of the terminal on the low speed side.

The operation clock supply circuit 54 supplies each FIFO buffer of the buffer memory circuit 53 with an operation clock signal of the operation speed of the corresponding terminal.

Since other configurations are the same as the configurations of the functional unit blocks described in the second embodiment, their description will be omitted. Further, the operation in which the terminal data control circuit 51 receives the terminal data from the respective terminals 11, 12 to 1n of the plurality of terminals 10 and transmits the first-come-first-served terminal data to the host 20 is also an operation of the second embodiment. Since they are the same, the description of the related operation is omitted. Here, the operation of the host data control circuit 52 receiving host data from the host 20 will be described.

The host data received from the host 20 is distributed by the host data control circuit 52, and is stored and stored in each FIFO buffer of the buffer memory circuit 53.

The host data control circuit 52 stores host data in all FIFO buffers, and when it receives a terminal data reception completion notification from the terminal data control circuit 51, it outputs a transmission instruction to release all FIFO buffers.

As a result, the host data is transmitted to each terminal, and at that time, in each FIFO buffer, the host data is replaced with the operation clock signal corresponding to the operation speed of each terminal supplied from the operation clock supply circuit 54. To each terminal.

Therefore, according to the data input / output control device 50 of the present embodiment, even if the operating speeds of the respective terminals 11, 12 to 1n of the plurality of terminals 10 and the one host 20 are different, the host 20 can perform processing according to the operating speed of the slowest terminal. Then, when the FIFO buffer is output, the host data can be transmitted at the operating speed of each terminal by processing the output by substituting the operating clock signal corresponding to the operating speed of each terminal supplied by the operating clock supply circuit 54. it can.

As described above, in the present embodiment, in an environment in which a plurality of terminals and one host perform serial communication with the same data, the communication between the host and each terminal is performed without performing sequential processing by each terminal. The processing time as a whole can be minimized. Moreover, even if the operating speeds of the terminals are different, the host can communicate without adjusting to the operating speeds of the respective terminals.

The data input / output control device of each of the above-described embodiments is realized by a hardware configuration similar to that of a general computer device, which performs arbitrary processing by causing a CPU (Central Processing Unit) to execute a computer program. Is also good. That is, the CPU loads the program stored in the auxiliary storage unit composed of the non-volatile memory or the like into the main storage unit such as the RAM (Random Access Memory) and executes the data input / output control device described above. Each function of may be realized by software.

10, 11, 12, 1n terminal 101, 102, 10n terminal 20, 200 Host 30, 40, 50 Data input / output control device 31 Data relay means 32 Buffer memory means 41, 51 Terminal data control circuit 42, 52 Host data control circuit 43, 53 Buffer memory circuit 54 Operation clock supply circuit 411 Terminal data interface unit 412, 421 Host data interface unit 413 Terminal data selection unit 414 Terminal data reception completion notification unit 422 Host data replication unit 423 Host data transmission control unit

Claims (10)

Multiple terminals that communicate with the outside using the serial communication method are connected to each terminal and one host that transmits and receives data, and the terminal data of the same content transmitted by each terminal at the same time A data relay means that transmits only the terminal data that arrives first to the host, receives the host data returned by the host according to the terminal data, duplicates the received host data, and distributes and outputs the data. ,
A buffer memory that is deployed corresponding to each terminal, accumulates the host data distributed and output by the data relay means, and when receiving a transmission instruction, transmits the accumulated host data to the connected terminal. With means,
When the data relay means identifies that the distributed and output host data is stored in the buffer memory means corresponding to each terminal and that the terminal data has arrived from all the terminals, the buffer memory means A data input / output control device characterized by outputting the transmission instruction to. The data relay means
The reception data lines from the plurality of terminals are connected to receive the terminal data having the same contents from each terminal, and only the terminal data that arrives first is transmitted via the transmission data line connected to the host. A terminal data control circuit that outputs a terminal data reception completion notification indicating that the terminal data has arrived from all the terminals when the terminal data is received from all the terminals of the plurality of terminals.
When the reception data line from the host is connected and the host data is received from the host, the host data is duplicated and distributed and output to the buffer memory means, and the terminal data reception completion notification output by the terminal data control circuit is notified. The data input / output control device according to claim 1, further comprising a host data control circuit that outputs the transmission instruction to the buffer memory means when the data is received. The terminal data control circuit
Terminal data that is deployed corresponding to each terminal of the plurality of terminals, connects a reception data line from the terminal, detects reception of the terminal data transmitted by the terminal, and outputs a terminal data reception notification. Interface part and
A host data interface unit that connects the transmission data line to the host,
A terminal data selection unit that receives the terminal data via the terminal data interface unit, selects only the terminal data that arrives first, and transmits the selected terminal data via the host data interface unit.
Terminal data that receives the terminal data reception notification output by each terminal data interface unit and outputs the terminal data reception completion notification when it is identified that the terminal data has been received from all the terminals of the plurality of terminals. Reception completion notification unit and
The data input / output control device according to claim 2, wherein the data input / output control device is provided. The host data control circuit
A host data interface unit that connects the reception data line from the host,
When the host data is received from the host, the host data is duplicated and distributed and output to the buffer memory means, and a notification is notified that the distributed and output host data is stored in the buffer memory means corresponding to each terminal. The host data replication unit that outputs the distribution output completion notification,
The data according to claim 2 or 3, further comprising a host data transmission control unit that outputs the transmission instruction to the buffer memory means when the distribution output completion notification and the terminal data reception completion notification are received. Input / output control device. When the host data transmission control unit outputs the transmission instruction to the buffer memory means, the terminal data reception completion notification and the distribution output completion notification are deleted, and the terminal data from each terminal of the plurality of terminals is deleted. The data input / output control device according to claim 4, wherein a reset notification instructing the reset of information regarding the arrival of the data is output to the terminal data control circuit. The buffer memory means provided corresponding to each terminal of the plurality of terminals is further provided with an operation clock supply circuit for supplying an operation clock signal of the corresponding operation speed of the terminal.
The operating speed with the host is set to the slowest operating speed of the terminal.
The buffer memory means, when receiving the transmission instruction, transmits the accumulated host data by transferring it to an operation clock signal corresponding to the operation speed of the connected terminal. The data input / output control device according to any one of claims 5. Of the terminal data of the same content transmitted simultaneously by each terminal of a plurality of terminals that communicate with the outside using the serial communication method, only the terminal data that arrives first is transmitted to the host.
The host data returned by the host is received according to the terminal data, and the received host data is duplicated and distributed and output.
The host data distributed and output is stored in the buffer memory deployed corresponding to each terminal.
When the distributed and output host data is stored in the buffer memory corresponding to each terminal and it is identified that the terminal data has arrived from all the terminals, the host data stored in the buffer memory is identified. A data input / output control method, characterized in that the data is transmitted to the connected terminal. Upon receiving the terminal data from each of the plurality of terminals
Detects the reception of the terminal data transmitted by each of the terminals and outputs a terminal data reception notification.
Based on the terminal data reception notification, a terminal data reception completion notification indicating that the terminal data has arrived from all the terminals of the plurality of terminals is output.
Upon receiving the host data returned by the host in response to the terminal data
When the host data is received from the host, the host data is duplicated, distributed to each of the buffer memories, and output.
A distribution output completion notification is output to notify that the distributed output host data has been stored in the buffer memory corresponding to each terminal.
A claim characterized in that when both the terminal data reception completion notification and the distribution output completion notification are output, the host data stored in the respective buffer memories is transmitted to the connected terminal. Item 7. The data input / output control method according to Item 7. When the host data stored in each of the buffer memories is transmitted to the connected terminal, the output terminal data reception completion notification and the distribution output completion notification are deleted, and each of the plurality of terminals is deleted. The data input / output control method according to claim 8, wherein the information regarding the arrival of the terminal data from the terminal is reset. The operation clock signal of the operation speed of the corresponding terminal is supplied to the buffer memory provided corresponding to each terminal of the plurality of terminals.
The operating speed with the host is set to the slowest operating speed of the terminal.
When transmitting the host data stored in the buffer memory to the connected terminal, the host data is transmitted by superimposing it on an operation clock signal corresponding to the operating speed of the connected terminal. The data input / output control method according to any one of claims 7 to 9, wherein the data input / output control method is characterized.

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