JP6800092B2 - Transistors and display devices - Google Patents

Description

The present invention relates to a product, a method, or a manufacturing method. Alternatively, the present invention relates to a process, machine, manufacture, or composition (composition of matter). In particular, one aspect of the present invention relates to a metal oxide or a method for producing the metal oxide. Alternatively, one aspect of the present invention relates to a semiconductor device, a display device, a liquid crystal display device, a light emitting device, a power storage device, a storage device, a method for driving them, or a method for manufacturing them.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic unit, and a storage device are one aspect of a semiconductor device. An image pickup device, a display device, a liquid crystal display device, a light emitting device, an electro-optical device, a power generation device (including a thin-film solar cell, an organic thin-film solar cell, etc.), and an electronic device may have a semiconductor device.

In-Zn-Ga-O-based oxides, In-Zn-Ga-Mg-O-based oxides, In-Zn-O-based oxides, In-Sn-O-based oxides, In-O-based oxides, In An electric field effect transistor having an amorphous oxide which is either a −Ga—O oxide or a Sn—In—Zn—O oxide is disclosed (see, for example, Patent Document 1). ..

Further, in Non-Patent Document 1, a structure having a two-layer laminated metal oxide of an In-Zn-O-based oxide and an In-Ga-Zn-O-based oxide as an active layer of a transistor has been studied. There is.

Japanese Patent No. 5118810

John F. Wager, "Oxide TFTs: A Progress Report", Information Display 1/16, SID 2016, Jan / Feb 2016, Vol. 32, No. 1, p. 16-21

In Patent Document 1, In-Zn-Ga-O-based oxide, In-Zn-Ga-Mg-O-based oxide, In-Zn-O-based oxide, In-Sn-O-based oxide, In-O The active layer of the transistor is formed by using an amorphous oxide which is one of a system oxide, an In—Ga—O system oxide, and a Sn—In—Zn—O system oxide. In other words, the active layer of the transistor has an amorphous oxide of any one of the above oxides. When the active layer of the transistor is composed of any one of the above amorphous oxides, there is a problem that the on-current, which is one of the electrical characteristics of the transistor, becomes low. Alternatively, when the active layer of the transistor is composed of any one of the above amorphous oxides, there is a problem that the reliability of the transistor deteriorates.

Further, in Non-Patent Document 1, in a channel-protected bottom gate type transistor, a channel is formed by stacking two layers of In-Zn oxide and In-Ga-Zn oxide as the active layer of the transistor. By setting the thickness of the In-Zn oxide to 10 nm, high field effect mobility (μ = 62 cm ² V ^-1 s ^-1 ) is realized. On the other hand, the S value (also referred to as Subthreshold Swing, SS), which is one of the transistor characteristics, is as large as 0.41 V / decade. Further, the threshold voltage (also referred to as Vth), which is one of the transistor characteristics, is -2.9V, which is a so-called normally-on transistor characteristic.

In view of the above problems, one aspect of the present invention is to provide a novel metal oxide. Alternatively, one aspect of the present invention is to impart good electrical characteristics to a semiconductor device. Alternatively, one of the issues is to provide a highly reliable semiconductor device. Alternatively, one of the issues is to provide a semiconductor device having a new configuration. Alternatively, one of the issues is to provide a display device having a new configuration.

The description of these issues does not prevent the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. Issues other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract issues other than these from the description of the description, drawings, claims, etc. Is.

One aspect of the present invention is a metal oxide having a plurality of energy bandwidths, and the metal oxide has a region in which the lower end of the conduction band of the energy band is low and a region in which the lower end of the conduction band of the energy band is high. However, the region where the lower end of the conduction band is low is a metal oxide having more carriers than the region where the lower end of the conduction band is high.

Another aspect of the present invention is a metal oxide having a plurality of energy bandwidths, wherein the metal oxide has a region where the lower end of the conduction band of the energy band is low and a region where the lower end of the conduction band of the energy band is high. The region where the lower end of the conduction band is low has more carriers than the region where the lower end of the conduction band is high, and the region where the lower end of the conduction band is high is a metal oxide which is more intrinsic than the region where the lower end of the conduction band is low.

Another aspect of the present invention is a metal oxide having a plurality of energy bandwidths, wherein the metal oxide has a region where the lower end of the conduction band of the energy band is low and a region where the lower end of the conduction band of the energy band is high. The region where the lower end of the conduction band is low has more carriers than the region where the lower end of the conduction band is high, and the region where the lower end of the conduction band is low and the region where the lower end of the conduction band is high have different conduction bands. Is.

In the above embodiment, the regions where the lower end of the conduction band is high are In, Zn, Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, It is preferable to have any one or more selected from Mg, V, Be, and Cu.

According to one aspect of the present invention, a novel metal oxide can be provided. Alternatively, according to one aspect of the present invention, good electrical characteristics can be imparted to the semiconductor device. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device having a new configuration can be provided. Alternatively, a display device having a new configuration can be provided.

The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not necessarily have to have all of these effects. It should be noted that the effects other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.

Conceptual diagram of the composition of metal oxides. The transistor and the schematic diagram explaining the distribution of the energy level in the transistor. The figure explaining the model of the schematic band diagram in a transistor. The figure explaining the model of the schematic band diagram in a transistor. Top view and sectional view explaining a semiconductor device. Top view and sectional view explaining a semiconductor device. A cross-sectional view illustrating a semiconductor device. The cross-sectional view explaining the manufacturing method of the semiconductor device. The cross-sectional view explaining the manufacturing method of the semiconductor device. The cross-sectional view explaining the manufacturing method of the semiconductor device. Top view and sectional view explaining a semiconductor device. Top view and sectional view explaining a semiconductor device. Top view and sectional view explaining a semiconductor device. Top view and sectional view explaining a semiconductor device. The figure explaining the range of the atomic number ratio of the metal oxide which concerns on this invention. The figure explaining the configuration example of the display panel. The figure explaining the configuration example of the display panel. The figure explaining the measurement result of the XRD spectrum of the sample which concerns on an Example. The figure explaining the cross-sectional TEM image of the sample which concerns on an Example, and the electron beam diffraction pattern. The figure explaining the method of deriving the rotation angle of a hexagon. The figure explaining the plane TEM image and the image analysis image of the sample which concerns on Example. The figure explaining the TEM image of the sample which concerns on Example, and EDX mapping. The figure explaining the TEM image of the sample which concerns on Example, and EDX mapping. The graph of the Id-Vg characteristic of the sample which concerns on an Example. The figure explaining the Id-Vg characteristic and the Id-Vd characteristic of a transistor. The figure explaining the Id-Vg characteristic and mobility curve (linear / saturation) calculated from GCA.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different embodiments, and that the embodiments and details can be variously changed without departing from the spirit and scope thereof. .. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings.

In addition, the ordinal numbers "first", "second", and "third" used in the present specification are added to avoid confusion of the components, and are not limited numerically. I will add it.

Further, in the present specification, terms indicating the arrangement such as "above" and "below" are used for convenience in order to explain the positional relationship between the configurations with reference to the drawings. Further, the positional relationship between the configurations changes appropriately depending on the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification, and can be appropriately paraphrased according to the situation.

Further, in the present specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. Then, a channel forming region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and between the source and drain via the channel forming region. It is possible to pass an electric current through. In the present specification and the like, the channel formation region means a region in which a current mainly flows.

Further, the functions of the source and the drain may be interchanged when transistors having different polarities are adopted or when the direction of the current changes in the circuit operation. Therefore, in the present specification and the like, the terms source and drain can be used interchangeably.

Further, in the present specification and the like, "electrically connected" includes a case where they are connected via "something having some kind of electrical action". Here, the "thing having some kind of electrical action" is not particularly limited as long as it enables the exchange of electric signals between the connection targets. For example, "things having some kind of electrical action" include electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

Further, in the present specification and the like, the silicon nitride film refers to a film having a higher oxygen content than nitrogen in its composition, and the silicon nitride film has a nitrogen content higher than oxygen in its composition. Refers to a film with a lot of oxygen.

Further, in the present specification and the like, when explaining the structure of the invention using drawings, reference numerals indicating the same may be commonly used between different drawings.

Further, in the present specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of −30 ° or more and 30 ° or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

Further, in the present specification and the like, the term "membrane" and the term "layer" can be interchanged with each other in some cases. For example, it may be possible to change the term "conductive layer" to the term "conductive layer". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

Even when the term "semiconductor" is used, for example, if the conductivity is sufficiently low, it may have characteristics as an "insulator". In addition, the boundary between "semiconductor" and "insulator" is ambiguous, and it may not be possible to strictly distinguish between them. Therefore, the "semiconductor" described in the present specification may be paraphrased as an "insulator". Similarly, the "insulator" described herein may be paraphrased as a "semiconductor."

In addition, in this specification and the like, normally-on means that it is in the on state when the electric potential is not applied by the power source (0V). For example, the normally-on characteristic may refer to an electrical characteristic in which the threshold voltage becomes negative when the voltage applied to the gate of the transistor is 0V.

In the present specification and the like, In: Ga: Zn = 4: 2: 3 or its vicinity means that when In is 4, Ga is 1 or more and 3 or less (1 ≦ Ga ≦) with respect to the total number of atoms. 3), and Zn is 2 or more and 4 or less (2 ≦ Zn ≦ 4). Further, In: Ga: Zn = 5: 1: 6 or its vicinity means that when In is 5, Ga is greater than 0.1 and 2 or less (0.1 <Ga ≦ 2) with respect to the total number of atoms. ), And Zn is 5 or more and 7 or less (5 ≦ Zn ≦ 7). Further, In: Ga: Zn = 1: 1: 1 or its vicinity means that when In is 1, Ga is greater than 0.1 and 2 or less (0.1 <Ga ≦ 2) with respect to the total number of atoms. ), And Zn is greater than 0.1 and 2 or less (0.1 <Zn ≦ 2).

(Embodiment 1)
In the present embodiment, a metal oxide which is one aspect of the present invention will be described.

The metal oxide of one aspect of the present invention preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to them, element M (element M is gallium, aluminum, silicon, boron, yttrium, copper, vanadium, berylium, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, It may contain one or more selected from tantalum, tungsten, magnesium and the like.

Moreover, it is preferable that the metal oxide of one aspect of the present invention has nitrogen. Specifically, in the metal oxide of one aspect of the present invention, the nitrogen concentration obtained by SIMS is 1 × 10 ¹⁶ atoms / cm ³ or more, preferably 1 × 10 ¹⁷ atoms / cm ³ or more 2 × 10 ²² atoms. / cm ³ it may be less. When nitrogen is added to the metal oxide, the band gap tends to be narrowed and the conductivity tends to be improved. Therefore, in the present specification and the like, the metal oxide according to one aspect of the present invention also includes a metal oxide to which nitrogen or the like is added. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

Here, consider the case where the metal oxide has indium, the element M, and zinc. The terms of the atomic number ratios of indium, element M, and zinc contained in the metal oxide are [In], [M], and [Zn].

<Composition of metal oxide>
FIG. 1 shows a conceptual diagram of a metal oxide having a CAC (Cloud-Aligned composite) configuration in the present invention. In addition, in this specification, when the metal oxide which is one aspect of this invention has a function of a semiconductor, it is defined as CAC (Cloud-Elemented composite) -OS (Oxide Semiconductor).

In CAC-OS, for example, as shown in FIG. 1, the elements constituting the metal oxide are unevenly distributed to form a region 001 and a region 002 containing each element as a main component, and the regions are mixed. And it is formed in a mosaic shape. That is, the elements constituting the metal oxide are one composition of the material unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size close thereto. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof. The state of being mixed with is also called a mosaic shape or a patch shape.

For example, the In—M—Zn oxide having a CAC configuration is an indium oxide (hereinafter, InO _X1 (X1 is a real number larger than 0)) or an indium zinc oxide (hereinafter, In _X2 Zn _Y2). O _Z2 (X2, Y2, and Z2 are real numbers larger than 0) and oxides containing the element M are separated into a mosaic-like material, and the mosaic-like InO _X1 or In _X2 Zn _Y2 O _Z2 is distributed in the film (hereinafter, also referred to as cloud-like).

In other words, the metal oxide of one aspect of the present invention is of In oxide, In-M oxide, M oxide, M-Zn oxide, In-Zn oxide, and In-M-Zn oxide. It has at least two or more oxides or materials selected from among them.

Typically, the metal oxide of one aspect of the present invention is In oxide, In—Zn oxide, In—Al—Zn oxide, In—Ga—Zn oxide, In—Y—Zn oxide, In-Cu-Zn Oxide, In-V-Zn Oxide, In-Be-Zn Oxide, In-B-Zn Oxide, In-Si-Zn Oxide, In-Ti-Zn Oxide, In- Fe-Zn oxide, In-Ni-Zn oxide, In-Ge-Zn oxide, In-Zr-Zn oxide, In-Mo-Zn oxide, In-La-Zn oxide, In-Ce- Selected from Zn oxide, In-Nd-Zn oxide, In-Hf-Zn oxide, In-Ta-Zn oxide, In-W-Zn oxide, and In-Mg-Zn oxide. , Have at least two or more. That is, the metal oxide of one aspect of the present invention can be said to be a composite metal oxide having a plurality of materials or a plurality of components.

Here, it is assumed that the concept shown in FIG. 1 is an In—M—Zn oxide having a CAC configuration. In that case, it can be said that the region 001 is a region containing an oxide containing the element M as a main component, and the region 002 is a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component. At this time, the peripheral portion is unclear between the region in which the oxide containing the element M is the main component, the region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component, and the region having at least Zn. Because it is (blurred), it may not be possible to observe clear boundaries.

That is, in the In—M—Zn oxide having a CAC configuration, a region containing an oxide containing the element M as a main component and a region containing In _X2 Zn _Y2 O _Z2 or In O _X1 as a main component are mixed. It is a metal oxide. Therefore, the metal oxide may be described as a composite metal oxide. In the present specification, for example, the atomic number ratio of In to the element M in the region 002 is larger than the atomic number ratio of In to the element M in the region 001, that the region 002 is compared with the region 001. It is assumed that the concentration of In is high.

It should be noted that the metal oxide having a CAC structure does not include a laminated structure of two or more types of films having different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing an oxide containing an element M as a main component.

Also, in the CAC configuration, the crystal structure is a secondary element. Therefore, in the In—M—Zn oxide having a CAC configuration, the crystal structures in the regions 001 and 002 are not particularly limited. Further, the region 001 and the region 002 may have different crystal structures, respectively.

For example, in the In—M—Zn oxide having a CAC structure, an oxide semiconductor having a non-single crystal structure is preferable. Examples of the non-single crystal structure include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystallineoxidemeticonductor), pseudo-amorphous oxide semiconductors (a-likeOS: amorphous-likeoxidesemiconductor) and amorphous oxide semiconductors. is there.

The CAAC-OS has a CAAC structure. The CAAC structure is an oxide semiconductor having a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and has a strain. The strain refers to a region in which a plurality of nanocrystals are connected, in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagons and may have non-regular hexagons. In addition, it may have a lattice arrangement such as a pentagon and a heptagon in distortion. Therefore, in CAAC-OS, a clear grain boundary (also referred to as grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS allows distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and that the bond distance between atoms changes due to the substitution of metal elements. It is thought that it can be done.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductors depending on the analysis method.

The a-likeOS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-likeOS has a void or low density region. That is, a-likeOS has an unstable structure as compared with nc-OS and CAAC-OS.

For example, CAC-OS preferably has a CAAC structure. The CAAC structure may be formed in a range including region 001 or region 002. That is, in CAC-OS, the region that becomes CAAC-OS is formed in the range of several nm to several tens of nm.

CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, in CAAC-OS, since a clear crystal grain boundary cannot be confirmed, it can be said that a decrease in electron mobility due to the crystal grain boundary is unlikely to occur. Therefore, by having CAAC-OS, the physical properties of the metal oxide are stabilized, so that it is possible to provide a metal oxide that is resistant to heat and has high reliability.

Specifically, CAC-OS in In-Ga-Zn oxide (Note that, among CAC-OS, In-Ga-Zn oxide may be particularly referred to as CAC-IGZO) will be described. CAC-OS in In-Ga-Zn oxide is InO _X1 , or In _X2 Zn _Y2 O _Z2 , and indium gallium zinc oxide (hereinafter, In _a Ga _b Zn _c O _d (a, b, c, and d0). It is a metal oxide in which the material is separated into a mosaic-like shape, and the mosaic-like InO _X1 or In _X2 Zn _Y2 O _Z2 is a cloud-like metal oxide.

That is, the CAC-OS in the In-Ga-Zn oxide has a region in which In _a Ga _b Zn _{c Od} is the main component and a region in which In _X2 Zn _Y2 O _Z2 or In O _X1 is the main component. It is a composite metal oxide having a mixed composition. Further, the peripheral portion of the region containing In _a Ga _b Zn _{c Od} as the main component and the region containing In _X2 Zn _Y2 O _Z2 or In O _X1 as the main component is unclear (blurred). , Clear boundaries may not be observable.

For example, in the conceptual diagram shown in FIG. 1, the region 001 corresponds to the region containing In _a Ga _b Zn _{c Od} as the main component, and the region 002 is the region containing In _X2 Zn _Y2 O _Z2 or In O _X1 as the main component. Corresponds to. The region containing In _a Ga _b Zn _{c Od} as a main component and the region containing In _X2 Zn _Y2 O _Z2 or In O _X1 as a main component may be referred to as nanoparticles, respectively. The nanoparticles have a particle diameter of 0.5 nm or more and 10 nm or less, and typically 1 nm or more and 2 nm or less. Further, since the peripheral portion of the nanoparticles is unclear (blurred), a clear boundary may not be observed.

The sizes of region 001 and region 002 can be evaluated by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-rayscopy). For example, region 001 may be observed when the diameter of region 001 is 0.5 nm or more and 10 nm or less, or 1 nm or more and 2 nm or less in EDX mapping of a cross-sectional photograph. Further, the density of the element as the main component gradually decreases from the central portion to the peripheral portion of the region. For example, when the number of elements that can be counted by EDX mapping (hereinafter, also referred to as abundance) is inclined from the central portion toward the peripheral portion, the peripheral portion of the region is unclear (blurred) in the EDX mapping of the cross-sectional photograph. Observed in the state. For example, in the region where In _a Ga _b Zn _{c Od} is the main component, the Ga atom gradually decreases from the central part to the peripheral part, and instead, the In atom and the Zn atom increase, so that In _X2 It gradually changes to the region where Zn _Y2 O _Z2 is the main component. Therefore, in the EDX mapping, the peripheral portion of the region in which In _a Ga _b Zn _{c Od} is the main component is observed in an unclear (blurred) state.

The crystal structure of the In-Ga-Zn oxide having a CAC structure is not particularly limited. Further, the region 001 and the region 002 may have different crystal structures, respectively.

Here, the In-Ga-Zn-O-based metal oxide may be referred to as IGZO, but IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. A crystalline compound is mentioned as an example of an In-Ga-Zn-O-based metal oxide. Crystalline compounds have a single crystal structure, a polycrystalline structure, or a CAAC (c-axis identified crystalline) structure. The CAAC structure is a layered crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without being oriented on the ab plane.

For example, the In-Ga-Zn oxide having a CAC structure is preferably an oxide semiconductor having a non-single crystal structure. In particular, the In-Ga-Zn oxide having a CAC configuration preferably has CAAC-IGZO. Further, it is preferable to have region 001 in the range of CAAC-IGZO. Since the possession of CAAC-IGZO stabilizes the physical properties of the metal oxide, it is possible to provide an In-Ga-Zn oxide that is resistant to heat and has high reliability.

The crystallinity of In-Ga-Zn oxide in CAC-OS can be evaluated by electron diffraction. For example, in the electron diffraction pattern image, a plurality of spots may be observed in a ring-shaped high-luminance region and a ring-shaped high-brightness region.

Here, the region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component is a region having higher conductivity than the region in which In _a Ga _b Zn _{c Od} or the like is the main component. That is, the conductivity as an oxide semiconductor is exhibited by the carrier flowing through the region where In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component. Therefore, a high field effect mobility (μ) can be realized by distributing the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as the main component in the oxide semiconductor in a cloud shape. The region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component can be said to be a semiconductor region having properties similar to those of a conductor.

On the other hand, the region in which In _a Ga _b Zn _{c Od} or the like is the main component is a region having lower conductivity than the region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component. That is, the region in which In _a Ga _b Zn _{c Od} or the like is the main component is distributed in the metal oxide, so that the leakage current can be suppressed and a good switching operation can be realized. It should be noted that the region in which In _a Ga _b Zn _{c Od} or the like is the main component can be said to be a semiconductor region close to the properties of an insulator.

Therefore, when CAC-OS in In-Ga-Zn oxide is used for a semiconductor element, the property caused by In _a Ga _b Zn _{c Od and the} like and the property caused by In _X2 Zn _Y2 O _Z2 or In O _X1. By acting in a complementary manner, high on-current (I _on ), high field-effect mobility (μ), and low off-current (I _off ) can be realized.

Further, the semiconductor device using CAC-OS in In-Ga-Zn oxide has high reliability. Therefore, CAC-OS in In-Ga-Zn oxide is most suitable for various semiconductor devices such as displays.

<Transistor with metal oxide>
Subsequently, a case where the metal oxide is used as a semiconductor in a transistor will be described.

By using the metal oxide as a semiconductor in a transistor, it is possible to realize a transistor having high field effect mobility and high switching characteristics. Moreover, a highly reliable transistor can be realized.

FIG. 2A is a schematic view of a transistor using the metal oxide in the channel forming region. In FIG. 2A, the transistor has a source, a drain, a first gate, a second gate, a first gate insulating portion, a second gate insulating portion, and a channel portion. .. The transistor can control the resistance of the channel portion by the potential applied to the gate. That is, the continuity (transistor is on state) and non-conductivity (transistor is off state) between the source and the drain can be controlled by the potential applied to the first gate or the second gate.

Here, the channel portion has a CAC-OS in which a region 001 having a first band gap and a region 002 having a second band gap are cloud-shaped. It is assumed that the first band gap is larger than the second band gap.

For example, a case where an In-Ga-Zn oxide having a CAC configuration is used as the CAC-OS of the channel portion will be described. The In-Ga-Zn oxide having a CAC configuration has a region 001 containing In _a Ga _b Zn _{c Od} having _a higher concentration of Ga than the region 002 as a main component, and a region 002 as a region 002 than the region 001. In _X2 Zn _Y2 O _Z2 with a high concentration of In, or a region containing In O _X1 as the main component, becomes a mosaic when the material is separated, and In O _X1 or In _X2 Zn _Y2 O _Z2 is distributed in the film. It is a configuration (cloud type). The region 001 containing In _a Ga _b Zn _{c Od} as a main component has a larger bandgap than the region 002 containing In _X2 Zn _Y2 O _Z2 or In O _X1 as a main component.

Here, the conduction model of the transistor shown in FIG. 2A having the CAC-OS in the channel portion will be described. FIG. 2B is a schematic diagram illustrating the distribution of energy levels between the source and drain of the transistor shown in FIG. 2A. Further, FIG. 2C is a conduction band diagram on the solid line indicated by XX'in the transistor shown in FIG. 2A. In each conduction band, the solid line indicates the energy at the lower end of the conduction band. The alternate long and short dash line indicated by E _f indicates the energy of the quasi-Fermi level of electrons. Further, here, as the first gate voltage, a negative voltage is applied between the gate and the source, and a drain voltage (V _d > 0) is applied between the source and the drain.

When a negative gate voltage is applied to the transistor shown in FIG. 2 (A), as shown in FIG. 2 (B), the conduction band CB ₀₀₁ derived from the region ₀₀₁ and the region 002 are formed between the source and the drain. The conduction band CB ₀₀₂ from which it is derived is formed. Here, since the first band gap is larger than the second band gap, the potential barrier in the conduction band CB ₀₀₁ is larger than the potential barrier in the conduction band CB ₀₀₂ . That is, the maximum value of the potential barrier in the channel portion takes a value due to the region 001. Therefore, by using CAC-OS for the channel portion, it is possible to suppress the leakage current and obtain a transistor having high switching characteristics.

Further, as shown in FIG. 2C, the region 001 having the first bandgap has the first bandgap because the bandgap is relatively wider than the region 002 having the second bandgap. The Ec end of the region can be located relatively higher than the Ec end of the region having the second bandgap.

For example, the component of region 001 having the first band gap is In-Ga-Zn oxide (In: Ga: Zn = 1: 1: 1 [atomic number ratio]) and has a second band gap. It is assumed that the component of region 002 is an In-Zn oxide (In: Zn = 2: 3 [atomic number ratio]). In this case, the first bandgap is 3.3 eV or its vicinity, and the second bandgap is 2.4 eV or its vicinity. As the band gap value, a value obtained by measuring a single film of each material with an ellipsometer is used.

In the case of the above assumption, the difference between the first bandgap and the second bandgap is 0.9 eV. In one aspect of the present invention, the difference between the first bandgap and the second bandgap may be at least 0.1 eV or more. However, the position of the valence band VB ₀₀₁ derived from the region 001 having the first bandgap and the position of the valence band VB ₀₀₂ derived from the region 002 having the second bandgap may be different. The difference between the band gap 1 and the band gap 2 is preferably 0.3 eV or more, more preferably 0.4 eV or more.

Further, in the above assumption, when the carriers flow through the CAC-OS, the carriers flow due to the second band gap, that is, the narrow band In—Zn oxide. At this time, carriers overflow from the second bandgap to the first bandgap, that is, the wide band In-Ga-Zn oxide side. In other words, the narrow band In-Zn oxide is more likely to generate carriers, and the carriers move to the wide band In-Ga-Zn oxide.

In the metal oxide forming the channel portion, the regions 001 and 002 are in a mosaic shape, and the regions 001 and 002 are irregularly distributed. Therefore, the conduction band diagram on the solid line indicated by XX'is an example.

Basically, as shown in FIG. 3A, the region 002 may form a band sandwiched between the regions 001. Alternatively, the region 001 may form a band sandwiched between the regions 002.

Further, in an actual CAC-OS, it is considered that the agglutination form and composition of the region at the junction between the region 001 having the first bandgap and the region 002 having the second bandgap are fluctuating. Therefore, as shown in FIGS. 3 (B) and 3 (C), the bands may change continuously rather than discontinuously. That is, it may be said that the first bandgap and the second bandgap are linked when the carrier flows through the CAC-OS.

FIG. 4 shows a model of a schematic band diagram on the solid line indicated by XX'in the transistor shown in FIG. 2 (A). When a voltage is applied to the first gate electrode, the same voltage is also applied to the second gate electrode at the same time. FIG. 4A shows a state (ONState) in which a positive voltage (V _g > 0) is applied between the gate and the source as the first gate voltage V _g . FIG. 4B shows a state in which the first gate voltage V _g is not applied (V _g = 0). FIG. 4C shows a state (OFFState) in which a negative voltage (V _g <0) is applied between the gate and the source as the first gate voltage V _g . In each conduction band, the solid line indicates the energy at the lower end of the conduction band. The alternate long and short dash line indicated by E _f indicates the energy of the quasi-Fermi level of electrons.

In the transistor having CAC-OS in the channel portion, the region 001 having the first band gap and the region 002 having the second band gap electrically interact with each other. In other words, the region 001 having the first bandgap and the region 002 having the second bandgap function complementarily.

As shown in FIG. 4A, when a potential (V _g > 0) in the direction of turning on the transistor is applied to the first gate electrode, a region having a second band gap with a low Ec end is applied. 002 is the main conduction path, and at the same time as the electrons flow, the electrons also flow in the region 001 having the first bandgap. Therefore, a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the on state of the transistor.

On the other hand, as shown in FIGS. 4 (B) and 4 (C), by applying a voltage (V _g ≤ 0) less than the threshold voltage to the first gate, the region 001 having the first band gap is applied. Behaves as a dielectric (insulator), so that the conduction path in region 001 is blocked. Further, the region 002 having the second bandgap is in contact with the region 001 having the first bandgap. Therefore, the region 001 having the first bandgap electrically interacts with the region 002 having the second bandgap in addition to itself, and even the conduction path in the region 002 having the second bandgap. Cut off. As a result, the entire channel portion is in a non-conducting state, and the transistor is turned off.

From the above, by using CAC-OS for the transistor, the leakage current between the gate and the source or drain can be reduced when the transistor is operating, for example, when a potential difference occurs between the gate and the source or drain. Can be reduced or prevented.

Further, it is preferable to use a semiconductor having a low carrier density for the transistor. Metal oxides of high purity or substantially high purity can have a low carrier density due to the small number of carrier sources. In addition, a metal oxide having high purity intrinsicity or substantially high purity intrinsicity may have a low trap level density because of its low defect level density.

In addition, the charge captured at the trap level of the metal oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in a metal oxide having a high trap level density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the metal oxide. Further, in order to reduce the impurity concentration in the metal oxide, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

Here, the influence of each impurity in the metal oxide will be described.

When silicon or carbon, which is one of the Group 14 elements, is contained in the metal oxide, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon near the interface with the metal oxide (concentration obtained by Secondary Ion Mass Spectrometry (SIMS)) are set to 2. × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

The hydrogen contained in the metal oxide is reacted with oxygen bonded to a metal atom to water, may form an oxygen vacancy (V _o). By hydrogen enters oxygen vacancies (V _o), there are cases where electrons serving as carriers are generated. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using a metal oxide containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in metal oxides, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

The oxygen deficiency in the metal oxide (V _o) is oxygen by introducing the metal oxide can be reduced. In other words, the oxygen deficiency in the metal oxide (V _o), that the oxygen is compensated, oxygen vacancy (V _o) is lost. Therefore, in the metal oxide, to diffuse the oxygen, reducing the oxygen vacancies in the transistor (V _o), thereby improving the reliability.

As a method for introducing oxygen into a metal oxide, for example, an oxide containing more oxygen than oxygen satisfying a stoichiometric composition can be provided in contact with the metal oxide. That is, it is preferable that the oxide has a region in which oxygen is excessively present (hereinafter, also referred to as an excess oxygen region) rather than the stoichiometric composition. In particular, when a metal oxide is used for the transistor, oxygen deficiency of the transistor can be reduced and reliability can be improved by providing an oxide having an excess oxygen region in the undercoat film or interlayer film in the vicinity of the transistor. it can.

Stable electrical characteristics can be imparted by using a metal oxide in which impurities are sufficiently reduced in the channel formation region of the transistor.

<Metal oxide film formation method>
Hereinafter, an example of the metal oxide will be described.

The temperature at which the metal oxide is formed is preferably 100 ° C. or higher and lower than 140 ° C. For example, a large substrate such as G8 has a limitation of substrate temperature according to its size. Therefore, a temperature higher than the vaporization temperature of water (100 ° C. or higher) and having good maintainability and throughput of the apparatus may be appropriately selected within a possible range.

Further, as the sputtering gas, a rare gas (typically argon), oxygen, a mixed gas of rare gas and oxygen is appropriately used. In the case of a mixed gas, the ratio of oxygen gas to the entire film-forming gas is 0% or more and 30% or less, preferably 5% or more and 20% or less.

It is also necessary to purify the sputtering gas. For example, the oxygen gas or argon gas used as the sputtering gas is a gas whose dew point is -40 ° C or lower, preferably -80 ° C or lower, more preferably -100 ° C or lower, and more preferably -120 ° C or lower. By using it, it is possible to prevent water and the like from being taken into the metal oxide as much as possible.

When a metal oxide is formed by a sputtering method, the chamber in the sputtering apparatus uses an adsorption type vacuum exhaust pump such as a cryopump to remove water and the like which are impurities for the metal oxide as much as possible. It is preferable to exhaust a high vacuum (from 5 × 10 ^-7 Pa to about 1 × 10 ^-4 Pa). Alternatively, it is preferable to combine a turbo molecular pump and a cold trap to prevent gas, particularly a gas containing carbon or hydrogen, from flowing back from the exhaust system into the chamber.

Further, an In-Ga-Zn metal oxide target can be used as the target. For example, [In]: [Ga]: [Zn] = 4: 2: 4.1 [atomic number ratio], or [In]: [Ga]: [Zn] = 5: 1: 7 [atomic number ratio]. It is preferable to use a metal oxide target which is an atomic number ratio of or close to that.

Further, in the sputtering apparatus, the target may be rotated or moved. The composite metal oxide of the present invention can be formed under film forming conditions, for example, by swinging the magnet unit up and down or / and left and right during film formation. For example, the target may be rotated or rocked with a beat of 0.1 Hz or more and 1 kHz or less (which may be paraphrased as a rhythm, a beat, a pulse, a frequency, a cycle, or a cycle). Alternatively, the magnet unit may be oscillated with a beat of 0.1 Hz or more and 1 kHz or less.

For example, a rare gas having an oxygen gas ratio of about 10% and a mixed gas of oxygen are used as the sputtering gas, the substrate temperature is set to 130 ° C., and [In]: [Ga]: [Zn] = 4: 2: 4 The metal oxide of the present invention can be formed by forming a film while swinging the In-Ga-Zn metal oxide target having an atomic number ratio.

As described above, the configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments or other examples as appropriate.

(Embodiment 2)
In the present embodiment, the semiconductor device according to one aspect of the present invention and the method for manufacturing the semiconductor device will be described with reference to FIGS. 5 to 14.

<2-1. Configuration example of semiconductor device 1>
FIG. 5 (A) is a top view of the transistor 100 which is a semiconductor device according to one aspect of the present invention, and FIG. 5 (B) is a cross section of a cut surface between the alternate long and short dash lines X1-X2 shown in FIG. 5 (A). Corresponding to the figure, FIG. 5 (C) corresponds to a cross-sectional view of a cut surface between the alternate long and short dash lines Y1-Y2 shown in FIG. 5 (A). In FIG. 5A, a part of the components of the transistor 100 (an insulating film that functions as a gate insulating film, etc.) is omitted in order to avoid complication. Further, the alternate long and short dash line X1-X2 direction may be referred to as the channel length direction, and the alternate long and short dash line Y1-Y2 direction may be referred to as the channel width direction. In the top view of the transistor, in the subsequent drawings, as in FIG. 5A, some of the components may be omitted.

The transistor 100 shown in FIGS. 5A, 5B and 5C is a transistor having a so-called top gate structure.

The transistor 100 includes an insulating film 104 on the substrate 102, a metal oxide 108 on the insulating film 104, an insulating film 110 on the metal oxide 108, a conductive film 112 on the insulating film 110, an insulating film 104, and a metal. It has an oxide 108 and an insulating film 116 on the conductive film 112.

Further, the metal oxide 108 has the metal oxide 108 on the insulating film 104 in the region where the conductive film 112 is superimposed. For example, the metal oxide 108 preferably has In, M (M is Al, Ga, Y, or Sn), and Zn.

Further, the metal oxide 108 has a region 108n in a region where the conductive film 112 does not overlap and the insulating film 116 is in contact with the conductive film 112. The region 108n is a region in which the metal oxide 108 described above is n-shaped. The region 108n is in contact with the insulating film 116, and the insulating film 116 has nitrogen or hydrogen. Therefore, when nitrogen or hydrogen in the insulating film 116 is added to the region 108n, the carrier density becomes high and the n-type is formed.

Further, the metal oxide 108 preferably has a region in which the atomic number ratio of In is larger than the atomic number ratio of M. As an example, it is preferable that the ratio of the atomic numbers of In, M, and Zn of the metal oxide 108 is in the vicinity of In: M: Zn = 4: 2: 3.

The metal oxide 108 is not limited to the above composition. For example, the ratio of the atomic numbers of In, M, and Zn of the metal oxide 108 may be in the vicinity of In: M: Zn = 5: 1: 6. Here, the term “neighborhood” includes, when In is 5, M is 0.5 or more and 1.5 or less, and Zn is 5 or more and 7 or less.

Since the metal oxide 108 has a region in which the atomic number ratio of In is larger than the atomic number ratio of M, the field effect mobility of the transistor 100 can be increased. Specifically, the field effect mobility of the transistor 100 can exceed 10 cm ² / V _s , and more preferably the field effect mobility of the transistor 100 can exceed 30 cm ² / V _s .

For example, by using the above-mentioned transistor having high field effect mobility as a gate driver for generating a gate signal, it is possible to provide a display device having a narrow frame width (also referred to as a narrow frame). Further, the above-mentioned transistor having high field effect mobility is used for a source driver (particularly, a demultiplexer connected to the output terminal of the shift register of the source driver) that supplies a signal from the signal line of the display device. Therefore, it is possible to provide a display device having a small number of wires connected to the display device.

On the other hand, even if the metal oxide 108 has a region in which the atomic number ratio of In is larger than the atomic number ratio of M, if the metal oxide 108 has high crystallinity, the electric field effect mobility may be low. is there.

The crystallinity of the metal oxide 108 can be analyzed by, for example, analysis using X-ray diffraction (XRD: X-Ray Diffraction) or analysis using a transmission electron microscope (TEM: Transmission Electron Microscope). ..

First, the oxygen deficiency that can be formed in the metal oxide 108 will be described.

The oxygen deficiency formed in the metal oxide 108 affects the transistor characteristics, which is a problem. For example, when an oxygen deficiency is formed in the metal oxide 108, hydrogen is bonded to the oxygen deficiency and becomes a carrier supply source. When a carrier supply source is generated in the metal oxide 108, fluctuations in the electrical characteristics of the transistor 100 having the metal oxide 108, typically a shift in the threshold voltage occur. Therefore, in the metal oxide 108, the smaller the oxygen deficiency, the more preferable.

Therefore, in one aspect of the present invention, the insulating film in the vicinity of the metal oxide 108, specifically, the insulating film 110 formed above the metal oxide 108 and the insulating film formed below the metal oxide 108. One or both of 104 are configured to contain excess oxygen. By moving oxygen or excess oxygen from either or both of the insulating film 104 and the insulating film 110 to the metal oxide 108, it is possible to reduce oxygen deficiency in the metal oxide.

Impurities such as hydrogen or water mixed in the metal oxide 108 affect the transistor characteristics, which is a problem. Therefore, in the metal oxide 108, it is preferable that there are few impurities such as hydrogen and water.

As the metal oxide 108, it is preferable to use a metal oxide having a low impurity concentration and a low defect level density, because a transistor having excellent electrical characteristics can be produced. Here, a low impurity concentration and a low defect level density (less oxygen deficiency) is referred to as high-purity intrinsic or substantially high-purity intrinsic. Metal oxides of high purity or substantially high purity can have a low carrier density due to the small number of carrier sources. Therefore, the transistor in which the channel formation region is formed in the metal oxide is unlikely to have an electrical characteristic (also referred to as normal on) in which the threshold voltage is negative. In addition, a metal oxide having high purity intrinsicity or substantially high purity intrinsicity may have a low trap level density because of its low defect level density. The metal oxide is a highly purified intrinsic or substantially highly purified intrinsic, the off current is extremely small, even the channel length a channel width of 1 × 10 ⁶ μm is an element of 10 [mu] m, a source electrode and a drain electrode When the voltage between them (drain voltage) is in the range of 1 V to 10 V, the off current can be obtained in the measurement limit of the semiconductor parameter analyzer or less, that is, 1 × 10 ^-13 A or less.

Further, as shown in FIGS. 5A, 5B, and 5C, the conductor 100 passes through the insulating film 118 on the insulating film 116 and the openings 141a provided in the insulating films 116, 118, and the region 108n. It may have a conductive film 120a electrically connected to the insulating film 116 and 118, and a conductive film 120b electrically connected to the region 108n via the openings 141b provided in the insulating films 116 and 118.

In the present specification and the like, the insulating film 104 is the first insulating film, the insulating film 110 is the second insulating film, the insulating film 116 is the third insulating film, and the insulating film 118 is the fourth insulating film. , Each may be called. Further, the conductive film 112 has a function as a gate electrode, the conductive film 120a has a function as a source electrode, and the conductive film 120b has a function as a drain electrode.

Further, the insulating film 110 has a function as a gate insulating film. In addition, the insulating film 110 has an excess oxygen region. Since the insulating film 110 has an excess oxygen region, excess oxygen can be supplied into the metal oxide 108. Therefore, the oxygen deficiency that can be formed in the metal oxide 108 can be compensated by excess oxygen, so that a highly reliable semiconductor device can be provided.

In order to supply excess oxygen into the metal oxide 108, excess oxygen may be supplied to the insulating film 104 formed below the metal oxide 108. In this case, the excess oxygen contained in the insulating film 104 can also be supplied to the region 108n. If excess oxygen is supplied into the region 108n, the resistance in the region 108n becomes high, which is not preferable. On the other hand, by configuring the insulating film 110 formed above the metal oxide 108 to have excess oxygen, it is possible to selectively supply excess oxygen only to the region superimposing on the conductive film 112.

<2-2. Components of semiconductor devices>
Next, the components included in the semiconductor device of the present embodiment will be described in detail.

[substrate]
There are no major restrictions on the material of the substrate 102, but at least it must have heat resistance sufficient to withstand the subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. It is also possible to apply a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like, and a semiconductor element is provided on these substrates. May be used as the substrate 102. When a glass substrate is used as the substrate 102, the 6th generation (1500 mm × 1850 mm), the 7th generation (1870 mm × 2200 mm), the 8th generation (2200 mm × 2400 mm), the 9th generation (2400 mm × 2800 mm), and the 10th generation. By using a large-area substrate of a generation (2950 mm × 3400 mm) or the like, a large-sized display device can be manufactured.

Further, a flexible substrate may be used as the substrate 102, and the transistor 100 may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the transistor 100. The release layer can be used for separating from the substrate 102 and reprinting it on another substrate after partially or completely completing the semiconductor device on the release layer. At that time, the transistor 100 can be reprinted on a substrate having poor heat resistance or a flexible substrate.

[First insulating film]
The insulating film 104 can be formed by appropriately using a sputtering method, a CVD method, a thin film deposition method, a pulse laser deposition (PLD) method, a printing method, a coating method, or the like. Further, as the insulating film 104, for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or laminated. In order to improve the interface characteristics with the metal oxide 108, it is preferable that at least the region of the insulating film 104 in contact with the metal oxide 108 is formed of the oxide insulating film. Further, by using an oxide insulating film that releases oxygen by heating as the insulating film 104, oxygen contained in the insulating film 104 can be transferred to the metal oxide 108 by heat treatment.

The thickness of the insulating film 104 can be 50 nm or more, 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. By thickening the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, the interface state at the interface between the insulating film 104 and the metal oxide 108, and the oxygen deficiency contained in the metal oxide 108. Can be reduced.

As the insulating film 104, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn oxide, or the like may be used, and the insulating film 104 may be provided as a single layer or laminated. In the present embodiment, a laminated structure of a silicon nitride film and a silicon oxide film is used as the insulating film 104. As described above, by using the insulating film 104 as a laminated structure, using the silicon nitride film on the lower layer side, and using the silicon oxide nitride film on the upper layer side, oxygen can be efficiently introduced into the metal oxide 108.

[Conducting film]
The conductive film 112 that functions as a gate electrode, the conductive film 120a that functions as a source electrode, and the conductive film 120b that functions as a drain electrode include chromium (Cr), copper (Cu), aluminum (Al), gold (Au), and silver. Select from (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (Co). It can be formed by using the above-mentioned metal element, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like.

Further, the conductive films 112, 120a and 120b include an oxide having indium and tin (In-Sn oxide), an oxide having indium and tungsten (In-W oxide), and indium, tungsten and zinc. Oxide having (In-W-Zn oxide), oxide having indium and titanium (In-Ti oxide), oxide having indium, titanium and tin (In-Ti-Sn oxide), Oxide having indium and zinc (In-Zn oxide), oxide having indium, tin and silicon (In-Sn-Si oxide), oxide having indium, gallium and zinc (In-Ga) Indium conductors such as −Zn oxide) or metal oxides can also be applied.

Here, the oxide conductor will be described. In the present specification and the like, the oxide conductor may be referred to as OC (Oxide Controller). As the oxide conductor, for example, when an oxygen deficiency is formed in a metal oxide and hydrogen is added to the oxygen deficiency, a donor level is formed in the vicinity of the conduction band. As a result, the metal oxide becomes highly conductive and becomes a conductor. A metal oxide that has been made into a conductor can be called an oxide conductor. In general, metal oxides have a large energy gap and therefore have translucency with respect to visible light. On the other hand, the oxide conductor is a metal oxide having a donor level near the conduction band. Therefore, the oxide conductor is less affected by absorption by the donor level and has the same level of translucency as the metal oxide with respect to visible light.

In particular, it is preferable to use the above-mentioned oxide conductor for the conductive film 112 because excess oxygen can be added to the insulating film 110.

Further, a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied to the conductive films 112, 120a, 120b. By using the Cu—X alloy film, it can be processed by a wet etching process, so that the manufacturing cost can be suppressed.

Further, it is preferable that the conductive films 112, 120a and 120b have one or more of the above-mentioned metal elements, particularly selected from titanium, tungsten, tantalum and molybdenum. In particular, it is preferable to use a tantalum nitride film as the conductive films 112, 120a and 120b. The tantalum nitride film has conductivity and has a high barrier property against copper or hydrogen. Further, since the tantalum nitride film emits less hydrogen from itself, it can be suitably used as a conductive film in contact with the metal oxide 108 or a conductive film in the vicinity of the metal oxide 108.

Further, the conductive films 112, 120a and 120b can be formed by an electroless plating method. As the material that can be formed by the electroless plating method, for example, any one or a plurality selected from Cu, Ni, Al, Au, Sn, Co, Ag, and Pd can be used. In particular, Cu or Ag is preferable because the resistance of the conductive film can be lowered.

[Second insulating film]
The insulating film 110 that functions as the gate insulating film of the transistor 100 includes a silicon oxide film, a silicon nitride film, a silicon nitride film, and silicon nitride by a plasma chemical vapor deposition (PECVD: (PlasmaEnchantedChemicalVaporDeposition)) method, a sputtering method, or the like. Use an insulating layer containing at least one film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film and neodymium oxide film. Can be done. The insulating film 110 may have a two-layer laminated structure or a three-layer or more laminated structure.

Further, the insulating film 110 in contact with the metal oxide 108 that functions as the channel forming region of the transistor 100 is preferably an oxide insulating film, and is a region containing oxygen in excess of the stoichiometric composition (excess oxygen region). ) Is more preferable. In other words, the insulating film 110 is an insulating film capable of releasing oxygen. In order to provide the excess oxygen region in the insulating film 110, for example, the insulating film 110 may be formed in an oxygen atmosphere, or the insulating film 110 after film formation may be heat-treated in an oxygen atmosphere.

Further, when hafnium oxide is used as the insulating film 110, the following effects are obtained. Hafnium oxide has a higher relative permittivity than silicon oxide and silicon nitride. Therefore, since the film thickness of the insulating film 110 can be increased as compared with the case where silicon oxide is used, the leakage current due to the tunnel current can be reduced. That is, a transistor having a small off-current can be realized. Further, hafnium oxide having a crystal structure has a higher relative permittivity than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor having a small off-current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. However, one aspect of the present invention is not limited to these.

Further, the insulating film 110 preferably has few defects, and typically, it is preferable that the insulating film 110 has few signals observed by an electron spin resonance method (ESR: Electron Spin Resolution). For example, the signal described above includes the E'center where the g value is observed at 2.001. The E'center is due to the dangling bond of silicon. As the insulating film 110, a silicon oxide film or a silicon nitride film having an E'center-induced spin density of 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ or less may be used. Good.

[Metal oxide]
As the metal oxide 108, the metal oxide shown above can be used.

<Atomic number ratio>
Hereinafter, a preferable range of atomic number ratios of indium, element M, and zinc contained in the metal oxide according to the present invention will be described with reference to FIGS. 15 (A), 15 (B), and 15 (C). .. Note that FIGS. 15 (A), 15 (B), and 15 (C) do not describe the atomic number ratio of oxygen. Further, the respective terms of the atomic number ratios of indium, element M, and zinc contained in the metal oxide are [In], [M], and [Zn].

In FIGS. 15 (A), 15 (B), and 15 (C), the broken line indicates the atomic number ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. Line where (-1 ≤ α ≤ 1), [In]: [M]: [Zn] = (1 + α): (1-α): Line where the atomic number ratio is 2, [In]: [M] : [Zn] = (1 + α): (1-α): A line having an atomic number ratio of 3, [In]: [M]: [Zn] = (1 + α): (1-α): 4 atomic numbers It represents a line having a ratio and a line having an atomic number ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 5.

The one-point chain line is a line having an atomic number ratio of [In]: [M]: [Zn] = 5: 1: β (β ≧ 0), [In]: [M]: [Zn] = 2: Line with an atomic number ratio of 1: β, [In]: [M]: [Zn] = 1: 1: Line with an atomic number ratio of β, [In]: [M]: [Zn] = 1: A line with an atomic number ratio of 2: β, [In]: [M]: [Zn] = 1: 3: a line with an atomic number ratio of β, and [In]: [M]: [Zn] = 1 : Represents a line having an atomic number ratio of 4: β.

Further, the atomic number ratio of [In]: [M]: [Zn] = 0: 2: 1 and its vicinity values shown in FIGS. 15 (A), 15 (B), and 15 (C). Metal oxides tend to have a spinel-type crystal structure.

In addition, a plurality of phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic number ratio is a neighborhood value of [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel-type crystal structure and a layered crystal structure tend to coexist. Further, when the atomic number ratio is a neighborhood value of [In]: [M]: [Zn] = 1: 0: 0, two phases of a big bite-type crystal structure and a layered crystal structure tend to coexist. When a plurality of phases coexist in a metal oxide, grain boundaries may be formed between different crystal structures.

The region A shown in FIG. 15 (A) shows an example of a preferable range of atomic number ratios of indium, element M, and zinc contained in the metal oxide.

By increasing the content of indium in the metal oxide, the carrier mobility (electron mobility) of the metal oxide can be increased. Therefore, a metal oxide having a high indium content has a higher carrier mobility than a metal oxide having a low indium content.

On the other hand, when the content of indium and zinc in the metal oxide is low, the carrier mobility is low. Therefore, when the atomic number ratio is [In]: [M]: [Zn] = 0: 1: 0 and its neighboring values (for example, region C shown in FIG. 15C), the insulating property is high. ..

Therefore, the metal oxide of one aspect of the present invention preferably has a high carrier mobility and an atomic number ratio shown in region A of FIG. 15 (A).

In particular, in the region B shown in FIG. 15B, an excellent metal oxide having high carrier mobility and high reliability can be obtained even in the region A.

The region B includes [In]: [M]: [Zn] = 4: 2: 3 to 4.1, and values in the vicinity thereof. The neighborhood value includes, for example, [In]: [M]: [Zn] = 5: 3: 4. Further, the region B includes [In]: [M]: [Zn] = 5: 1: 6 and its neighboring values, and [In]: [M]: [Zn] = 5: 1: 7 and its vicinity. Includes neighborhood values.

The properties of metal oxides are not uniquely determined by the atomic number ratio. Even if the atomic number ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. For example, when a metal oxide is formed by a sputtering apparatus, a film having an atomic number ratio deviating from the target atomic number ratio is formed. Further, depending on the substrate temperature at the time of film formation, the film [Zn] may be smaller than the target [Zn]. Therefore, the region shown is a region showing an atomic number ratio in which the metal oxide tends to have a specific property, and the boundary between the regions A and C is not strict.

When the metal oxide 108 is an In-M-Zn oxide, it is preferable to use a target containing a polycrystalline In-M-Zn oxide as the sputtering target. The atomic number ratio of the metal oxide 108 to be formed includes a variation of plus or minus 40% of the atomic number ratio of the metal element contained in the sputtering target. For example, when the composition of the sputtering target used for the metal oxide 108 is In: Ga: Zn = 4: 2: 4.1 [atomic number ratio], the composition of the metal oxide 108 to be formed is In: Ga :. It may be in the vicinity of Zn = 4: 2: 3 [atomic number ratio]. When the composition of the sputtering target used for the metal oxide 108 is In: Ga: Zn = 5: 1: 7 [atomic number ratio], the composition of the metal oxide 108 to be formed is In: Ga: Zn =. It may be in the vicinity of 5: 1: 6 [atomic number ratio].

Further, the metal oxide 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. As described above, by using the metal oxide having a wide energy gap, the off-current of the transistor 100 can be reduced.

Further, the metal oxide 108 preferably has a non-single crystal structure. Non-single crystal structures include, for example, CAAC-OS, polycrystalline, microcrystalline, or amorphous structures described below. Among the non-single crystal structures, the amorphous structure has the highest defect level density.

[Third insulating film]
The insulating film 116 has nitrogen or hydrogen. Examples of the insulating film 116 include a nitride insulating film. The nitride insulating film can be formed by using silicon nitride, silicon nitride oxide, silicon nitride nitride, or the like. The hydrogen concentration contained in the insulating film 116 is preferably 1 × 10 ²² atoms / cm ³ or more. Further, the insulating film 116 is in contact with the region 108n of the metal oxide 108. Therefore, the concentration of impurities (nitrogen or hydrogen) in the region 108n in contact with the insulating film 116 increases, and the carrier density in the region 108n can be increased.

[Fourth insulating film]
An oxide insulating film can be used as the insulating film 118. Further, as the insulating film 118, a laminated film of an oxide insulating film and a nitride insulating film can be used. As the insulating film 118, for example, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn oxide, or the like may be used.

Further, the insulating film 118 is preferably a film that functions as a barrier film for hydrogen, water, etc. from the outside.

The thickness of the insulating film 118 can be 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less.

<2-3. Transistor configuration example 2>
Next, a configuration different from the transistors shown in FIGS. 5A, 5B, and 6C will be described with reference to FIGS. 6A, 6B, and 6C.

6 (A) is a top view of the transistor 150, FIG. 6 (B) is a cross-sectional view between the alternate long and short dash lines X1-X2 of FIG. 6 (A), and FIG. 6 (C) is FIG. 6 (A). It is sectional drawing between one-dot chain line Y1-Y2.

The transistors 150 shown in FIGS. 6 (A), (B) and (C) have a conductive film 106 on the substrate 102, an insulating film 104 on the conductive film 106, a metal oxide 108 on the insulating film 104, and a metal oxide. It has an insulating film 110 on the 108, a conductive film 112 on the insulating film 110, an insulating film 104, a metal oxide 108, and an insulating film 116 on the conductive film 112.

The metal oxide 108 has the same configuration as the transistor 100 shown in FIGS. 5A, 5B, and 5C. The transistor 150 shown in FIGS. 6 (A), (B) and (C) has a conductive film 106 and an opening 143 in addition to the configuration of the transistor 100 shown above.

The opening 143 is provided in the insulating films 104 and 110. Further, the conductive film 106 is electrically connected to the conductive film 112 via the opening 143. Therefore, the same potential is applied to the conductive film 106 and the conductive film 112. It should be noted that different potentials may be applied to the conductive film 106 and the conductive film 112 without providing the opening 143. Alternatively, the conductive film 106 may be used as a light-shielding film without providing the opening 143. For example, by forming the conductive film 106 with a light-shielding material, it is possible to suppress the light from below that irradiates the second region 108i.

Further, in the case of the configuration of the transistor 150, the conductive film 106 has a function as a first gate electrode (also referred to as a bottom gate electrode), and the conductive film 112 has a second gate electrode (also referred to as a top gate electrode). ). Further, the insulating film 104 has a function as a first gate insulating film, and the insulating film 110 has a function as a second gate insulating film.

As the conductive film 106, the same materials as those of the conductive films 112, 120a and 120b described above can be used. In particular, the conductive film 106 is preferably formed of a material containing copper because the resistance can be lowered. For example, the conductive film 106 has a laminated structure in which a copper film is provided on a titanium nitride film, a tantalum nitride film, or a tungsten film, and the conductive films 120a and 120b are provided with a copper film on a titanium nitride film, a tantalum nitride film, or a tungsten film. A laminated structure is preferable. In this case, by using the transistor 150 for either one or both of the pixel transistor and the drive transistor of the display device, the parasitic capacitance generated between the conductive film 106 and the conductive film 120a, and the conductive film 106 and the conductive film 120b The parasitic capacitance generated between them can be reduced. Therefore, the conductive film 106, the conductive film 120a, and the conductive film 120b are used not only as the first gate electrode, the source electrode, and the drain electrode of the transistor 150, but also for wiring for power supply of the display device and for signal supply. It can also be used for wiring or wiring for connection.

As described above, the transistor 150 shown in FIGS. 6 (A), (B), and (C) has a structure having a conductive film that functions as a gate electrode above and below the metal oxide 108, unlike the transistor 100 described above. As shown in the transistor 150, the semiconductor device of one aspect of the present invention may be provided with a plurality of gate electrodes.

Further, as shown in FIGS. 6B and 6C, the metal oxide 108 faces each of the conductive film 106 that functions as the first gate electrode and the conductive film 112 that functions as the second gate electrode. It is sandwiched between two conductive films that function as gate electrodes.

Further, the length of the conductive film 112 in the channel width direction is longer than the length of the metal oxide 108 in the channel width direction, and the entire length of the metal oxide 108 in the channel width direction sandwiches the insulating film 110 in between. It is covered with. Further, since the conductive film 112 and the conductive film 106 are connected by the insulating film 104 and the opening 143 provided in the insulating film 110, one of the side surfaces of the metal oxide 108 in the channel width direction has the insulating film 110. It faces the conductive film 112 with a gap between them.

In other words, the conductive film 106 and the conductive film 112 have a region connected at the opening 143 provided in the insulating films 104 and 110 and located outside the side end portion of the metal oxide 108.

With such a configuration, the metal oxide 108 contained in the transistor 150 is electrically surrounded by the electric fields of the conductive film 106 that functions as the first gate electrode and the conductive film 112 that functions as the second gate electrode. be able to. Like the transistor 150, the device structure of the transistor that electrically surrounds the metal oxide 108 in which the channel forming region is formed by the electric fields of the first gate electrode and the second gate electrode is referred to as a Surrounded channel (S-channel) structure. Can be called.

Since the transistor 150 has an S-channel structure, an electric field for inducing a channel by the conductive film 106 or the conductive film 112 can be effectively applied to the metal oxide 108, so that the current driving capability of the transistor 150 can be increased. It is possible to improve and obtain high on-current characteristics. Further, since the on-current can be increased, the transistor 150 can be miniaturized. Further, since the metal oxide 108 of the transistor 150 has a structure surrounded by the conductive film 106 and the conductive film 112, the mechanical strength of the transistor 150 can be increased.

In the channel width direction of the transistor 150, an opening different from the opening 143 may be formed on the side where the opening 143 of the metal oxide 108 is not formed.

Further, as shown in the transistor 150, when the transistor has a pair of gate electrodes existing with a semiconductor film in between, a signal A is sent to one gate electrode and a fixed potential is attached to the other gate electrode. Vb may be given. Further, a signal A may be given to one gate electrode and a signal B may be given to the other gate electrode. Further, a fixed potential Va may be given to one gate electrode, and a fixed potential Vb may be given to the other gate electrode.

The signal A is, for example, a signal for controlling a conductive state or a non-conducting state. The signal A may be a digital signal having two types of potentials, the potential V1 and the potential V2 (V1> V2). For example, the potential V1 can be a high power supply potential and the potential V2 can be a low power supply potential. The signal A may be an analog signal.

The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of the transistor. The fixed potential Vb may be the potential V1 or the potential V2. In this case, it is not necessary to separately provide a potential generation circuit for generating a fixed potential Vb, which is preferable. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. By lowering the fixed potential Vb, the threshold voltage VthA may be increased. As a result, the drain current when the gate-source voltage Vgs is 0V may be reduced, and the leakage current of the circuit having the transistor may be reduced. For example, the fixed potential Vb may be lower than the low power supply potential. On the other hand, the threshold voltage VthA may be lowered by increasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is a high power supply potential can be improved, and the operating speed of the circuit having a transistor may be improved. For example, the fixed potential Vb may be higher than the low power supply potential.

The signal B is, for example, a signal for controlling a conductive state or a non-conducting state. The signal B may be a digital signal having two types of potentials, the potential V3 or the potential V4 (V3> V4). For example, the potential V3 can be a high power supply potential and the potential V4 can be a low power supply potential. The signal B may be an analog signal.

When both the signal A and the signal B are digital signals, the signal B may be a signal having the same digital value as the signal A. In this case, the on-current of the transistor may be improved, and the operating speed of the circuit having the transistor may be improved. At this time, the potentials V1 and V2 in the signal A may be different from the potentials V3 and V4 in the signal B. For example, when the gate insulating film corresponding to the gate to which the signal B is input is thicker than the gate insulating film corresponding to the gate to which the signal A is input, the potential amplitude (V3-V4) of the signal B is set to the signal A. It may be larger than the potential amplitude (V1-V2). By doing so, the influence of the signal A and the influence of the signal B on the conducting state or the non-conducting state of the transistor may be made comparable.

When both the signal A and the signal B are digital signals, the signal B may be a signal having a digital value different from that of the signal A. In this case, the transistor can be controlled separately by the signal A and the signal B, and a higher function may be realized. For example, when the transistor is an n-channel type, the conduction state is obtained only when the signal A has the potential V1 and the signal B has the potential V3, or the signal A has the potential V2 and the signal B has the potential V2. When the non-conducting state occurs only when the potential is V4, it may be possible to realize functions such as a NAND circuit and a NOR circuit with one transistor. Further, the signal B may be a signal for controlling the threshold voltage VthA. For example, the signal B may be a signal having different potentials depending on the period during which the circuit having the transistor is operating and the period during which the circuit is not operating. The signal B may be a signal having a different potential according to the operation mode of the circuit. In this case, the potential of the signal B may not switch as frequently as the signal A.

When both signal A and signal B are analog signals, signal B is an analog signal having the same potential as signal A, an analog signal obtained by multiplying the potential of signal A by a constant, or the potential of signal A added or subtracted by a constant. It may be an analog signal or the like. In this case, the on-current of the transistor may be improved, and the operating speed of the circuit having the transistor may be improved. The signal B may be an analog signal different from the signal A. In this case, the transistor can be controlled separately by the signal A and the signal B, and a higher function may be realized.

The signal A may be a digital signal and the signal B may be an analog signal. Alternatively, the signal A may be an analog signal and the signal B may be a digital signal.

When a fixed potential is applied to both gate electrodes of a transistor, the transistor may be able to function as an element equivalent to a resistance element. For example, when the transistor is an n-channel type, the effective resistance of the transistor may be lowered (high) by raising (lowering) the fixed potential Va or the fixed potential Vb. By increasing (lowering) both the fixed potential Va and the fixed potential Vb, an effective resistance lower (higher) than the effective resistance obtained by a transistor having only one gate may be obtained.

The other configurations of the transistor 150 are the same as those of the transistor 100 shown above, and the same effect is obtained.

Further, an insulating film may be further formed on the transistor 150. The transistor 150 shown in FIGS. 6A, 6B, and C has an insulating film 122 on the conductive films 120a, 120b, and the insulating film 118.

The insulating film 122 has a function of flattening irregularities and the like caused by transistors and the like. The insulating film 122 may be insulating, and is formed by using an inorganic material or an organic material. Examples of the inorganic material include a silicon oxide film, a silicon nitride film, a silicon nitride film, a silicon nitride film, an aluminum oxide film, and an aluminum nitride film. Examples of the organic material include a photosensitive resin material such as an acrylic resin or a polyimide resin.

<2-4. Transistor configuration example 3>
Next, a configuration different from the transistor 150 shown in FIGS. 6 (A), (B), and (C) will be described with reference to FIG. 7.

7 (A) and 7 (B) are cross-sectional views of the transistor 160. Since the top view of the transistor 160 is the same as that of the transistor 150 shown in FIG. 6A, the description thereof is omitted here.

The transistor 160 shown in FIGS. 7A and 7B is different from the transistor 150 in the laminated structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110.

The conductive film 112 of the transistor 160 has a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the conductive film 112_1. For example, by using an oxide conductive film as the conductive film 112_1, excess oxygen can be added to the insulating film 110. The oxide conductive film may be formed in an atmosphere containing oxygen gas by using a sputtering method. Examples of the oxide conductive film include an oxide having indium and tin, an oxide having tungsten and indium, an oxide having tungsten, indium and zinc, and an oxide having titanium and indium. Examples thereof include oxides having titanium, indium and tin, oxides having indium and zinc, oxides having silicon, indium and tin, and oxides having indium, gallium and zinc.

Further, as shown in FIG. 7B, the conductive film 112_2 and the conductive film 106 are connected at the opening 143. When the opening 143 is formed, the shape shown in FIG. 7B can be obtained by forming the conductive film to be the conductive film 112_1 and then forming the opening 143. When the oxide conductive film is applied to the conductive film 112_1, the connection resistance between the conductive film 112 and the conductive film 106 can be lowered by configuring the conductive film 112_2 and the conductive film 106 to be connected to each other.

Further, the conductive film 112 and the insulating film 110 of the transistor 160 have a tapered shape. More specifically, the lower end portion of the conductive film 112 is formed outside the upper end portion of the conductive film 112. Further, the lower end portion of the insulating film 110 is formed outside the upper end portion of the insulating film 110. Further, the lower end portion of the conductive film 112 is formed at substantially the same position as the upper end portion of the insulating film 110.

By forming the conductive film 112 and the insulating film 110 of the transistor 160 into a tapered shape, the coverage of the insulating film 116 can be improved as compared with the case where the conductive film 112 and the insulating film 110 of the transistor 160 are rectangular, which is preferable. is there.

The other configurations of the transistor 160 are the same as those of the transistor 150 shown above, and the same effect is obtained.

<2-5. Manufacturing method of semiconductor device>
Next, an example of the method for manufacturing the transistor 150 shown in FIGS. 6 (A), (B), and (C) will be described with reference to FIGS. 8 to 10. 8 to 10 are cross-sectional views in the channel length direction and the channel width direction for explaining the method for manufacturing the transistor 150.

First, the conductive film 106 is formed on the substrate 102. Next, the insulating film 104 is formed on the substrate 102 and the conductive film 106, and the metal oxide film is formed on the insulating film 104. Then, the metal oxide film is processed into an island shape to form the metal oxide 108a (see FIG. 8 (A)).

The conductive film 106 can be formed by selecting the material described above. In the present embodiment, a sputtering device is used as the conductive film 106 to form a laminated film of a tungsten film having a thickness of 50 nm and a copper film having a thickness of 400 nm.

As a method for processing the conductive film to be the conductive film 106, either one or both of the wet etching method and the dry etching method may be used. In the present embodiment, the copper film is etched by the wet etching method, and then the tungsten film is etched by the dry etching method to process the conductive film to form the conductive film 106.

The insulating film 104 can be formed by appropriately using a sputtering method, a CVD method, a thin film deposition method, a pulse laser deposition (PLD) method, a printing method, a coating method, or the like. In the present embodiment, a PECVD apparatus is used as the insulating film 104 to form a silicon nitride film having a thickness of 400 nm and a silicon oxide film having a thickness of 50 nm.

Further, oxygen may be added to the insulating film 104 after the insulating film 104 is formed. Examples of oxygen added to the insulating film 104 include oxygen radicals, oxygen atoms, oxygen atom ions, oxygen molecule ions and the like. Further, as the addition method, there are an ion doping method, an ion implantation method, a plasma treatment method and the like. Further, after forming a film that suppresses the desorption of oxygen on the insulating film, oxygen may be added to the insulating film 104 via the film.

As the film that suppresses the desorption of oxygen, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten is used. Can be formed.

Further, when oxygen is added by plasma treatment, the amount of oxygen added to the insulating film 104 can be increased by exciting oxygen with microwaves to generate high-density oxygen plasma.

Further, when forming the metal oxide 108a, an inert gas (for example, helium gas, argon gas, xenon gas, etc.) may be mixed in addition to the oxygen gas. The ratio of oxygen gas to the total film-forming gas when forming the metal oxide 108a (hereinafter, also referred to as oxygen flow rate ratio) is 0% or more and 30% or less, preferably 5% or more and 20% or less. ..

Further, as the formation condition of the metal oxide 108a, the substrate temperature may be room temperature or more and 180 ° C. or less, and preferably the substrate temperature may be room temperature or more and 140 ° C. or less. It is preferable that the substrate temperature at the time of forming the metal oxide 108a is, for example, room temperature or more and less than 140 ° C., because the productivity is high.

The thickness of the metal oxide 108a may be 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 60 nm or less.

When a large glass substrate (for example, 6th to 10th generation) is used as the substrate 102, and the substrate temperature at the time of forming the metal oxide 108a is 200 ° C. or higher and 300 ° C. or lower, the substrate 102 May be deformed (distorted or warped). Therefore, when a large glass substrate is used, deformation of the glass substrate can be suppressed by setting the substrate temperature at the time of forming the metal oxide 108a to room temperature or higher and lower than 200 ° C.

It is also necessary to purify the sputtering gas. For example, the oxygen gas or argon gas used as the sputtering gas is a gas whose dew point is -40 ° C or lower, preferably -80 ° C or lower, more preferably -100 ° C or lower, and more preferably -120 ° C or lower. By using it, it is possible to prevent water and the like from being taken into the metal oxide as much as possible.

When a metal oxide is formed by a sputtering method, the chamber in the sputtering apparatus uses an adsorption type vacuum exhaust pump such as a cryopump to remove water and the like which are impurities for the metal oxide as much as possible. , It is preferable to exhaust to a high vacuum (from 5 × 10 ^-7 Pa to about 1 × 10 ^-4 Pa). In particular, the partial pressure of gas molecules (gas molecules corresponding to m / z = 18) corresponding to H ₂ O in the chamber during standby of the sputtering apparatus is 1 × 10 ^-4 Pa or less, preferably 5 × 10 ^-5. It is preferably Pa or less.

In the present embodiment, the formation conditions of the metal oxide 108a are as follows.

The formation conditions of the metal oxide 108a are formed by a sputtering method using an In-Ga-Zn metal oxide target. Further, the substrate temperature at the time of forming the metal oxide 108a and the oxygen flow rate ratio can be appropriately set. Further, the pressure in the chamber is set to 0.6 Pa, and 2500 W of AC power is supplied to the metal oxide target installed in the sputtering apparatus to form an oxide film.

In order to process the formed metal oxide into the metal oxide 108a, either one or both of the wet etching method and the dry etching method may be used.

Further, after forming the metal oxide 108a, heat treatment may be performed to dehydrogenate or dehydrate the metal oxide 108a. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the strain point of the substrate, 250 ° C. or higher and 450 ° C. or lower, or 300 ° C. or higher and 450 ° C. or lower.

The heat treatment can be carried out in an inert atmosphere containing a rare gas such as helium, neon, argon, xenon, krypton, or nitrogen. Alternatively, after heating in an inert atmosphere, heating may be performed in an oxygen atmosphere. It is preferable that the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water or the like. The processing time may be 3 minutes or more and 24 hours or less.

An electric furnace, an RTA device, or the like can be used for the heat treatment. By using the RTA device, the heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

By forming a film while heating the metal oxide, or by performing heat treatment after forming the metal oxide, the hydrogen concentration obtained by SIMS in the metal oxide is 5 × 10 ¹⁹ atoms / cm ³ or less, or 1 × 10 ¹⁹ atoms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm ³ or less, or 1 × 10 ¹⁸ atoms / cm ³ or less, or 5 × 10 ¹⁷ atoms / cm ³ or less, or 1 × 10 ¹⁶ atoms / cm It can be ³ or less.

Next, the insulating film 110_0 is formed on the insulating film 104 and the metal oxide 108a. (See FIG. 8 (B)).

As the insulating film 110_0, a silicon oxide film or a silicon nitride nitride film can be formed by using a plasma chemical vapor deposition apparatus (PECVD apparatus, or simply referred to as a plasma CVD apparatus). In this case, it is preferable to use a sedimentary gas containing silicon and an oxidizing gas as the raw material gas. Typical examples of the sedimentary gas containing silicon include silane, disilane, trisilane, fluorinated silane and the like. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide and the like.

Further, as the insulating film 110_0, PECVD is such that the flow rate of the oxidizing gas is greater than 20 times and less than 100 times, or 40 times or more and 80 times or less with respect to the flow rate of the deposited gas, and the pressure in the processing chamber is less than 100 Pa or 50 Pa or less. By using the apparatus, a silicon nitride film having a small amount of defects can be formed.

Further, as the insulating film 110_0, the substrate placed in the vacuum-exhausted processing chamber of the PECVD apparatus is held at 280 ° C. or higher and 400 ° C. or lower, and the raw material gas is introduced into the processing chamber to increase the pressure in the treatment chamber at 20 Pa or higher and 250 Pa or higher. Hereinafter, more preferably, it is set to 100 Pa or more and 250 Pa or less, and a dense silicon oxide film or silicon nitride film can be formed as the insulating film 110_0 under the condition of supplying high frequency power to the electrodes provided in the processing chamber.

Further, the insulating film 110_0 may be formed by using the PECVD method using microwaves. Microwave refers to the frequency range of 300 MHz to 300 GHz. Microwaves have low electron temperature and low electron energy. In addition, in the supplied power, the ratio used for accelerating electrons is small, it can be used for dissociation and ionization of more molecules, and it is possible to excite a high-density plasma (high-density plasma). .. Therefore, it is possible to form the insulating film 110_0 with less plasma damage to the surface to be filmed and deposits and less defects.

Further, the insulating film 110_0 can be formed by using a CVD method using an organic silane gas. As the organosilane gas, tetraethoxysilane (TEOS: _{Si (OC 2 H 5) 4} ), tetramethylsilane (TMS: chemical formula Si _{(CH 3)} 4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane Silicon-containing compounds such as (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), and trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ) can be used. it can. By using the CVD method using an organic silane gas, an insulating film 110_0 having a high coating property can be formed.

In the present embodiment, a PECVD apparatus is used as the insulating film 110_0 to form a silicon oxide film having a thickness of 100 nm.

Next, a mask is formed at a desired position on the insulating film 110_0 by lithography, and then the insulating film 110_0 and a part of the insulating film 104 are etched to form an opening 143 reaching the conductive film 106 (. (See FIG. 8C).

As a method for forming the opening 143, either one or both of the wet etching method and the dry etching method may be used. In the present embodiment, the dry etching method is used to form the opening 143.

Next, the conductive film 112_0 is formed on the conductive film 106 and the insulating film 110_0 so as to cover the opening 143. Further, when a metal oxide film is used as the conductive film 112_0, oxygen may be added to the insulating film 110_0 when the conductive film 112_0 is formed (see FIG. 8D).

In FIG. 8D, the oxygen added to the insulating film 110_0 is schematically represented by an arrow. Further, by forming the conductive film 112_0 so as to cover the opening 143, the conductive film 106 and the conductive film 112_0 are electrically connected.

When a metal oxide film is used as the conductive film 112_0, it is preferable to use a sputtering method as a method for forming the conductive film 112_0 and to form the conductive film 112_0 in an atmosphere containing oxygen gas at the time of formation. By forming the conductive film 112_0 in an atmosphere containing oxygen gas at the time of formation, oxygen can be suitably added to the insulating film 110_0. The method for forming the conductive film 112_0 is not limited to the sputtering method, and other methods, for example, the ALD method may be used.

In the present embodiment, the conductive film 112_0 is an IGZO film (In: Ga: Zn = 4: 2: 4.1 (atomic)) which is an In-Ga-Zn oxide having a film thickness of 100 nm by using a sputtering method. Further, an oxygen addition treatment may be performed in the insulating film 110_0 before the formation of the conductive film 112_0 or after the formation of the conductive film 112_0. As a method of the oxygen addition treatment, the insulating film may be formed. It may be the same as the oxygen addition treatment that can be performed after the formation of 104.

Next, a mask 140 is formed at a desired position on the conductive film 112_0 by a lithography process (see FIG. 9A).

Next, etching is performed on the mask 140 to process the conductive film 112_0 and the insulating film 110_0. Further, the mask 140 is removed after processing the conductive film 112_0 and the insulating film 110_0. By processing the conductive film 112_0 and the insulating film 110_0, the island-shaped conductive film 112 and the island-shaped insulating film 110 are formed (see FIG. 9B).

In the present embodiment, the conductive film 112_0 and the insulating film 110_0 are processed by using a dry etching method.

When the conductive film 112 and the insulating film 110 are processed, the film thickness of the metal oxide 108a in the region where the conductive film 112 does not overlap may be reduced. Alternatively, when the conductive film 112 and the insulating film 110 are processed, the film thickness of the insulating film 104 in the region where the metal oxide 108a does not overlap may be reduced. Further, when the conductive film 112_0 and the insulating film 110_0 are processed, an etchant or an etching gas (for example, chlorine) is added to the metal oxide 108a, or the conductive film 112_0 or the constituent elements of the insulating film 110_0 are added. It may be added in the metal oxide 108.

Next, the insulating film 116 is formed on the insulating film 104, the metal oxide 108, and the conductive film 112. By forming the insulating film 116, a part of the metal oxide 108a in contact with the insulating film 116 becomes a region 108n. Here, the metal oxide 108a superimposed on the conductive film 112 is a metal oxide 108. (See FIG. 9 (C)).

The insulating film 116 can be formed by selecting the material described above. In the present embodiment, a PECVD apparatus is used as the insulating film 116 to form a silicon nitride film having a thickness of 100 nm. Further, at the time of forming the silicon nitride film, two steps of plasma treatment and film formation treatment are performed at a temperature of 220 ° C. In the plasma treatment, an argon gas having a flow rate of 100 sccm and a nitrogen gas having a flow rate of 1000 sccm are introduced into the chamber before the film formation, the pressure in the chamber is set to 40 Pa, and the power of 1000 W is supplied to the RF power supply (27.12 MHz). To supply. Further, as the film forming process, a silane gas having a flow rate of 50 sccm, a nitrogen gas having a flow rate of 5000 sccm, and an ammonia gas having a flow rate of 100 sccm are introduced into the chamber, the pressure in the chamber is set to 100 Pa, and an RF power source (27.12 MHz) is used. Is supplied with 1000 W of power.

By using the silicon nitride film as the insulating film 116, nitrogen or hydrogen in the silicon nitride film can be supplied to the region 108n in contact with the insulating film 116. Further, by setting the temperature at the time of forming the insulating film 116 to the above-mentioned temperature, it is possible to suppress the excess oxygen contained in the insulating film 110 from being released to the outside.

Next, the insulating film 118 is formed on the insulating film 116 (see FIG. 10 (A)).

The insulating film 118 can be formed by selecting the material described above. In the present embodiment, a PECVD apparatus is used as the insulating film 118 to form a silicon oxide film having a thickness of 300 nm.

Next, a mask is formed at a desired position of the insulating film 118 by lithography, and then a part of the insulating film 118 and the insulating film 116 is etched to form openings 141a and 141b reaching the region 108n (FIG. FIG. 10 (B)).

As a method for etching the insulating film 118 and the insulating film 116, either one or both of the wet etching method and the dry etching method may be used. In the present embodiment, the insulating film 118 and the insulating film 116 are processed by using a dry etching method.

Next, a conductive film is formed on the region 108n and the insulating film 118 so as to cover the openings 141a and 141b, and the conductive film is processed into a desired shape to form the conductive films 120a and 120b (FIG. 10). (C)).

The conductive films 120a and 120b can be formed by selecting the materials described above. In the present embodiment, as the conductive films 120a and 120b, a sputtering apparatus is used to form a laminated film of a tungsten film having a thickness of 50 nm and a copper film having a thickness of 400 nm.

As a method for processing the conductive film to be the conductive film 120a and 120b, either one or both of the wet etching method and the dry etching method may be used. In the present embodiment, the copper film is etched by the wet etching method, and then the tungsten film is etched by the dry etching method to process the conductive film to form the conductive films 120a and 120b.

Subsequently, the insulating film 122 is formed by covering the conductive films 120a and 120b and the insulating film 118.

Through the above steps, the transistors 150 shown in FIGS. 6A, 6B, and 6C can be manufactured.

As the film (insulating film, metal oxide film, conductive film, etc.) constituting the transistor 150, in addition to the above-mentioned forming method, a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a pulse laser deposition, etc. It can be formed by using the (PLD) method or the ALD method. Alternatively, it can be formed by a coating method or a printing method. As a film forming method, a sputtering method and a plasma chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may also be used. An example of a thermal CVD method is the metalorganic chemical vapor deposition (MOCVD) method.

In the thermal CVD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, the raw material gas and the oxidizing agent are sent into the chamber at the same time, reacted in the vicinity of the substrate or on the substrate, and deposited on the substrate to form a film. As described above, since the thermal CVD method is a film forming method that does not generate plasma, it has an advantage that defects are not generated due to plasma damage.

A thermal CVD method such as the MOCVD method can form a film such as the conductive film, an insulating film, or a metal oxide film described above.

For example, when a hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide or tetrakisdimethylamide hafnium (TDHA, Hf [N (CH ₃ ) ₂ ] ₂ ] ₄ ) and and tetrakis (ethylmethylamido) material gases hafnium amide) is vaporized, such as hafnium, using two types of gas ozone (O ₃₎ as an oxidizing agent.

In addition, when an aluminum oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and an aluminum precursor (trimethylaluminum (TMA, Al (CH ₃ ) ₃ ), etc.) is vaporized with a raw material gas. , using two types of gases _{H 2} O as the oxidizing agent. Other materials include tris (dimethylamide) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanetone) and the like.

In the case of forming the silicon oxide film using a deposition apparatus employing ALD is hexachlorodisilane adsorbed on the film-forming surface, and supplying radicals for oxidizing gas (O _2, dinitrogen monoxide) adsorption React with things.

When a tungsten film is formed by a film forming apparatus using ALD, WF ₆ gas and B ₂ H ₆ gas are sequentially introduced to form an initial tungsten film, and then WF ₆ gas and H ₂ gas are formed. To form a tungsten film using. In addition, SiH ₄ gas may be used instead of B ₂ H ₆ gas.

Further, when a metal oxide, for example, an In-Ga-Zn-O film is formed by a film forming apparatus using ALD, the In-O layer is formed by using In (CH ₃ ) ₃ gas and O ₃ gas. After that, a GaO layer is formed using Ga (CH ₃ ) ₃ gas and O ₃ gas, and then a ZnO layer is formed using Zn (CH ₃ ) ₂ gas and O ₃ gas. The order of these layers is not limited to this example. Further, these gases may be used to form a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, and a Ga—Zn—O layer. Instead of the O ₃ gas, an H ₂ O gas obtained by bubbling water with an inert gas such as Ar may be used, but it is preferable to use an O ₃ gas containing no H.

<2-5. Transistor configuration example 4>
11 (A) is a top view of the transistor 300A, and FIG. 11 (B) corresponds to a cross-sectional view of a cut surface between the alternate long and short dash lines X1-X2 shown in FIG. 11 (A). Corresponds to the cross-sectional view of the cut surface between the alternate long and short dash lines Y1-Y2 shown in FIG. 11 (A). Note that, in FIG. 11A, in order to avoid complication, a part of the components of the transistor 300A (an insulating film that functions as a gate insulating film, etc.) is omitted. Further, the alternate long and short dash line X1-X2 direction may be referred to as the channel length direction, and the alternate long and short dash line Y1-Y2 direction may be referred to as the channel width direction. In the top view of the transistor, in the subsequent drawings, as in FIG. 11A, some of the components may be omitted.

The transistor 300A shown in FIG. 11 includes a conductive film 304 on the substrate 302, an insulating film 306 on the substrate 302 and the conductive film 304, an insulating film 307 on the insulating film 306, and a metal oxide 308 on the insulating film 307. , The conductive film 312a on the metal oxide 308 and the conductive film 312b on the metal oxide 308. Further, the insulating films 314 and 316 and the insulating film 318 are provided on the transistor 300A, more specifically, on the conductive films 312a and 312b and the metal oxide 308.

In the transistor 300A, the insulating films 306 and 307 have a function as a gate insulating film of the transistor 300A, and the insulating films 314, 316 and 318 have a function as a protective insulating film of the transistor 300A. Further, in the transistor 300A, the conductive film 304 has a function as a gate electrode, the conductive film 312a has a function as a source electrode, and the conductive film 312b has a function as a drain electrode.

In the present specification and the like, the insulating films 306 and 307 may be referred to as a first insulating film, the insulating films 314 and 316 may be referred to as a second insulating film, and the insulating film 318 may be referred to as a third insulating film. is there.

The transistor 300A shown in FIG. 11 has a channel-etched transistor structure. The metal oxide of one aspect of the present invention can be suitably used for a channel etch type transistor.

<2-6. Transistor configuration example 5>
12 (A) is a top view of the transistor 300B, and FIG. 12 (B) corresponds to a cross-sectional view of a cut surface between the alternate long and short dash lines X1-X2 shown in FIG. 12 (A). Corresponds to the cross-sectional view of the cut surface between the alternate long and short dash lines Y1-Y2 shown in FIG. 12 (A).

The transistor 300B shown in FIG. 12 includes a conductive film 304 on the substrate 302, an insulating film 306 on the substrate 302 and the conductive film 304, an insulating film 307 on the insulating film 306, and a metal oxide 308 on the insulating film 307. , Conductivity electrically connected to the metal oxide 308 via the insulating film 314 on the metal oxide 308, the insulating film 316 on the insulating film 314, and the openings 341a provided in the insulating film 314 and the insulating film 316. It has a film 312a and a conductive film 312b that is electrically connected to the metal oxide 308 via an opening 341b provided in the insulating film 314 and the insulating film 316. Further, an insulating film 318 is provided on the transistor 300B, more specifically, on the conductive films 312a and 312b, and on the insulating film 316.

In the transistor 300B, the insulating films 306 and 307 have a function as a gate insulating film of the transistor 300B, and the insulating films 314 and 316 have a function as a protective insulating film of the metal oxide 308. 318 has a function as a protective insulating film of the transistor 300B. Further, in the transistor 300B, the conductive film 304 has a function as a gate electrode, the conductive film 312a has a function as a source electrode, and the conductive film 312b has a function as a drain electrode.

The transistor 300A shown in FIG. 11 has a channel-etched structure, whereas the transistor 300B shown in FIGS. 12 (A), (B), and (C) has a channel-protected structure. The metal oxide of one aspect of the present invention can also be suitably used for a channel protection type transistor.

<2-7. Transistor configuration example 6>
13 (A) is a top view of the transistor 300C, and FIG. 13 (B) corresponds to a cross-sectional view of a cut surface between the alternate long and short dash lines X1-X2 shown in FIG. 13 (A). Corresponds to the cross-sectional view of the cut surface between the alternate long and short dash lines Y1-Y2 shown in FIG. 13 (A).

The transistor 300C shown in FIG. 13 is different in the shape of the insulating films 314 and 316 from the transistor 300B shown in FIGS. 12 (A), (B) and (C). Specifically, the insulating films 314 and 316 of the transistor 300C are provided in an island shape on the channel forming region of the metal oxide 308. Other configurations are the same as those of the transistor 300B.

<2-8. Transistor configuration example 7>
14 (A) is a top view of the transistor 300D, and FIG. 14 (B) corresponds to a cross-sectional view of a cut surface between the alternate long and short dash lines X1-X2 shown in FIG. 14 (A). Corresponds to the cross-sectional view of the cut surface between the alternate long and short dash lines Y1-Y2 shown in FIG. 14 (A).

The transistor 300D shown in FIG. 14 includes a conductive film 304 on the substrate 302, an insulating film 306 on the substrate 302 and the conductive film 304, an insulating film 307 on the insulating film 306, and a metal oxide 308 on the insulating film 307. , The conductive film 312a on the metal oxide 308, the conductive film 312b on the metal oxide 308, the metal oxide 308, the insulating film 314 on the conductive film 312a, 312b, and the insulating film 316 on the insulating film 314. It has an insulating film 318 on the insulating film 316 and conductive films 320a and 320b on the insulating film 318.

In the transistor 300D, the insulating films 306 and 307 have a function as the first gate insulating film of the transistor 300D, and the insulating films 314, 316 and 318 have a function as the second gate insulating film of the transistor 300D. Has. Further, in the transistor 300D, the conductive film 304 has a function as a first gate electrode, the conductive film 320a has a function as a second gate electrode, and the conductive film 320b is a pixel used in a display device. It has a function as an electrode. Further, the conductive film 312a has a function as a source electrode, and the conductive film 312b has a function as a drain electrode.

Further, as shown in FIG. 14C, the conductive film 320a is connected to the conductive film 304 at the openings 342b and 342c provided in the insulating films 306, 307, 314, 316 and 318. Therefore, the same potential is applied to the conductive film 320a and the conductive film 304.

In the transistor 300D, the configuration in which the openings 342b and 342c are provided and the conductive film 320a and the conductive film 304 are connected has been illustrated, but the present invention is not limited to this. For example, a configuration in which only one of the openings 342b and 342c is formed to connect the conductive film 320a and the conductive film 304, or the conductive film 320a and the conductive film 320a are not provided without the opening 342b and the opening 342c. The conductive film 304 may not be connected. When the conductive film 320a and the conductive film 304 are not connected, different potentials can be applied to the conductive film 320a and the conductive film 304.

Further, the conductive film 320b is connected to the conductive film 312b via the openings 342a provided in the insulating films 314, 316 and 318.

The transistor 300D has the S-channel structure described above.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 3)
In the present embodiment, an example of a display panel that can be used as a display unit or the like of a display device using the semiconductor device of one aspect of the present invention will be described with reference to FIGS. 16 and 17. The display panel illustrated below is a display panel that has both a reflective liquid crystal element and a light emitting element and can display both a transmission mode and a reflection mode. The metal oxide of one aspect of the present invention and the transistor having the metal oxide are suitable for a transistor of pixels of a display device, a driver for driving the display device, an LSI for supplying data to the display device, and the like. Can be used.

<Display panel configuration example>
FIG. 16 is a schematic perspective view of a display panel 600 according to an aspect of the present invention. The display panel 600 has a configuration in which a substrate 651 and a substrate 661 are bonded together. In FIG. 16, the substrate 661 is clearly indicated by a broken line.

The display panel 600 has a display unit 662, a circuit 659, wiring 666, and the like. The substrate 651 is provided with, for example, a circuit 659, wiring 666, and a conductive film 663 that functions as a pixel electrode. Further, FIG. 16 shows an example in which IC673 and FPC672 are mounted on the substrate 651. Therefore, the configuration shown in FIG. 16 can be said to be a display module having a display panel 600, an FPC 672, and an IC 673.

As the circuit 659, for example, a circuit that functions as a scanning line drive circuit can be used.

The wiring 666 has a function of supplying signals and electric power to the display unit and the circuit 659. The signal or electric power is input to the wiring 666 from the outside or IC673 via FPC672.

Further, FIG. 16 shows an example in which the IC673 is provided on the substrate 651 by the COG (ChipOnGlass) method or the like. As the IC 673, an IC having a function as, for example, a scanning line drive circuit or a signal line drive circuit can be applied. When the display panel 600 is provided with a circuit that functions as a scanning line drive circuit and a signal line drive circuit, or if a circuit that functions as a scanning line drive circuit or a signal line drive circuit is provided externally, the display panel 600 is driven via the FPC 672. In the case of inputting a signal for this purpose, the IC673 may not be provided. Further, the IC673 may be mounted on the FPC672 by a COF (ChipOnFilm) method or the like.

FIG. 16 shows an enlarged view of a part of the display unit 662. The conductive film 663 of the plurality of display elements is arranged in a matrix on the display unit 662. The conductive film 663 has a function of reflecting visible light and functions as a reflecting electrode of the liquid crystal element 640 described later.

Further, as shown in FIG. 16, the conductive film 663 has an opening. Further, the light emitting element 660 is provided on the substrate 651 side of the conductive film 663. The light from the light emitting element 660 is emitted to the substrate 661 side through the opening of the conductive film 663.

<Cross-section configuration example>
FIG. 17 shows an example of a cross section of the display panel illustrated in FIG. 16 when a part of the area including the FPC 672, a part of the area including the circuit 659, and a part of the area including the display unit 662 are cut. Shown.

The display panel has an insulating film 620 between the substrate 651 and the substrate 661. Further, a light emitting element 660, a transistor 601 and a transistor 605, a transistor 606, a colored layer 634 and the like are provided between the substrate 651 and the insulating film 620. Further, a liquid crystal element 640, a colored layer 631 and the like are provided between the insulating film 620 and the substrate 661. Further, the substrate 661 and the insulating film 620 are adhered to each other via the adhesive layer 641, and the substrate 651 and the insulating film 620 are adhered to each other via the adhesive layer 642.

The transistor 606 is electrically connected to the liquid crystal element 640, and the transistor 605 is electrically connected to the light emitting element 660. Since both the transistor 605 and the transistor 606 are formed on the surface of the insulating film 620 on the substrate 651 side, they can be manufactured by using the same process.

The substrate 661 is provided with a colored layer 631, a light-shielding film 632, an insulating film 621, a conductive film 613 that functions as a common electrode of the liquid crystal element 640, an alignment film 633b, an insulating film 617, and the like. The insulating film 617 functions as a spacer for holding the cell gap of the liquid crystal element 640.

Insulating layers such as an insulating film 681, an insulating film 682, an insulating film 683, an insulating film 684, and an insulating film 685 are provided on the substrate 651 side of the insulating film 620. A part of the insulating film 681 functions as a gate insulating layer of each transistor. The insulating film 682, the insulating film 683, and the insulating film 684 are provided so as to cover each transistor. Further, an insulating film 685 is provided so as to cover the insulating film 684. The insulating film 684 and the insulating film 685 have a function as a flattening layer. Although the case where three layers of the insulating film 682, the insulating film 683, and the insulating film 684 are provided as the insulating layer covering the transistor and the like is shown here, the case is not limited to this, and four or more layers may be used. It may be a layer or two layers. Further, the insulating film 684 that functions as a flattening layer may not be provided if it is unnecessary.

Further, the transistor 601 and the transistor 605 and the transistor 606 have a conductive film 654 partially functioning as a gate, a conductive film 652 partially functioning as a source or drain, and a semiconductor film 653. Here, the same hatching pattern is attached to a plurality of layers obtained by processing the same conductive film.

The liquid crystal element 640 is a reflective liquid crystal element. The liquid crystal element 640 has a laminated structure in which the conductive film 635, the liquid crystal layer 612, and the conductive film 613 are laminated. Further, a conductive film 663 that reflects visible light is provided in contact with the substrate 651 side of the conductive film 635. The conductive film 663 has an opening 655. Further, the conductive film 635 and the conductive film 613 include a material that transmits visible light. Further, an alignment film 633a is provided between the liquid crystal layer 612 and the conductive film 635, and an alignment film 633b is provided between the liquid crystal layer 612 and the conductive film 613. Further, a polarizing plate 656 is provided on the outer surface of the substrate 661.

In the liquid crystal element 640, the conductive film 663 has a function of reflecting visible light, and the conductive film 613 has a function of transmitting visible light. The light incident from the substrate 661 side is polarized by the polarizing plate 656, passes through the conductive film 613 and the liquid crystal layer 612, and is reflected by the conductive film 663. Then, it passes through the liquid crystal layer 612 and the conductive film 613 again and reaches the polarizing plate 656. At this time, the orientation of the liquid crystal can be controlled by the voltage applied between the conductive film 663 and the conductive film 613, and the optical modulation of light can be controlled. That is, the intensity of the light emitted through the polarizing plate 656 can be controlled. Further, the light is absorbed by the colored layer 631 in a wavelength region other than the specific wavelength region, so that the extracted light becomes, for example, red light.

The light emitting element 660 is a bottom emission type light emitting element. The light emitting element 660 has a laminated structure in which the conductive film 643, the EL layer 644, and the conductive film 645b are laminated in this order from the insulating film 620 side. Further, the conductive film 645a is provided so as to cover the conductive film 645b. The conductive film 645b includes a material that reflects visible light, and the conductive film 643 and the conductive film 645a include a material that transmits visible light. The light emitted by the light emitting element 660 is emitted to the substrate 661 side via the colored layer 634, the insulating film 620, the opening 655, the conductive film 613, and the like.

Here, as shown in FIG. 17, it is preferable that the opening 655 is provided with a conductive film 635 that transmits visible light. As a result, the liquid crystal layer 612 is oriented in the region overlapping the opening 655 as in the other regions, so that it is possible to prevent unintended light leakage due to poor alignment of the liquid crystal at the boundary between these regions. ..

Here, a linear polarizing plate may be used as the polarizing plate 656 arranged on the outer surface of the substrate 661, but a circular polarizing plate may also be used. As the circular polarizing plate, for example, a linear polarizing plate and a 1/4 wavelength retardation plate laminated can be used. Thereby, the reflection of external light can be suppressed. Further, the desired contrast may be realized by adjusting the cell gap, orientation, driving voltage, etc. of the liquid crystal element used for the liquid crystal element 640 according to the type of the polarizing plate.

An insulating film 647 is provided on the insulating film 646 that covers the end of the conductive film 643. The insulating film 647 has a function as a spacer that prevents the insulating film 620 and the substrate 651 from coming closer to each other than necessary. Further, when the EL layer 644 or the conductive film 645a is formed by using a shielding mask (metal mask), it may have a function of suppressing the shielding mask from coming into contact with the surface to be formed. The insulating film 647 may not be provided if it is unnecessary.

One of the source and drain of the transistor 605 is electrically connected to the conductive film 643 of the light emitting element 660 via the conductive film 648.

One of the source and drain of the transistor 606 is electrically connected to the conductive film 663 via the connecting portion 607. The conductive film 663 and the conductive film 635 are provided in contact with each other, and they are electrically connected to each other. Here, the connecting portion 607 is a portion that connects the conductive layers provided on both sides of the insulating film 620 via the openings provided in the insulating film 620.

A connecting portion 604 is provided in a region where the substrate 651 and the substrate 661 do not overlap. The connection portion 604 is electrically connected to the FPC 672 via the connection layer 649. The connection unit 604 has the same configuration as the connection unit 607. On the upper surface of the connecting portion 604, a conductive layer obtained by processing the same conductive film as the conductive film 635 is exposed. As a result, the connection portion 604 and the FPC 672 can be electrically connected via the connection layer 649.

A connecting portion 687 is provided in a part of the region where the adhesive layer 641 is provided. In the connecting portion 687, the conductive layer obtained by processing the same conductive film as the conductive film 635 and a part of the conductive film 613 are electrically connected by the connecting body 686. Therefore, the signal or potential input from the FPC 672 connected to the substrate 651 side can be supplied to the conductive film 613 formed on the substrate 661 side via the connecting portion 687.

As the connecting body 686, for example, conductive particles can be used. As the conductive particles, those obtained by coating the surface of particles such as organic resin or silica with a metal material can be used. It is preferable to use nickel or gold as the metal material because the contact resistance can be reduced. Further, it is preferable to use particles in which two or more kinds of metal materials are coated in layers, such as by further coating nickel with gold. Further, it is preferable to use a material that is elastically deformed or plastically deformed as the connecting body 686. At this time, the connecting body 686, which is a conductive particle, may have a shape that is crushed in the vertical direction as shown in FIG. By doing so, the contact area between the connecting body 686 and the conductive layer electrically connected to the connecting body 686 can be increased, the contact resistance can be reduced, and the occurrence of defects such as poor connection can be suppressed.

The connecting body 686 is preferably arranged so as to be covered with the adhesive layer 641. For example, the connecting body 686 may be dispersed in the adhesive layer 641 before curing.

FIG. 17 shows an example in which the transistor 601 is provided as an example of the circuit 659.

In FIG. 17, as an example of the transistor 601 and the transistor 605, a configuration in which the semiconductor film 653 on which the channel is formed is sandwiched between two gates is applied. One gate is composed of a conductive film 654, and the other gate is composed of a conductive film 623 that overlaps the semiconductor film 653 via an insulating film 682. With such a configuration, the threshold voltage of the transistor can be controlled. At this time, the transistor may be driven by connecting two gates and supplying the same signal to them. Such a transistor can increase the field effect mobility as compared with other transistors, and can increase the on-current. As a result, a circuit capable of high-speed driving can be manufactured. Further, the occupied area of the circuit unit can be reduced. By applying a transistor with a large on-current, it is possible to reduce the signal delay in each wiring even if the number of wirings increases when the display panel is enlarged or the definition is increased, and display unevenness is suppressed. can do.

The transistor included in the circuit 659 and the transistor included in the display unit 662 may have the same structure. Further, the plurality of transistors included in the circuit 659 may all have the same structure, or transistors having different structures may be used in combination. Further, the plurality of transistors included in the display unit 662 may all have the same structure, or transistors having different structures may be used in combination.

For at least one of the insulating film 682 and the insulating film 683 covering each transistor, it is preferable to use a material in which impurities such as water and hydrogen are difficult to diffuse. That is, the insulating film 682 or the insulating film 683 can function as a barrier film. With such a configuration, it is possible to effectively suppress the diffusion of impurities from the outside to the transistor, and a highly reliable display panel can be realized.

On the substrate 661 side, an insulating film 621 is provided so as to cover the colored layer 631 and the light-shielding film 632. The insulating film 621 may have a function as a flattening layer. Since the surface of the conductive film 613 can be made substantially flat by the insulating film 621, the orientation state of the liquid crystal layer 612 can be made uniform.

An example of a method for manufacturing the display panel 600 will be described. For example, a conductive film 635, a conductive film 663, and an insulating film 620 are formed in this order on a supporting substrate having a release layer, and then a transistor 605, a transistor 606, a light emitting element 660, and the like are formed, and then an adhesive layer 642 is used. The substrate 651 and the supporting base material are bonded together. Then, the supporting base material and the peeling layer are removed by peeling at the respective interfaces of the peeling layer and the insulating film 620, and the peeling layer and the conductive film 635. Separately from this, a substrate 661 on which a colored layer 631, a light-shielding film 632, a conductive film 613, and the like are previously formed is prepared. Then, the liquid crystal is dropped on the substrate 651 or the substrate 661, and the substrate 651 and the substrate 661 are bonded to each other by the adhesive layer 641, so that the display panel 600 can be manufactured.

As the release layer, a material that causes release at the interface between the insulating film 620 and the conductive film 635 can be appropriately selected. In particular, a layer containing a refractory metal material such as tungsten and a layer containing an oxide of the metal material are laminated and used as the release layer, and silicon nitride, silicon oxide, and silicon nitride are used as the insulating film 620 on the release layer. It is preferable to use a layer in which a plurality of such layers are laminated. When a refractory metal material is used for the release layer, it is possible to raise the formation temperature of the layer to be formed later, reduce the concentration of impurities, and realize a highly reliable display panel.

As the conductive film 635, it is preferable to use a metal oxide or an oxide or a nitride such as a metal nitride. When a metal oxide is used, a material in which at least one of the concentrations of hydrogen, boron, phosphorus, nitrogen, and other impurities and the amount of oxygen deficiency is higher than that of the semiconductor layer used for the transistor is used as the conductive film 635. It may be used for.

<About each component>
In the following, each component shown above will be described. The description of the configuration having the same function as the function shown in the previous embodiment will be omitted.

[Adhesive layer]
As the adhesive layer, various curable adhesives such as a photocurable adhesive such as an ultraviolet curable type, a reaction curable type adhesive, a thermosetting type adhesive, and an anaerobic type adhesive can be used. Examples of these adhesives include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin and the like. In particular, a material having low moisture permeability such as an epoxy resin is preferable. Further, a two-component mixed type resin may be used. Moreover, you may use an adhesive sheet or the like.

Further, the resin may contain a desiccant. For example, a substance that adsorbs water by chemisorption, such as an oxide of an alkaline earth metal (calcium oxide, barium oxide, etc.), can be used. Alternatively, a substance that adsorbs water by physical adsorption, such as zeolite or silica gel, may be used. When a desiccant is contained, impurities such as water can be suppressed from entering the element, and the reliability of the display panel is improved, which is preferable.

Further, the light extraction efficiency can be improved by mixing the resin with a filler having a high refractive index or a light scattering member. For example, titanium oxide, barium oxide, zeolite, zirconium and the like can be used.

[Connection layer]
As the connecting layer, an anisotropic conductive film (ACF: Anisotropic Conducive Film), an anisotropic conductive paste (ACP: Anisotropic Conducive Paste), or the like can be used.

[Colored layer]
Examples of the material that can be used for the colored layer include a metal material, a resin material, a resin material containing a pigment or a dye, and the like.

[Shading layer]
Examples of the material that can be used as the light-shielding layer include carbon black, titanium black, metal, metal oxide, and composite oxide containing a solid solution of a plurality of metal oxides. The light-shielding layer may be a film containing a resin material or a thin film of an inorganic material such as metal. Further, as the light-shielding layer, a laminated film of a film containing a material of a colored layer can also be used. For example, a laminated structure of a film containing a material used for a colored layer that transmits light of a certain color and a film containing a material used for a colored layer that transmits light of another color can be used. By using the same material for the colored layer and the light-shielding layer, it is preferable because the device can be shared and the process can be simplified.

The above is a description of each component.

<Example of manufacturing method>
Here, an example of a method for manufacturing a display panel using a flexible substrate will be described.

Here, a layer including a display element, a circuit, a wiring, an electrode, an optical member such as a coloring layer or a light-shielding layer, and an insulating layer is collectively referred to as an element layer. For example, the element layer includes a display element, and may include elements such as wiring, pixels, and transistors used in circuits, which are electrically connected to the display element, in addition to the display element.

Further, here, a member that supports the element layer and has flexibility at the stage when the display element is completed (the manufacturing process is completed) is referred to as a substrate. For example, the substrate also includes an extremely thin film having a thickness of 10 nm or more and 300 μm or less.

As a method of forming an element layer on a substrate having flexibility and having an insulating surface, there are typically the following two methods. One is a method of forming an element layer directly on the substrate. The other is a method in which the element layer is formed on a support base material different from the substrate, the element layer and the support base material are peeled off, and the element layer is transposed to the substrate. Although not described in detail here, in addition to the above two methods, a method of forming an element layer on a non-flexible substrate and thinning the substrate by polishing or the like to give flexibility. There is also.

When the material constituting the substrate has heat resistance to the heat applied to the element layer forming process, it is preferable to form the element layer directly on the substrate because the process is simplified. At this time, it is preferable to form the element layer in a state where the substrate is fixed to the supporting base material because it is easy to carry the element layer in and between the devices.

Further, when the method of transferring the element layer to the substrate after forming the element layer on the support base material is used, first, the release layer and the insulating layer are laminated on the support base material, and the element layer is formed on the insulating layer. Subsequently, it is peeled off between the support base material and the element layer, and the element layer is transposed to the substrate. At this time, a material that causes peeling at the interface between the support base material and the release layer, the interface between the release layer and the insulating layer, or the release layer may be selected. In this method, by using a material having high heat resistance for the supporting base material and the release layer, the upper limit of the temperature applied when forming the element layer can be raised, and the element layer having a more reliable element is formed. It is preferable because it can be done.

For example, as the release layer, a layer containing a refractory metal material such as tungsten and a layer containing an oxide of the metal material are laminated and used, and as an insulating layer on the release layer, silicon oxide, silicon nitride, silicon nitride, It is preferable to use a layer in which a plurality of layers such as silicon nitride are laminated.

Examples of the method of peeling the element layer and the supporting base material include applying a mechanical force, etching the peeling layer, and infiltrating a liquid into the peeling interface. Alternatively, the peeling may be performed by heating or cooling by utilizing the difference in the coefficient of thermal expansion of the two layers forming the peeling interface.

Further, if peeling is possible at the interface between the supporting base material and the insulating layer, the peeling layer may not be provided.

For example, glass can be used as the supporting base material, and an organic resin such as polyimide can be used as the insulating layer. At this time, a part of the organic resin is locally heated by using a laser beam or the like, or a part of the organic resin is physically cut or penetrated by a sharp member to form a starting point of peeling. Peeling may be performed at the interface between the glass and the organic resin. Further, as the above-mentioned organic resin, it is preferable to use a photosensitive material because it is easy to form a shape such as an opening. Further, the laser light is preferably light in the wavelength range from visible light to ultraviolet light, for example. For example, light having a wavelength of 200 nm or more and 400 nm or less, preferably light having a wavelength of 250 nm or more and 350 nm or less can be used. In particular, it is preferable to use an excimer laser having a wavelength of 308 nm because it is excellent in productivity. Further, a solid-state UV laser (also referred to as a semiconductor UV laser) such as a UV laser having a wavelength of 355 nm, which is the third harmonic of the Nd: YAG laser, may be used.

Alternatively, a heat generating layer may be provided between the supporting base material and the insulating layer made of an organic resin, and the heat generating layer may be heated to perform peeling at the interface between the heat generating layer and the insulating layer. As the heat generating layer, various materials such as a material that generates heat by passing an electric current, a material that generates heat by absorbing light, and a material that generates heat by applying a magnetic field can be used. For example, the heat generating layer can be selected from semiconductors, metals, and insulators.

In the above method, the insulating layer made of an organic resin can be used as a substrate after peeling.

The above is the description of the method for producing a flexible display panel.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

In this example, the result of measuring the metal oxide which is one aspect of the present invention formed on the substrate by using various measuring methods will be described. In this example, sample 1A was prepared.

<Sample composition and preparation method>
Hereinafter, the sample 1A according to one aspect of the present invention will be described. Sample 1A has a substrate and a metal oxide on the substrate.

Next, a method for producing sample 1A will be described.

First, a glass substrate was used as the substrate. Subsequently, using a sputtering apparatus, an In-Ga-Zn oxide having a thickness of 100 nm was formed as a metal oxide on the substrate. The film forming conditions were such that the substrate temperature was 130 ° C., the oxygen (O ₂ ) flow rate as the sputter gas was 30 sccm, and the argon (Ar) flow rate was 270 sccm, so that the oxygen flow rate ratio was 10%. The pressure in the chamber was 0.6 Pa, and a metal oxide target (In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]) was used as the target. Further, a metal oxide was formed by supplying 2500 W of AC power to the metal oxide target installed in the sputtering apparatus.

By the above steps, sample 1A of this example was prepared.

<Analysis by X-ray diffraction>
In this item, the result of performing X-ray diffraction (XRD) measurement on the metal oxide on the glass substrate will be described. As the XRD apparatus, D8ADVANCE manufactured by Bruker was used. In addition, the condition was a θ / 2θ scan by the Out-of-plane method, and the scanning range was set to 15 deg. To 50 deg. , Step width is 0.02 deg. , Scanning speed is 3.0 deg. / Minute.

FIG. 18 shows the results of measuring the XRD spectrum using the Out-of-plane method.

In the XRD spectrum shown in FIG. 18, a peak intensity near 2θ = 31 ° was detected. The peak near 2θ = 31 ° is derived from the crystalline In-Ga-Zn oxide (also referred to as CAAC-IGZO) oriented in the c-axis in the direction substantially perpendicular to the surface to be formed or the upper surface. I know I will.

Therefore, it was confirmed that sample 1A has a region that becomes CAAC-IGZO.

<TEM image and electron diffraction>
In this item, the result of observing and analyzing Sample 1A by HAADF (High-AngleAnnularDarkField) -STEM (ScanningTransmission Electron Microscope) will be described (hereinafter, the image acquired by HAADF-STEM is also referred to as a TEM image).

The TEM image was observed using the spherical aberration correction function. The HAADF-STEM image was photographed by irradiating an electron beam with an accelerating voltage of 200 kV and a beam diameter of about 0.1 nmφ using an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

Further, in this item, the result of acquiring an electron beam diffraction pattern by irradiating the sample 1A with an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam) will be described.

In addition, the electron diffraction pattern was observed while irradiating the electron beam and moving the electron beam from the position of 0 seconds to the position of 35 seconds at a constant speed.

FIG. 19A shows a TEM image of the cross section of the sample 1A (hereinafter, also referred to as a cross section TEM).

Here, for example, when an electron beam having a probe diameter of 300 nm is incident on CAAC-OS having a crystal of InGaZnO ₄ in parallel with the sample surface, a spot caused by the (009) plane of the crystal of InGaZnO ₄ is included. It is known that a diffraction pattern can be seen. That is, it can be seen that CAAC-OS has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface. On the other hand, when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface, a ring-shaped diffraction pattern is confirmed. That is, it can be seen that the CAAC-OS has no orientation on the a-axis and the b-axis.

Further, an electron beam having a large probe diameter (for example, 50 nm or more) is used for a metal oxide having microcrystals (particularly, when it has a function equivalent to that of a semiconductor, it is referred to as a nanodiffraction linear diffraction; hereinafter referred to as nc-OS). When electron diffraction is performed, a diffraction pattern such as a halo pattern is observed. Further, when nanobeam electron diffraction is performed on a metal oxide having microcrystals using an electron beam having a small probe diameter (for example, less than 50 nm), a bright spot is observed. Further, when nanobeam electron diffraction is performed on a metal oxide having microcrystals, a region having high brightness (in a ring shape) may be observed in a circular motion. Furthermore, a plurality of bright spots may be observed in the ring-shaped region.

As shown in FIG. 19A, the sample 1A had a CAAC structure and microcrystals (nanocrystal, also referred to as nc) observed from the cross-sectional TEM observation results. Further, as shown in FIG. 19B, as a result of the electronic analysis pattern for the sample 1A, a region having high brightness could be observed in a circular motion (ring shape). In addition, multiple spots could be observed in the ring-shaped region. In addition, a few diffraction patterns including spots due to the (009) plane were also observed.

The features observed in the cross-sectional TEM image and the planar TEM image as described above are one-sided captures of the structure of the metal oxide.

Therefore, sample 1A is a composite material having at least two types of crystal structures, an nc structure and a CAAC structure, and may have properties that are clearly different from those of an amorphous metal oxide and a single crystal metal oxide. Do you get it.

From the above, the electron diffraction pattern of sample 1A has a ring-shaped region having high brightness and a plurality of bright spots in the ring region. Therefore, it was found that the electron diffraction pattern of Sample 1A was microcrystals and metal oxides having a CAAC structure, and had no orientation in the planar direction and the cross-sectional direction.

<Image analysis of TEM image>
In this item, the results of observing and analyzing sample 1A by HAADF-STEM will be described with reference to FIG.

Hereinafter, the results of image analysis of a TEM image on a plane (hereinafter, also referred to as a plane TEM) will be described. FIG. 21 (A) shows a flat TEM image of the sample 1A, and FIG. 21 (B) shows an image of the flat TEM image processed.

The method of image processing and image analysis will be described. First, as image processing, an FFT image was obtained by performing a fast Fourier transform (FFT) process on the planar TEM image shown in FIG. 21. Next, an FFT image obtained was subjected to mask processing, leaving the scope of 5.0 nm ^-1 from 2.8 nm ^-1. Next, the masked FFT image was subjected to an inverse fast Fourier transform (IFFT) process to obtain an FFT filtering image.

As an image analysis, first, grid points were extracted from the FFT filtering image. The grid points were extracted according to the following procedure. First, a process of removing noise from the FFT filtering image was performed. As a process for removing noise, the brightness in a radius of 0.05 nm was smoothed by the following equation.

Here, S_Int (x, y) indicates the smoothed brightness at the coordinates (x, y), r indicates the distance between the coordinates (x, y) and the coordinates (x', y'), and Int ( x', y') indicates the brightness at the coordinates (x', y'). When r was 0, r was set to 1 for calculation.

Next, the grid points were searched. The grid point conditions were coordinates with higher brightness than all grid point candidates within a radius of 0.22 nm. Here, grid point candidates were extracted. If the radius is within 0.22 nm, the frequency of false detection of grid points due to noise can be reduced. Further, since there is a certain distance between the grid points in the TEM image, it is unlikely that two or more grid points are included in the radius of 0.22 nm.

Next, the coordinates with the highest brightness within a radius of 0.22 nm were extracted centering on the extracted grid point candidates, and the grid point candidates were updated. The extraction of grid point candidates was repeated, and the coordinates when new grid point candidates did not appear were recognized as grid points. Similarly, at a position more than 0.22 nm away from the certified grid points, the grid points were certified in the entire range by performing the certification of new grid points. The obtained plurality of grid points are collectively referred to as a grid point group.

Next, the method of deriving the angle of the hexagonal grid from the extracted grid point cloud is shown in FIGS. 20 (A), 20 (B), 20 (C), and 20 (D). This will be described using a flowchart. First, a reference grid point was determined, and the six closest grid points were connected to form a hexagonal grid (see steps S101 in FIGS. 20 (A) and 20 (D)). Then, the average value R of the distances from the reference lattice point, which is the center point of the hexagonal lattice, to each lattice point, which is the apex, was derived. The calculated R was used as the distance to each vertex, and a regular hexagon centered on the reference grid point was formed (see step S102 in FIG. 20 (D)). At this time, the distances between the vertices of the regular hexagon and the nearest grid points closest to each are set to distance d1, distance d2, distance d3, distance d4, distance d5, and distance d6 (see step S103 in FIG. 20 (D)). ). Next, the regular hexagon is rotated from 0 ° to 60 ° in 0.1 ° increments with respect to the center point, and the average deviation [D = (d1 + d2 + d3 + d4 + d5 + d6) / 6] between the rotated regular hexagon and the hexagonal grid is calculated. Calculated (see step S104 in FIG. 20 (D)). Then, the rotation angle θ of the regular hexagon when the average deviation D is minimized was obtained and used as the angle of the hexagonal grid (step S105 in FIG. 20D).

Next, in the observation range of the plane TEM image, the ratio of the hexagonal lattice angle to 30 ° was adjusted to be the highest. Here, the average value of the angles of the hexagonal lattice was calculated in the range of a radius of 1 nm. Subsequently, the planar TEM image obtained through the image processing was displayed in color or shade according to the angle of the hexagonal lattice of the region. The image of the planar TEM image shown in FIG. 21 is an image obtained by image-analyzing the planar TEM image shown in FIG. 21 by the above-mentioned method and showing shading according to the angle of the hexagonal lattice. That is, the image processed from the planar TEM image is an image obtained by extracting the orientation of the grid points of each specific frequency domain by color-coding the specific frequency domain in the FFT filtering image of the planar TEM image.

From FIG. 21 (A), nc was observed in sample 1A. Further, from FIG. 21 (B), a region (CAAC-OS) in which the directions of the hexagons show the same direction over a wide range of several nm to several tens of nm and the directions of the hexagons are random and distributed in a mosaic pattern. It was found to have a region (nc-OS).

<Elemental analysis>
In this section, the result of elemental analysis of sample 1A will be described by acquiring and evaluating EDX mapping using Energy Dispersive X-ray Spectroscopy (EDX). For the EDX measurement, an energy dispersive X-ray analyzer JED-2300T manufactured by JEOL Ltd. is used as an elemental analyzer. A Si drift detector is used to detect the X-rays emitted from the sample.

In the EDX measurement, electron beam irradiation is performed at each point in the analysis target region of the sample, and the energy and the number of generations of the characteristic X-ray of the sample generated by this are measured to obtain the EDX spectrum corresponding to each point. In this embodiment, the peak of the EDX spectrum at each point is transferred to the electron transition of the In atom to the L shell, the electron transition of the Ga atom to the K shell, the electron transition of the Zn atom to the K shell, and the electron transition of the O atom to the K shell. It is attributed to the electron transition of, and the ratio of each atom at each point is calculated. By doing this for the analysis target region of the sample, EDX mapping showing the distribution of the ratio of each atom can be obtained.

FIG. 22 shows a cross-sectional TEM image of sample 1A and EDX mapping. Further, FIG. 23 shows a planar TEM image of sample 1A and EDX mapping. In the EDX mapping, the ratio of elements was shown in light and dark so that the more the measurement element was, the brighter the image was, and the less the measurement element was, the darker the image. The magnification of the EDX mapping shown in FIG. 23 was set to 7.2 million times.

22 (A) is a cross-sectional TEM image, and FIG. 23 (A) is a flat TEM image.

FIG. 22B is an EDX mapping of O atoms in a cross section, and FIG. 23B is an EDX mapping of O atoms in a plane. The ratio of O atoms to all atoms in the EDX mapping shown in FIG. 22 (B) was in the range of 32.76 to 73.08 [atomic%]. The ratio of O atoms to all atoms in the EDX mapping shown in FIG. 23 (B) was in the range of 21.57 to 61.56 [atomic%].

FIG. 22C is an EDX mapping of Zn atoms in a cross section, and FIG. 23C is an EDX mapping of Zn atoms in a plane. The ratio of Zn atoms to all atoms in the EDX mapping shown in FIG. 22C was in the range of 6.13 to 28.45 [atomic%]. The ratio of Zn atoms to all atoms in the EDX mapping shown in FIG. 23 (C) was in the range of 7.5 to 31.90 [atomic%].

FIG. 22 (D) is an EDX mapping of Ga atoms in a cross section, and FIG. 23 (D) is an EDX mapping of Ga atoms in a plane. The ratio of Ga atoms to all atoms in the EDX mapping shown in FIG. 22 (D) was in the range of 0.00 to 21.14 [atomic%]. The ratio of Ga atoms to all atoms in the EDX mapping shown in FIG. 23 (D) was in the range of 1.28 to 23.63 [atomic%].

FIG. 22 (E) is an EDX mapping of In atoms in a cross section, and FIG. 23 (E) is an EDX mapping of In atoms in a plane. The ratio of In atoms to all atoms in the EDX mapping shown in FIG. 22 (E) was in the range of 9.61 to 40.10 [atomic%]. The ratio of In atoms to all atoms in the EDX mapping shown in FIG. 23 (E) was in the range of 13.83 to 45.10 [atomic%].

In the EDX mapping shown in FIGS. 22 (A), 22 (B), 22 (C), 22 (D), 23 (A), 23 (B), and 23 (D), the image is shown. A relative light-dark distribution was observed, and it was confirmed that each atom had a distribution in sample 1A.

Further, the atoms are unevenly distributed in FIGS. 22 (A), 22 (B), 22 (C), 22 (D), 23 (A), 23 (B), and 23 (D). The size of the region was observed at 0.5 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less.

From the above, it was found that CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. That is, the CAC-OS is phase-separated into a region in which In _a Ga _b Zn _{c Od} or the like is the main component and a region in which In _X2 Zn _Y2 O _Z2 or In O _X1 is the main component, and each element is separated from each other. It was confirmed that the region mainly composed of zinc has a mosaic-like structure.

Therefore, when CAC-OS is used for a semiconductor element, the properties caused by In _a Ga _b Zn _{c Od and the} like and the properties caused by In _X2 Zn _Y2 O _Z2 or In O _X1 act in a complementary manner. This can be expected to achieve high on-current (I _on ), high field-effect mobility (μ), and low off-current (I _off ). Further, the semiconductor element using CAC-IGZO has high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices such as displays.

This example can be carried out at least in part in combination with other embodiments described herein or in combination with other examples as appropriate.

In this example, a transistor 150 having a metal oxide 108, which is one aspect of the present invention, was produced and tested for electrical characteristics and reliability. In this example, sample 2A was prepared as the transistor 150 having the metal oxide 108.

<Sample composition and preparation method>
Hereinafter, the sample 2A according to one aspect of the present invention will be described. As sample 2A, a transistor 150 having the structure of FIG. 6 was produced by the production method described in the second embodiment and FIGS. 9 to 11.

The sample 2A was prepared by the production method described in the second embodiment. Further, in the film forming process of the metal oxide 108, the film forming conditions are such that the substrate temperature is 130 ° C., the oxygen (O ₂ ) flow rate as the sputter gas is 30 sccm, and the argon (Ar) flow rate is 270 sccm. The flow rate ratio was set to 10%. The pressure in the chamber was 0.6 Pa, and a metal oxide target (In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]) was used as the target. Further, 2500 W of AC power was supplied to the metal oxide target installed in the sputtering apparatus.

The channel length of the transistor 150 is 2 μm and the channel width is 3 μm (hereinafter, also referred to as L / W = 2/3 μm), or the channel length is 2 μm and the channel width is 50 μm (hereinafter, also referred to as L / W = 2/50 μm). ).

<Electrical characteristics of transistors>
Next, the electrical characteristics of the transistor (L / W = 2/3 μm) of the prepared sample 2A were measured. The measurement result is shown in FIG.

As the measurement conditions for the Id-Vg characteristic of the transistor, the voltage applied to the conductive film 112 that functions as the first gate electrode (hereinafter, also referred to as the gate voltage (Vg)) and the function as the second gate electrode. The voltage (also referred to as Vbg) applied to the conductive film 106 was applied in steps of 0.25 V from −10 V to + 10 V. Further, the voltage applied to the conductive film 120a functioning as a source electrode (hereinafter, a source voltage (referred to _{V s)} and also) and 0V (comm), the voltage applied to the conductive film 120b functioning as a drain electrode (hereinafter, the drain voltage (Also referred to as (Vd)) was 0.1 V and 20 V.

[Transistor Id-Vg characteristics]
Here, the drain current-gate voltage characteristic (Id-Vg characteristic) of the transistor will be described. FIG. 25A is a diagram illustrating an example of the Id-Vg characteristic of the transistor. In FIG. 25A, it is assumed that polycrystalline silicon is used as the active layer of the transistor for the sake of simplicity. Further, in FIG. 25A, the vertical axis represents Id and the horizontal axis represents Vg.

As shown in FIG. 25 (A), the Id-Vg characteristic can be roughly divided into three regions. The first region is referred to as an OFF region, the second region is referred to as a subthreshold region, and the third region is referred to as an ON region. Further, the gate voltage at the boundary between the subthreshold region and the on region is referred to as a threshold voltage (Vth).

As the characteristics of the transistor, it is desirable that the drain current in the off region (also referred to as off current or If) is low and the drain current in the on region (also referred to as on current or Ion) is high. The field-effect mobility is often used as an index for the on-current of the transistor. The details of the field effect mobility will be described later.

Further, in order to drive the transistor at a low voltage, it is desirable that the slope of the Id-Vg characteristic in the subthreshold region is steep. As an index showing the magnitude of the change in the Id-Vg characteristic of the subthreshold region, it is called SS (subthresholdswing) or S value. The S value is represented by the following equation (1).

The S value is the minimum value of the amount of change in the gate voltage required for the drain current to change by an order of magnitude in the subthreshold region. The smaller the S value, the steeper the switching operation between on and off can be performed.

[Transistor Id-Vd characteristics]
Next, the drain current-drain voltage characteristic (Id-Vd characteristic) of the transistor will be described. FIG. 25B is a diagram illustrating an example of the Id-Vd characteristic of the transistor. Further, in FIG. 25B, the vertical axis represents Id and the horizontal axis represents Vd.

As shown in FIG. 25 (B), the on region is further divided into two regions. The first region is referred to as a linear region, and the second region is referred to as a saturation region. In the linear region, the drain current increases in a parabolic manner as the drain voltage rises. On the other hand, in the saturated region, the drain current does not change significantly even if the drain voltage changes. According to the vacuum tube, the linear region may be referred to as a triode region and the saturated region may be referred to as a pentode region.

Further, the linear region may refer to a state in which Vg is larger than Vd (Vd <Vg). Further, the saturation region may refer to a state in which Vd is larger than Vg (Vg <Vd). However, in practice, it is necessary to consider the threshold voltage of the transistor. Therefore, the value obtained by subtracting the threshold voltage of the transistor (Vd <Vg-Vth) may be set as the linear region. Similarly, the saturation region may be a value obtained by subtracting the threshold voltage of the transistor (Vg-Vth <Vd).

In the Id-Vd characteristic of a transistor, a characteristic in which the current in the saturation region is constant may be expressed as "good saturation". Good transistor saturation is especially important in applications to organic EL displays. For example, by using a transistor having good saturation as a transistor of a pixel of an organic EL display, it is possible to suppress a change in the brightness of the pixel even if the drain voltage changes.

[Drain current analysis model]
Next, an analysis model of the drain current will be described. As an analysis model of the drain current, an analysis formula of the drain current based on the Global channel approximation (GCA) is known. Based on GCA, the drain current of the transistor is represented by the following equation (2).

In the formula (2), the upper part is the formula of the drain current in the linear region, and the lower part is the formula of the drain current in the saturated region. In formula (2), Id is the drain current, μ is the mobility of the active layer, L is the transistor channel length, W is the transistor channel width, Cox is the gate capacitance, Vg is the gate voltage, Vd is the drain voltage, and Vth is. Represents the threshold voltage of each transistor.

[Electric field effect mobility]
Next, the electric field effect mobility will be described. The field effect mobility is used as an index of the current driving force of the transistor. As described above, the on region of the transistor is divided into a linear region and a saturated region. From the characteristics of each region, the field effect mobility of the transistor can be calculated based on the analysis formula of the drain current based on GCA. When it is necessary to distinguish between them, they are called linear mobility and saturation mobility, respectively. The linear mobility is represented by the following equation (3), and the saturated mobility is represented by the following equation (4).

In the present specification and the like, the curves calculated from the equations (3) and (4) are referred to as mobility curves. FIG. 26 shows the mobility curve calculated from the analysis formula of the drain current based on GCA. In FIG. 26, the Id-Vg characteristic of Vd = 10V when GCA is effective and the mobility curves of the linear mobility and the saturation mobility are shown in an overlapping manner.

In FIG. 26, the Id-Vg characteristic is calculated from the analysis formula of the drain current based on GCA. The shape of the mobility curve is a clue to understand the inside of the transistor.

FIG. 24 shows the Id-Vg characteristic result of sample 2A and the field effect mobility. The solid line shows Id when Vd is 20V, and the alternate long and short dash line shows Id when Vd is 0.1V. The broken line indicates the electric field effect mobility. In FIG. 24, the first vertical axis represents Id [A], the second vertical axis represents field effect mobility (μFE [cm ² / V _s ]), and the horizontal axis represents Vg [V]. The field effect mobility was calculated from the value measured with Vd set to 20V.

From FIG. 24, it was found that the sample 2A had a good rise near 0 V and exhibited a high on-current (I _on ). It was also found to have high field effect mobility.

Therefore, it was found that the use of the metal oxide of one aspect of the present invention in a transistor has a high on-current ( _Ion ) and a high field effect mobility. It can be inferred that this is due to the high carrier density in the metal oxide.

This example can be carried out at least in part in combination with other embodiments described herein or in combination with other examples as appropriate.

001 region 002 region 100 transistor 102 substrate 104 insulating film 106 conductive film 108 metal oxide 108a metal oxide 108i region 108n region 110 insulating film 110_0 insulating film 112 conductive film 112_0 conductive film 112_1 conductive film 112_2 conductive film 116 insulating film 118 insulating film 120a Conductive 120b Conductive 122 Insulating film 140 Mask 141a Opening 141b Opening 143 Opening 150 Transistor 160 Transistor 300A Transistor 300B Transistor 300C Transistor 300D Transistor 302 Substrate 304 Conductive 306 Insulating film 307 Insulating film 308 Metal oxide 312a Conductive 312b Conductive 314 Insulating film 316 Insulating film 318 Insulating film 320a Conductive 320b Conductive 341a Opening 341b Opening 342a Opening 342b Opening 342c Opening 600 Display panel 601 Transistor 604 Connection 605 Transistor 606 Transistor 607 Connection 612 Liquid crystal Layer 613 Conductive 617 Insulating film 620 Insulating film 621 Insulating film 623 Conductive 631 Colored layer 632 Light shielding film 633a Alignment film 633b Alignment film 634 Colored layer 635 Conductive 640 Liquid crystal element 641 Adhesive layer 642 Adhesive layer 643 Conductive 644 EL layer 645a Conductive Film 645b Conductive 646 Insulating film 647 Insulating film 648 Conductive 649 Connection layer 651 Substrate 652 Conductive 653 Semiconductor film 654 Conductive 655 Opening 656 Plate plate 659 Circuit 660 Light emitting element 661 Board 662 Display 663 Conductive 666 Wiring 672 FPC
673IC
681 Insulation film 682 Insulation film 683 Insulation film 684 Insulation film 685 Insulation film 686 Connection body 687 Connection part

Claims (7)

A transistor having a metal oxide in the channel region
The metal oxide has a first region and a second region.
The first region has In, Ga and Zn and has
The second region has In, Ga and Zn and has
The lower end of the conduction band of the energy band of the first region is lower than that of the second region.
The first region is a transistor having more carriers than the second region. (However, this excludes the case where the first region and the second region are films and are laminated.) A transistor having a metal oxide in the channel region
The metal oxide has a first region and a second region.
The first region has In, Ga and Zn and has
The second region has In, Ga and Zn and has
The lower end of the conduction band of the energy band of the first region is lower than that of the second region.
The first region has more carriers than the region where the lower end of the conduction band is high.
A transistor in which the position of each valence band is different between the first region and the second region. (However, this excludes the case where the first region and the second region are films and are laminated.) In claim 1 or 2,
A transistor in which the second region has a higher concentration of Ga than the first region, and the first region has a higher concentration of In than the second region. In any one of claims 1 to 3,
The metal oxide is a transistor having particles having a diameter of 0.5 nm or more and 10 nm or less. A display device having the transistor according to any one of claims 1 to 4.
The display device has a display unit and a driver for driving the display unit on a substrate.
The driver is a display device having the transistor. A display device having the transistor according to any one of claims 1 to 4.
The display device has a scanning line drive circuit and a display unit on the substrate.
The scanning line drive circuit is a display device having the transistor. A display device having the transistor according to any one of claims 1 to 4.
The display device has a signal line drive circuit and a display unit on the substrate.
The signal line drive circuit is a display device having the transistor.