JP6798952B2 - Manufacturing method of semiconductor device, light emitting device and semiconductor device - Google Patents

Manufacturing method of semiconductor device, light emitting device and semiconductor device Download PDF

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JP6798952B2
JP6798952B2 JP2017167514A JP2017167514A JP6798952B2 JP 6798952 B2 JP6798952 B2 JP 6798952B2 JP 2017167514 A JP2017167514 A JP 2017167514A JP 2017167514 A JP2017167514 A JP 2017167514A JP 6798952 B2 JP6798952 B2 JP 6798952B2
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神野 優志
優志 神野
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Kyocera Corp
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本発明は、半導体層を含んで構成される薄膜トランジスタ(Thin Film Transistor:TFT)を有する半導体装置、その半導体装置に発光ダイオード(Light Emitting Diode:LED)等の発光素子を実装して構成される発光装置、及び半導体装置の製造方法に関するものである。 The present invention is a semiconductor device having a thin film transistor (TFT) composed of a semiconductor layer, and light emission configured by mounting a light emitting element such as a light emitting diode (LED) on the semiconductor device. It relates to a device and a method of manufacturing a semiconductor device.

従来、発光装置の一種として、LED等の発光素子を複数有する、バックライト装置が不要な自発光型の表示装置が知られている。そのような表示装置の基本構成のブロック回路図を図5(a)に示す。また、図5(a)の構成の表示装置の下面図を図5(b)に示し、図5(a)のA1−A2線における断面図を図6(a)に示し、図5(a)における一つの発光素子14と発光制御部の回路図を図6(b)に示す。表示装置は、ガラス基板等から成る絶縁基板1と、絶縁基板1上の所定の方向(例えば、行方向)に配置された走査信号線2と、走査信号線2と交差させて所定の方向と交差する方向(例えば、列方向)に配置された発光制御信号線3と、走査信号線2と発光制御信号線3によって区分けされた画素部(Pmn)の複数から構成された表示部11と、表示部11を覆う絶縁層上に配置された複数の発光領域(Lmn)と、を有する構成である。走査信号線2および発光制御信号線3は、絶縁基板1の側面に配置された側面配線1sを介して絶縁基板1の裏面にある裏面配線9に接続される。裏面配線9は、絶縁基板1の裏面に設置されたIC,LSI等の駆動素子6に接続される。即ち、表示装置は絶縁基板1の裏面にある駆動素子6によって表示が駆動制御される。駆動素子6は、例えば、絶縁基板1の裏面側にCOG(Chip On Glass)方式等の手段によって搭載される。また、絶縁基板1の裏面側には、駆動素子6との間で引き出し線を介して駆動信号、制御信号等を入出力するためのFPCが設置される場合がある。また側面配線1sに替えてスルーホール等の貫通導体を用いる場合がある。 Conventionally, as a kind of light emitting device, a self-luminous display device having a plurality of light emitting elements such as LEDs and which does not require a backlight device is known. A block circuit diagram of the basic configuration of such a display device is shown in FIG. 5 (a). Further, a bottom view of the display device having the configuration of FIG. 5 (a) is shown in FIG. 5 (b), and a cross-sectional view taken along line A1-A2 of FIG. 5 (a) is shown in FIG. 6 (a). The circuit diagram of one light emitting element 14 and the light emitting control unit in) is shown in FIG. 6 (b). The display device has an insulating substrate 1 made of a glass substrate or the like, a scanning signal line 2 arranged in a predetermined direction (for example, a row direction) on the insulating substrate 1, and a predetermined direction intersecting the scanning signal line 2. A display unit 11 composed of a plurality of light emission control signal lines 3 arranged in intersecting directions (for example, column directions), and a plurality of pixel units (Pmn) separated by scanning signal lines 2 and light emission control signal lines 3. It has a configuration having a plurality of light emitting regions (Lmn) arranged on an insulating layer covering the display unit 11. The scanning signal line 2 and the light emission control signal line 3 are connected to the back surface wiring 9 on the back surface of the insulating substrate 1 via the side surface wiring 1s arranged on the side surface of the insulating substrate 1. The back surface wiring 9 is connected to a drive element 6 such as an IC or LSI installed on the back surface of the insulating substrate 1. That is, the display of the display device is driven and controlled by the drive element 6 on the back surface of the insulating substrate 1. The drive element 6 is mounted on the back surface side of the insulating substrate 1 by means such as a COG (Chip On Glass) method. Further, on the back surface side of the insulating substrate 1, an FPC for inputting / outputting a drive signal, a control signal, or the like to / from the drive element 6 via a lead wire may be installed. Further, a through conductor such as a through hole may be used instead of the side wiring 1s.

それぞれの画素部15(Pmn)には、発光領域(Lmn)にある発光素子14(LDmn)の発光、非発光、発光強度等を制御するための発光制御部22が配置されている。この発光制御部22は、発光素子14のそれぞれに発光信号を入力するためのスイッチ素子としての薄膜トランジスタ(Thin Film Transistor:TFT)12(図6(b)に示す)と、発光制御信号(発光制御信号線3を伝達する信号)のレベル(電圧)に応じた、正電圧(アノード電圧:3〜5V程度)と負電圧(カソード電圧:−3V〜0V程度)の電位差(発光信号)から発光素子14を電流駆動するための駆動素子としてのTFT13(図6(b)に示す)と、を含む。TFT13のゲート電極とソース電極とを接続する接続線上には容量素子43(図6(b)に示す)が配置されており、容量素子43はTFT13のゲート電極に入力された発光制御信号の電圧を次の書き換えまでの期間(1フレームの期間)保持する保持容量として機能する。 Each pixel unit 15 (Pmn) is provided with a light emission control unit 22 for controlling light emission, non-light emission, light emission intensity, etc. of the light emitting element 14 (LDmn) in the light emitting region (Lmn). The light emission control unit 22 includes a thin film transistor (TFT) 12 (shown in FIG. 6B) as a switch element for inputting a light emission signal to each of the light emission elements 14, and a light emission control signal (light emission control). Light emitting element from the potential difference (light emitting signal) between positive voltage (anode voltage: about 3 to 5V) and negative voltage (cathode voltage: about -3V to 0V) according to the level (voltage) of the signal line 3). A TFT 13 (shown in FIG. 6B) as a driving element for driving the 14 with a current is included. A capacitive element 43 (shown in FIG. 6B) is arranged on a connecting line connecting the gate electrode and the source electrode of the TFT 13, and the capacitive element 43 is the voltage of the light emission control signal input to the gate electrode of the TFT 13. Functions as a holding capacity for holding the period until the next rewriting (a period of one frame).

発光素子14は、表示部11を覆う絶縁層31(図6(a)に示す)を貫通するスルーホール等の貫通導体23a,23bを介して、発光制御部22、正電圧入力線16、負電圧入力線17に電気的に接続されている。即ち、発光素子14の正電極は、貫通導体23a及び発光制御部22を介して正電圧入力線16に接続されており、発光素子14の負電極は、貫通導体23bを介して負電圧入力線17に接続されている。また表示装置は、平面視において、表示部11と絶縁基板1の端1tとの間に額縁部1gがある。 The light emitting element 14 has a light emitting control unit 22, a positive voltage input line 16, and a negative voltage through through conductors 23a and 23b such as through holes that penetrate the insulating layer 31 (shown in FIG. 6A) that covers the display unit 11. It is electrically connected to the voltage input line 17. That is, the positive electrode of the light emitting element 14 is connected to the positive voltage input line 16 via the through conductor 23a and the light emission control unit 22, and the negative electrode of the light emitting element 14 is connected to the negative voltage input line via the through conductor 23b. It is connected to 17. Further, the display device has a frame portion 1g between the display portion 11 and the end 1t of the insulating substrate 1 in a plan view.

なお、画素部15は、それぞれが赤色発光用の副画素部、緑色発光用の副画素部、青色発光用の副画素部から成る場合がある。赤色発光用の副画素部は赤色LED等から成る赤色発光素子を有し、緑色発光用の副画素部は緑色LED等から成る緑色発光素子を有し、青色発光用の副画素部は青色LED等から成る青色発光素子を有している。例えば、これらの副画素部は、行方向あるいは列方向に並んでいる。 The pixel unit 15 may be composed of a sub-pixel unit for red light emission, a sub-pixel unit for green light emission, and a sub-pixel unit for blue light emission, respectively. The sub-pixel part for red light emission has a red light emitting element composed of a red LED or the like, the sub pixel part for green light emission has a green light emitting element composed of a green LED or the like, and the sub pixel part for blue light emission has a blue LED. It has a blue light emitting element made of such as. For example, these sub-pixel portions are arranged in the row direction or the column direction.

図7(a),(b)は、正電圧入力線16と負電圧入力線17のそれぞれに貫通導体16k,17kが接続された構成を示すブロック回路図である。図7(a)は、額縁部1gに貫通導体16k,17kが配置されている構成を示し、図7(b)は、表示部11に貫通導体16k,17kが配置されている構成を示している。これらの貫通導体16k,17kは、側面配線1sと比較して低抵抗であるために、正電圧入力線16及び負電圧入力線17における電源電圧の電圧降下を小さくする目的で設けられる。表示部11に貫通導体16k,17kが配置されている場合、正電圧入力線16及び負電圧入力線17における電源電圧の電圧降下をより小さくすることができる。貫通導体16k,17kは、絶縁基板1の裏面配線9に接続されており、さらに駆動素子6、他の駆動素子または外部装置に接続されるフレキシブルプリント回路基板(Flexible Printed Circuit:FPC)の回路配線等に、電気的に接続される。 7 (a) and 7 (b) are block circuit diagrams showing a configuration in which through conductors 16k and 17k are connected to the positive voltage input line 16 and the negative voltage input line 17, respectively. FIG. 7A shows a configuration in which the through conductors 16k and 17k are arranged in the frame portion 1g, and FIG. 7B shows a configuration in which the through conductors 16k and 17k are arranged in the display unit 11. There is. Since these through conductors 16k and 17k have lower resistance than the side wiring 1s, they are provided for the purpose of reducing the voltage drop of the power supply voltage in the positive voltage input line 16 and the negative voltage input line 17. When the through conductors 16k and 17k are arranged on the display unit 11, the voltage drop of the power supply voltage on the positive voltage input line 16 and the negative voltage input line 17 can be made smaller. The through conductors 16k and 17k are connected to the back surface wiring 9 of the insulating substrate 1, and further, the circuit wiring of the flexible printed circuit board (FPC) connected to the driving element 6, another driving element, or an external device. Etc., are electrically connected.

図8は、図7(b)のB1−B2線における断面図であって、TFT13及び発光素子14の部位を透視した断面図である。図8に示すように、絶縁基板1は貫通導体16kを有しており、絶縁基板1上には複数の絶縁層31が配置され、複数の絶縁層31の層間には貫通導体16kに電気的に接続されているTFT13がある。貫通導体16kを構成する導体は、Cu,Ni,Cr,Al,Ag,Mo等の金属またはそれらの1種以上を含む合金から成る。複数の絶縁層31は、絶縁基板1側から順に第1絶縁層31a、第2絶縁層31b、第3絶縁層31c、第4絶縁層31dが積層されており、第1絶縁層31a、第2絶縁層31b、第3絶縁層31cは、それぞれ酸化珪素(SiO2),窒化珪素(SiNx)等から成り、第4絶縁層31dはアクリル系樹脂,ポリカーボネート等から成る。貫通導体16kは、絶縁基板1上にある、Mo層/Al層/Mo層(Mo層上にAl層、Mo層が順次積層された積層構造を示す)等から成る正電圧入力線16に接続されており、正電圧入力線16はTFT13のソース電極13sにスルーホール52を介して接続されている。 FIG. 8 is a cross-sectional view taken along the line B1-B2 of FIG. 7 (b), which is a cross-sectional view showing the portions of the TFT 13 and the light emitting element 14. As shown in FIG. 8, the insulating substrate 1 has a through conductor 16k, a plurality of insulating layers 31 are arranged on the insulating substrate 1, and the through conductor 16k is electrically connected between the layers of the plurality of insulating layers 31. There is a TFT 13 connected to. The conductor constituting the through conductor 16k is made of a metal such as Cu, Ni, Cr, Al, Ag, Mo or an alloy containing one or more of them. In the plurality of insulating layers 31, the first insulating layer 31a, the second insulating layer 31b, the third insulating layer 31c, and the fourth insulating layer 31d are laminated in this order from the insulating substrate 1 side, and the first insulating layer 31a and the second insulating layer 31a are laminated. The insulating layer 31b and the third insulating layer 31c are made of silicon oxide (SiO 2 ), silicon nitride (SiN x ), etc., respectively, and the fourth insulating layer 31d is made of acrylic resin, polycarbonate, etc. The through-conductor 16k is connected to a positive voltage input line 16 composed of a Mo layer / Al layer / Mo layer (indicating a laminated structure in which an Al layer and a Mo layer are sequentially laminated on the Mo layer) on the insulating substrate 1. The positive voltage input line 16 is connected to the source electrode 13s of the TFT 13 via a through hole 52.

TFT13のゲート電極13gは、第1絶縁層31aと第2絶縁層31bとの層間に配置され、TFT13の半導体層13aは、第2絶縁層32bと第3絶縁層31cとの層間に配置され、TFT13のソース電極13sとドレイン電極13dは、第3絶縁層32cと第4絶縁層31dとの層間に配置されている。ソース電極13sは半導体層13aにスルーホール53を介して接続され、ドレイン電極13dは半導体層13aにスルーホール54を介して接続され、またドレイン電極13dは、正電極44aを構成する電極層42aにスルーホール55を介して接続されている。 The gate electrode 13g of the TFT 13 is arranged between the first insulating layer 31a and the second insulating layer 31b, and the semiconductor layer 13a of the TFT 13 is arranged between the second insulating layer 32b and the third insulating layer 31c. The source electrode 13s and the drain electrode 13d of the TFT 13 are arranged between the third insulating layer 32c and the fourth insulating layer 31d. The source electrode 13s is connected to the semiconductor layer 13a via a through hole 53, the drain electrode 13d is connected to the semiconductor layer 13a via a through hole 54, and the drain electrode 13d is connected to the electrode layer 42a constituting the positive electrode 44a. It is connected via a through hole 55.

発光素子14は、絶縁層31上に配置された正電極44aと負電極44bにハンダ等の導電性接続部材を介して電気的に接続されて、絶縁層31上に実装される。正電極44aは、Mo層/Al層/Mo層等から成る電極層42aと、それを覆う酸化インジウム錫(Indium Tin Oxide:ITO)等から成る透明電極43aと、から成る。負電極44bも同様の構成であり、Mo層/Al層/Mo層等から成る電極層42bと、それを覆うITO等から成る透明電極43bと、から成る。絶縁層31と、透明電極43a,43bのそれぞれの一部(発光素子14が重ならない部位)と、を覆って、絶縁層45が配置されており、この絶縁層45は酸化珪素(SiO2),窒化珪素(SiNx)等から成る(例えば、特許文献1を参照)。 The light emitting element 14 is electrically connected to the positive electrode 44a and the negative electrode 44b arranged on the insulating layer 31 via a conductive connecting member such as solder, and mounted on the insulating layer 31. The positive electrode 44a is composed of an electrode layer 42a made of a Mo layer / Al layer / Mo layer or the like, and a transparent electrode 43a made of indium tin oxide (ITO) or the like covering the electrode layer 42a. The negative electrode 44b has the same configuration, and is composed of an electrode layer 42b made of a Mo layer / Al layer / Mo layer or the like, and a transparent electrode 43b made of ITO or the like covering the electrode layer 42b. An insulating layer 45 is arranged so as to cover the insulating layer 31 and a part of each of the transparent electrodes 43a and 43b (the portion where the light emitting element 14 does not overlap), and the insulating layer 45 is silicon oxide (SiO 2 ). , Silicon nitride (SiN x ), etc. (see, for example, Patent Document 1).

特開2017−9725号公報JP-A-2017-9725

しかしながら、図8に示す構成の上記従来の表示装置においては、以下の問題点があった。貫通導体16kを構成する導体は、高い導電性の点でCuから成る場合が多く、CuはTFT13の半導体層13aに対して汚染物質となるという問題点があった。また、貫通導体16kには電源電流等の大電流を流すことが多く、その場合貫通導体16kに電流集中が生じて貫通導体16kが発熱し、その結果、貫通導体16kに重なる絶縁層31の部位にクラックが発生したり、貫通導体16kと正電圧入力線16との接続部に断線が発生するという問題点があった。また、絶縁基板1に貫通導体16kを設けることによって、貫通導体16kに接続される電源配線等の配線における信号の電圧降下を小さくすることができるが、多数の発光素子14が配置される発光装置においては配線の長さが長くなるために、信号の電圧降下を小さくすることが難しくなるという問題点があった。また、一般に貫通導体を形成した絶縁基板1にTFT等を形成するため、貫通導体はその位置やサイズのばらつき、精度が悪く、TFTの微細化による位置ずれなどが生じる結果として、高密度の半導体装置の実現が難しいと言う問題点があった。 However, the conventional display device having the configuration shown in FIG. 8 has the following problems. The conductor constituting the through conductor 16k is often made of Cu in terms of high conductivity, and there is a problem that Cu becomes a pollutant with respect to the semiconductor layer 13a of the TFT 13. Further, a large current such as a power supply current is often passed through the through conductor 16k, and in that case, a current concentration occurs in the through conductor 16k and the through conductor 16k generates heat, and as a result, a portion of the insulating layer 31 overlapping the through conductor 16k. There are problems that cracks occur in the conductor and that the connection between the through conductor 16k and the positive voltage input line 16 is broken. Further, by providing the through conductor 16k on the insulating substrate 1, the voltage drop of the signal in the wiring such as the power supply wiring connected to the through conductor 16k can be reduced, but the light emitting device in which a large number of light emitting elements 14 are arranged is arranged. In the above case, since the length of the wiring becomes long, there is a problem that it becomes difficult to reduce the voltage drop of the signal. Further, since a TFT or the like is generally formed on an insulating substrate 1 on which a through conductor is formed, the position and size of the through conductor vary, the accuracy is poor, and the position shift due to the miniaturization of the TFT occurs, resulting in a high-density semiconductor. There was a problem that it was difficult to realize the device.

本発明は、上記の問題点に鑑みて完成されたものであり、その目的は、貫通導体の発熱によって貫通導体に重なる絶縁層の部位にクラックが発生したり、貫通導体とそれに接続される配線との接続部に断線が発生することを効果的に抑えることができる、半導体装置及び発光装置を提供することである。また、貫通導体に接続される配線における信号の電圧降下をより小さくすることができる、半導体装置及び発光装置を提供することである。また、高密度なTFTを形成した後に精度の劣る貫通導体を作成することにより、結果として高密度の半導体装置の実現を可能とすることである。また、貫通導体を構成する導体がTFTの半導体層を汚染することを抑えることができるとともに、貫通導体の発熱による上記問題点の発生を抑えることができる結果、信頼性が高く長寿命の半導体装置を製造できる半導体装置の製造方法を提供することである。 The present invention has been completed in view of the above problems, and an object of the present invention is to generate a crack in a portion of an insulating layer overlapping the through conductor due to heat generation of the through conductor, or to generate a through conductor and wiring connected to the through conductor. It is an object of the present invention to provide a semiconductor device and a light emitting device capable of effectively suppressing the occurrence of disconnection in the connection portion with the device. It is also an object of the present invention to provide a semiconductor device and a light emitting device capable of reducing the voltage drop of a signal in the wiring connected to the through conductor. Further, by forming a through conductor having inferior accuracy after forming a high-density TFT, it is possible to realize a high-density semiconductor device as a result. Further, it is possible to prevent the conductor constituting the through conductor from contaminating the semiconductor layer of the TFT, and it is possible to suppress the occurrence of the above-mentioned problems due to the heat generation of the through conductor. As a result, the semiconductor device has high reliability and long life. It is to provide the manufacturing method of the semiconductor device which can manufacture.

本発明の半導体装置は、絶縁基板と、前記絶縁基板を貫通する貫通導体と、前記絶縁基板上に配置された複数の絶縁層と、前記複数の絶縁層の層間に配置されるとともに前記貫通導体に電気的に接続されている薄膜トランジスタと、を有している半導体装置であって、前記複数の絶縁層における前記貫通導体と重なる部位に、貫通孔が配置されており、前記貫通孔の開口の径が前記貫通導体の径よりも大きく、かつ前記貫通孔の開口の内側に前記貫通導体が位置している構成である。 The semiconductor device of the present invention is arranged between an insulating substrate, a penetrating conductor penetrating the insulating substrate, a plurality of insulating layers arranged on the insulating substrate, and the penetrating conductors arranged between the plurality of insulating layers. A semiconductor device having a thin film electrically connected to the above, wherein a through hole is arranged at a portion of the plurality of insulating layers overlapping the through conductor, and the opening of the through hole is formed. The diameter is larger than the diameter of the through conductor, and the through conductor is located inside the opening of the through hole.

本発明の半導体装置は、好ましくは、前記貫通導体は、複数個が前記絶縁基板に均等に配置されている。 In the semiconductor device of the present invention, preferably, a plurality of the through conductors are evenly arranged on the insulating substrate.

また本発明の半導体装置は、好ましくは、前記貫通導体は前記絶縁基板に複数配置されているとともに、それらは前記絶縁基板の端との距離が互いに異なるものを含んでおり、前記絶縁基板の端に最も近い前記貫通導体の平面視での面積が他の前記貫通導体の平面視での面積よりも大きい。 Further, in the semiconductor device of the present invention, preferably, a plurality of the through conductors are arranged on the insulating substrate, and they include those having different distances from the ends of the insulating substrate, and the ends of the insulating substrate. The area of the penetrating conductor closest to is larger than the area of the other penetrating conductor in plan view.

また本発明の半導体装置は、好ましくは、前記絶縁基板の端に最も近い前記貫通導体を流れる電流が、他の前記貫通導体を流れる電流よりも大きい。 Further, in the semiconductor device of the present invention, the current flowing through the through conductor closest to the edge of the insulating substrate is preferably larger than the current flowing through the other through conductors.

また本発明の半導体装置は、好ましくは、前記絶縁基板は、側面に配置された側面導体を有しており、前記貫通導体は、前記側面導体に電気的に接続されている。 Further, in the semiconductor device of the present invention, preferably, the insulating substrate has a side conductor arranged on a side surface, and the through conductor is electrically connected to the side conductor.

また本発明の半導体装置は、好ましくは、前記絶縁基板は、側面に前記側面導体と電気的に独立している側面配線が配置されている。 Further, in the semiconductor device of the present invention, preferably, the insulating substrate is provided with side wiring that is electrically independent of the side conductor on the side surface.

本発明の発光装置は、上記本発明の構成の半導体装置を有する発光装置であって、前記複数の絶縁層の上に前記薄膜トランジスタと電気的に接続される電極が配置されており、前記電極に接続された発光素子を有している構成である。 The light emitting device of the present invention is a light emitting device having the semiconductor device having the configuration of the present invention, in which electrodes electrically connected to the thin film transistor are arranged on the plurality of insulating layers, and the electrodes are provided. It is configured to have a connected light emitting element.

本発明の半導体装置の製造方法は、前記絶縁基板上に前記複数の絶縁層を積層するとともにそれらの層間に前記薄膜トランジスタを形成し、次に、前記複数の絶縁層を貫通する前記貫通孔を形成し、次に、前記貫通孔の開口の内側に露出した前記絶縁基板の部位に、前記絶縁基板を貫通する孔を形成し、前記孔に導体柱を配置することによって前記貫通導体を形成する構成である。 In the method for manufacturing a semiconductor device of the present invention, the plurality of insulating layers are laminated on the insulating substrate, the thin film is formed between the layers, and then the through holes penetrating the plurality of insulating layers are formed. Next, a hole penetrating the insulating substrate is formed in a portion of the insulating substrate exposed inside the opening of the through hole, and a conductor column is arranged in the hole to form the penetrating conductor. Is.

本発明の半導体装置の製造方法は、好ましくは、前記貫通孔をエッチング法によって形成し、前記絶縁基板を貫通する孔をレーザ光照射法によって形成する。 In the method for manufacturing a semiconductor device of the present invention, preferably, the through hole is formed by an etching method, and the hole penetrating the insulating substrate is formed by a laser light irradiation method.

また本発明の半導体装置の製造方法は、好ましくは、前記導体柱は銅柱である。 Further, in the method for manufacturing a semiconductor device of the present invention, the conductor column is preferably a copper column.

また本発明の半導体装置の製造方法は、好ましくは、前記貫通孔は、前記貫通導体の側の径よりも反対側の径が大きい。 Further, in the method for manufacturing a semiconductor device of the present invention, preferably, the through hole has a diameter on the opposite side of the diameter on the side of the through conductor.

本発明の半導体装置は、絶縁基板と、前記絶縁基板を貫通する貫通導体と、前記絶縁基板上に配置された複数の絶縁層と、前記複数の絶縁層の層間に配置されるとともに前記貫通導体に電気的に接続されている薄膜トランジスタと、を有している半導体装置であって、前記複数の絶縁層における前記貫通導体と重なる部位に、貫通孔が配置されており、前記貫通孔の開口の径が前記貫通導体の径よりも大きく、かつ前記貫通孔の開口の内側に前記貫通導体が位置している構成であることから、以下の効果を奏する。複数の絶縁層における貫通導体と重なる部位に貫通孔が配置されていることから、貫通導体の放熱性が向上し、
貫通導体に電源電流等の大きな電流を流したとしても、貫通導体の発熱によって貫通導体に重なる絶縁層の部位にクラックが発生したり、貫通導体とそれに接続される配線との接続部に断線が発生することを効果的に抑えることができる。
The semiconductor device of the present invention is arranged between an insulating substrate, a penetrating conductor penetrating the insulating substrate, a plurality of insulating layers arranged on the insulating substrate, and the penetrating conductors arranged between the plurality of insulating layers. A semiconductor device having a thin film electrically connected to the above, wherein a through hole is arranged at a portion of the plurality of insulating layers overlapping the through conductor, and the opening of the through hole is formed. Since the diameter is larger than the diameter of the through conductor and the through conductor is located inside the opening of the through hole, the following effects are obtained. Since the through holes are arranged in the portions of the plurality of insulating layers that overlap with the through conductors, the heat dissipation of the through conductors is improved.
Even if a large current such as a power supply current is passed through the through conductor, the heat generated by the through conductor may cause cracks in the part of the insulating layer that overlaps the through conductor, or the connection between the through conductor and the wiring connected to it may be broken. It can be effectively suppressed from occurring.

本発明の半導体装置は、前記貫通導体は、複数個が前記絶縁基板に均等に配置されている場合、絶縁基板において複数個の貫通導体の発熱による熱集中を抑えることができる。その結果、絶縁層の部位にクラックが発生したり、貫通導体とそれに接続される配線との接続部に断線が発生することをより効果的に抑えることができる。また、複数個の貫通導体を均等に配置することにより絶縁基板の面内での電圧降下を最小で均一なものとすることが可能となり、電圧降下に伴う発光輝度の不均一などが無い発光装置等の実現が可能となる。 In the semiconductor device of the present invention, when a plurality of the through conductors are evenly arranged on the insulating substrate, heat concentration due to heat generation of the plurality of through conductors on the insulating substrate can be suppressed. As a result, it is possible to more effectively suppress the occurrence of cracks in the portion of the insulating layer and the occurrence of disconnection in the connection portion between the through conductor and the wiring connected to the through conductor. Further, by arranging a plurality of through conductors evenly, it is possible to make the voltage drop in the plane of the insulating substrate minimum and uniform, and the light emitting device does not have uneven emission brightness due to the voltage drop. Etc. can be realized.

また本発明の半導体装置は、前記貫通導体は前記絶縁基板に複数配置されているとともに、それらは前記絶縁基板の端との距離が互いに異なるものを含んでおり、前記絶縁基板の端に最も近い前記貫通導体の平面視での面積が他の前記貫通導体の平面視での面積よりも大きい場合、絶縁基板の端に最も近い貫通導体の抵抗を、他の貫通導体の抵抗よりも小さくすることができる。従って、それらの貫通導体に電源電流等の大きな電流を流したとしても、貫通導体に接続される配線における電圧降下のばらつきを小さくすることができる。また、それらの貫通導体の放熱性のばらつきも小さくすることができる。貫通導体の発熱による上記諸問題点の発生をより効果的に抑えることができる。 Further, in the semiconductor device of the present invention, a plurality of the through conductors are arranged on the insulating substrate, and they include those having different distances from the end of the insulating substrate, and are closest to the end of the insulating substrate. When the area of the through conductor in the plan view is larger than the area of the other through conductor in the plan view, the resistance of the through conductor closest to the edge of the insulating substrate should be smaller than the resistance of the other through conductor. Can be done. Therefore, even if a large current such as a power supply current is passed through the through conductors, the variation in the voltage drop in the wiring connected to the through conductors can be reduced. In addition, the variation in heat dissipation of those through conductors can be reduced. It is possible to more effectively suppress the occurrence of the above-mentioned problems due to the heat generated by the through conductor.

また本発明の半導体装置は、前記絶縁基板の端に最も近い前記貫通導体を流れる電流が、他の前記貫通導体を流れる電流よりも大きい場合、絶縁基板の端に最も近い貫通導体の抵抗を、他の貫通導体の抵抗よりも小さくしているので、絶縁基板の端に最も近い貫通導体に電源電流等の大電流を流すことができる。 Further, in the semiconductor device of the present invention, when the current flowing through the through conductor closest to the edge of the insulating substrate is larger than the current flowing through the other through conductor, the resistance of the through conductor closest to the edge of the insulating substrate is increased. Since the resistance is smaller than that of the other through-conductors, a large current such as a power supply current can be passed through the through-conductor closest to the edge of the insulating substrate.

また本発明の半導体装置において、前記絶縁基板は、側面に配置された側面導体を有しており、前記貫通導体は、前記側面導体に電気的に接続されている場合、貫通導体及び側面導体のそれぞれに電流が分配されるので、貫通導体を流れる電流が小さくなる。その結果、貫通導体の発熱による上記諸問題点の発生をより効果的に抑えることができる。また、複数の貫通導体がある場合、貫通導体に接続された配線における信号の電圧降下のばらつきを小さくすることができる。また、それらの貫通導体の放熱性のばらつきも小さくすることができる。また、一般に側面導体は貫通導体より低抵抗化が難しく、大電流を流した場合はマイグレーションなど信頼性の低下も懸念されていたが、貫通導体で冗長接続する事により、側面導体の高信頼性化が可能になる。 Further, in the semiconductor device of the present invention, the insulating substrate has side conductors arranged on the side surface, and when the through conductor is electrically connected to the side conductor, the through conductor and the side conductor Since the current is distributed to each, the current flowing through the through conductor becomes small. As a result, it is possible to more effectively suppress the occurrence of the above-mentioned problems due to the heat generation of the through conductor. Further, when there are a plurality of through conductors, it is possible to reduce the variation in the voltage drop of the signal in the wiring connected to the through conductors. In addition, the variation in heat dissipation of those through conductors can be reduced. In addition, it is generally difficult to reduce the resistance of side conductors compared to through conductors, and there was concern about deterioration of reliability such as migration when a large current was applied. However, by making redundant connections with through conductors, the reliability of side conductors is high. It becomes possible to change.

また本発明の半導体装置は、前記絶縁基板は、側面に前記側面導体と電気的に独立している側面配線が配置されている場合、薄膜トランジスタのゲート電極に入力する走査信号等を側面配線を介して供給することができるので、貫通導体の数が増加することを抑えることができる。また、大電流の接続を側面配線だけでは無く貫通導体でも実施することで、大電流用に大面積の側面導体の形成が不要となり、側面配線領域の縮小や形成する辺をより少なくすることができるなど狭額縁化に大いに寄与する。また、貫通導体の発熱による上記諸問題点の発生をより効果的に抑えることができる。 Further, in the semiconductor device of the present invention, when the insulating substrate has side wiring electrically independent of the side conductor on the side surface, a scanning signal or the like input to the gate electrode of the thin film transistor is transmitted via the side wiring. Therefore, it is possible to suppress an increase in the number of through conductors. In addition, by connecting a large current not only with the side wiring but also with a through conductor, it is not necessary to form a large area side conductor for a large current, and the side wiring area can be reduced or the number of sides to be formed can be reduced. It greatly contributes to narrowing the frame, such as being able to do it. Further, it is possible to more effectively suppress the occurrence of the above-mentioned problems due to the heat generation of the through conductor.

本発明の発光装置は、上記本発明の構成の半導体装置を有する発光装置であって、前記複数の絶縁層の上に前記薄膜トランジスタと電気的に接続される電極が配置されており、前記電極に接続された発光素子を有している構成であることから、貫通導体の発熱による上記諸問題点の発生を効果的に抑えることができる結果、信頼性が高く長寿命の発光装置となる。 The light emitting device of the present invention is a light emitting device having the semiconductor device having the configuration of the present invention, in which electrodes electrically connected to the thin film transistor are arranged on the plurality of insulating layers, and the electrodes are provided. Since the structure has the connected light emitting elements, the occurrence of the above-mentioned problems due to the heat generation of the through conductor can be effectively suppressed, and as a result, the light emitting device has high reliability and long life.

本発明の半導体装置の製造方法は、前記絶縁基板上に前記複数の絶縁層を積層するとともにそれらの層間に前記薄膜トランジスタを形成し、次に、前記複数の絶縁層を貫通する前記貫通孔を形成し、次に、前記貫通孔の開口の内側に露出した前記絶縁基板の部位に、前記絶縁基板を貫通する孔を形成し、前記孔に導体柱を配置することによって前記貫通導体を形成する構成であることから、以下の効果を奏する。薄膜トランジスタを形成した後に、貫通導体を形成することができるので、貫通導体を構成する導体がTFTの半導体層を汚染することを抑えることができる。また、貫通導体の発熱による上記諸問題点の発生を抑えることができる結果、信頼性が高く長寿命の半導体装置を製造できる。また、高密度、高精度にTFTを絶縁基板に形成した後に、位置精度、サイズの精度の劣る貫通導体を絶縁基板に形成することにより、TFTと貫通導体との配線を介しての接続が容易になる結果として、高密度の半導体装置の実現が可能となる。 In the method for manufacturing a semiconductor device of the present invention, the plurality of insulating layers are laminated on the insulating substrate, the thin film is formed between the layers, and then the through holes penetrating the plurality of insulating layers are formed. Next, a hole penetrating the insulating substrate is formed in a portion of the insulating substrate exposed inside the opening of the through hole, and a conductor column is arranged in the hole to form the penetrating conductor. Therefore, the following effects are obtained. Since the through conductor can be formed after the thin film transistor is formed, it is possible to prevent the conductor constituting the through conductor from contaminating the semiconductor layer of the TFT. Further, as a result of suppressing the occurrence of the above-mentioned problems due to the heat generation of the through conductor, a highly reliable and long-life semiconductor device can be manufactured. Further, by forming the TFT on the insulating substrate with high density and high accuracy and then forming the through conductor having inferior position accuracy and size accuracy on the insulating substrate, it is easy to connect the TFT and the through conductor via the wiring. As a result, it becomes possible to realize a high-density semiconductor device.

本発明の半導体装置の製造方法は、前記貫通孔をエッチング法によって形成し、前記絶縁基板を貫通する孔をレーザ光照射法によって形成する場合、絶縁基板を貫通する孔の位置及び大きさを正確なものとして形成できる。その結果、放熱性に優れた貫通導体を形成することが容易になる。 In the method for manufacturing a semiconductor device of the present invention, when the through hole is formed by an etching method and the hole penetrating the insulating substrate is formed by a laser beam irradiation method, the position and size of the hole penetrating the insulating substrate are accurately determined. Can be formed as an object. As a result, it becomes easy to form a through conductor having excellent heat dissipation.

また本発明の半導体装置の製造方法は、前記導体柱は銅柱である場合、高い導電性を有する貫通導体を形成できる。従って、貫通導体の発熱による上記諸問題点の発生をより抑えることができるとともに、貫通導体を構成する銅がTFTの半導体層を汚染することを抑えることができ、長寿命の半導体装置を製造できる。 Further, in the method for manufacturing a semiconductor device of the present invention, when the conductor column is a copper column, a through conductor having high conductivity can be formed. Therefore, it is possible to further suppress the occurrence of the above-mentioned problems due to the heat generation of the through conductor, and it is possible to suppress the copper constituting the through conductor from contaminating the semiconductor layer of the TFT, and it is possible to manufacture a semiconductor device having a long life. ..

また本発明の半導体装置の製造方法は、前記貫通孔は、前記貫通導体の側の径よりも反対側の径が大きい場合、貫通導体の放熱性が向上する。その結果、貫通導体の発熱による上記諸問題点の発生をより抑えることができる。 Further, in the method for manufacturing a semiconductor device of the present invention, when the through hole has a diameter on the opposite side of the diameter on the side of the through conductor, the heat dissipation of the through conductor is improved. As a result, it is possible to further suppress the occurrence of the above-mentioned problems due to the heat generation of the through conductor.

図1は、本発明の半導体装置を有する発光装置について実施の形態の1例を示す図であり、図3(a)のC1−C2線における断面図であって、薄膜トランジスタ及び発光素子の部位を透視した断面図である。FIG. 1 is a diagram showing an example of an embodiment of a light emitting device having the semiconductor device of the present invention, which is a cross-sectional view taken along the line C1-C2 of FIG. 3A, showing a portion of a thin film transistor and a light emitting device. It is a perspective sectional view. 図2(a),(b)は、それぞれ本発明の発光装置について実施の形態の他例を示す図であり、図1と同様の部位を示す断面図である。2 (a) and 2 (b) are views showing another example of the embodiment of the light emitting device of the present invention, respectively, and are cross-sectional views showing the same parts as in FIG. 図3(a),(b)は、それぞれ本発明の発光装置について実施の形態の他例を示す図であり、発光装置のブロック回路図である。3A and 3B are diagrams showing other examples of the embodiment of the light emitting device of the present invention, respectively, and are block circuit diagrams of the light emitting device. 図4(a),(b)は、それぞれ本発明の発光装置について実施の形態の他例を示す図であり、発光装置のブロック回路図である。4 (a) and 4 (b) are diagrams showing other examples of the embodiment of the light emitting device of the present invention, respectively, and are block circuit diagrams of the light emitting device. 図5(a),(b)は、それぞれ従来の発光装置の一例を示す図であり、(a)は発光装置のブロック回路図、(b)は(a)の発光装置の下面図である。5 (a) and 5 (b) are diagrams showing an example of a conventional light emitting device, respectively, (a) is a block circuit diagram of the light emitting device, and (b) is a bottom view of the light emitting device of (a). .. 図6(a)は図5(a)のA1−A2線における断面図、(b)は図5(a)における一つの発光素子及びそれに接続される発光制御部の回路図である。6 (a) is a cross-sectional view taken along the line A1-A2 of FIG. 5 (a), and FIG. 6 (b) is a circuit diagram of one light emitting element in FIG. 5 (a) and a light emitting control unit connected thereto. 図7(a),(b)は、それぞれ従来の発光装置の一例を示す図であり、発光装置のブロック回路図である。7 (a) and 7 (b) are diagrams showing an example of a conventional light emitting device, respectively, and are block circuit diagrams of the light emitting device. 図8は、図7(b)のB1−B2線における断面図であって、薄膜トランジスタ及び発光素子の部位を透視した断面図である。FIG. 8 is a cross-sectional view taken along the line B1-B2 of FIG. 7B, which is a cross-sectional view of the thin film transistor and the light emitting element.

以下、本発明の半導体装置、発光装置及び半導体装置の製造方法の実施の形態について、図面を参照しながら説明する。但し、以下で参照する各図は、本発明の半導体装置及び発光装置の実施の形態における構成部材のうち、半導体装置及び発光装置を説明するための主要部を示している。従って、本発明に係る半導体装置及び発光装置は、図に示されていない配線導体、制御IC,LSI等の周知の構成部材を備えていてもよい。なお、本発明の半導体装置、発光装置及び半導体装置の製造方法の実施の形態を示す図1〜図4において、図5〜図8と同じ部位には同じ符号を付しており、それらの詳細な説明は省く。 Hereinafter, embodiments of the semiconductor device, the light emitting device, and the method for manufacturing the semiconductor device of the present invention will be described with reference to the drawings. However, each figure referred to below shows a main part for explaining the semiconductor device and the light emitting device among the constituent members in the embodiment of the semiconductor device and the light emitting device of the present invention. Therefore, the semiconductor device and the light emitting device according to the present invention may include well-known components such as wiring conductors, control ICs, and LSIs (not shown in the figure). In FIGS. 1 to 4 showing embodiments of the semiconductor device, the light emitting device, and the method for manufacturing the semiconductor device of the present invention, the same parts as those in FIGS. 5 to 8 are designated by the same reference numerals, and details thereof are given. I will omit the explanation.

本発明の半導体装置は、TFTに接続されて動作が制御される種々の電子素子が搭載されることによって、種々の電子装置を構成し得る。電子素子としては、LED等の発光素子、有機EL素子、無機EL素子、微小電気機械システム(Micro Electro Mechanical Systems)素子等がある。図1〜図4は、本発明の半導体装置を用いた発光装置について実施の形態の各種例を示す図であり、以下、発光装置用の半導体装置及び発光装置について説明する。 The semiconductor device of the present invention can constitute various electronic devices by mounting various electronic elements connected to the TFT and whose operation is controlled. Examples of the electronic element include a light emitting element such as an LED, an organic EL element, an inorganic EL element, and a Micro Electro Mechanical Systems element. 1 to 4 are diagrams showing various examples of embodiments of a light emitting device using the semiconductor device of the present invention, and the semiconductor device and the light emitting device for the light emitting device will be described below.

図1に示すように、本発明の半導体装置は、ガラス基板等から成る絶縁基板1と、絶縁基板1を貫通する貫通導体16k1と、絶縁基板1上に配置された複数の絶縁層31と、複数の絶縁層31の層間に配置されるとともに貫通導体16k1に電気的に接続されているTFT13と、を有している半導体装置であって、複数の絶縁層31における貫通導体16k1と重なる部位に、貫通孔60が配置されており、貫通孔60の開口の径が貫通導体16k1の径よりも大きく、かつ貫通孔60の開口の内側に貫通導体16k1が位置している構成である。この構成により、貫通導体16k1の放熱性が向上し、貫通導体16k1に電源電流(数μA〜数10μA程度)等の大きな電流を流したとしても、貫通導体16k1の発熱によって貫通導体16k1に重なる絶縁層31の部位にクラックが発生したり、貫通導体16k1とそれに接続される正電圧入力線16との接続部に断線が発生することを効果的に抑えることができる。 As shown in FIG. 1, the semiconductor device of the present invention includes an insulating substrate 1 made of a glass substrate or the like, a through conductor 16k1 penetrating the insulating substrate 1, and a plurality of insulating layers 31 arranged on the insulating substrate 1. A semiconductor device having a TFT 13 arranged between layers of a plurality of insulating layers 31 and electrically connected to a penetrating conductor 16k1 at a portion overlapping the penetrating conductor 16k1 in the plurality of insulating layers 31. , The through hole 60 is arranged, the diameter of the opening of the through hole 60 is larger than the diameter of the through conductor 16k1, and the through conductor 16k1 is located inside the opening of the through hole 60. With this configuration, the heat dissipation of the through conductor 16k1 is improved, and even if a large current such as a power supply current (about several μA to several tens of μA) is passed through the through conductor 16k1, the insulation that overlaps with the through conductor 16k1 due to the heat generated by the through conductor 16k1. It is possible to effectively suppress the occurrence of cracks in the portion of the layer 31 and the occurrence of disconnection in the connection portion between the through conductor 16k1 and the positive voltage input line 16 connected to the through conductor 16k1.

本発明の半導体装置において、絶縁基板1は、ガラス基板、プラスチック基板、セラミック基板等の電気的に絶縁性の基板であるが、絶縁性の基板に金属基板等の放熱性が高い基板が付加されていてもよい。また、絶縁基板1は透明なガラス基板であってもよいが、不透明なものであってもよい。絶縁基板1が不透明なものである場合、絶縁基板1は着色されたガラス基板、摺りガラスから成るガラス基板、プラスチック基板、セラミック基板、あるいはそれらの基板を積層した複合基板であってもよい。 In the semiconductor device of the present invention, the insulating substrate 1 is an electrically insulating substrate such as a glass substrate, a plastic substrate, or a ceramic substrate, but a substrate having high heat dissipation such as a metal substrate is added to the insulating substrate. You may be. Further, the insulating substrate 1 may be a transparent glass substrate, but may be an opaque one. When the insulating substrate 1 is opaque, the insulating substrate 1 may be a colored glass substrate, a glass substrate made of frosted glass, a plastic substrate, a ceramic substrate, or a composite substrate in which these substrates are laminated.

貫通導体16k1の径、貫通孔60の径は、円柱状の貫通導体16k1、円筒状の貫通孔60である場合、横断面における直径を意味する。貫通導体16k1が楕円柱状、貫通孔60が楕円筒状である場合、横断面における長径(最大径)または平均径である。貫通導体16k1がその他の四角柱状等の柱状、貫通孔60がその他の四角筒状等の筒状である場合、横断面における最大幅または平均幅である。いすれにしても、平面視において、貫通孔60の開口の内側に貫通導体16k1が位置している構成である。 The diameter of the through conductor 16k1 and the diameter of the through hole 60 mean the diameter in the cross section in the case of the cylindrical through conductor 16k1 and the cylindrical through hole 60. When the through conductor 16k1 has an elliptical columnar shape and the through hole 60 has an elliptical cylinder shape, it is the major axis (maximum diameter) or the average diameter in the cross section. When the through conductor 16k1 is a columnar shape such as another square columnar shape and the through hole 60 is a tubular shape such as another square tubular shape, it is the maximum width or the average width in the cross section. In any case, the through conductor 16k1 is located inside the opening of the through hole 60 in a plan view.

貫通孔60の径は貫通導体16k1の径よりも10μm〜50μm程度外側に位置し、例えば、貫通導体16k1の径は、円柱状の貫通導体16k1であれば10μm〜500μm程度の長さの直径である。貫通孔60の径は、円筒状の貫通孔60であれば30μm〜600μm程度の長さの直径である。 The diameter of the through hole 60 is located about 10 μm to 50 μm outside the diameter of the through conductor 16k1, and for example, the diameter of the through conductor 16k1 is about 10 μm to 500 μm for the cylindrical through conductor 16k1. is there. The diameter of the through hole 60 is a diameter of about 30 μm to 600 μm in the case of the cylindrical through hole 60.

貫通孔60は、貫通導体16k1の側の径(図1では下端側の径)よりも反対側の径(図1では上端側の径)が大きいことが好ましい。この場合、貫通孔60が上側に向かって大きく開いた構成となるために、貫通導体16k1で発生した熱が空間に放散されやすくなり、貫通導体16k1の放熱性が向上する。その結果、貫通導体16k1の発熱による上述の諸問題点の発生をより抑えることができる。図2(a)は、貫通導体16k1の側の径よりも反対側の径を大きくする場合に、段階的に大きくした構成を示すものである。この場合、貫通導体16k1で発生した熱が空間により放散されやすくなり、貫通導体16k1の放熱性がより向上する。貫通孔60の上端側の径と下端側の径の比は、例えば1.1倍〜2倍程度であればよい。また、貫通導体16k1上方の空間を構成する窪みには黒色絶縁膜などの透明絶縁膜よりも熱伝導性、放熱性に優れた保護膜や加飾膜を設けてもよい。 The through hole 60 preferably has a diameter on the opposite side (diameter on the upper end side in FIG. 1) larger than the diameter on the side of the through conductor 16k1 (diameter on the lower end side in FIG. 1). In this case, since the through hole 60 is configured to be wide open toward the upper side, the heat generated by the through conductor 16k1 is easily dissipated into the space, and the heat dissipation of the through conductor 16k1 is improved. As a result, it is possible to further suppress the occurrence of the above-mentioned problems due to the heat generated by the through conductor 16k1. FIG. 2A shows a configuration in which the diameter on the opposite side of the through conductor 16k1 is increased in stages when the diameter on the opposite side is increased. In this case, the heat generated by the through conductor 16k1 is easily dissipated by the space, and the heat dissipation of the through conductor 16k1 is further improved. The ratio of the diameter on the upper end side to the diameter on the lower end side of the through hole 60 may be, for example, about 1.1 times to 2 times. Further, a protective film or a decorative film having better thermal conductivity and heat dissipation than a transparent insulating film such as a black insulating film may be provided in the recess forming the space above the through conductor 16k1.

図2(b)は、貫通導体16k1について、絶縁基板1の第1主面(発光素子搭載主面)側の径が、絶縁基板1の第2主面(発光素子搭載主面と反対側の主面)側の径よりも小さい、好適な構成を示すものである。即ち、貫通導体16k1の第2主面側(下端側)の径が第1主面側(上端側)の径より大きい構成である。この場合、貫通導体16k1で発生した熱が絶縁基板1の第2主面の側に放散されやすくなり、絶縁層31への熱の影響を小さくすることができる。従って、貫通導体16k1の発熱による上述の諸問題点の発生をより抑えることができる。 FIG. 2B shows that the diameter of the through conductor 16k1 on the first main surface (light emitting element mounting main surface) side of the insulating substrate 1 is opposite to the second main surface (light emitting element mounting main surface) of the insulating substrate 1. It shows a suitable configuration that is smaller than the diameter on the main surface) side. That is, the diameter of the through conductor 16k1 on the second main surface side (lower end side) is larger than the diameter on the first main surface side (upper end side). In this case, the heat generated by the through conductor 16k1 is likely to be dissipated to the side of the second main surface of the insulating substrate 1, and the influence of the heat on the insulating layer 31 can be reduced. Therefore, it is possible to further suppress the occurrence of the above-mentioned problems due to the heat generated by the through conductor 16k1.

図3(a)は、複数の貫通導体16k1〜16kn,17k1〜17knが表示部11に配置されている構成を示すものである。この場合、複数の貫通導体16k1〜16kn,17k1〜17knのそれぞれが、それが接続される配線である、正電圧入力線16、負電圧入力線17の中央部に接続されていることが良い。この構成の場合、正電圧入力線16、負電圧入力線17における電圧降下がより小さくなる。正電圧入力線16、負電圧入力線17の中央部は、例えば、それらの線の中心から−15%〜+15%の長さの範囲、即ち線の中心を含む30%程度の長さの範囲である。 FIG. 3A shows a configuration in which a plurality of through conductors 16k1 to 16kn and 17k1 to 17kn are arranged on the display unit 11. In this case, it is preferable that each of the plurality of through conductors 16k1 to 16kn and 17k1 to 17kn is connected to the central portion of the positive voltage input line 16 and the negative voltage input line 17, which are the wirings to which they are connected. In the case of this configuration, the voltage drop in the positive voltage input line 16 and the negative voltage input line 17 becomes smaller. The central portion of the positive voltage input line 16 and the negative voltage input line 17 is, for example, in the range of -15% to + 15% from the center of the line, that is, the range of about 30% including the center of the line. Is.

図3(b)は、複数の貫通導体16k1〜16kn,17k1〜17knが表示部11に配置されており、それらの隣接間の間隔がほぼ同じである、好適な構成を示すものである。この場合、絶縁基板1において、複数の貫通導体16k1〜16kn,17k1〜17knで発生した熱が局所的に集中することを抑えることができる。複数の貫通導体16k1〜16kn,17k1〜17knの隣接間の間隔は、全く同じである必要はなく、間隔の比を1倍〜1.5倍程度の範囲内として調整し得る。その範囲を外れると、絶縁基板1に局所的な熱集中が発生しやすくなる傾向がある。 FIG. 3B shows a suitable configuration in which a plurality of through conductors 16k1 to 16kn and 17k1 to 17kn are arranged on the display unit 11 and the intervals between the adjacent conductors are substantially the same. In this case, it is possible to prevent the heat generated by the plurality of through conductors 16k1 to 16kn and 17k1 to 17kn from being locally concentrated in the insulating substrate 1. The spacing between the adjacent conductors 16k1 to 16kn and 17k1 to 17kn need not be exactly the same, and the ratio of the spacing can be adjusted within the range of about 1 to 1.5 times. If it is out of the range, local heat concentration tends to easily occur on the insulating substrate 1.

本発明の半導体装置は、貫通導体は、複数個が絶縁基板1に均等に配置されていることが好ましい。この場合、絶縁基板1内での抵抗分布や電圧降下が均一となり、また絶縁基板1において複数個の貫通導体の発熱による熱集中を抑えることができる。その結果、絶縁層31の部位にクラックが発生したり、貫通導体とそれに接続される配線との接続部に断線が発生することをより効果的に抑えることができる。複数個の貫通導体が絶縁基板1に均等に配置されている構成は、複数個の貫通導体が発熱したときに絶縁基板1の熱分布が均等になるような構成である。例えば、矩形状の絶縁基板1の主面を行列状に均等の面積でもって区分するに際して、貫通導体の数と区分された部位の数が同じになるようにする。そして、それぞれの区分された部位の中心部に貫通導体を配置する構成である。図3においては、各入力線毎に貫通導体を設けているが、複数本毎に束ね、束ねた毎に貫通導体を設けても良い。それらの貫通導体間は上下千鳥配置なども含め均等に配置されている構成であることが良い。 In the semiconductor device of the present invention, it is preferable that a plurality of through conductors are evenly arranged on the insulating substrate 1. In this case, the resistance distribution and the voltage drop in the insulating substrate 1 become uniform, and the heat concentration due to the heat generation of the plurality of through conductors in the insulating substrate 1 can be suppressed. As a result, it is possible to more effectively suppress the occurrence of cracks in the portion of the insulating layer 31 and the occurrence of disconnection in the connection portion between the through conductor and the wiring connected to the through conductor. The configuration in which the plurality of through conductors are evenly arranged on the insulating substrate 1 is such that the heat distribution of the insulating substrate 1 becomes even when the plurality of through conductors generate heat. For example, when the main surface of the rectangular insulating substrate 1 is divided in a matrix with an even area, the number of through conductors and the number of divided parts are set to be the same. Then, a through conductor is arranged at the center of each of the divided portions. In FIG. 3, a through conductor is provided for each input line, but a plurality of through conductors may be bundled and a through conductor may be provided for each bundled line. It is preferable that the through conductors are evenly arranged including the vertical staggered arrangement.

図4(a)は、貫通導体は絶縁基板1に複数配置されているとともに、それらの貫通導体16k1〜16kn,17k1〜17knは、絶縁基板1の端1tとの距離が互いに異なるものを含んでおり、絶縁基板1の端1tに最も近い貫通導体16k1〜16knの平面視での各面積が、他の貫通導体17k1〜17knの平面視での各面積よりも大きい、好適な構成を示すものである。この場合、絶縁基板1の端1tに最も近い貫通導体16k1〜16knの抵抗を、他の貫通導体17k1〜17knの抵抗よりも小さくすることができる。従って、それらの貫通導体16k1〜16kn,17k1〜17knに電源電流等の大きな電流を流したとしても、貫通導体16k1〜16kn,17k1〜17knに接続される正電圧入力線16、負電圧入力線17における電圧降下のばらつきを小さくすることができる。即ち、貫通導体16k1〜16knは正電圧入力線16の端部において接続されているが、貫通導体16k1〜16knの抵抗が小さいために、正電圧入力線16における信号の電圧降下を小さくすることができる。従って、負電圧入力線17における信号の電圧降下と、正電圧入力線16における信号の電圧降下と、を同程度とすることができる。また、それらの貫通導体16k1〜16kn,17k1〜17knの放熱性のばらつきも小さくすることができる。従って、貫通導体16k1〜16kn,17k1〜17knの発熱による上記諸問題点の発生をより効果的に抑えることができる。 In FIG. 4A, a plurality of through conductors are arranged on the insulating substrate 1, and the through conductors 16k1 to 16kn and 17k1 to 17kn include those having different distances from the end 1t of the insulating substrate 1. The area of the penetrating conductors 16k1 to 16kn closest to the end 1t of the insulating substrate 1 in plan view is larger than the area of each of the other penetrating conductors 17k1 to 17kn in plan view, indicating a suitable configuration. is there. In this case, the resistance of the through conductors 16k1 to 16kn closest to the end 1t of the insulating substrate 1 can be made smaller than the resistance of the other through conductors 17k1 to 17kn. Therefore, even if a large current such as a power supply current is passed through the through conductors 16k1 to 16kn and 17k1 to 17kn, the positive voltage input line 16 and the negative voltage input line 17 connected to the through conductors 16k1 to 16kn and 17k1 to 17kn are connected. It is possible to reduce the variation of the voltage drop in. That is, although the through conductors 16k1 to 16kn are connected at the end of the positive voltage input line 16, the voltage drop of the signal on the positive voltage input line 16 can be reduced because the resistance of the through conductors 16k1 to 16kn is small. it can. Therefore, the voltage drop of the signal on the negative voltage input line 17 and the voltage drop of the signal on the positive voltage input line 16 can be made about the same. Further, the variation in heat dissipation of the penetrating conductors 16k1 to 16kn and 17k1 to 17kn can be reduced. Therefore, it is possible to more effectively suppress the occurrence of the above-mentioned problems due to heat generation of the penetrating conductors 16k1 to 16kn and 17k1 to 17kn.

貫通導体16k1〜16knの平面視での各面積と、他の貫通導体17k1〜17knの平面視での各面積と、の比は、1.1倍〜5倍程度の範囲内で調整することができる。1.1倍未満では、上記の電圧降下のばらつきを小さくする効果、放熱性のばらつきも小さくする効果が得られにくい傾向がある。5倍を超えると、貫通導体16k1〜16knを配置するスペースが得られにくい傾向がある。好ましくは、1.5倍〜3倍程度の範囲内で調整することができる。 The ratio of each area of the penetrating conductors 16k1 to 16kn in a plan view and each area of the other penetrating conductors 17k1 to 17kn in a plan view can be adjusted within a range of about 1.1 times to 5 times. it can. If it is less than 1.1 times, it tends to be difficult to obtain the effect of reducing the variation in the voltage drop and the effect of reducing the variation in heat dissipation. If it exceeds 5 times, it tends to be difficult to obtain a space for arranging the through conductors 16k1 to 16kn. Preferably, it can be adjusted within the range of about 1.5 times to 3 times.

図4(a)の構成において、絶縁基板1の端1tに最も近い貫通導体16k1〜16knを流れる電流が、他の貫通導体17k1〜17knを流れる電流よりも大きいことが好ましい。この場合、絶縁基板1の端1tに最も近い貫通導体16k1〜16knの抵抗を、他の貫通導体17k1〜17knの抵抗よりも小さくしているので、絶縁基板1の端1tに最も近い貫通導体16k1〜16knに電源電流等の大きな電流を流すことができる。 In the configuration of FIG. 4A, it is preferable that the current flowing through the through conductors 16k1 to 16kn closest to the end 1t of the insulating substrate 1 is larger than the current flowing through the other through conductors 17k1 to 17kn. In this case, since the resistance of the penetrating conductor 16k1 to 16kn closest to the end 1t of the insulating substrate 1 is smaller than the resistance of the other penetrating conductors 17k1 to 17kn, the penetrating conductor 16k1 closest to the end 1t of the insulating substrate 1 is made smaller. A large current such as a power supply current can be passed through ~ 16 kn.

図4(b)は、絶縁基板1が、側面に配置された側面導体16s1〜16sn,17s1〜17snを有しており、貫通導体16k1〜16kn,17k1〜17knのそれぞれは、側面導体16s1〜16sn,17s1〜17snのそれぞれに電気的に接続されている、好適な構成を示すものである。この場合、貫通導体16k1と側面導体16s1についてみたとき、貫通導体16k1と側面導体16s1のそれぞれに電流が分配されるので、貫通導体16k1を流れる電流が小さくなる。その結果、貫通導体16k1の発熱による上記諸問題点の発生をより効果的に抑えることができる。また、複数の貫通導体16k1〜16kn,17k1〜17knがある場合、貫通導体16k1〜16kn,17k1〜17knに接続された、正電圧入力線16及び負電圧入力線17のそれぞれにおける信号の電圧降下のばらつきを小さくすることができる。また、それらの貫通導体16k1〜16kn,17k1〜17knの放熱性のばらつきも小さくすることができる。 In FIG. 4B, the insulating substrate 1 has side conductors 16s1 to 16sn and 17s1 to 17sn arranged on the side surface, and the through conductors 16k1 to 16kn and 17k1 to 17kn are side conductors 16s1 to 16sn, respectively. , 17s1 to 17sn, respectively, which are electrically connected to each other, and show a suitable configuration. In this case, when looking at the through conductor 16k1 and the side conductor 16s1, the current is distributed to each of the through conductor 16k1 and the side conductor 16s1, so that the current flowing through the through conductor 16k1 becomes small. As a result, it is possible to more effectively suppress the occurrence of the above-mentioned problems due to the heat generated by the through conductor 16k1. Further, when there are a plurality of through conductors 16k1 to 16kn and 17k1 to 17kn, the voltage drop of the signal at each of the positive voltage input line 16 and the negative voltage input line 17 connected to the through conductors 16k1 to 16kn and 17k1 to 17kn. The variation can be reduced. Further, the variation in heat dissipation of the penetrating conductors 16k1 to 16kn and 17k1 to 17kn can be reduced.

側面導体16s1〜16sn,17s1〜17snは、それぞれ絶縁基板1の側面の所定部位に、メッキ法、蒸着法、CVD法等の薄膜形成法等によって導体層を成膜する方法で形成される。あるいは、側面導体16s1〜16sn,17s1〜17snは、それぞれ絶縁基板1の側面の所定部位にエッチング法等によって溝を形成し、次にその溝に、メッキ法、蒸着法、CVD法等の薄膜形成法等によって導体層を成膜する方法で形成される。あるいは、側面導体16s1〜16sn,17s1〜17snは、それぞれ絶縁基板1の側面の所定部位に、銀(Ag)等の導電性粒子,樹脂成分,アルコール等を含む導体ペーストを塗布し焼成して導体層を作製する厚膜形成法等によって形成される。あるいは、側面導体16s1〜16sn,17s1〜17snは、それぞれ絶縁基板1の側面の所定部位にエッチング法等によって溝を形成し、次にその溝に導体ペーストを塗布し焼成して導体層を作製する厚膜形成法等によって形成される。 The side conductors 16s1 to 16sn and 17s1 to 17sn are formed by forming a conductor layer on a predetermined portion of the side surface of the insulating substrate 1 by a thin film forming method such as a plating method, a vapor deposition method, or a CVD method. Alternatively, the side conductors 16s1 to 16sn and 17s1 to 17sn each form grooves on the side surfaces of the insulating substrate 1 by an etching method or the like, and then thin films such as a plating method, a vapor deposition method, or a CVD method are formed in the grooves. It is formed by a method of forming a conductor layer by a method or the like. Alternatively, the side conductors 16s1 to 16sn and 17s1 to 17sn are conductors obtained by applying a conductor paste containing conductive particles such as silver (Ag), a resin component, alcohol, etc. to a predetermined portion on the side surface of the insulating substrate 1, and firing the conductors. It is formed by a thick film forming method for producing a layer or the like. Alternatively, the side conductors 16s1 to 16sn and 17s1 to 17sn each form grooves on the side surfaces of the insulating substrate 1 by an etching method or the like, and then a conductor paste is applied to the grooves and fired to prepare a conductor layer. It is formed by a thick film forming method or the like.

また側面導体16s1〜16sn,17s1〜17snは、銀(Ag),銅(Cu),アルミニウム(Al),モリブデン(Mo)等の導体材料から成る。さらに側面導体16s1〜16sn,17s1〜17snは、それぞれの幅が10μm〜1000μm程度である。 The side conductors 16s1 to 16sn and 17s1 to 17sn are made of a conductor material such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo). Further, the widths of the side conductors 16s1 to 16sn and 17s1 to 17sn are each about 10 μm to 1000 μm.

また本発明の半導体装置は、絶縁基板1は、側面に側面導体16s1〜16sn,17s1〜17snと電気的に独立している側面配線1sが配置されていることが好ましい。この場合、TFT13のゲート電極に入力する走査信号等を側面配線1sを介して供給することができるので、貫通導体16k1〜16kn,17k1〜17knの数が増加することを抑えることができる。その結果、貫通導体16k1〜16kn,17k1〜17knの発熱による上記諸問題点の発生をより効果的に抑えることができる。勿論、TFT13のドレイン電極に入力する発光制御信号を側面配線1sを介して供給することもできる。側面配線1sは、上記の側面導体16s1〜16sn,17s1〜17snと同様の形成方法によって形成し得る。 Further, in the semiconductor device of the present invention, it is preferable that the insulating substrate 1 is provided with side wiring 1s that is electrically independent of the side conductors 16s1 to 16sn and 17s1 to 17sn on the side surface. In this case, since the scanning signal or the like input to the gate electrode of the TFT 13 can be supplied via the side wiring 1s, it is possible to suppress an increase in the number of through conductors 16k1 to 16kn and 17k1 to 17kn. As a result, it is possible to more effectively suppress the occurrence of the above-mentioned problems due to heat generation of the through conductors 16k1 to 16kn and 17k1 to 17kn. Of course, the light emission control signal input to the drain electrode of the TFT 13 can also be supplied via the side wiring 1s. The side wiring 1s can be formed by the same forming method as the side conductors 16s1 to 16sn and 17s1 to 17sn described above.

本発明の発光装置は、図1、図2に示すように、上記本発明の構成の半導体装置を有する発光装置であって、複数の絶縁層31の上にTFT13と電気的に接続される、正電極44a及び負電極44bが配置されており、正電極44a及び負電極44bにアノード電極及びカソード電極が接続された発光素子14を有している構成である。この構成により、貫通導体16k1の発熱による上記諸問題点の発生を効果的に抑えることができる結果、信頼性が高く長寿命の発光装置となる。 As shown in FIGS. 1 and 2, the light emitting device of the present invention is a light emitting device having the semiconductor device having the configuration of the present invention, and is electrically connected to the TFT 13 on a plurality of insulating layers 31. A positive electrode 44a and a negative electrode 44b are arranged, and a light emitting element 14 in which an anode electrode and a cathode electrode are connected to the positive electrode 44a and the negative electrode 44b is provided. With this configuration, the occurrence of the above-mentioned problems due to the heat generated by the through conductor 16k1 can be effectively suppressed, and as a result, a highly reliable and long-life light emitting device is obtained.

本発明の発光装置において、発光素子14としては、マイクロチップ型の発光ダイオード(LED)、モノリシック型の発光ダイオード、有機EL、無機EL、半導体レーザ素子等の自発光型のものであれば採用し得る。 In the light emitting device of the present invention, as the light emitting element 14, any self-luminous element such as a microchip type light emitting diode (LED), a monolithic type light emitting diode, an organic EL, an inorganic EL, or a semiconductor laser element is adopted. obtain.

本発明の発光装置は表示装置等に適用できる。本発明の発光装置が適用された表示装置は、一つの画素部15に、異なる発光波長(発光色)の発光素子14が複数配置されており、それぞれに接続される発光制御部がある構成であってもよい。例えば、一つの画素部15に、赤色LED(RLED)等から成る赤色発光素子と緑色LED(GLED)等から成る緑色発光素子と青色LED(BLED)等から成る青色発光素子と、が配置されており、それぞれに接続される発光制御部(Rドライバ、Gドライバ、Bドライバ)がある構成であってもよい。この場合、例えば、画素部15の中心部にRLED、GLED、BLEDが集約的に正三角形の各頂点に位置するように配置されており、RドライバとGドライバとBドライバが、RLEDとGLEDとBLEDよりも絶縁基板1の内側に配置される構成とし得る。また、画素部15の中心部にRLED、GLED、BLEDが、走査信号線2または発光制御信号線3に平行な一直線上、すなわち行方向または列方向に平行な一直線上、に配列された構成とすることもできる。 The light emitting device of the present invention can be applied to a display device or the like. The display device to which the light emitting device of the present invention is applied has a configuration in which a plurality of light emitting elements 14 having different light emitting wavelengths (emission colors) are arranged in one pixel unit 15, and a light emitting control unit connected to each of them is provided. There may be. For example, a red light emitting element composed of a red LED (RLED) or the like, a green light emitting element composed of a green LED (GLED) or the like, and a blue light emitting element composed of a blue LED (BLED) or the like are arranged in one pixel unit 15. There may be a configuration in which there are light emission control units (R driver, G driver, B driver) connected to each. In this case, for example, the RLED, GLED, and BLED are arranged at the center of the pixel portion 15 so as to be collectively located at each vertex of the equilateral triangle, and the R driver, the G driver, and the B driver are the RLED and the GLED. It may be configured to be arranged inside the insulating substrate 1 with respect to the BLED. Further, the RLEDs, GLEDs, and BLEDs are arranged in the center of the pixel unit 15 on a straight line parallel to the scanning signal line 2 or the light emission control signal line 3, that is, on a straight line parallel to the row direction or the column direction. You can also do it.

また、隣接する3つの画素部15のそれぞれに、互いに異なる発光波長(発光色)の発光素子14が配置されており、それぞれに接続される発光制御部がある構成であってもよい。例えば、第1の画素部15に赤色LED(RLED)等から成る赤色発光素子が配置され、第2の画素部15に緑色LED(GLED)等から成る緑色発光素子が配置され、第3の画素部15に青色LED(BLED)等から成る青色発光素子が配置されており、それぞれに接続される発光制御部(Rドライバ、Gドライバ、Bドライバ)が各画素部15にある構成であってもよい。第1の画素部15と第2の画素部15と第3の画素部15は、行方向に並んでいてもよく、列方向に並んでいてもよい。 Further, light emitting elements 14 having different emission wavelengths (emission colors) may be arranged in each of the three adjacent pixel units 15, and a light emission control unit connected to each of them may be provided. For example, a red light emitting element composed of a red LED (RLED) or the like is arranged in the first pixel unit 15, a green light emitting element composed of a green LED (GLED) or the like is arranged in the second pixel unit 15, and a third pixel. Even if a blue light emitting element composed of a blue LED (BLED) or the like is arranged in the unit 15, and a light emitting control unit (R driver, G driver, B driver) connected to each is provided in each pixel unit 15. Good. The first pixel unit 15, the second pixel unit 15, and the third pixel unit 15 may be arranged in the row direction or in the column direction.

本発明の半導体装置の製造方法は、絶縁基板1上に複数の絶縁層31を積層するとともにそれらの層間にTFT13を形成し、次に、複数の絶縁層31を貫通する貫通孔60を形成し、次に、貫通孔60の開口の内側に露出した絶縁基板1の部位に、絶縁基板1を貫通する孔を形成し、その孔に導体柱を配置することによって貫通導体16k1を形成する構成である。この構成により以下の効果を奏する。TFT13を形成した後に、貫通導体16k1を形成することができるので、貫通導体16k1を構成する導体がTFT13の半導体層13aを汚染することを抑えることができる。また、貫通導体16k1の発熱による上記諸問題点の発生を抑えることができる結果、信頼性が高く長寿命の半導体装置を製造できる。従来、貫通導体16k1を形成した後にTFT13を形成した場合、TFT13を形成するための加熱工程等において、貫通導体16k1を構成する銅(Cu)等の導体がTFT13の半導体層13aに拡散し汚染するという問題点があったが、本発明においてはこの問題点は解消される。なお、半導体層13aは、低温焼成ポリシリコン(Low-Temperature Poly Silicon:LTPS),アモルファスシリコン等から成る。 In the method for manufacturing a semiconductor device of the present invention, a plurality of insulating layers 31 are laminated on an insulating substrate 1, TFTs 13 are formed between the layers, and then through holes 60 penetrating the plurality of insulating layers 31 are formed. Next, a hole penetrating the insulating substrate 1 is formed in the portion of the insulating substrate 1 exposed inside the opening of the through hole 60, and a conductor column is arranged in the hole to form the penetrating conductor 16k1. is there. This configuration produces the following effects. Since the through conductor 16k1 can be formed after the TFT 13 is formed, it is possible to prevent the conductor constituting the through conductor 16k1 from contaminating the semiconductor layer 13a of the TFT 13. Further, as a result of suppressing the occurrence of the above-mentioned problems due to the heat generation of the through conductor 16k1, a highly reliable and long-life semiconductor device can be manufactured. Conventionally, when the TFT 13 is formed after the through conductor 16k1 is formed, the conductors such as copper (Cu) constituting the through conductor 16k1 diffuse and contaminate the semiconductor layer 13a of the TFT 13 in the heating step for forming the TFT 13. However, in the present invention, this problem is solved. The semiconductor layer 13a is made of low-temperature polysilicon (LTPS), amorphous silicon, or the like.

貫通導体16k1は、レーザ加工法、エッチング法等によって絶縁基板1を貫通する孔を形成し、次に孔に導体柱を配置することによって形成される。導体柱は、孔に導体ペーストを充填し焼成して導体柱を作製する厚膜形成法等によって形成される。あるいは、別途作製した導体柱を孔に挿入し、導電性接着材等によって孔に導体柱を接着することによって形成される。貫通導体16k1は、銅(Cu),アルミニウム(Al),銀(Ag),モリブデン(Mo),ニッケル(Ni),クロム(Cr)等の金属またはそれらの1種以上を含む合金から成る。 The through conductor 16k1 is formed by forming a hole penetrating the insulating substrate 1 by a laser processing method, an etching method, or the like, and then arranging a conductor column in the hole. The conductor column is formed by a thick film forming method or the like in which a conductor paste is filled in a hole and fired to produce a conductor column. Alternatively, it is formed by inserting a separately prepared conductor pillar into the hole and adhering the conductor pillar to the hole with a conductive adhesive or the like. The through conductor 16k1 is made of a metal such as copper (Cu), aluminum (Al), silver (Ag), molybdenum (Mo), nickel (Ni), chromium (Cr), or an alloy containing one or more of them.

複数の絶縁層31は、無機材料又は有機材料から構成される。無機材料としては、酸化珪素(SiO2),窒化珪素(SiNx)等を用いることができる。有機材料としては、アクリル樹脂,ポリイミド,ポリアミド,ポリイミドアミド,ベンゾシクロブテン,ポリシロキサン,ポリシラザン等を用いることができる。複数の絶縁層31は、CVD(Chemical Vapor Deposition)法等によって形成される。 The plurality of insulating layers 31 are composed of an inorganic material or an organic material. As the inorganic material, silicon oxide (SiO 2 ), silicon nitride (SiN x ) and the like can be used. As the organic material, acrylic resin, polyimide, polyamide, polyimide amide, benzocyclobutene, polysiloxane, polysilazane and the like can be used. The plurality of insulating layers 31 are formed by a CVD (Chemical Vapor Deposition) method or the like.

貫通導体16k1とTFT13を電気的に接続する正電圧入力線16、負電圧入力線17等の配線は、アルミニウム(Al),チタン(Ti),モリブデン(Mo),タンタル(Ta),タングステン(W),クロム(Cr),銀(Ag),銅(Cu),ネオジウム(Nd),金(Au)等から選ばれた元素から成る金属材料、これらの元素を主成分とする合金材料を用いて形成される。また配線は、透光性が必要な場合、インジウム錫酸化物(ITO),インジウム亜鉛酸化物(IZO),酸化珪素を添加したインジウム錫酸化物(ITSO),酸化亜鉛(ZnO)等の酸化物から成る透明導電性材料、またはリン,ボロンを含むシリコン(Si)等の導電性材料であって透光性を有する材料を用いて形成される。また配線は、メッキ法、蒸着法、スパッタリング法、CVD法等によって形成される。 The wiring of the positive voltage input line 16, the negative voltage input line 17, etc. that electrically connects the through conductor 16k1 and the TFT 13 is aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W). ), Chromium (Cr), silver (Ag), copper (Cu), neodymium (Nd), gold (Au), etc., using a metal material composed of elements, and an alloy material containing these elements as the main components. It is formed. If translucency is required for wiring, oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide (ITSO) to which silicon oxide is added, and zinc oxide (ZnO) are used. It is formed by using a transparent conductive material made of, or a conductive material such as silicon (Si) containing phosphorus and boron, which has translucency. The wiring is formed by a plating method, a vapor deposition method, a sputtering method, a CVD method, or the like.

本発明の半導体装置の製造方法は、貫通孔16k1をエッチング法によって形成し、絶縁基板1を貫通する孔をレーザ光照射法によって形成することが好ましい。この場合、絶縁基板1を貫通する孔の位置及び大きさを正確なものとして形成できる。その結果、放熱性に優れた貫通導体16k1を形成することが容易になる。 In the method for manufacturing a semiconductor device of the present invention, it is preferable that the through hole 16k1 is formed by an etching method and the hole penetrating the insulating substrate 1 is formed by a laser light irradiation method. In this case, the position and size of the hole penetrating the insulating substrate 1 can be accurately formed. As a result, it becomes easy to form the through conductor 16k1 having excellent heat dissipation.

貫通孔16k1をエッチング法によって形成するには、絶縁層31上にフォトレジストを塗布して貫通孔16k1を形成するためのパターンを露光した後に、エッチング法により不要な絶縁層31の部位を除去することによって、形成し得る。エッチング法としては、弗酸等のエッチング液を用いるウェットエッチング法、四フッ化炭素ガス等のエッチングガスを用いるドライエッチング法等の公知のエッチング法を採用し得る。 In order to form the through hole 16k1 by the etching method, a photoresist is applied on the insulating layer 31 to expose a pattern for forming the through hole 16k1, and then an unnecessary portion of the insulating layer 31 is removed by the etching method. By doing so, it can be formed. As the etching method, known etching methods such as a wet etching method using an etching solution such as fluoroacid and a dry etching method using an etching gas such as carbon tetrafluoride gas can be adopted.

絶縁基板1を貫通する孔をレーザ光照射法によって形成するには、光波長780nm〜1400nm程度の赤外線を発振する赤外線レーザ(Infrared Laser:IR)装置等を用いて形成し得る。赤外線は熱作用が大きく、IRレーザ光を用いると、鋼板、ガラス基板等の被照射部材の溶断、穴あけ等の加工が容易である。IRレーザ装置としては、炭酸ガス(CO2)レーザ装置、Nd:YAG(NdドープYAG)レーザ装置等のYAG(イットリウム・アルミニウム・ガーネット)レーザ装置等がある。YAGレーザ装置のレーザ光は、炭酸ガス(CO2)レーザ装置のレーザ光よりも短波長であり、加熱効率が高いために好適である。YAGレーザ装置のメリットとしては、熱が集中し、被照射部材への入熱が少ないために被照射部材の歪が少なくなること、パルス制御によって仕上がりが良好な孔の形状が得られること、光の焦点の大きさを変えることによって孔の大きさを制御できること、被照射部材の材料に対する依存性が小さく種々の材料の被照射部材を選択できること、がある。 In order to form a hole penetrating the insulating substrate 1 by a laser light irradiation method, it can be formed by using an infrared laser (IR) device or the like that oscillates infrared rays having a light wavelength of about 780 nm to 1400 nm. Infrared rays have a large thermal effect, and when IR laser light is used, processing such as fusing and drilling of irradiated members such as steel plates and glass substrates is easy. Examples of the IR laser device include a carbon dioxide (CO 2 ) laser device, a YAG (yttrium aluminum garnet) laser device such as an Nd: YAG (Nd-doped YAG) laser device, and the like. The laser beam of the YAG laser device has a shorter wavelength than the laser beam of the carbon dioxide (CO 2 ) laser device, and is suitable because of its high heating efficiency. The merits of the YAG laser device are that the heat is concentrated and the heat input to the irradiated member is small, so that the strain of the irradiated member is reduced, and the shape of the hole with a good finish can be obtained by pulse control. The size of the hole can be controlled by changing the size of the focal point, and the irradiated member of various materials can be selected with less dependence on the material of the irradiated member.

また本発明の半導体装置の製造方法は、導体柱は銅柱であることが好ましい。この場合、高い導電性を有する貫通導体16k1を形成できる。従って、貫通導体16k1の発熱による上記諸問題点の発生をより抑えることができるとともに、貫通導体16k1を構成する銅(Cu)がTFTの半導体層を汚染することを抑えることができ、長寿命の半導体装置を製造できる。 Further, in the method for manufacturing a semiconductor device of the present invention, it is preferable that the conductor column is a copper column. In this case, a through conductor 16k1 having high conductivity can be formed. Therefore, it is possible to further suppress the occurrence of the above-mentioned problems due to the heat generated by the through conductor 16k1, and it is possible to prevent the copper (Cu) constituting the through conductor 16k1 from contaminating the semiconductor layer of the TFT, resulting in a long life. Can manufacture semiconductor devices.

なお、本発明の半導体装置、発光装置、半導体装置の製造方法は、上記実施の形態に限定されるものではなく、適宜の変更、改良を含んでいてもよい。 The method for manufacturing the semiconductor device, the light emitting device, and the semiconductor device of the present invention is not limited to the above embodiment, and may include appropriate changes and improvements.

本発明の半導体装置を有する発光装置は、LED表示装置、有機EL表示装置等の表示装置に適用し得、またその表示装置は、各種の電子機器に適用できる。その電子機器としては、複合型かつ大型の表示装置(マルチディスプレイ)、自動車経路誘導システム(カーナビゲーションシステム)、船舶経路誘導システム、航空機経路誘導システム、スマートフォン端末、携帯電話、タブレット端末、パーソナルデジタルアシスタント(PDA)、ビデオカメラ、デジタルスチルカメラ、電子手帳、電子書籍、電子辞書、パーソナルコンピュータ、複写機、ゲーム機器の端末装置、テレビジョン、商品表示タグ、価格表示タグ、産業用のプログラマブル表示装置、カーオーディオ、デジタルオーディオプレイヤー、ファクシミリ、プリンター、現金自動預け入れ払い機(ATM)、自動販売機、ヘッドマウントディスプレイ(HMD)、デジタル表示式腕時計、スマートウォッチなどがある。 The light emitting device having the semiconductor device of the present invention can be applied to a display device such as an LED display device and an organic EL display device, and the display device can be applied to various electronic devices. The electronic devices include a complex and large display device (multi-display), an automobile route guidance system (car navigation system), a ship route guidance system, an aircraft route guidance system, a smartphone terminal, a mobile phone, a tablet terminal, and a personal digital assistant. (PDA), video cameras, digital still cameras, electronic notebooks, electronic books, electronic dictionaries, personal computers, copying machines, game equipment terminals, televisions, product display tags, price display tags, industrial programmable display devices, Car audio, digital audio players, facsimiles, printers, automatic cash deposit / payment machines (ATMs), vending machines, head mount displays (HMDs), digital display watches, smart watches, etc.

1 絶縁基板
2 走査信号線
3 発光制御信号線
13 TFT
14 発光素子
16 正電圧入力線
16k1 貫通導体
17 負電圧入力線
31 絶縁層
60 貫通孔
1 Insulated substrate 2 Scanning signal line 3 Light emission control signal line 13 TFT
14 Light emitting element 16 Positive voltage input line 16k1 Through conductor 17 Negative voltage input line 31 Insulation layer 60 Through hole

Claims (11)

絶縁基板と、
前記絶縁基板を貫通する貫通導体と、
前記絶縁基板上に配置された複数の絶縁層と、
前記複数の絶縁層の層間に配置されるとともに前記貫通導体に電気的に接続されている薄膜トランジスタと、を有している半導体装置であって、
前記複数の絶縁層における前記貫通導体と重なる部位に、貫通孔が配置されており、
前記貫通孔の開口の径が前記貫通導体の径よりも大きく、かつ前記貫通孔の開口の内側に前記貫通導体が位置している半導体装置。
Insulated substrate and
A through conductor penetrating the insulating substrate and
A plurality of insulating layers arranged on the insulating substrate,
A semiconductor device having a thin film transistor arranged between layers of the plurality of insulating layers and electrically connected to the through conductor.
Through holes are arranged in the portions of the plurality of insulating layers that overlap with the through conductors.
A semiconductor device in which the diameter of the opening of the through hole is larger than the diameter of the through conductor and the through conductor is located inside the opening of the through hole.
前記貫通導体は、複数個が前記絶縁基板に均等に配置されている請求項1に記載の半導体装置。 The semiconductor device according to claim 1, wherein a plurality of the through conductors are evenly arranged on the insulating substrate. 前記貫通導体は前記絶縁基板に複数配置されているとともに、それらは前記絶縁基板の端との距離が互いに異なるものを含んでおり、
前記絶縁基板の端に最も近い前記貫通導体の平面視での面積が他の前記貫通導体の平面視での面積よりも大きい請求項1に記載の半導体装置。
A plurality of the through conductors are arranged on the insulating substrate, and they include those having different distances from the edges of the insulating substrate.
The semiconductor device according to claim 1, wherein the area of the through conductor closest to the edge of the insulating substrate in a plan view is larger than the area of another through conductor in a plan view.
前記絶縁基板の端に最も近い前記貫通導体を流れる電流が、他の前記貫通導体を流れる電流よりも大きい請求項3に記載の半導体装置。 The semiconductor device according to claim 3, wherein the current flowing through the penetrating conductor closest to the edge of the insulating substrate is larger than the current flowing through the other penetrating conductor. 前記絶縁基板は、側面に配置された側面導体を有しており、
前記貫通導体は、前記側面導体に電気的に接続されている請求項1乃至請求項4のいずれか1項に記載の半導体装置。
The insulating substrate has side conductors arranged on the side surface.
The semiconductor device according to any one of claims 1 to 4, wherein the through conductor is electrically connected to the side conductor.
前記絶縁基板は、側面に前記側面導体と電気的に独立している側面配線が配置されている請求項5に記載の半導体装置。 The semiconductor device according to claim 5, wherein the insulating substrate is provided with side wiring that is electrically independent of the side conductor on the side surface. 請求項1乃至請求項6のいずれか1項に記載の半導体装置を有する発光装置であって、
前記複数の絶縁層の上に前記薄膜トランジスタと電気的に接続される電極が配置されており、
前記電極に接続された発光素子を有している発光装置。
A light emitting device having the semiconductor device according to any one of claims 1 to 6.
Electrodes that are electrically connected to the thin film transistor are arranged on the plurality of insulating layers.
A light emitting device having a light emitting element connected to the electrode.
請求項1乃至請求項6のいずれか1項に記載の半導体装置の製造方法であって、
前記絶縁基板上に前記複数の絶縁層を積層するとともにそれらの層間に前記薄膜トランジスタを形成し、
次に、前記複数の絶縁層を貫通する前記貫通孔を形成し、
次に、前記貫通孔の開口の内側に露出した前記絶縁基板の部位に、前記絶縁基板を貫通する孔を形成し、前記孔に導体柱を配置することによって前記貫通導体を形成する半導体装置の製造方法。
The method for manufacturing a semiconductor device according to any one of claims 1 to 6.
The plurality of insulating layers are laminated on the insulating substrate, and the thin film transistor is formed between the layers.
Next, the through hole penetrating the plurality of insulating layers is formed.
Next, the semiconductor device for forming the penetrating conductor by forming a hole penetrating the insulating substrate in a portion of the insulating substrate exposed inside the opening of the through hole and arranging a conductor column in the hole. Production method.
前記貫通孔をエッチング法によって形成し、
前記絶縁基板を貫通する孔をレーザ光照射法によって形成する請求項8に記載の半導体装置の製造方法。
The through hole is formed by an etching method.
The method for manufacturing a semiconductor device according to claim 8, wherein the holes penetrating the insulating substrate are formed by a laser light irradiation method.
前記導体柱は銅柱である請求項8または請求項9に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 8 or 9, wherein the conductor column is a copper column. 前記貫通孔は、前記貫通導体の側の径よりも反対側の径が大きい請求項8乃至請求項10のいずれか1項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 8 to 10, wherein the through hole has a diameter on the side opposite to the diameter on the side of the through conductor.
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