JP6790804B2 - Semiconductor device, electronic device and test method for electronic device - Google Patents

Description

The present invention relates to semiconductor devices, electronic devices and test methods for electronic devices.

In an electronic device having a plurality of semiconductor devices such as electronic components, for example, after a plurality of semiconductor devices are mounted on a substrate such as a printed circuit board, a connection failure between the semiconductor devices connected to each other via the wiring of the substrate is detected. The test is performed. For example, when an open failure occurs in which the signal path between semiconductor devices is opened due to a disconnection of wiring on the signal path, the test signal output from one semiconductor device to the other semiconductor device is a signal path. It reflects at the point where the above open failure occurs. Therefore, a test method has been proposed in which a reflected signal reflected at a location where an open failure occurs is detected to identify a location where an open failure occurs (see, for example, Patent Documents 1, 2 and 3).

Japanese Unexamined Patent Publication No. 2006-278977 Japanese Unexamined Patent Publication No. 2008-232892 Japanese Unexamined Patent Publication No. 2006-145527

In the test for detecting a connection failure between semiconductor devices, in addition to an open failure, a short-circuit failure in which a signal path is short-circuited to a power source or the like is also detected as a connection failure between semiconductor devices. When a short-circuit failure is detected, for example, a visual inspection of the connection portion between the semiconductor device and the wiring is performed to identify the location where the short-circuit failure occurs. However, with the high-density mounting of semiconductor devices, it has become difficult to visually inspect the connection portion between the semiconductor device and the wiring. In this case, the location where the short failure occurs is not specified.

On one aspect, it is an object of the present invention to determine where a failure occurs in a signal path between a plurality of semiconductor devices.

In one embodiment, the semiconductor device connected to the other semiconductor device has a test signal output unit that outputs a test signal from the terminal to be tested to the other semiconductor device, and a propagation propagating to the terminal to be tested. A comparison unit that receives a signal, compares the threshold value according to the type of failure that occurred in the signal path with the propagated signal, and generates a comparison signal showing the comparison result, and connects the terminal to be tested and another semiconductor device. It is used to determine the location of a failure by receiving a comparison signal from the timing adjustment unit that sets the determination timing determined based on the length of the wiring and the comparison signal at the determination timing. It has a holding unit that holds a comparison signal as a signal.

In another embodiment, the electronic device has a plurality of semiconductor devices connected to each other, and one of the plurality of semiconductor devices outputs a test signal from the terminal under test to the other semiconductor device. A comparison that receives the propagated signal propagated to the terminal to be tested, compares the threshold value and the propagated signal according to the type of failure that occurred in the signal path, and generates a comparison signal that shows the comparison result. A timing adjustment unit that sets a determination timing determined based on the length of the wiring that connects the unit, the terminal to be tested, and another semiconductor device, and a comparison signal received from the comparison unit and compared at the determination timing. It has a holding unit that holds a comparison signal as a signal used when determining a location where a failure has occurred.

According to one aspect of a test method for an electronic device having a plurality of semiconductor devices connected to each other, a test signal output unit of the semiconductor device of any of the plurality of semiconductor devices outputs a test signal from a terminal to be tested. Output to another semiconductor device, the comparison unit of one of the semiconductor devices receives the propagated signal propagated to the terminal to be tested, and compares the threshold value and the propagated signal according to the type of failure that occurred in the signal path. Then, a comparison signal indicating the comparison result is generated, and the holding unit of one of the semiconductor devices receives the comparison signal from the comparison unit and is based on the length of the wiring connecting the terminal to be tested and the other semiconductor device. By taking in the comparison signal at the determined determination timing, a test method for holding the comparison signal as a signal used when determining the location where the failure has occurred is provided.

On one aspect, the present invention can determine where a failure occurs in a signal path between a plurality of semiconductor devices.

It is a figure which shows one Embodiment of the semiconductor device, the electronic device, and the test method of the electronic device. It is a figure which shows another embodiment of the semiconductor device, the electronic device, and the test method of the electronic device. It is a figure which shows an example of the voltage waveform of the driver side and the receiver side when an open failure occurs. It is a figure which shows an example of the voltage waveform of the driver side and the receiver side when a short-circuit failure occurs. It is a figure which shows an example of the test method of the electronic apparatus shown in FIG. It is a figure which shows an example of the determination method of the failure occurrence part of the electronic device shown in FIG. It is a figure which shows another embodiment of the semiconductor device, the electronic device, and the test method of the electronic device. It is a figure which shows an example of the voltage waveform of the driver side and the receiver side when an open failure occurs. It is a figure which shows an example of the voltage waveform of the driver side and the receiver side when a short-circuit failure occurs. It is a figure which shows another embodiment of the semiconductor device, the electronic device, and the test method of the electronic device. It is a figure which shows an example of the voltage waveform on the driver side when an open failure occurs. It is a figure which shows an example of the voltage waveform on the driver side when a short-circuit failure occurs. It is a figure which shows another example of the voltage waveform on the driver side when a short-circuit failure occurs. It is a figure which shows an example of the determination method of the failure occurrence part of the electronic device shown in FIG. It is a figure which shows another embodiment of the semiconductor device, the electronic device, and the test method of the electronic device. It is a figure which shows an example of the voltage waveform on the driver side when an open failure occurs. It is a figure which shows an example of the voltage waveform on the driver side when a short-circuit failure occurs. It is a figure which shows an example of the test method of the electronic apparatus shown in FIG. It is a figure which shows an example of the determination method of the failure occurrence part of the electronic device shown in FIG.

Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 shows an embodiment of a semiconductor device, an electronic device, and a test method for the electronic device. The electronic device 10 shown in FIG. 1 is, for example, an information processing device such as a server. The electronic device 10 has a plurality of semiconductor devices 20 (20A, 20B) connected to each other. The number of semiconductor devices 20 included in the electronic device 10 is not limited to two.

The semiconductor devices 20A and 20B are mounted on a printed circuit board, for example, and are connected to each other by a wiring 32 (hereinafter, also referred to as a printed wiring board 32) arranged on the printed circuit board. For example, the terminal 30d of the semiconductor device 20A is connected to the terminal 30r of the semiconductor device 20B by a printed wiring 32 having a length L (hereinafter, also referred to as a wiring length L). The configuration of the test block used for testing the poor connection between the semiconductor devices 20A and 20B is the same as or similar to that of the semiconductor devices 20A and 20B. Therefore, FIG. 1 describes the semiconductor device 20A.

The semiconductor device 20A includes a test signal output unit 40, a comparison unit 50, a timing adjustment unit 60, and a holding unit 70 as test blocks in addition to a logic circuit that realizes the original functions of the semiconductor device 20A. The test signal output unit 40, the comparison unit 50, the timing adjustment unit 60, and the holding unit 70 are provided, for example, for each terminal 30d to be tested.

The test signal output unit 40 outputs a test signal (hereinafter, also referred to as a test signal) from the terminal 30d to be tested to the terminal 30r of another semiconductor device 20B. Hereinafter, the semiconductor device 20 that outputs the test signal is also referred to as a driver side, and the semiconductor device 20 that receives the test signal is also referred to as a receiver side. For example, when the test signal output unit 40 determines a location where an open failure occurs in which the signal path between the terminals 30d and 30r is in an open state, the test signal output unit 40 sets the initial state of the test signal to the ground voltage and then sets the test signal of the voltage VH. Is output to the terminal 30r via the terminal 30d. The voltage VH is, for example, a power supply voltage of a logic circuit or the like that realizes the original function of the semiconductor device 20A.

When determining the location of a short-circuit failure in which the signal path between the terminals 30d and 30r is short-circuited to the power supply, the test signal output unit 40 differs depending on whether the signal path is short-circuited to the ground voltage or the power supply voltage. Is output to the terminal 30r. For example, when the test signal output unit 40 determines the location where a short-circuit failure occurs in which the signal path between the terminals 30d and 30r is short-circuited to the ground voltage, the test signal output unit 40 outputs the same or similar test signal as when determining the location where an open failure occurs. , Output to terminal 30r via terminal 30d. Further, when determining the location of a short-circuit failure in which the signal path between the terminals 30d and 30r is short-circuited to the power supply voltage, the test signal output unit 40 sets the initial state of the test signal to the power supply voltage and then tests the ground voltage. The signal is output to the terminal 30r via the terminal 30d.

The comparison unit 50 is connected to the terminal 30d to be tested and receives a propagation signal propagated to the terminal 30d to be tested. Then, the comparison unit 50 compares the threshold VTH (VTH1, VTH2) according to the type of failure generated in the signal path between the semiconductor devices 20A and 20B with the propagation signal, and generates a comparison signal showing the comparison result. The types of failures are classified into, for example, open failures, short failures, and the like.

For example, the comparison unit 50 compares the threshold value VTH2 associated with the open failure with the propagation signal when the type of failure is open failure, and when the type of failure is short failure, the threshold value associated with the short failure. Compare VTH1 with the propagated signal. The threshold value VTH2 associated with the open failure is preset to, for example, a voltage value between the voltage VH of the test signal and a voltage twice the voltage VH (for example, 1.5 times the voltage VH). Further, the threshold value VTH1 associated with the short-circuit failure is preset to, for example, a voltage value between the ground voltage and the voltage VH of the test signal (for example, 0.5 times the voltage VH). In this way, the threshold value VTH2 associated with the open failure is set to a voltage value larger than the threshold value VTH1 associated with the short failure.

An example of the voltage waveform of the propagated signal propagated to the comparison unit 50 when a failure occurs in the signal path between the semiconductor devices 20A and 20B is shown in parentheses in FIG. The vertical axis of the timing diagram shown in parentheses in FIG. 1 indicates the voltage of the propagation signal, and the horizontal axis indicates time. In the example shown in FIG. 1, the test signal of the voltage VH output from the test signal output unit 40 at time t0 reaches the comparison unit 50 at time t1 when the propagation delay time in the semiconductor device 20A has elapsed. After time t1, the voltage of the propagated signal propagated to the comparison unit 50 changes depending on the type of failure, the location of failure, and the like when a failure occurs in the signal path between the semiconductor devices 20A and 20B. The location where the failure occurs is the terminal 30r on the receiver side, the terminal 30d on the driver side, and the like.

For example, when an open failure occurs at the terminal 30r on the receiver side, the voltage VH test signal is reflected at the location where the failure occurs (for example, the end of the printed wiring board 32 on the terminal 30r side). Then, the test signal reflected at the location where the failure occurs (hereinafter, also referred to as a reflected wave of the test signal) reaches the comparison unit 50 at time t4. The time from time t0 to time t4 is the propagation time when the signal reciprocates in the signal path including the signal path in the semiconductor device 20A and the printed wiring 32 having the wiring length L.

That is, when an open failure occurs at the terminal 30r on the receiver side, the comparison unit 50 receives the test signal as a propagation signal between the time t1 and the time t4, and after the time t4, the reflected wave of the test signal is added to the test signal. Receives the propagated signal with the addition of. In this case, the voltage of the propagated signal propagated to the comparison unit 50 changes from the ground voltage to the voltage VH of the test signal at time t1, and is maintained at the voltage VH of the test signal between time t1 and time t4. .. The voltage of the propagated signal propagated to the comparison unit 50 is the voltage obtained by adding the voltage VH of the reflected wave of the test signal to the voltage VH at time t4, that is, a voltage twice the voltage VH of the test signal (2). It changes to × VH), and after time t4, the voltage is maintained at twice the voltage VH of the test signal.

Further, when an open failure occurs at the terminal 30d on the driver side, the test signal of the voltage VH is reflected at the terminal 30d where the failure occurs, and the reflected wave of the test signal reaches the comparison unit 50 at time t2. .. The time from time t0 to time t2 is the propagation time when the signal reciprocates in the signal path in the semiconductor device 20A.

That is, when an open failure occurs at the terminal 30d on the driver side, the comparison unit 50 receives the test signal as a propagation signal between the time t1 and the time t2, and after the time t2, the reflected wave of the test signal is added to the test signal. Receives the propagated signal with the addition of. In this case, the voltage of the propagated signal propagated to the comparison unit 50 changes from the ground voltage to the voltage VH of the test signal at time t1, and is maintained at the voltage VH of the test signal between time t1 and time t2. .. Then, the voltage of the propagated signal propagated to the comparison unit 50 changes to a voltage (2 × VH) twice the voltage VH of the test signal at time t2, and after time t2, the voltage VH of the test signal is 2 It is maintained at double the voltage.

Further, when a short-circuit failure occurs in which the terminal 30r on the receiver side is short-circuited to the ground voltage, the propagation signal from the terminal 30r short-circuited to the ground voltage after the test signal of the voltage VH reaches the terminal 30r where the failure occurs. (Propagation signal of ground voltage) reaches the comparison unit 50 at time t4. That is, when a short-circuit failure occurs in which the terminal 30r on the receiver side is short-circuited to the ground voltage, the comparison unit 50 receives the test signal of the voltage VH as a propagation signal between the time t1 and the time t4, and after the time t4, the comparison unit 50 receives the test signal. Receives the propagation signal of the ground voltage. In this case, the voltage of the propagated signal propagated to the comparison unit 50 changes from the ground voltage to the voltage VH of the test signal at time t1, and is maintained at the voltage VH of the test signal between time t1 and time t4. .. Then, the voltage of the propagation signal propagated to the comparison unit 50 changes from the voltage VH to the ground voltage at time t4, and is maintained at the ground voltage after time t4.

Further, when a short-circuit failure occurs in which the terminal 30d on the driver side is short-circuited to the ground voltage, the propagation signal from the terminal 30d short-circuited to the ground voltage after the test signal of the voltage VH reaches the terminal 30d where the failure occurs. (Propagation signal of ground voltage) reaches the comparison unit 50 at time t2. That is, when a short-circuit failure occurs in which the terminal 30d on the receiver side is short-circuited to the ground voltage, the comparison unit 50 receives a signal for testing the voltage VH as a propagation signal between the time t1 and the time t2, and after the time t2. Then, it receives the propagation signal of the ground voltage. In this case, the voltage of the propagated signal propagated to the comparison unit 50 changes from the ground voltage to the voltage VH of the test signal at time t1, and is maintained at the voltage VH of the test signal between time t1 and time t2. .. Then, the voltage of the propagation signal propagated to the comparison unit 50 changes from the voltage VH to the ground voltage at time t2, and is maintained at the ground voltage after time t2.

As described above, between the time t2 and the time t4, the voltage of the propagation signal propagated to the comparison unit 50 differs depending on the location where the failure occurs. Therefore, between the time t2 and the time t4, the comparison result between the threshold value VTH and the propagation signal according to the type of failure differs depending on the location where the failure occurs. For example, between time t2 and time t4, the voltage of the propagated signal propagated to the comparison unit 50 is smaller than the threshold value VTH2 when an open failure occurs at the receiver side terminal 30r, and the open failure occurs at the driver side terminal 30d. Is greater than the threshold VTH2. Further, between time t2 and time t4, the voltage of the propagation signal propagated to the comparison unit 50 is larger than the threshold value VTH1 when the terminal 30r on the receiver side is short-circuited to the ground voltage, and the terminal 30d on the driver side is the ground voltage. When short-circuited to, it is smaller than the threshold value VTH1.

For example, when the voltage of the propagation signal is larger than the threshold value VTH compared according to the type of failure, the comparison unit 50 outputs a signal having a logic value “1” (for example, a power supply voltage) to the holding unit 70 as a comparison signal. Further, when the voltage of the propagation signal is smaller than the threshold value VTH compared according to the type of failure, the comparison unit 50 outputs a signal having a logic value “0” (for example, a ground voltage) to the holding unit 70 as a comparison signal. The logical value of the comparison signal indicating the magnitude relationship between the voltage of the propagate signal and the threshold value VTH may be the opposite of the above-mentioned example.

The timing adjusting unit 60 is set with a determination timing determined based on the length L of the wiring 32 connecting the terminal 30d to be tested and the other semiconductor device 20B. When the determination time TJ elapses from the time t0 when the test signal is output from the test signal output unit 40, the timing adjustment unit 60 outputs a signal such as a pulse indicating that the determination timing is reached to the holding unit 70. The determination time TJ is set so that, for example, the determination timing is between the time t2 and the time t4. For example, the determination time TJ is the time obtained by adding the propagation time when the signal reciprocates in the signal path in the semiconductor device 20A and the one-way propagation time when the signal propagates through the printed wiring 32 having the wiring length L. ..

The holding unit 70 receives the comparison signal from the comparison unit 50 and captures the comparison signal at the determination timing to hold the comparison signal as a signal used when determining the location where the failure has occurred. For example, the holding unit 70 captures and holds the comparison signal received from the comparison unit 50 at the time (t0 + TJ) when the signal such as a pulse indicating that it is the determination timing is received from the timing adjusting unit 60.

As a result, for example, when an open failure occurs at the terminal 30r on the receiver side, the holding unit 70 holds a comparison signal (for example, a signal having a logic value “0”) indicating that the voltage of the propagate signal is smaller than the threshold value VTH2. To do. When an open failure occurs at the terminal 30d on the driver side, the holding unit 70 holds a comparison signal (a signal having a logical value “1”) indicating that the voltage of the propagate signal is larger than the threshold value VTH2.

Further, for example, when a short-circuit failure occurs in which the terminal 30r on the receiver side is short-circuited to the ground voltage, the holding unit 70 indicates that the voltage of the propagation signal is larger than the threshold value VTH1 (for example, the logic value “1”. Signal) is held. When a short-circuit failure occurs in which the terminal 30d on the driver side is short-circuited to the ground voltage, the holding unit 70 holds a comparison signal (for example, a signal having a logic value “0”) indicating that the voltage of the propagated signal is smaller than the threshold value VTH1. To do.

Further, for example, when a short-circuit failure occurs in which the terminal 30r on the receiver side is short-circuited to the power supply voltage, the holding unit 70 has a comparison signal (for example, a logic value “0”” indicating that the voltage of the propagation signal is smaller than the threshold value VTH1. Signal) is held. When a short-circuit failure occurs in which the terminal 30d on the driver side is short-circuited to the power supply voltage, the holding unit 70 holds a comparison signal (for example, a signal having a logic value “1”) indicating that the voltage of the propagate signal is larger than the threshold value VTH1. To do.

Therefore, in the test device (not shown) for testing the electronic device 10, whether the failure location is on the receiver side based on the type of failure and the level (logical value) of the comparison signal held in the holding unit 70. It can be determined whether it is the driver side.

For example, when each semiconductor device 20 has a boundary scan circuit specified by IEEE 1149.1, the test device for testing the electronic device 10 uses the boundary scan circuit to fail the signal path between the semiconductor devices 20A and 20B. Perform a test to detect. Then, the test apparatus determines the type of the detected failure. Hereinafter, IEEE1149.1 is also referred to as JTAG (Joint Test Action Group).

Further, after determining the type of failure, the test apparatus controls the test signal output unit 40, the comparison unit 50, the timing adjustment unit 60, the holding unit 70, and the like to execute a test for determining the location where the failure occurs. For example, when determining the location of a short-circuit failure in which the signal path is short-circuited to the ground voltage, the test signal output unit 40 sets the initial state of the test signal to the ground voltage according to the control from the test device, and then the voltage. The VH test signal is output to the terminal 30r via the terminal 30d. Further, the comparison unit 50 selects the threshold value VTH1 among the threshold values VTH1 and VTH2 as the threshold value VTH to be compared with the propagated signal according to the control from the test apparatus. Then, the comparison unit 50 compares the threshold value VTH1 selected according to the control from the test apparatus with the voltage of the propagation signal, and outputs a comparison signal indicating the comparison result to the holding unit 70. The holding unit 70 captures and holds the comparison signal at the determination timing set in the timing adjusting unit 60. The test apparatus reads out the comparison signal held by the holding unit 70 via a boundary scan circuit or the like. Then, the test apparatus determines the location of the short-circuit failure in which the signal path is short-circuited to the ground voltage based on the logical value of the comparison signal read from the holding unit 70.

In this way, by using the comparison signal held by the holding unit 70, it is possible to determine the location of failure in the signal path between the plurality of semiconductor devices 20 without performing the visual inspection. Here, for example, in the semiconductor device 20 mounted on the printed circuit board by BGA (Ball Grid Array) or the like, it is difficult to inspect the appearance of the inner BGA terminal, so that the location where the failure occurs (for example, the failure) It is difficult to determine which defective parts have. Therefore, a non-defective product may be replaced or repaired. In this case, the manufacturing cost increases. On the other hand, in the test of the electronic device 10, as described above, it is possible to determine whether the location where the failure occurs is the receiver side or the driver side without performing the visual inspection. As a result, it is possible to reduce the cost of repairing when a failure occurs. The configurations of the electronic device 10 and the semiconductor device 20 are not limited to the example shown in FIG.

As described above, in the embodiment shown in FIG. 1, the test signal output unit 40 included in the semiconductor device 20A of the plurality of semiconductor devices 20A and 20B transmits the test signal from the terminal 30d to be tested to the other semiconductor device 20B. Output. Then, the comparison unit 50 included in the semiconductor device 20A receives the propagation signal propagated to the terminal 30d to be tested, compares the threshold value VTH according to the type of failure generated in the signal path with the propagation signal, and compares the comparison result. Generate the comparison signal shown.

Further, the holding unit 70 included in the semiconductor device 20A receives a comparison signal from the comparison unit 50. Then, when the holding unit 70 determines the location where the failure has occurred by taking in the comparison signal at the determination timing determined based on the length L of the wiring 32 connecting the terminal 30d to be tested and the semiconductor device 20B. The comparison signal is held as the signal used for.

By using the comparison signal captured in the holding unit 70 at the determination timing determined based on the wiring length L, the location where a failure occurs in the signal path between the plurality of semiconductor devices 20 is determined without performing an visual inspection. can do.

FIG. 2 shows another embodiment of a semiconductor device, an electronic device, and a test method for the electronic device. Elements that are the same as or similar to those described in FIG. 1 are designated by the same or similar reference numerals, and detailed description thereof will be omitted. The electronic device 100 shown in FIG. 2 is, for example, an information processing device such as a server. The electronic device 100 has a plurality of semiconductor devices 200 (200A, 200B) corresponding to JTAG defined by IEEE1149.1. For example, the electronic device 100 has terminals TCK (Test ClocK), TMS (Test Mode Select), TRST (Test ReSeT), TDI (Test Data In), and TDO (Test) for interface signals called TAP (Test Access Port). Data Out) is provided. When testing the electronic device 100, the electronic device 100 is connected to the test device 1000 via terminals TCK, TMS, TRST, TDI, and TDO. Hereinafter, the same code as the terminal name is used for the signal supplied via the terminals TCK, TMS, TRST, TDI, and TDO.

The semiconductor devices 200A and 200B are mounted on a printed circuit board, for example, and are connected to each other by wiring 320 (hereinafter, also referred to as printed wiring board 320) arranged on the printed circuit board. For example, one of the plurality of terminals 300d of the semiconductor device 200A is connected to one of the plurality of terminals 300r of the semiconductor device 200B by the printed wiring 320 having a wiring length L. The terminal 300d indicates a terminal 300 that outputs a test signal for testing the signal path between the semiconductor devices 200A and 200B, and the terminal 300r indicates a terminal 300 that receives the test signal.

In FIG. 2, in order to make the figure easier to see, the description of the logic circuit or the like that realizes the original function of the semiconductor device 200 is omitted. Further, in the semiconductor device 200B, the description of the blocks other than the test circuit 400B is omitted in order to make the figure easier to see. The configuration of the test block used for testing the poor connection between the semiconductor devices 200A and 200B is the same as or similar to that of the semiconductor devices 200A and 200B. Therefore, FIG. 2 describes the semiconductor device 200A.

The semiconductor device 200A includes a test circuit 400A, a pulse generation unit 440, a comparison unit 500, a delay unit 600, and a holding unit 700. The test circuit 400 (400A, 400B) is, for example, a boundary scan circuit defined by IEEE 1149.1, and has a TAP controller 410, a boundary cell 420, and an output buffer 430. Hereinafter, the boundary cell is also referred to as a BC (Boundary Cell).

The TAP controller 410 is a synchronous state machine controlled by signals TCK, TMS, TRST and the like. For example, the TAP controller 410 receives a signal TMS or the like for selecting a test mode, and outputs a control signal for controlling the boundary cell 420 or the like.

The boundary cell 420 is a boundary scan register provided at each terminal 300 of the semiconductor device 200. For example, when the test device 1000 executes reading and writing to each terminal 300 of the semiconductor device 200, the boundary cell 420 is serially connected in the test circuit 400B as shown by a broken line to function as a shift register. Then, the test device 1000 executes reading / writing to each terminal 300 of the semiconductor device 200 by scanning the boundary cell 420. In the semiconductor device 200A shown in FIG. 2, the description of the wiring and the like when the boundary cell 420 is operated for scanning is omitted in order to make the figure easier to see.

The boundary cell 420a outputs, for example, the signal held by the scanning operation to the output buffer 430 or the like as a test signal. The boundary cell 420a is an example of a test signal output unit that outputs a test signal (test signal) from the terminal 300d to be tested to another semiconductor device 200B. Further, the boundary cell 420b holds the comparison signal received from the holding unit 700. The comparison signal held in the boundary cell 420b is read out to the test apparatus 1000 by the scanning operation.

The output buffer 430 outputs the test signal received from the boundary cell 420a to the terminal 300r of the semiconductor device 200B via the terminal 300d. The block including the boundary cell 420a and the output buffer 430 may be defined as a test signal output unit that outputs a test signal from the terminal 300d to be tested to another semiconductor device 200B.

The pulse generation unit 440 receives the test signal output from the boundary cell 420a. Then, the pulse generation unit 440 detects the rising edge or the falling edge of the test signal, and generates a pulse synchronized with the detected edge. For example, the pulse generation unit 440 generates a pulse in response to the change of the test signal from the ground voltage to the voltage VH, and outputs the generated pulse to the delay unit 600. In this way, the pulse generation unit 440 generates a pulse in synchronization with the timing when the test signal is output from the boundary cell 420a, and outputs the generated pulse to the delay unit 600.

The delay unit 600 is set with a delay time corresponding to a determination timing determined based on the length L of the wiring 320 connecting the terminal 300d to be tested and the other semiconductor device 200B. For example, the delay unit 600 is set with the determination time TJ shown in FIG. 3 or the like as the delay time corresponding to the determination timing. Then, the delay unit 600 delays the pulse received from the pulse generation unit 440 by the determination time TJ and outputs the pulse to the holding unit 700. That is, the delay unit 600 is an example of the timing adjustment unit, and the determination time TJ is an example of the delay time corresponding to the determination timing.

The comparison unit 500 is connected to the terminal 300d to be tested and receives a propagation signal propagated to the terminal 300d to be tested. Then, the comparison unit 500 compares the threshold value VTH according to the type of failure generated in the signal path between the semiconductor devices 200A and 200B with the propagation signal, and generates a comparison signal showing the comparison result. For example, the comparison unit 500 has a threshold selection unit 510 and a signal comparison unit 520.

The threshold selection unit 510 selects, for example, the threshold VTH to be compared with the propagated signal from the thresholds VTH1 and VTH2 predetermined for each type of failure based on the type of failure occurring in the signal path.

The signal comparison unit 520 is an example of a comparison signal generation unit that outputs a signal corresponding to the magnitude relationship between the threshold value VTH selected by the threshold value selection unit 510 and the propagation signal to the holding unit 700 as a comparison signal. For example, the signal comparison unit 520 is connected to the terminal 300d to be tested and receives a propagation signal propagated to the terminal 300d to be tested. Further, the signal comparison unit 520 receives the threshold value VTH according to the type of failure occurring in the signal path from the threshold value selection unit 510. Then, when the voltage of the propagation signal is larger than the threshold value VTH received from the threshold value selection unit 510, the signal comparison unit 520 outputs a signal having a logic value “1” (for example, a power supply voltage) to the holding unit 700 as a comparison signal. Further, when the voltage of the propagation signal is smaller than the threshold value VTH received from the threshold value selection unit 510, the signal comparison unit 520 outputs a signal having a logic value “0” (for example, the ground voltage) to the holding unit 700 as a comparison signal. The logical value of the comparison signal indicating the magnitude relationship between the voltage of the propagate signal and the threshold value VTH may be the opposite of the above-mentioned example.

The holding unit 700 receives the comparison signal from the signal comparison unit 520 of the comparison unit 500, and captures the comparison signal at the determination timing to hold the comparison signal as a signal used when determining the location where the failure has occurred. The holding unit 700 is, for example, a D flip-flop, and captures the comparison signal received from the signal comparison unit 520 in synchronization with the pulse received from the delay unit 600. As a result, the comparison signal at the determination timing is held by the holding unit 700. Then, the holding unit 700 outputs the held comparison signal to the boundary cell 420b.

The boundary cells 420a and 420b, the output buffer 430, the pulse generation unit 440, the comparison unit 500, the delay unit 600, and the holding unit 700 are provided, for example, for each terminal 300d to be tested. Further, the configurations of the electronic device 100 and the semiconductor device 200 are not limited to the example shown in FIG. For example, the number of semiconductor devices 200 included in the electronic device 100 is not limited to two.

FIG. 3 shows an example of voltage waveforms on the driver side and the receiver side when an open failure occurs. Note that FIG. 3 shows an example of a voltage waveform when a pull-down resistor connected to the ground wire is connected to the terminal 300r on the receiver side. In FIG. 3, the semiconductor device 200A will be described as the driver side, and the semiconductor device 200B will be described as the receiver side. The boundary cell 420a, signal comparison unit 520, pulse generation unit 440, delay unit 600, and holding unit 700 shown in FIG. 3 are the boundary cell 420a, signal comparison unit 520, pulse generation unit 440, and delay on the driver side (semiconductor device 200A). The unit 600 and the holding unit 700.

First, the voltage waveform when an open failure occurs on the receiver side will be described.

The output of the boundary cell 420a (BC420a) changes from the ground voltage to the voltage VH when the test signal of the voltage VH is output from the boundary cell 420a. Then, the output of the boundary cell 420a is maintained at the voltage VH.

The input of the signal comparison unit 520, that is, the propagation signal changes from the ground voltage to the voltage VH at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. For example, the time Tpf is the propagation time when the signal propagates along the signal path from the boundary cell 420a to the terminal 300d. Then, the input of the signal comparison unit 520 changes from the voltage VH to twice the voltage VH by the reflected wave of the propagated signal at the time when the time Tlpp elapses from the time when the ground voltage changes to the voltage VH. The time Tlp is the propagation time Tpb (hereinafter, time Tpb) when the signal propagates in the signal path from the terminal 300d to the signal comparison unit 520 during the propagation time when the signal reciprocates through the printed wiring 320 having the wiring length L. It is also the time obtained by adding). The propagation time when the signal reciprocates through the printed wiring 320 having the wiring length L is expressed as "2 x Tl" when the one-way propagation time when the signal propagates through the printed wiring 320 having the wiring length L is time Tl. Will be done.

Further, when the change in the output of the boundary cell 420a is used as a reference, the input of the signal comparison unit 520 is from the voltage VH at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. The voltage changes to twice the voltage VH. Then, the input of the signal comparison unit 520 changes from the voltage VH to a voltage twice the voltage VH, and then is maintained at a voltage twice the voltage VH. The time Tr is represented by the formula (1) using the time Tpf, Tpb, and Tl.

Tr = Tpf + (2 × Tl) + Tpb ・ ・ ・ (1)
The output of the signal comparison unit 520, that is, the comparison signal is maintained at the ground voltage during the period when the voltage of the propagated signal is less than the threshold value VTH2, and is maintained at the power supply voltage during the period when the voltage of the propagated signal exceeds the threshold value VTH2. Therefore, the output of the signal comparison unit 520 changes from the ground voltage to the power supply voltage at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the signal comparison unit 520 is maintained at the power supply voltage after changing from the ground voltage to the power supply voltage. For example, the ground voltage comparison signal corresponds to the signal having the logic value "0", and the power supply voltage comparison signal corresponds to the signal having the logic value "1". Hereinafter, when indicating the signal level, the ground voltage is also referred to as a logical value “0”, and the power supply voltage and the voltage VH are also referred to as a logical value “1”.

The output of the pulse generation unit 440 changes from the ground voltage to the power supply voltage at the same time or substantially the same time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the pulse generation unit 440 changes from the power supply voltage to the ground voltage after a predetermined time elapses from the time when the ground voltage changes to the power supply voltage. That is, the pulse generation unit 440 outputs the pulse to the delay unit 600 in synchronization with the rising edge of the output of the boundary cell 420a.

The output of the delay unit 600 changes from the ground voltage to the power supply voltage at the time when the determination time TJ elapses from the time when the output of the pulse generation unit 440 changes from the ground voltage to the power supply voltage. Then, the output of the delay unit 600 changes from the power supply voltage to the ground voltage at the time when the determination time TJ elapses from the time when the output of the pulse generation unit 440 changes from the power supply voltage to the ground voltage. That is, the delay unit 600 outputs the pulse to the holding unit 700 at the determination timing at which the determination time TJ has elapsed from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. The determination time TJ (delay time set in the delay unit 600) will be described after explaining the voltage waveform when an open failure occurs on the driver side.

The logical value held by the holding unit 700 is the logical value in the initial state because the output of the signal comparison unit 520 at the time (determination timing) when the output of the delay unit 600 changes from the ground voltage to the power supply voltage is the ground voltage. It is maintained at 0 ”(ground voltage).

The logical value of the boundary cell 420c (BC420c) on the receiver side is in the initial state even when the voltage VH test signal is transmitted from the boundary cell 420a on the driver side because an open failure has occurred on the receiver side. It is maintained at the logical value "0" (ground voltage).

Next, the voltage waveform when an open failure occurs on the driver side will be described. Even if an open failure occurs on the driver side, the logical value of the boundary cell 420c (BC420c) on the receiver side is the logical value "0" (ground voltage) in the initial state, as in the case of an open failure on the receiver side. Is maintained at. A detailed description will be omitted for the same or similar voltage waveform as when an open failure occurs on the receiver side.

The output of the boundary cell 420a (BC420a) is the same as or similar to the case where an open failure occurs on the receiver side.

The input of the signal comparison unit 520, that is, the propagation signal changes from the ground voltage to the voltage VH at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the input of the signal comparison unit 520 changes from the voltage VH to twice the voltage VH by the reflected wave of the propagated signal at the time when the time Tpb elapses from the time when the ground voltage changes to the voltage VH.

When the change in the output of the boundary cell 420a is used as a reference, the input of the signal comparison unit 520 is from the voltage VH at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. The voltage changes to twice the voltage VH. Then, the input of the signal comparison unit 520 changes from the voltage VH to a voltage twice the voltage VH, and then is maintained at a voltage twice the voltage VH. The time Td is represented by the formula (2) using the time Tpf and Tpb.

Td = Tpf + Tpb ... (2)
The output of the signal comparison unit 520, that is, the comparison signal changes from the ground voltage to the power supply voltage at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the signal comparison unit 520 is maintained at the power supply voltage after changing from the ground voltage to the power supply voltage.

The output of the pulse generation unit 440 and the output of the delay unit 600 are the same as or the same as when an open failure occurs on the receiver side.

The logical value held in the holding unit 700 is the logical value in the initial state because the output of the signal comparison unit 520 at the time (determination timing) when the output of the delay unit 600 changes from the ground voltage to the power supply voltage is the power supply voltage. The voltage changes from 0 "(ground voltage) to the logical value" 1 "(power supply voltage). That is, the logical value held in the holding unit 700 becomes the logical value "1" (power supply voltage) after the determination timing in which the determination time TJ has elapsed from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Be maintained.

In this way, the holding unit 700 captures and holds the comparison signal of the logical value "0" when an open failure occurs on the receiver side, and compares the logical value "1" when the open failure occurs on the driver side. Capture and hold the signal.

The determination time TJ (delay time set in the delay unit 600) is expressed by, for example, the equation (3).

TJ = (Td + Tr) / 2 = Td + Tl ... (3)
In this case, the determination timing is the timing at which the reflected wave of the test signal due to the open failure on the driver side reaches the signal comparison unit 520 and the timing at which the reflected wave of the test signal due to the open failure on the receiver side reaches the signal comparison unit 520. Be in the middle. Hereinafter, the timing at which the reflected wave of the test signal due to the open failure on the driver side reaches the signal comparison unit 520 is also referred to as the timing at which the reflected wave arrives from the driver side. Further, the timing at which the reflected wave of the test signal due to the open failure on the receiver side reaches the signal comparison unit 520 is also referred to as the timing at which the reflected wave arrives from the receiver side.

The determination time TJ is not limited to the time represented by the equation (3). The determination time TJ may be a time larger than the time Td and less than the time Tr. That is, the determination time TJ is determined based on the wiring length L so that the determination timing is between the reflection wave arrival timing from the driver side and the reflected wave arrival timing from the receiver side. For example, when the time Td is less than the time Tl, the determination time TJ set in the delay unit 600 may be the time Tl.

FIG. 4 shows an example of voltage waveforms on the driver side and the receiver side when a short-circuit failure occurs. Note that FIG. 4 shows an example of a voltage waveform when one of the terminals 300d and 300r is short-circuited to the ground voltage. A detailed description of the voltage waveform that is the same as or similar to the voltage waveform described in FIG. 3 will be omitted.

First, the voltage waveform when a short-circuit failure occurs on the receiver side will be described.

The output of the boundary cell 420a (BC420a), the output of the pulse generation unit 440, and the output of the delay unit 600 are the same as or similar to the case where the open failure described with reference to FIG. 3 occurs. That is, the determination timing is the same when an open failure occurs and when a short failure occurs.

The input of the signal comparison unit 520, that is, the propagation signal changes from the ground voltage to the voltage VH at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the input of the signal comparison unit 520 is changed from the voltage VH to the ground voltage by the propagation signal from the terminal 300r on the receiver side short-circuited to the ground voltage at the time when the time Tlpp elapses from the time when the voltage VH is changed from the ground voltage. Change.

When the change in the output of the boundary cell 420a is used as a reference, the input of the signal comparison unit 520 is from the voltage VH at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. It changes to the ground voltage. Then, the input of the signal comparison unit 520 is maintained at the ground voltage after changing from the voltage VH to the ground voltage.

The output of the signal comparison unit 520, that is, the comparison signal is maintained at the ground voltage during the period when the voltage of the propagate signal is less than the threshold VTH1, and is maintained at the power supply voltage during the period when the voltage of the propagation signal exceeds the threshold VTH1. Therefore, the output of the signal comparison unit 520 changes from the ground voltage to the power supply voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the signal comparison unit 520 changes from the power supply voltage to the ground voltage at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Further, the output of the signal comparison unit 520 is maintained at the ground voltage after changing from the power supply voltage to the ground voltage.

The logical value held in the holding unit 700 is the logical value in the initial state because the output of the signal comparison unit 520 at the time (determination timing) when the output of the delay unit 600 changes from the ground voltage to the power supply voltage is the power supply voltage. The voltage changes from 0 "(ground voltage) to the logical value" 1 "(power supply voltage). That is, the logical value held in the holding unit 700 becomes the logical value "1" (power supply voltage) after the determination timing in which the determination time TJ has elapsed from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Be maintained.

The logical value of the boundary cell 420c (BC420c) on the receiver side is "0" even when the voltage VH test signal is transmitted from the boundary cell 420a on the driver side because the terminal 300r is short-circuited to the ground voltage. It is maintained at (ground voltage). Hereinafter, among the short-circuit failures, a short-circuit failure in which the signal path is short-circuited to the ground voltage is also referred to as a “0” fixed short-circuit failure.

Next, the voltage waveform when a short-circuit failure occurs on the driver side will be described. A detailed description will be omitted for the same or similar voltage waveform as when a short failure occurs on the receiver side.

The output of the boundary cell 420a (BC420a), the output of the pulse generation unit 440, and the output of the delay unit 600 are the same as or the same as when a short failure occurs on the receiver side.

The input of the signal comparison unit 520, that is, the propagation signal changes from the ground voltage to the voltage VH at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the input of the signal comparison unit 520 is changed from the voltage VH to the ground voltage by the propagation signal from the terminal 300d on the driver side short-circuited to the ground voltage at the time when the time Tpb elapses from the time when the voltage VH is changed from the ground voltage. Change.

When the change in the output of the boundary cell 420a is used as a reference, the input of the signal comparison unit 520 is from the voltage VH at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. It changes to the ground voltage. Then, the input of the signal comparison unit 520 is maintained at the ground voltage after changing from the voltage VH to the ground voltage.

The output of the signal comparison unit 520, that is, the comparison signal changes from the ground voltage to the power supply voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the signal comparison unit 520 changes from the power supply voltage to the ground voltage at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Further, the output of the signal comparison unit 520 is maintained at the ground voltage after changing from the power supply voltage to the ground voltage.

The logical value held by the holding unit 700 is the logical value in the initial state because the output of the signal comparison unit 520 at the time (determination timing) when the output of the delay unit 600 changes from the ground voltage to the power supply voltage is the ground voltage. It is maintained at 0 ”(ground voltage).

The logical value of the boundary cell 420c (BC420c) on the receiver side is "0" even when the voltage VH test signal is transmitted from the boundary cell 420a on the driver side because the terminal 300d is short-circuited to the ground voltage. It is maintained at (ground voltage).

In this way, when a short-circuit failure fixed at "0" occurs on the receiver side, the holding unit 700 captures and holds a comparison signal having a logical value of "1", and a short-circuit failure fixed at "0" occurs on the driver side. If so, the comparison signal with the logical value "0" is taken in and held.

When a short-circuit failure occurs in which the signal path is short-circuited to the power supply voltage, the boundary cell 420a (BC420a) outputs a test signal having the opposite polarity to the test signal shown in FIG. 4 to the output buffer 430. In this case, as shown in FIG. 9, the output of the boundary cell 420a, the input of the signal comparison unit 520, the output of the signal comparison unit 520, the logical value held in the holding unit 700, and the logical value of the boundary cell 420c on the receiver side are , The polarity is opposite to the example shown in FIG. For example, in a short-circuit failure in which the signal path is short-circuited to the power supply voltage, the logical value of the boundary cell 420c (BC420c) on the receiver side is the logical value even when the test signal of the voltage VH is transmitted from the boundary cell 420a on the driver side. It is maintained at 1 ”(power supply voltage). Hereinafter, among the short-circuit failures, the short-circuit failure in which the signal path is short-circuited to the power supply voltage is also referred to as a “1” fixed short-circuit failure.

FIG. 5 shows an example of the test method of the electronic device 100 shown in FIG. The test shown in FIG. 5 is, for example, a test for detecting a failure of the signal path between the semiconductor devices 200A and 200B shown in FIG. 2, and is executed based on the control from the test device 1000 for testing the electronic device 100. Will be done.

In step S100, the test device 1000 selects the signal path to be tested from the signal paths between the semiconductor devices 200A and 200B. As a result, the terminal 300d to be tested is selected.

Next, in step S110, the test apparatus 1000 outputs a test signal having a logical value of “1” (power supply voltage) from the boundary cell 420 on the driver side to the receiver side using the signal path selected in step S100. For example, the test apparatus 1000 sets the logical value “1” in the boundary cell 420a corresponding to the terminal 300d to be tested selected in step S100 by scanning the boundary cell 420.

As a result, for example, the boundary cell 420a corresponding to the test target terminal 300d selected in step S100 transmits the test signal of the logical value “1” from the test target terminal 300d to the receiver side terminal via the output buffer 430. Output to 300r. For example, the initial values of all boundary cells 420 are set to logical values "0" (ground voltage) before the processing of step S110 is executed.

Next, in step S120, the test apparatus 1000 reads the logical value of the boundary cell 420 on the receiver side of the signal path selected in step S100. For example, the test apparatus 1000 reads the logical value of the boundary cell 420 by scanning the boundary cell 420.

Next, in step S130, the test apparatus 1000 determines whether or not the logical value (hereinafter, also referred to as a reading value) read from the boundary cell 420 on the receiver side in step S120 is the logical value “1”. When the reading value is the logical value “1”, the operation of the test apparatus 1000 proceeds to step S140. On the other hand, when the reading value is not the logical value "1", that is, when the reading value is the logical value "0", the test apparatus 1000 determines that the signal path selected in step S100 has a failure. The operation is moved to step S170.

In step S140, the test apparatus 1000 outputs a test signal having a logic value of “0” from the boundary cell 420 on the driver side to the receiver side using the signal path selected in step S100. For example, the test apparatus 1000 sets the initial values of all the boundary cells 420 to the logical value "1" by scanning the boundary cells 420. Then, the test apparatus 1000 sets the logical value “0” in the boundary cell 420a corresponding to the terminal 300d to be tested selected in step S100 by scanning the boundary cell 420. As a result, for example, the boundary cell 420a corresponding to the test target terminal 300d selected in step S100 transmits the test signal of the logical value “0” from the test target terminal 300d to the receiver side terminal via the output buffer 430. Output to 300r.

Next, in step S150, the test apparatus 1000 reads the logical value of the boundary cell 420 on the receiver side of the signal path selected in step S100. For example, the test apparatus 1000 reads the logical value of the boundary cell 420 by scanning the boundary cell 420.

Next, in step S160, the test apparatus 1000 determines whether or not the logical value (reading value) read from the boundary cell 420 on the receiver side in step S150 is the logical value “0”. When the reading value is the logical value “0”, the operation of the test apparatus 1000 proceeds to step S180. On the other hand, when the read value is not the logical value "0", that is, when the read value is the logical value "1", the test apparatus 1000 causes a short failure of "1" fixed in the signal path selected in step S100. It is determined that the operation is performed, and the operation is moved to step S170.

In step S170, the test apparatus 1000 determines the type of failure that occurred in the signal path selected in step S100, associates the determined failure type with the signal path, and registers it in the defective net list. The defective netlist is stored in, for example, a storage device such as a memory accessible to the test device 1000, or a storage device such as a memory built in the test device 1000. The method for determining whether the type of failure is an open failure or a short failure is not particularly limited. After the process of step S170 is executed, the operation of the test apparatus 1000 shifts to step S180.

In step S180, the test device 1000 determines whether or not the test has been completed for all the signal paths of the failure detection targets among the signal paths between the semiconductor devices 200A and 200B. When the test is completed for all the signal paths, the operation of the test apparatus 1000 proceeds to step S190. On the other hand, if there is a signal path for which the test has not been completed, the operation of the test apparatus 1000 returns to step S100.

In step S190, the test apparatus 1000 determines whether the defective netlist is empty. The defective netlist is in an empty state (initial state) because the process of step S170 is not executed when the signal path determined to have failed does not exist. If the bad netlist is empty, the operation of the test apparatus 1000 proceeds to step S200. On the other hand, when the defective netlist is not empty, that is, when the signal path in which the failure has occurred is registered in the defective netlist, the operation of the test apparatus 1000 proceeds to step S300.

In step S200, the test device 1000 determines that the electronic device 100 is a non-defective product, and ends the test for detecting the failure of the signal path between the semiconductor devices 200A and 200B.

In step S300, the test device 1000 determines the location of the failure. For example, the test apparatus 1000 executes the test shown in FIG. 6 to determine whether the location where the failure occurs is the receiver side or the driver side. The electronic device 100 is repaired based on the determination result of the location where the failure occurs. For example, if the location where the failure occurs is the terminal 300 on the receiver side, the connection failure of the terminal 300 on the receiver side is repaired, and when the location where the failure occurs is the terminal 300 on the driver side, the connection of the terminal 300 on the driver side Defects etc. are repaired. When the process of step S300 is completed, the test for detecting the failure of the signal path between the semiconductor devices 200A and 200B is completed.

The test method of the electronic device 100 is not limited to the example shown in FIG. For example, the determination of the type of failure in the process of step S170 may be executed when the process of step S300 for determining the location where the failure occurs is executed. In this case, in step S170, information indicating whether or not the short failure is fixed at “1” is registered in the defective net list in association with the signal path.

FIG. 6 shows an example of a method for determining a failure occurrence location of the electronic device 100 shown in FIG. The test shown in FIG. 6 is the process of step S300 shown in FIG. 5, and is executed based on the control from the test device 1000 that tests the electronic device 100. Further, the test shown in FIG. 6 is executed for each signal path registered in the defective netlist in step S170 shown in FIG. The series of processes from step S320 to step S328 is the process of determining the occurrence location of the "0" fixed short failure, and the series of processes from step S330 to step S338 is the process of determining the occurrence of the "1" fixed short failure. This is a process for determining a location. Further, the series of processes from step S340 to step S348 is a process of determining the occurrence location of the open failure.

In step S310, the test apparatus 1000 determines whether or not the type of failure of the signal path to be tested is a short failure based on the defective netlist. When the type of failure of the signal path is a short failure, the operation of the test apparatus 1000 shifts to step S312. On the other hand, when the type of failure of the signal path is not a short failure, that is, when the type of failure of the signal path is an open failure, the operation of the test apparatus 1000 shifts to step S340.

In step S312, the test apparatus 1000 determines whether or not the short-circuit failure of the signal path is a short-circuit failure fixed at “0” based on the defective netlist. When the short-circuit failure of the signal path is a short-circuit failure fixed at "0", the operation of the test device 1000 shifts to step S320. On the other hand, when the short-circuit failure of the signal path is not a short-circuit failure fixed at "0", that is, when the short-circuit failure of the signal path is a short-circuit failure fixed at "1", the operation of the test apparatus 1000 shifts to step S330.

In step S320, the test apparatus 1000 sets the threshold value VTH to be compared with the propagated signal propagated to the signal comparison unit 520 to the threshold value VTH 1 associated with the short failure. For example, the test apparatus 1000 transmits the type information indicating that the type of failure generated in the signal path is a short failure to the threshold value selection unit 510, and sets the threshold value VTH 1 as the threshold value VTH to be compared with the propagated signal from the threshold value selection unit 510. Output to the signal comparison unit 520.

That is, when the type information received from the test apparatus 1000 indicates a short failure, the threshold selection unit 510 propagates the threshold VTH1 out of the threshold VTH1 associated with the short failure and the threshold VTH2 associated with the open failure. Select as the threshold VTH to compare with the signal. As a result, the voltage of one of the two inputs of the signal comparison unit 520 is set to the threshold value VTH1. After the process of step S320 is executed, the operation of the test apparatus 1000 shifts to step S322.

In step S322, the test apparatus 1000 changes the output of the boundary cell 420 on the driver side corresponding to the signal path to be tested from the logical value “0” to the logical value “1”. That is, the test apparatus 1000 changes the logical value of the test signal from the logical value “0” to the logical value “1”.

For example, the test apparatus 1000 sets the initial values of all the boundary cells 420 to the logical value "0" by scanning the boundary cells 420. Then, the test apparatus 1000 sets the logical value "1" in the boundary cell 420a corresponding to the terminal 300d to be tested by scanning the boundary cell 420.

As a result, for example, the test signal output from the boundary cell 420a corresponding to the terminal 300d to be tested changes from the logical value “0” to the logical value “1”. That is, the boundary cell 420a corresponding to the terminal 300d to be tested outputs a test signal having a logical value “1” from the terminal 300d to be tested to the receiver side in accordance with the control from the test apparatus 1000.

Further, as the output of the boundary cell 420a changes from the logical value “0” to the logical value “1”, the pulse generation unit 440 generates a pulse synchronized with the rising edge of the test signal as described with reference to FIG. Output to the delay unit 600. After the process of step S322 is executed, the operation of the test apparatus 1000 shifts to step S324.

In step S324, the test apparatus 1000 determines whether or not the determination time TJ has elapsed after changing the logical value of the test signal from the logical value “0” to the logical value “1”. If the determination time TJ has not elapsed, the operation of the test apparatus 1000 returns to step S324. That is, the test apparatus 1000 waits for the process of step S326 until the holding unit 700 captures the comparison signal at the determination timing corresponding to the determination time TJ.

For example, the holding unit 700 receives a pulse from the delay unit 600 at the determination timing at which the determination time TJ has elapsed from the time when the test signal changes from the logical value “0” to the logical value “1”. Then, the holding unit 700 takes in and holds a comparison signal indicating the magnitude relationship between the threshold value VTH1 and the propagation signal from the signal comparison unit 520 in synchronization with the pulse received from the delay unit 600.

Then, after the holding unit 700 takes in and holds the comparison signal at the determination timing, the operation of the test apparatus 1000 shifts to step S326. That is, when the determination time TJ has elapsed, the operation of the test apparatus 1000 shifts to step S326.

In step S326, the test apparatus 1000 reads the logical value of the comparison signal held in the holding unit 700. For example, the test apparatus 1000 writes the logical value of the comparison signal held in the holding unit 700 in the boundary cell 420b. Then, the test apparatus 1000 reads the logical value of the boundary cell 420b by scanning the boundary cell 420. In this way, the test apparatus 1000 reads the logical value of the comparison signal taken into the holding unit 700 at the determination timing from the holding unit 700.

Next, in step S328, the test apparatus 1000 determines whether or not the logical value (reading value) read from the holding unit 700 in step S326 is the logical value “1”. When the reading value is the logical value "1", the test apparatus 1000 determines in step S350 that the location where the failure has occurred is on the receiver side, and ends the test for determining the location where the failure has occurred. On the other hand, when the reading value is not the logical value "1", that is, when the reading value is the logical value "0", the test apparatus 1000 determines in step S352 that the location where the failure occurs is the driver side, and the failure occurs. Complete the test to determine the location. In this way, the test apparatus 1000 determines the location where the failure occurs based on the logical value of the comparison signal read from the holding unit 700.

In step S330, the test apparatus 1000 sets the threshold value VTH to be compared with the propagated signal propagated to the signal comparison unit 520 to the threshold value VTH 1 associated with the short failure by the same or the same processing as in step S320.

Next, in step S332, the test apparatus 1000 changes the output of the boundary cell 420 on the driver side corresponding to the signal path to be tested from the logical value “1” to the logical value “0”. That is, the test apparatus 1000 changes the logical value of the test signal from the logical value “1” to the logical value “0”. The process of step S332 is the same as or similar to the process of step S322, except that the polarity of the test signal is opposite to that of step S322.

For example, the test apparatus 1000 sets the initial values of all the boundary cells 420 to the logical value "1" by scanning the boundary cells 420. Then, the test apparatus 1000 sets the logical value “0” in the boundary cell 420a corresponding to the terminal 300d to be tested by scanning the boundary cell 420.

As described above, the boundary cell 420a corresponding to the terminal 300d to be tested outputs a test signal having a logical value “0” from the terminal 300d to be tested to the receiver side in accordance with the control from the test apparatus 1000. Further, when the output of the boundary cell 420a changes from the logical value “1” to the logical value “0”, the pulse generation unit 440 outputs a pulse synchronized with the falling edge of the test signal to the delay unit 600.

Next, in step S334, the test apparatus 1000 determines whether or not the determination time TJ has elapsed after changing the logical value of the test signal from the logical value “1” to the logical value “0”. If the determination time TJ has not elapsed, the operation of the test apparatus 1000 returns to step S334. That is, the test apparatus 1000 waits for the process of step S336 until the holding unit 700 captures the comparison signal indicating the magnitude relationship between the threshold value VTH1 and the propagation signal at the determination timing corresponding to the determination time TJ.

On the other hand, when the determination time TJ has elapsed, the operation of the test apparatus 1000 shifts to step S336. That is, after the holding unit 700 takes in and holds the comparison signal indicating the magnitude relationship between the threshold value VTH1 and the propagation signal at the determination timing, the operation of the test apparatus 1000 shifts to step S336.

In step S336, the test apparatus 1000 reads the logical value of the comparison signal held in the holding unit 700 by the same or the same processing as in step S326.

Next, in step S338, the test apparatus 1000 determines whether or not the logical value (reading value) read from the holding unit 700 in step S336 is the logical value “1”. When the reading value is the logical value "1", the test apparatus 1000 determines in step S352 that the location where the failure has occurred is the driver side, and ends the test for determining the location where the failure has occurred. On the other hand, when the reading value is not the logical value "1", that is, when the reading value is the logical value "0", the test apparatus 1000 determines in step S350 that the location where the failure occurs is the receiver side, and the failure occurs. Complete the test to determine the location.

In step S340, the test apparatus 1000 sets the threshold value VTH to be compared with the propagated signal propagated to the signal comparison unit 520 to the threshold value VTH2 associated with the open failure. For example, the test apparatus 1000 transmits the type information indicating that the type of failure generated in the signal path is an open failure to the threshold value selection unit 510, and sets the threshold value VTH2 as the threshold value VTH to be compared with the propagated signal from the threshold value selection unit 510. Output to the signal comparison unit 520.

That is, when the type information received from the test apparatus 1000 indicates an open failure, the threshold selection unit 510 propagates the threshold VTH2 out of the threshold VTH1 associated with the open failure and the threshold VTH2 associated with the open failure. Select as the threshold VTH to compare with the signal. As a result, the voltage of one of the two inputs of the signal comparison unit 520 is set to the threshold value VTH2. After the process of step S340 is executed, the operation of the test apparatus 1000 shifts to step S342.

In step S342, the test apparatus 1000 changes the output of the boundary cell 420 on the driver side corresponding to the signal path to be tested from the logical value “0” to the logical value “1” by the same or the same processing as the processing in step S322. change. That is, the test apparatus 1000 changes the logical value of the test signal from the logical value “0” to the logical value “1”. As described in step S322, the boundary cell 420a corresponding to the terminal 300d to be tested sends a test signal having a logical value “0” from the terminal 300d to be tested to the receiver side in response to the control from the test apparatus 1000. Output. Further, the pulse generation unit 440 outputs a pulse synchronized with the rising edge of the test signal to the delay unit 600.

Next, in step S344, the test apparatus 1000 determines whether or not the determination time TJ has elapsed after changing the logical value of the test signal from the logical value “0” to the logical value “1”. If the determination time TJ has not elapsed, the operation of the test apparatus 1000 returns to step S344. That is, the test apparatus 1000 waits for the process of step S346 until the holding unit 700 captures the comparison signal indicating the magnitude relationship between the threshold value VTH2 and the propagation signal at the determination timing corresponding to the determination time TJ.

On the other hand, when the determination time TJ has elapsed, the operation of the test apparatus 1000 shifts to step S346. That is, after the holding unit 700 takes in and holds the comparison signal indicating the magnitude relationship between the threshold value VTH2 and the propagation signal at the determination timing, the operation of the test apparatus 1000 shifts to step S346.

In step S346, the test apparatus 1000 reads the logical value of the comparison signal held in the holding unit 700 by the same or the same processing as in step S326.

Next, in step S348, the test apparatus 1000 determines whether or not the logical value (reading value) read from the holding unit 700 in step S346 is the logical value "1". When the reading value is the logical value "1", the test apparatus 1000 determines in step S352 that the location where the failure has occurred is the driver side, and ends the test for determining the location where the failure has occurred. On the other hand, when the reading value is not the logical value "1", that is, when the reading value is the logical value "0", the test apparatus 1000 determines in step S350 that the location where the failure occurs is the receiver side, and the failure occurs. Complete the test to determine the location.

In this way, the test apparatus 1000 changes the logical value of the test signal in any one of steps S322, S332, and S342. For example, the boundary cell 420a included in the semiconductor device 200A of any of the plurality of semiconductor devices 200 outputs a test signal from the terminal 300d to be tested to the other semiconductor device 200B in any one of steps S322, S332, and S342. To do. As a result, the comparison unit 500 included in the semiconductor device 200A receives the propagation signal propagated to the terminal 300d to be tested.

Further, in any of steps S320, S330, and S340, the comparison unit 500 receives type information indicating the type of failure that has occurred in the signal path, and determines a threshold value VTH to be compared with the propagated signal in advance for each type of failure. Select from the threshold values VTH1 and VTH2 based on the type information. As described above, in any of steps S320, S330, and S340, the comparison unit 500 determines the threshold value VTH to be compared with the propagated signal in advance for each type of failure based on the type of failure that occurred in the signal path. Select from threshold values VTH1 and VTH2. Then, the comparison unit 500 compares the threshold value VTH according to the type of failure occurring in the signal path with the propagated signal, and generates a comparison signal indicating the comparison result. For example, the comparison unit 500 outputs a signal according to the magnitude relationship between the threshold value VTH selected based on the type information received from the test apparatus 1000 and the propagation signal to the holding unit 700 as a comparison signal.

As a result, the holding unit 700 of the semiconductor device 200A receives from the comparison unit 500 a comparison signal indicating the magnitude relationship between the threshold value VTH and the propagation signal. Then, the holding unit 700 determines the location where the failure has occurred by taking in the comparison signal at the determination timing determined based on the length L of the wiring 320 connecting the terminal 300d to be tested and the other semiconductor device 200B. A comparison signal is held as a signal to be used when performing.

Therefore, the test apparatus 1000 waits for the reading of the logical value of the comparison signal held by the holding unit 700 until the determination time TJ elapses after the logical value of the test signal is changed. As a result, the test apparatus 1000 reads the logical value of the comparison signal taken into the holding unit 700 at the determination timing from the holding unit 700 in any of steps S326, S336, and S346. Then, in steps S350, S352, and the like, the test apparatus 1000 determines the location where the failure has occurred based on the logical value of the comparison signal read from the holding unit 700.

The method for determining the location of failure is not limited to the example shown in FIG. For example, the test apparatus 1000 may determine whether it is an open failure or a “0” fixed short failure when determining the location of the failure. In this case, the test apparatus 1000 executes both a series of processes from step S320 to step S328 and a series of processes from step S340 to step S348, except for a short failure fixed at "1", for example. Then, the test apparatus 1000 may determine the type of failure and the location where the failure occurs based on the combination of the logical values read in the processes of steps S326 and S346, respectively.

As described above, even in the embodiments shown in FIGS. 2 to 6, the same effects as those in the embodiment shown in FIG. 1 can be obtained. For example, the pulse generation unit 440 of the semiconductor device 200A of the plurality of semiconductor devices 200A or 200B generates a pulse in synchronization with the timing at which the test signal is output from the boundary cell 420a (test signal output unit). To do. Then, the pulse generation unit 440 outputs the pulse generated in synchronization with the test signal to the delay unit 600 (timing adjustment unit) of the semiconductor device 200A. The delay unit 600 delays the pulse received from the pulse generation unit 440 by the determination time TJ (delay time) corresponding to the determination timing, and outputs the pulse to the holding unit 700. Then, the holding unit 700 takes in the comparison signal received from the comparison unit 500 in synchronization with the pulse received from the delay unit 600. For example, the test device 1000 reads the comparison signal captured in the holding unit 700 at a determination timing determined based on the wiring length L, so that the signal path between the plurality of semiconductor devices 200 is not executed without performing a visual inspection. It is possible to determine the location of the failure in.

FIG. 7 shows another embodiment of a semiconductor device, an electronic device, and a test method for the electronic device. Elements that are the same as or similar to the elements described with reference to FIGS. 1 to 6 are designated by the same or similar reference numerals, and detailed description thereof will be omitted. The electronic device 102 shown in FIG. 7 is the same as the electronic device 100 shown in FIG. 2 except that the semiconductor device 202 (202A, 202B) is provided instead of the semiconductor device 200 (200A, 200B) shown in FIG. Or similar. For example, the electronic device 102 is an information processing device such as a server, and has a plurality of semiconductor devices 202 (202A, 202B) corresponding to JTAG. Then, when testing the electronic device 102, the electronic device 102 is connected to the test device 1000 via terminals TCK, TMS, TRST, TDI, and TDO.

The semiconductor device 202 (202A, 202B) has a test circuit 402 (402A, 402B) instead of the test circuit 400 (400A, 400B) shown in FIG. Further, in the semiconductor device 202, the pulse generation unit 440 shown in FIG. 2 is omitted from the semiconductor device 200. Other configurations of the semiconductor device 202 are the same as or similar to those of the semiconductor device 200 shown in FIG. Note that, in FIG. 7, in order to make the figure easier to see, the description of the logic circuit or the like that realizes the original function of the semiconductor device 202 is omitted as in FIG.

The semiconductor devices 202A and 202B are mounted on a printed circuit board, for example, and are connected to each other by a printed wiring 320 arranged on the printed circuit board. For example, one of the plurality of terminals 300d of the semiconductor device 202A is connected to one of the plurality of terminals 300r of the semiconductor device 202B by the printed wiring 320 having a wiring length L. The configuration of the test block used for testing the poor connection between the semiconductor devices 202A and 202B is the same as or similar to that of the semiconductor devices 202A and 202B. Therefore, FIG. 7 describes the semiconductor device 202A.

The semiconductor device 202A includes a test circuit 402A, a comparison unit 500, a delay unit 600, and a holding unit 700. The test circuit 402A is the same as or similar to the test circuit 400A shown in FIG. 2, except that it has a TAP controller 412 instead of the TAP controller 410 shown in FIG. For example, the test circuit 402A is a boundary scan circuit defined by IEEE 1149.1 and has a TAP controller 412, a boundary cell 420 and an output buffer 430.

The TAP controller 412 is the same as or similar to the TAP controller 410 shown in FIG. 2, except that the signal UpdataDR is output to the delay unit 600 as a pulse. The signal UpdataDR can be found in Fig. IEEE1149.1-2013. It is UpdataDR described in 6.5 (TAP controller implementation-state registers and output logic). The TAP controller 412 outputs the signal Updata DR to the delay unit 600 in synchronization with the state transition to the Updata-DR state. That is, the TAP controller 412 outputs the signal UpdataDR (pulse) to the delay unit 600 in synchronization with the timing when the test signal is output from the boundary cell 420a.

The boundary cell 420 (420a, 420b) and the output buffer 430 are the same as or similar to the boundary cell 420 (420a, 420b) and the output buffer 430 shown in FIG. For example, the boundary cell 420b captures and holds a comparison signal received from the holding unit 700 when the state of the TAP controller 412 transitions to the Capture-DR state. For example, the state of the TAP controller 412 transitions to the Capture-DR state after 2.5 cycles of the signal TCK, which is the test clock, after the boundary cell 420a outputs the test signal to the output buffer 430 in the Updata-DR state. Hereinafter, the signal TCK is also referred to as a test clock TCK.

The comparison unit 500, the delay unit 600, and the holding unit 700 are the same as or similar to the comparison unit 500, the delay unit 600, and the holding unit 700 shown in FIG. The delay unit 600 shown in FIG. 7 receives the signal UpdataDR from the TAP controller 412 instead of the pulse generated by the pulse generation unit 440 shown in FIG. Boundary cells 420a and 420b, an output buffer 430, a comparison unit 500, a delay unit 600, and a holding unit 700 are provided, for example, for each terminal 300d to be tested.

The test method of the electronic device 102 and the method of determining the location where the failure of the electronic device 102 occurs are the same as or the same as the test method shown in FIG. 5 and the determination method shown in FIG. For example, in FIG. 6, the method of determining the location where a failure occurs in the electronic device 102 is as follows by replacing the electronic device 100, the semiconductor device 200, the pulse generator 440, etc. with the electronic device 102, the semiconductor device 202, the TAP controller 412, etc. Explained.

The configurations of the electronic device 102 and the semiconductor device 202 are not limited to the example shown in FIG. 7. For example, the number of semiconductor devices 202 included in the electronic device 102 is not limited to two. Further, for example, when the transition time from the Updata-DR state to the Capture-DR state of the TAP controller 412 is greater than the time Td and less than the time Tr, the delay unit 600 and the holding unit 700 may be omitted. .. That is, when the 2.5 cycle of the test clock TCK is larger than the time Td and less than the time Tr, the delay unit 600 and the holding unit 700 may be omitted.

FIG. 8 shows an example of voltage waveforms on the driver side and the receiver side when an open failure occurs. Note that FIG. 8 shows an example of a voltage waveform when a pull-down resistor connected to the ground wire is connected to the terminal 300r on the receiver side. A detailed description of the voltage waveform that is the same as or similar to the voltage waveform described in FIG. 3 will be omitted.

The output voltage waveform of the boundary cell 420a (BC420a), the input voltage waveform of the signal comparison unit 520, and the output voltage waveform of the signal comparison unit 520 are the same as or similar to the respective voltage waveforms described with reference to FIG.

The voltage waveform of the signal UpdataDR is the same as or similar to the voltage waveform of the output of the pulse generator 440 described with reference to FIG. For example, the voltage of the signal UpdataDR changes from the ground voltage to the power supply voltage at the same time or almost the same time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the voltage of the signal UpdataDR changes from the power supply voltage to the ground voltage after 0.5 cycles of the test clock TCK from the time when the ground voltage changes to the power supply voltage. That is, the signal UpdataDR is output from the TAP controller 412 to the delay unit 600 in synchronization with the output of the boundary cell 420a.

The voltage waveform of the output of the delay unit 600 is the same as or similar to the voltage waveform of the output of the delay unit 600 described with reference to FIG. Further, the logical value held in the holding unit 700 and the logical value of the boundary cell 420c (BC420c) on the receiver side are the logical value held in the holding unit 700 and the boundary cell 420c (BC420c) on the receiver side described with reference to FIG. Is or is the same as the logical value of.

FIG. 9 shows an example of voltage waveforms on the driver side and the receiver side when a short-circuit failure occurs. Note that FIG. 9 shows an example of a voltage waveform when one of the terminals 300d and 300r is short-circuited to the power supply voltage. Detailed description will be omitted for voltage waveforms that are the same as or similar to the voltage waveforms described in FIGS. 3, 4, and 8. For example, the output of the signal UpdataDR and the delay unit 600 is the same as or similar to the case where the open failure described with reference to FIG. 8 occurs.

First, the voltage waveform when a short-circuit failure occurs on the receiver side will be described.

The output of the boundary cell 420a (BC420a) changes from the voltage VH to the ground voltage when the test signal of the ground voltage is output from the boundary cell 420a. Then, the output of the boundary cell 420a is maintained at the ground voltage. As described above, when a short-circuit failure occurs in which the signal path is short-circuited to the power supply voltage, the boundary cell 420a (BC420a) outputs a test signal having the opposite polarity to the test signal shown in FIG. 4 to the output buffer 430.

The input of the signal comparison unit 520, that is, the propagation signal changes from the voltage VH to the ground voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Then, the input of the signal comparison unit 520 is changed from the ground voltage to the voltage VH by the propagation signal from the terminal 300r on the receiver side short-circuited to the power supply voltage at the time when the time Tlpp elapses from the time when the voltage VH changes to the ground voltage. Change.

When the change in the output of the boundary cell 420a is used as a reference, the input of the signal comparison unit 520 is from the ground voltage at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. It changes to voltage VH. Then, the input of the signal comparison unit 520 is maintained at the voltage VH after changing from the ground voltage to the voltage VH.

The output of the signal comparison unit 520, that is, the comparison signal is maintained at the ground voltage during the period when the voltage of the propagate signal is less than the threshold VTH1, and is maintained at the power supply voltage during the period when the voltage of the propagation signal exceeds the threshold VTH1. Therefore, the output of the signal comparison unit 520 changes from the power supply voltage to the ground voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Then, the output of the signal comparison unit 520 changes from the ground voltage to the power supply voltage at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Further, the output of the signal comparison unit 520 is maintained at the ground voltage after changing from the ground voltage to the power supply voltage.

The logical value held by the holding unit 700 is the logical value in the initial state because the output of the signal comparison unit 520 at the time (determination timing) when the output of the delay unit 600 changes from the ground voltage to the power supply voltage is the ground voltage. It is maintained at 0 ”(ground voltage).

The logical value of the boundary cell 420c (BC420c) on the receiver side is "1" even when the ground voltage test signal is transmitted from the boundary cell 420a on the driver side because the terminal 300r is short-circuited to the power supply voltage. It is maintained at (power supply voltage).

Next, the voltage waveform when a short-circuit failure occurs on the driver side will be described. A detailed description will be omitted for the same or similar voltage waveform as when a short failure occurs on the receiver side.

The output of the boundary cell 420a (BC420a), the signal UpdataDR, the output of the delay unit 600, and the logical value of the boundary cell 420c (BC420c) on the receiver side are the same as or the same as when a short failure occurs on the receiver side.

The input of the signal comparison unit 520, that is, the propagation signal changes from the voltage VH to the ground voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Then, the input of the signal comparison unit 520 is changed from the ground voltage to the voltage VH by the propagation signal from the terminal 300d on the driver side short-circuited to the power supply voltage at the time when the time Tpb elapses from the time when the voltage VH changes to the ground voltage. Change.

When the change in the output of the boundary cell 420a is used as a reference, the input of the signal comparison unit 520 is from the ground voltage at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. It changes to voltage VH. Then, the input of the signal comparison unit 520 is maintained at the voltage VH after changing from the ground voltage to the voltage VH.

The output of the signal comparison unit 520 changes from the power supply voltage to the ground voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Then, the output of the signal comparison unit 520 changes from the ground voltage to the power supply voltage at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Further, the output of the signal comparison unit 520 is maintained at the power supply voltage after changing from the ground voltage to the power supply voltage.

The logical value held in the holding unit 700 is the logical value in the initial state because the output of the signal comparison unit 520 at the time (determination timing) when the output of the delay unit 600 changes from the ground voltage to the power supply voltage is the power supply voltage. The voltage changes from 0 "(ground voltage) to the logical value" 1 "(power supply voltage). That is, the logical value held in the holding unit 700 becomes the logical value "1" (power supply voltage) after the determination timing in which the determination time TJ has elapsed from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Be maintained.

In this way, when a short-circuit failure fixed at "1" occurs on the receiver side, the holding unit 700 captures and holds a comparison signal having a logical value of "0", and a short-circuit failure fixed at "1" occurs on the driver side. If so, the comparison signal with the logical value "1" is taken in and held.

When a short-circuit failure occurs in which the signal path is short-circuited to the ground voltage, the output of the boundary cell 420a, the input and output of the signal comparison unit 520, the logical value held by the holding unit 700, and the like are shown in FIG. Same as or similar to the example.

As described above, even in the embodiments shown in FIGS. 7 to 9, the same effects as those in the embodiments shown in FIGS. 2 to 6 can be obtained. For example, the TAP controller 412 outputs the signal UpdataDR to the delay unit 600 in synchronization with the timing when the test signal is output from the boundary cell 420a. The delay unit 600 delays the signal UpdataDR received from the TAP controller 412 by the determination time TJ corresponding to the determination timing, and outputs the signal to the holding unit 700. Then, the holding unit 700 takes in the comparison signal received from the comparison unit 500 in synchronization with the pulse (signal UpdataDR delayed by the determination time TJ) received from the delay unit 600. For example, the test device 1000 reads the comparison signal captured in the holding unit 700 at the determination timing determined based on the wiring length L, so that the signal path between the plurality of semiconductor devices 202 is not executed without performing the visual inspection. It is possible to determine the location of the failure in.

Further, in the semiconductor device 202, in order to control the timing of capturing the comparison signal by the holding unit 700 by using the pulse obtained by delaying the signal UpdataDR generated by the TAP controller 412, as compared with the case where the pulse generating unit 440 is provided. , The circuit scale can be reduced.

FIG. 10 shows another embodiment of a semiconductor device, an electronic device, and a test method for the electronic device. Elements that are the same as or similar to the elements described with reference to FIGS. 1 to 9 are designated by the same or similar reference numerals, and detailed description thereof will be omitted. The electronic device 104 shown in FIG. 10 is the same as the electronic device 100 shown in FIG. 2 except that the semiconductor device 204 (204A, 204B) is provided instead of the semiconductor device 200 (200A, 200B) shown in FIG. Or similar. For example, the electronic device 104 is an information processing device such as a server, and has a plurality of semiconductor devices 204 (204A, 204B) corresponding to JTAG. Then, when testing the electronic device 104, the electronic device 104 is connected to the test device 1000 via terminals TCK, TMS, TRST, TDI, and TDO.

The semiconductor device 204 (204A, 204B) is the same as or similar to the semiconductor device 200 shown in FIG. 2, except that it has a comparison unit 502 instead of the comparison unit 500 shown in FIG. Note that, in FIG. 10, in order to make the figure easier to see, the description of the logic circuit or the like that realizes the original function of the semiconductor device 204 is omitted as in FIG.

The semiconductor devices 204A and 204B are mounted on a printed circuit board, for example, and are connected to each other by a printed wiring 320 arranged on the printed circuit board. For example, one of the plurality of terminals 300d of the semiconductor device 204A is connected to one of the plurality of terminals 300r of the semiconductor device 204B by the printed wiring 320 having a wiring length L. The configuration of the test block used for testing the poor connection between the semiconductor devices 204A and 204B is the same as or similar to that of the semiconductor devices 204A and 204B. Therefore, in FIG. 10, the semiconductor device 204A will be described.

The semiconductor device 204A includes a test circuit 400A, a pulse generation unit 440, a comparison unit 502, a delay unit 600, and a holding unit 700. The test circuit 400A, the pulse generation unit 440, the delay unit 600, and the holding unit 700 are the same as or similar to the test circuit 400A, the pulse generating unit 440, the delay unit 600, and the holding unit 700 shown in FIG.

The comparison unit 502 is connected to the terminal 300d to be tested and receives a propagation signal propagated to the terminal 300d to be tested. Then, the comparison unit 502 generates a comparison signal showing the comparison result between the threshold value VTH and the propagation signal according to the type of failure that occurred in the signal path between the semiconductor devices 204A and 204B. For example, the comparison unit 502 includes a signal comparison unit 522, an inverter 530, and a Noah circuit 540.

The signal comparison unit 522 is an example of a first signal generation unit that generates a first comparison signal according to the magnitude relationship between the threshold value VTH2 associated with the open failure and the propagation signal. For example, the signal comparison unit 522 generates a first comparison signal indicating true when the propagation signal propagated to the terminal 300d to be tested is larger than the threshold value VTH2 associated with the open failure, and the propagation signal is from the threshold value VTH2. Generates a first comparison signal that indicates false when small. Then, the signal comparison unit 522 outputs the first comparison signal indicating the magnitude relationship between the threshold value VTH2 and the propagation signal to the Noah circuit 540. Here, for example, the first comparison signal indicating true is a signal having a logical value “1” (power supply voltage), and the first comparison signal indicating false is a signal having a logical value “0” (ground voltage). ..

The inverter 530 is an example of a second signal generation unit that generates a second comparison signal according to the magnitude relationship between the threshold value VTH1 associated with the short failure and the propagation signal. For example, the inverter 530 outputs a signal obtained by inverting the propagation signal propagated to the terminal 300d to be tested to the Noah circuit 540 as a second comparison signal. The threshold value of the inverter 530 is, for example, the threshold value VTH1 associated with a short failure. Therefore, the inverter 530 generates a second comparison signal indicating false when the propagation signal is larger than the threshold value VTH1 associated with the short failure, and produces a second comparison signal indicating true when the propagation signal is smaller than the threshold value VTH1. Generate. For example, the second comparison signal indicating true is a signal having a logic value of "1" (power supply voltage), and the second comparison signal indicating false is a signal having a logic value of "0" (ground voltage).

The Noah circuit 540 is an example of a comparison signal generation unit that generates a comparison signal based on the first comparison signal and the second comparison signal and outputs the generated comparison signal to the holding unit 700. For example, the Noah circuit 540 calculates the NOR of the first comparison signal and the second comparison signal, and outputs the calculation result to the holding unit 700 as a comparison signal.

As a result, for example, when the voltage of the propagation signal is less than the threshold value VTH1 or the voltage of the propagation signal is larger than the threshold value VTH2, the Noah circuit 540 outputs a signal having a logic value “0” to the holding unit 700 as a comparison signal. To do. Further, when the voltage of the propagation signal is larger than the threshold value VTH1 and less than the threshold value VTH2, the Noah circuit 540 outputs a signal having a logic value “1” to the holding unit 700 as a comparison signal. As described above, the comparison unit 502 does not execute the process of switching the threshold value VTH according to the type of failure occurring in the signal path, and the comparison signal showing the magnitude relationship between the threshold value VTH and the propagation signal according to the type of failure. Can be generated.

The boundary cells 420a and 420b, the output buffer 430, the pulse generation unit 440, the comparison unit 502, the delay unit 600, and the holding unit 700 are provided, for example, for each terminal 300d to be tested. Further, the configurations of the electronic device 104 and the semiconductor device 204 are not limited to the example shown in FIG. For example, the number of semiconductor devices 204 included in the electronic device 104 is not limited to two. Further, the semiconductor device 204 has the test circuit 402A shown in FIG. 7 instead of the test circuit 400A, and the pulse generation unit 440 may be omitted. That is, the semiconductor device 202 shown in FIG. 7 may have a comparison unit 502 instead of the comparison unit 500.

FIG. 11 shows an example of the voltage waveform on the driver side when an open failure occurs. Detailed description of the voltage waveforms that are the same as or similar to the voltage waveforms described with reference to FIGS. 3, 4, 8 and 9 will be omitted. For example, the output of the boundary cell 420a (BC420a), the output of the pulse generation unit 440, and the output of the delay unit 600 are the same as or similar to the case where the open failure described with reference to FIG. 3 occurs.

First, the voltage waveform when an open failure occurs on the receiver side will be described.

The voltage waveform of the input of the signal comparison unit 522 and the inverter 530, that is, the propagation signal is the same as or similar to the voltage waveform of the input of the signal comparison unit 520 described with reference to FIG. For example, the inputs of the signal comparison unit 522 and the inverter 530 change from the ground voltage to the voltage VH at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the input of the signal comparison unit 522 and the inverter 530 changes from the voltage VH to twice the voltage VH at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. ..

The output of the signal comparison unit 522, that is, the first comparison signal is maintained at the ground voltage during the period when the voltage of the propagate signal is less than the threshold VTH2, and is maintained at the power supply voltage during the period when the voltage of the propagation signal exceeds the threshold VTH2. Therefore, the voltage waveform of the output of the signal comparison unit 522 is the same as or similar to the voltage waveform of the output of the signal comparison unit 520 described with reference to FIG. For example, the output of the signal comparison unit 522 changes from the ground voltage to the power supply voltage at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the signal comparison unit 522 is maintained at the power supply voltage after changing from the ground voltage to the power supply voltage. That is, the output of the signal comparison unit 522 is maintained at the power supply voltage after the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH.

The output of the inverter 530, that is, the second comparison signal, is maintained at the power supply voltage during the period when the voltage of the propagate signal is less than the threshold value VTH1, and is maintained at the ground voltage during the period when the voltage of the propagation signal exceeds the threshold value VTH1. Therefore, the output of the inverter 530 changes from the power supply voltage to the ground voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the inverter 530 is maintained at the ground voltage after changing from the power supply voltage to the ground voltage.

The output of the Noah circuit 540 changes from the ground voltage to the power supply voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the Noah circuit 540 changes from the power supply voltage to the ground voltage at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Further, the output of the Noah circuit 540 is maintained at the ground voltage after changing from the power supply voltage to the ground voltage.

The logical value held in the holding unit 700 is the logical value "0" in the initial state because the output of the Noah circuit 540 at the time (determination timing) when the output of the delay unit 600 changes from the ground voltage to the power supply voltage is the power supply voltage. "(Ground voltage) changes to the logical value" 1 "(power supply voltage). That is, the logical value held in the holding unit 700 becomes the logical value "1" (power supply voltage) after the determination timing in which the determination time TJ has elapsed from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Be maintained.

Next, the voltage waveform when an open failure occurs on the driver side will be described. A detailed description will be omitted for the same or similar voltage waveform as when an open failure occurs on the receiver side.

The output of the boundary cell 420a (BC420a), the output of the pulse generation unit 440, and the output of the delay unit 600 are the same as or the same as when an open failure occurs on the receiver side.

The voltage waveform of the input of the signal comparison unit 522 and the inverter 530, that is, the propagation signal is the same as or similar to the voltage waveform of the input of the signal comparison unit 520 described with reference to FIG. For example, the inputs of the signal comparison unit 522 and the inverter 530 change from the ground voltage to the voltage VH at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the input of the signal comparison unit 522 and the inverter 530 changes from the voltage VH to twice the voltage VH at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. ..

The output of the signal comparison unit 522, that is, the voltage waveform of the first comparison signal is the same as or similar to the voltage waveform of the output of the signal comparison unit 520 described with reference to FIG. For example, the output of the signal comparison unit 522 changes from the ground voltage to the power supply voltage at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the signal comparison unit 522 is maintained at the power supply voltage after changing from the ground voltage to the power supply voltage. That is, the output of the signal comparison unit 522 is maintained at the power supply voltage after the time Td has elapsed from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH.

The output of the inverter 530, that is, the second comparison signal is the same as or similar to the case where an open failure occurs on the receiver side. For example, the output of the inverter 530 changes from the power supply voltage to the ground voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH.

The output of the Noah circuit 540 changes from the ground voltage to the power supply voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the Noah circuit 540 changes from the power supply voltage to the ground voltage at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Further, the output of the Noah circuit 540 is maintained at the ground voltage after changing from the power supply voltage to the ground voltage.

The logical value held in the holding unit 700 is the logical value "0" in the initial state because the output of the Noah circuit 540 at the time (determination timing) when the output of the delay unit 600 changes from the ground voltage to the power supply voltage is the ground voltage. "(Ground voltage) is maintained.

In this way, the holding unit 700 captures and holds the comparison signal of the logical value "1" when an open failure occurs on the receiver side, and compares the logical value "0" when the open failure occurs on the driver side. Capture and hold the signal.

FIG. 12 shows an example of the voltage waveform on the driver side when a short-circuit failure occurs. Note that FIG. 12 shows an example of a voltage waveform when one of the terminals 300d and 300r is short-circuited to the ground voltage. Detailed description of the voltage waveforms that are the same as or similar to the voltage waveforms described with reference to FIGS. 3, 4, 8, 9, and 11 will be omitted. For example, the output of the boundary cell 420a (BC420a), the output of the pulse generation unit 440, and the output of the delay unit 600 are the same as or similar to the case where the open failure described with reference to FIG. 4 occurs.

First, the voltage waveform when a short-circuit failure occurs on the receiver side will be described.

The voltage waveform of the input of the signal comparison unit 522 and the inverter 530, that is, the propagation signal is the same as or similar to the voltage waveform of the input of the signal comparison unit 520 described with reference to FIG. For example, the inputs of the signal comparison unit 522 and the inverter 530 change from the ground voltage to the voltage VH at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the input of the signal comparison unit 522 and the inverter 530 changes from the voltage VH to the ground voltage at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH.

The output of the signal comparison unit 522, that is, the first comparison signal is maintained at the ground voltage because the input voltage of the signal comparison unit 522 is less than the threshold value VTH2.

The output of the inverter 530, that is, the second comparison signal, changes from the power supply voltage to the ground voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the inverter 530 changes from the ground voltage to the power supply voltage at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Further, the output of the inverter 530 is maintained at the power supply voltage after changing from the ground voltage to the power supply voltage.

The output of the Noah circuit 540 changes from the ground voltage to the power supply voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the Noah circuit 540 changes from the power supply voltage to the ground voltage at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Further, the output of the Noah circuit 540 is maintained at the ground voltage after changing from the power supply voltage to the ground voltage. In this way, the output of the Noah circuit 540 is the same as or similar to the case where an open failure occurs on the receiver side.

The logical value held in the holding unit 700 is the logical value "0" in the initial state because the output of the Noah circuit 540 at the time (determination timing) when the output of the delay unit 600 changes from the ground voltage to the power supply voltage is the power supply voltage. "(Ground voltage) changes to the logical value" 1 "(power supply voltage). That is, the logical value held in the holding unit 700 becomes the logical value "1" (power supply voltage) after the determination timing in which the determination time TJ has elapsed from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Be maintained.

Next, the voltage waveform when a short-circuit failure occurs on the driver side will be described. A detailed description will be omitted for the same or similar voltage waveform as when a short failure occurs on the receiver side.

The output of the boundary cell 420a (BC420a), the output of the pulse generation unit 440, and the output of the delay unit 600 are the same as or the same as when a short failure occurs on the receiver side.

The voltage waveform of the input of the signal comparison unit 522 and the inverter 530, that is, the propagation signal is the same as or similar to the voltage waveform of the input of the signal comparison unit 520 described with reference to FIG. For example, the inputs of the signal comparison unit 522 and the inverter 530 change from the ground voltage to the voltage VH at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the input of the signal comparison unit 522 and the inverter 530 changes from the voltage VH to the ground voltage at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH.

The output of the signal comparison unit 522, that is, the first comparison signal is maintained at the ground voltage because the input voltage of the signal comparison unit 522 is less than the threshold value VTH2.

The output of the inverter 530, that is, the second comparison signal, changes from the power supply voltage to the ground voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the inverter 530 changes from the ground voltage to the power supply voltage at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Further, the output of the inverter 530 is maintained at the power supply voltage after changing from the ground voltage to the power supply voltage.

The output of the Noah circuit 540 changes from the ground voltage to the power supply voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Then, the output of the Noah circuit 540 changes from the power supply voltage to the ground voltage at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Further, the output of the Noah circuit 540 is maintained at the ground voltage after changing from the power supply voltage to the ground voltage. In this way, the output of the Noah circuit 540 is the same as or similar to the case where an open failure occurs on the driver side.

The logical value held in the holding unit 700 is the logical value "0" in the initial state because the output of the Noah circuit 540 at the time (determination timing) when the output of the delay unit 600 changes from the ground voltage to the power supply voltage is the ground voltage. "(Ground voltage) is maintained.

In this way, when a short-circuit failure fixed at "0" occurs on the receiver side, the holding unit 700 captures and holds a comparison signal having a logical value of "1", and a short-circuit failure fixed at "0" occurs on the driver side. If so, the comparison signal with the logical value "0" is taken in and held.

FIG. 13 shows another example of the voltage waveform on the driver side when a short-circuit failure occurs. Note that FIG. 13 shows an example of a voltage waveform when one of the terminals 300d and 300r is short-circuited to the power supply voltage. Detailed description of the voltage waveforms that are the same as or similar to the voltage waveforms described with reference to FIGS. 3, 4, 8, 9, 11 and 12 will be omitted. For example, the output of the boundary cell 420a (BC420a) is the same as or similar to the case where the short-circuit failure described with reference to FIG. 9 occurs. That is, the output of the boundary cell 420a (BC420a) has the opposite polarity to the case where a short-circuit failure fixed at “0” occurs on the receiver side shown in FIG. Further, for example, the output of the pulse generation unit 440 and the output of the delay unit 600 are the same as or the same as when the short-circuit failure described with reference to FIG. 12 occurs.

First, the voltage waveform when a short-circuit failure occurs on the receiver side will be described.

The input of the signal comparison unit 522 and the inverter 530, that is, the voltage waveform of the propagation signal is the same as or similar to the voltage waveform of the input of the signal comparison unit 520 described with reference to FIG. For example, the inputs of the signal comparison unit 522 and the inverter 530 change from the voltage VH to the ground voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Then, the input of the signal comparison unit 522 and the inverter 530 changes from the ground voltage to the voltage VH at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage.

The output of the signal comparison unit 522, that is, the first comparison signal is maintained at the ground voltage because the input voltage of the signal comparison unit 522 is less than the threshold value VTH2. In this way, the output of the signal comparison unit 522 is the same as or the same as when a short-circuit failure fixed at "0" occurs on the receiver side.

The output of the inverter 530, that is, the second comparison signal, changes from the ground voltage to the power supply voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Then, the output of the inverter 530 changes from the power supply voltage to the ground voltage at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Further, the output of the inverter 530 is maintained at the ground voltage after changing from the power supply voltage to the ground voltage. In this way, the output of the inverter 530 has the opposite polarity to the case where a short-circuit failure fixed at "0" occurs on the receiver side.

The output of the Noah circuit 540 changes from the power supply voltage to the ground voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Then, the output of the Noah circuit 540 changes from the ground voltage to the power supply voltage at the time when the time Tr elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Further, the output of the Noah circuit 540 is maintained at the power supply voltage after changing from the ground voltage to the power supply voltage. In this way, the output of the Noah circuit 540 has the opposite polarity to the case where a short-circuit failure fixed at "0" occurs on the receiver side.

The logical value held in the holding unit 700 is the logical value "0" in the initial state because the output of the Noah circuit 540 at the time (determination timing) when the output of the delay unit 600 changes from the ground voltage to the power supply voltage is the ground voltage. "(Ground voltage) is maintained.

Next, the voltage waveform when a short-circuit failure occurs on the driver side will be described. A detailed description will be omitted for the same or similar voltage waveform as when a short failure occurs on the receiver side.

The output of the boundary cell 420a (BC420a), the output of the pulse generation unit 440, and the output of the delay unit 600 are the same as or the same as when a short failure occurs on the receiver side.

The input of the signal comparison unit 522 and the inverter 530, that is, the voltage waveform of the propagation signal is the same as or similar to the voltage waveform of the input of the signal comparison unit 520 described with reference to FIG. For example, the inputs of the signal comparison unit 522 and the inverter 530 change from the voltage VH to the ground voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Then, the inputs of the signal comparison unit 522 and the inverter 530 change from the ground voltage to the voltage VH at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage.

The output of the signal comparison unit 522, that is, the first comparison signal is maintained at the ground voltage because the input voltage of the signal comparison unit 522 is less than the threshold value VTH2. In this way, the output of the signal comparison unit 522 is the same as or similar to the case where a short-circuit failure fixed at "0" occurs on the driver side. That is, the output of the signal comparison unit 522 is maintained at the ground voltage when a short-circuit failure occurs.

The output of the inverter 530, that is, the second comparison signal, changes from the ground voltage to the power supply voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Then, the output of the inverter 530 changes from the power supply voltage to the ground voltage at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Further, the output of the inverter 530 is maintained at the ground voltage after changing from the power supply voltage to the ground voltage. In this way, the output of the inverter 530 has the opposite polarity to the case where a short-circuit failure fixed at "0" occurs on the driver side.

The output of the Noah circuit 540 changes from the power supply voltage to the ground voltage at the time when the time Tpf elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Then, the output of the Noah circuit 540 changes from the ground voltage to the power supply voltage at the time when the time Td elapses from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Further, the output of the Noah circuit 540 is maintained at the power supply voltage after changing from the ground voltage to the power supply voltage. In this way, the output of the Noah circuit 540 has the opposite polarity to the case where a short-circuit failure fixed at "0" occurs on the driver side.

The logical value held in the holding unit 700 is the logical value "0" in the initial state because the output of the Noah circuit 540 at the time (determination timing) when the output of the delay unit 600 changes from the ground voltage to the power supply voltage is the power supply voltage. "(Ground voltage) changes to the logical value" 1 "(power supply voltage). That is, the logical value held in the holding unit 700 becomes the logical value "1" (power supply voltage) after the determination timing in which the determination time TJ has elapsed from the time when the output of the boundary cell 420a changes from the voltage VH to the ground voltage. Be maintained.

In this way, when a short-circuit failure fixed at "1" occurs on the receiver side, the holding unit 700 captures and holds a comparison signal having a logical value of "0", and a short-circuit failure fixed at "1" occurs on the driver side. If so, the comparison signal with the logical value "1" is taken in and held. That is, the holding unit 700 holds a comparison signal having the opposite polarity to that when a “1” fixed short failure occurs and a “0” fixed short failure occurs.

FIG. 14 shows an example of a method for determining a failure occurrence location of the electronic device 104 shown in FIG. The test method of the electronic device 104 is the same as or the same as the test method shown in FIG. That is, the test shown in FIG. 14 is the process of step S300 shown in FIG. 5, and is executed based on the control from the test device 1000 that tests the electronic device 104. Further, the test shown in FIG. 14 is executed for each signal path registered in the defective netlist in step S170 shown in FIG. In the test shown in FIG. 14, the process of step S314 is executed instead of the processes of steps S310 and S312 shown in FIG. Further, in the test shown in FIG. 14, each process of steps S320, S330, and S340 shown in FIG. 6 and a series of processes from step S340 to step S348 are omitted from the test shown in FIG. The other steps of the test shown in FIG. 14 are the same as or similar to the steps shown in FIG. Detailed description of the same or similar steps as those described in FIG. 6 will be omitted.

The series of processes from step S322 to step S328 is a process of determining the location where a short failure occurs fixed at "0" or the location where an open failure occurs. Further, the series of processes from step S332 to step S338 is a process of determining the occurrence location of a short failure fixed at "1".

In step S314, the test apparatus 1000 determines whether or not the type of failure of the signal path to be tested is a short failure with a fixed value of "1" based on the defective netlist. When the type of failure of the signal path is a short failure with a fixed “1”, the operation of the test device 1000 shifts to step S332. On the other hand, when the type of failure of the signal path is not a fixed short failure of "1", that is, when the type of failure of the signal path is a fixed short failure of "0" or an open failure, the operation of the test device 1000 is , Step S322.

The series of processes from step S322 to step S328 is the same as or similar to the series of processes from step S322 to step S328 shown in FIG. For example, when the logical value (reading value) read from the holding unit 700 in step S326 is the logical value “1”, the test apparatus 1000 determines in step S350 that the location where the failure occurs is the receiver side, and the failure occurs. Complete the test to determine the location. Further, for example, when the logical value (reading value) read from the holding unit 700 in step S326 is the logical value "0", the test apparatus 1000 determines in step S352 that the location where the failure occurs is the driver side, and the failure occurs. The test for determining the location of occurrence of is completed.

The series of processes from step S332 to step S338 is the same as or similar to the series of processes from step S332 to step S338 shown in FIG. For example, when the logical value (reading value) read from the holding unit 700 in step S336 is the logical value "1", the test apparatus 1000 determines in step S352 that the location where the failure occurs is the driver side, and the failure occurs. Complete the test to determine the location. Further, for example, when the logical value (reading value) read from the holding unit 700 in step S336 is the logical value "0", the test apparatus 1000 determines in step S350 that the location where the failure occurs is the receiver side, and the failure occurs. The test for determining the location of occurrence of is completed.

As described above, in the electronic device 104, the comparison signal showing the magnitude relationship between the threshold value VTH and the propagation signal according to the type of failure without executing the process of switching the threshold value VTH according to the type of failure occurring in the signal path. Can be held by the holding unit 700. The method for determining the location of failure is not limited to the example shown in FIG.

As described above, even in the embodiments shown in FIGS. 10 to 14, the same effects as those in the embodiments shown in FIGS. 2 to 6 can be obtained. For example, the pulse generation unit 440 outputs the pulse to the delay unit 600 in synchronization with the timing at which the test signal is output from the boundary cell 420a. The delay unit 600 delays the pulse received from the pulse generation unit 440 by the determination time TJ corresponding to the determination timing and outputs the pulse to the holding unit 700. Then, the holding unit 700 takes in the comparison signal received from the comparison unit 502 in synchronization with the pulse received from the delay unit 600. For example, the test device 1000 reads the comparison signal captured in the holding unit 700 at the determination timing determined based on the wiring length L, so that the signal path between the plurality of semiconductor devices 204 is not executed. It is possible to determine the location of the failure in.

Further, the comparison unit 502 generates a comparison signal indicating the magnitude relationship between the threshold value VTH and the propagation signal according to the type of failure without executing the process of switching the threshold value VTH according to the type of failure occurring in the signal path. it can. As a result, the control at the time of determining the occurrence location of the failure can be simplified as compared with the case of executing the process of switching the threshold value VTH according to the type of the failure.

FIG. 15 shows another embodiment of a semiconductor device, an electronic device, and a test method for the electronic device. Elements that are the same as or similar to the elements described with reference to FIGS. 1 to 14 are designated by the same or similar reference numerals, and detailed description thereof will be omitted. The electronic device 106 shown in FIG. 15 is the same as the electronic device 104 shown in FIG. 10 except that it has a semiconductor device 206 (206A, 206B) instead of the semiconductor device 204 (204A, 204B) shown in FIG. Or similar. For example, the electronic device 106 is an information processing device such as a server, and has a plurality of semiconductor devices 206 (206A, 206B) corresponding to JTAG. Then, when testing the electronic device 106, the electronic device 106 is connected to the test device 1000 via terminals TCK, TMS, TRST, TDI, and TDO.

The semiconductor device 206 (206A, 206B) replaces the test circuit 400 (400A, 400B), the comparison unit 502, and the delay unit 600 shown in FIG. 10 with the test circuit 402 (402A, 402B), the comparison unit 504, and the delay unit. It has 602. Further, in the semiconductor device 206, the pulse generation unit 440 shown in FIG. 10 is omitted from the semiconductor device 204, and the selector 610 is added to the semiconductor device 204. Other configurations of the semiconductor device 206 are the same as or similar to those of the semiconductor device 204 shown in FIG. Note that, in FIG. 15, in order to make the figure easier to see, the description of the logic circuit or the like that realizes the original function of the semiconductor device 206 is omitted as in FIG.

The semiconductor devices 206A and 206B are mounted on a printed circuit board, for example, and are connected to each other by a printed wiring 320 arranged on the printed circuit board. For example, one of the plurality of terminals 300d of the semiconductor device 206A is connected to one of the plurality of terminals 300r of the semiconductor device 206B by the printed wiring 320 having a wiring length L. The configuration of the test block used for testing the poor connection between the semiconductor devices 206A and 206B is the same as or similar to that of the semiconductor devices 206A and 206B. Therefore, in FIG. 15, the semiconductor device 206A will be described.

The semiconductor device 206A includes a test circuit 402A, a comparison unit 504, a delay unit 602, a selector 610, and a holding unit 700. The test circuit 402A is the same as or similar to the test circuit 402A shown in FIG. For example, the TAP controller 412 included in the test circuit 402A outputs the signal UpdataDR to the delay unit 602.

The delay unit 602 is an example of a timing adjustment unit. For example, the delay unit 602 has a determination as shown in FIG. 16 or the like as a delay time corresponding to a determination timing determined based on the length L of the wiring 320 connecting the terminal 300d to be tested and the other semiconductor device 206B. The time TJ1 is set. Then, the delay unit 602 outputs the pulse PLS1 in which the signal UpdataDR received from the TAP controller 412 is delayed by the determination time TJ1 to the selector 610. The determination time TJ1 is the determination time TJ described with reference to FIG. 3 and the like. That is, the determination time TJ1 is an example of the delay time corresponding to the determination timing. Therefore, the pulse PLS1 has an edge corresponding to the determination timing.

Further, the delay unit 602 is set with the determination time TJ2 shown in FIG. 16 or the like as a delay time larger than the time Tr. Then, the delay unit 602 outputs the pulse PLS2 in which the signal UpdataDR received from the TAP controller 412 is delayed by the determination time TJ2 to the selector 610. Hereinafter, the pulses PLS1 and PLS2 are also referred to as pulse PLS without distinction.

The selector 610 selects, for example, one of the pulses PLS1 and PLS2 received from the delay unit 602 based on the control from the test apparatus 1000. Then, the selector 610 outputs the pulse PLS selected based on the control from the test apparatus 1000 to the holding unit 700. For example, the selector 610 outputs the pulse PLS2 to the holding unit 700 when determining the type of failure, and outputs the pulse PLS1 to the holding unit 700 when determining the location where the failure occurs.

The comparison unit 504 is connected to the terminal 300d to be tested and receives a propagation signal propagated to the terminal 300d to be tested. Then, the comparison unit 504 generates a comparison signal SIG3 showing a comparison result between the threshold value VTH and the propagation signal according to the type of failure that occurred in the signal path between the semiconductor devices 206A and 206B. Further, the comparison unit 504 generates a first comparison signal SIG1 (hereinafter, also referred to as a comparison signal SIG1) indicating the magnitude relationship between the propagation signal propagated to the terminal 300d to be tested and the threshold value VTH2. Then, the comparison unit 504 outputs one of the comparison signals SIG1 and SIG3 to the holding unit 700, for example, based on the control from the test apparatus 1000.

For example, the comparison unit 504 is the same as or similar to the comparison unit 502, except that the selector 550 is added to the comparison unit 502 shown in FIG. That is, the comparison unit 504 has a signal comparison unit 522, an inverter 530, a Noah circuit 540, and a selector 550.

The signal comparison unit 522, the inverter 530, and the Noah circuit 540 are the same as or similar to the signal comparison unit 522, the inverter 530, and the Noah circuit 540 shown in FIG. For example, the signal comparison unit 522 outputs the first comparison signal SIG1 indicating the magnitude relationship between the propagation signal propagated to the terminal 300d to be tested and the threshold value VTH2 to the Noah circuit 540. Further, the signal comparison unit 522 outputs the first comparison signal SIG1 to the selector 550. Further, for example, the inverter 530 outputs a second comparison signal SIG2 (hereinafter, also referred to as a comparison signal SIG2) in which the propagation signal propagated to the terminal 300d to be tested is inverted to the Noah circuit 540. Then, the Noah circuit 540 calculates the NOR of the first comparison signal SIG1 and the second comparison signal SIG2, and outputs the comparison signal SIG3 indicating the calculation result to the selector 550.

Therefore, when the voltage of the propagation signal is less than the threshold value VTH1 or the voltage of the propagation signal is larger than the threshold value VTH2, the Noah circuit 540 outputs a signal having a logic value “0” to the selector 550 as a comparison signal SIG3. Further, when the voltage of the propagation signal is larger than the threshold value VTH1 and less than the threshold value VTH2, the Noah circuit 540 outputs the signal of the logic value “1” to the selector 550 as the comparison signal SIG3. Hereinafter, the comparison signals SIG11, SIG2, and SIG3 are also referred to as comparison signals SIG without distinction.

The selector 550 selects, for example, one of the comparison signal SIG1 received from the signal comparison unit 522 and the comparison signal SIG3 received from the Noah circuit 540 based on the control from the test apparatus 1000. Then, the selector 550 outputs the comparison signal SIG selected based on the control from the test apparatus 1000 to the holding unit 700. For example, the selector 550 outputs the comparison signal SIG1 to the holding unit 700 when determining the type of failure, and outputs the comparison signal SIG3 to the holding unit 700 when determining the location of the failure.

As described above, the comparison unit 504 does not execute the process of switching the threshold value VTH according to the type of failure occurring in the signal path, and the comparison signal showing the magnitude relationship between the threshold value VTH and the propagation signal according to the type of failure. SIG3 can be generated.

The holding portion 700 is the same as or similar to the holding portion 700 shown in FIG. For example, the holding unit 700 captures and holds the comparison signal SIG received from the selector 550 of the comparison unit 504 in synchronization with the pulse PLS received from the delay unit 602 via the selector 610. Then, the holding unit 700 outputs the held comparison signal SIG to the boundary cell 420b.

For example, when determining the type of failure, the holding unit 700 captures and holds the comparison signal SIG1 received from the selector 550 in synchronization with the pulse PLS2 received from the selector 610. Further, when determining the location where a failure has occurred, the holding unit 700 captures and holds the comparison signal SIG3 received from the selector 550 in synchronization with the pulse PLS1 received from the selector 610.

In this way, the holding unit 700 holds the comparison signal SIG3 as a signal used when determining the location where the failure has occurred by taking in the comparison signal SIG3 in synchronization with the pulse PLS1 having an edge corresponding to the determination timing. .. Further, the holding unit 700 holds the comparison signal SIG1 as a signal used when determining the type of failure by taking in the comparison signal SIG1 in synchronization with the pulse PLS2.

The boundary cells 420a and 420b, the output buffer 430, the comparison unit 504, the delay unit 602, the selector 610, and the holding unit 700 are provided, for example, for each terminal 300d to be tested. Further, the configurations of the electronic device 106 and the semiconductor device 206 are not limited to the example shown in FIG. For example, the number of semiconductor devices 206 included in the electronic device 106 is not limited to two. Further, the semiconductor device 206 has the test circuit 400A shown in FIG. 10 instead of the test circuit 402A, and the pulse generation unit 440 may be added.

FIG. 16 shows an example of the voltage waveform on the driver side when an open failure occurs. In FIG. 16, as the output of the delay portion 602, the pulse PLS1 is shown by a broken line and the pulse PLS2 is shown by a solid line. Further, the logical value held by the holding unit 700 indicates a case where the holding unit 700 takes in the comparison signal SIG in synchronization with the pulse PLS2. Detailed description of the same or similar voltage waveforms as those described in FIGS. 3, 4, 8, 9, 11, 12, and 13 will be omitted.

The output voltage waveform of the boundary cell 420a (BC420a) and the input voltage waveforms of the signal comparison unit 522 and the inverter 530 are the same as or similar to the respective voltage waveforms described with reference to FIG. The voltage waveform of the output of the signal comparison unit 522 (comparison signal SIG1), the voltage waveform of the output of the inverter 530 (comparison signal SIG2), and the voltage waveform of the output of the Noah circuit 540 (comparison signal SIG3) are described with reference to FIG. It is the same as or similar to each voltage waveform. The voltage waveform of the signal UpdataDR is the same as or similar to the voltage waveform of the signal UpdataDR described with reference to FIG. For example, the signal UpdataDR is output from the TAP controller 412 to the delay unit 602 in synchronization with the output of the boundary cell 420a.

As shown by the broken line, the voltage waveform of the pulse PLS1, which is one of the two outputs of the delay unit 602, is the same as or similar to the voltage waveform of the output of the delay unit 600 described with reference to FIG. That is, the delay unit 602 outputs the pulse PLS1 to the selector 610 at the determination timing at which the determination time TJ1 has elapsed from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH.

Further, the voltage of the pulse PLS2, which is the other output of the two outputs of the delay unit 602, is set to the time when the determination time TJ2 elapses from the time when the signal UpdataDR changes from the ground voltage to the power supply voltage, as shown by the solid line. , Change from ground voltage to power supply voltage. Then, the pulse PLS2 changes from the power supply voltage to the ground voltage at the time when the determination time TJ2 elapses from the time when the signal UpdataDR changes from the power supply voltage to the ground voltage. That is, the delay unit 602 outputs the pulse PLS2 to the selector 610 at the timing when the determination time TJ2 elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. As described with reference to FIG. 15, the determination time TJ2 is preset in the delay unit 602 as a delay time larger than the time Tr.

In the example shown in FIG. 16, the logical value held in the holding unit 700 indicates the logical value held in the holding unit 700 when determining the type of failure. In this case, the holding unit 700 receives the pulse PLS2 of the pulses PLS1 and PLS2 from the selector 610, and the comparison signal SIG1 of the comparison signals SIG1 and SIG3 from the selector 550.

Therefore, as for the logical value held in the holding unit 700, since the voltage of the comparison signal SIG1 at the rising edge of the pulse PLS2 is the power supply voltage, the logical value "0" (ground voltage) in the initial state to the logical value "1" (power supply). Change to voltage). That is, when determining the type of failure, the logical value held in the holding unit 700 is a logical value after the timing at which the determination time TJ2 elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. It is maintained at 1 ”(power supply voltage).

When determining the location where a failure has occurred, the logical value held in the holding unit 700 is the same as or similar to the logical value held in the holding unit 700 described with reference to FIG.

FIG. 17 shows an example of the voltage waveform on the driver side when a short-circuit failure occurs. In FIG. 17, as in FIG. 16, the pulse PLS1 is shown by a broken line and the pulse PLS2 is shown by a solid line as the output of the delay portion 602. Further, the logical value held by the holding unit 700 indicates a case where the holding unit 700 takes in the comparison signal SIG in synchronization with the pulse PLS2, as in FIG. Detailed description will be omitted for voltage waveforms that are the same as or similar to the voltage waveforms described with reference to FIGS. 3, 4, 8, 9, 11, 12, 12, and 16.

The output voltage waveform of the boundary cell 420a (BC420a) and the input voltage waveforms of the signal comparison unit 522 and the inverter 530 are the same as or similar to the respective voltage waveforms described with reference to FIG. The voltage waveform of the output of the signal comparison unit 522 (comparison signal SIG1), the voltage waveform of the output of the inverter 530 (comparison signal SIG2), and the voltage waveform of the output of the Noah circuit 540 (comparison signal SIG3) are described with reference to FIG. It is the same as or similar to each voltage waveform. The voltage waveform of the signal UpdataDR and the voltage waveform of the output of the delay unit 602 are the same as or similar to the voltage waveform of the signal UpdataDR and the output voltage waveform of the delay unit 602 described with reference to FIG.

In the example shown in FIG. 17, the logical value held in the holding unit 700 indicates the logical value held in the holding unit 700 when determining the type of failure. In this case, the holding unit 700 receives the pulse PLS2 of the pulses PLS1 and PLS2 from the selector 610, and the comparison signal SIG1 of the comparison signals SIG1 and SIG3 from the selector 550.

Therefore, the logical value held by the holding unit 700 is maintained at the logical value “0” (ground voltage) in the initial state because the voltage of the comparison signal SIG1 at the rising edge of the pulse PLS2 is the ground voltage. When determining the location where a failure has occurred, the logical value held in the holding unit 700 is the same as or the same as the logical value held in the holding unit 700 described with reference to FIG.

As shown in FIGS. 16 and 17, at the timing when the determination time TJ2 elapses from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH, the logical value of the comparison signal SIG1 is that the type of failure is open failure. It depends on whether or not. Therefore, the holding unit 700 can hold the comparison signal SIG1 used when determining the type of failure by taking in the comparison signal SIG1 in synchronization with the pulse PLS2. For example, as shown in FIG. 16, when an open failure occurs, the holding unit 700 holds the comparison signal SIG having a logical value of “1” regardless of the location of the failure. Further, as shown in FIG. 17, when a short-circuit failure occurs, the holding unit 700 holds the comparison signal SIG having a logical value of “0” regardless of the location of the failure. Therefore, for example, the test device 1000 can determine the type of failure that has occurred in the signal path between the semiconductor devices 204 based on the logical value of the comparison signal SIG taken into the holding unit 700 in synchronization with the pulse PLS 2. it can.

FIG. 18 shows an example of the test method of the electronic device 106 shown in FIG. The test shown in FIG. 18 is, for example, a test for detecting a failure of the signal path between the semiconductor devices 206A and 206B shown in FIG. 15, and is executed based on the control from the test device 1000 for testing the electronic device 106. Will be done. In the test shown in FIG. 18, steps S102, S112, and S114 are added to the test shown in FIG. 5, and the processes of steps S172, S174, and S176 are executed instead of the process of step S170 shown in FIG. The other steps of the test shown in FIG. 18 are the same as or similar to the steps shown in FIG. Detailed description of the same or similar steps as those described in FIG. 5 will be omitted.

In step S100, the test device 1000 selects the signal path to be tested from the signal paths between the semiconductor devices 206A and 206B. As a result, the terminal 300d to be tested is selected.

Next, in step S102, the test apparatus 1000 selects pulse PLS2 from pulse PLS1 and PLS2 as the output of the selector 610 corresponding to the terminal 300d to be tested selected in step S100. Further, the test apparatus 1000 selects the comparison signal SIG1 from the comparison signals SIG1 and SIG3 as the output of the selector 550 of the comparison unit 504 corresponding to the terminal 300d to be tested selected in step S100. As a result, for example, the selector 610 corresponding to the terminal 300d to be tested selected in step S100 outputs the pulse PLS2 of the pulses PLS1 and PLS2 received from the delay unit 602 to the holding unit 700. Further, the selector 550 of the comparison unit 504 corresponding to the terminal 300d to be tested selected in step S100 outputs the comparison signal SIG1 among the comparison signals SIG1 and SIG3 to the holding unit 700.

Next, in step S110, the test apparatus 1000 outputs a test signal having a logical value of “1” (power supply voltage) from the boundary cell 420 on the driver side to the receiver side using the signal path selected in step S100. As described with reference to FIG. 5, the initial values of all boundary cells 420 are set to the logical value “0” (ground voltage) before the process of step S110 is executed.

By the processing of step S110, for example, the boundary cell 420a corresponding to the test target terminal 300d selected in step S100 receives the test signal of the logical value “1” from the test target terminal 300d via the output buffer 430. Output to the terminal 300r on the side. Further, the holding unit 700 receives the pulse PLS2 from the delay unit 602 via the selector 610 at the timing when the determination time TJ2 elapses from the time when the test signal changes from the logical value “0” to the logical value “1”. Then, the holding unit 700 captures and holds the comparison signal SIG1 received from the selector 550 of the comparison unit 504 in synchronization with the pulse PLS2. The test apparatus 1000 waits for the process of step S112 until the holding unit 700 takes in the comparison signal SIG1 in synchronization with the pulse PLS2. For example, when the determination time TJ2 elapses after executing the process of step S110, the test apparatus 1000 shifts the operation to step S112.

In step S112, the test apparatus 1000 reads the logical value of the comparison signal SIG1 held by the holding unit 700. For example, the test apparatus 1000 writes the logical value of the comparison signal SIG1 held in the holding unit 700 in the boundary cell 420b. Then, the test apparatus 1000 reads the logical value of the boundary cell 420b by scanning the boundary cell 420. In this way, the test apparatus 1000 reads the logical value of the comparison signal SIG1 taken into the holding unit 700 at the timing corresponding to the determination time TJ2 from the holding unit 700.

Next, in step S114, the test apparatus 1000 determines whether or not the logical value (reading value) read from the holding unit 700 in step S112 is the logical value “0”. When the reading value is the logical value “0”, the operation of the test apparatus 1000 proceeds to step S120. On the other hand, when the reading is not the logical value "0", that is, when the reading is the logical value "1", the test apparatus 1000 determines that an open failure has occurred in the signal path selected in step S100. , The operation is moved to step S172.

In step S120, the test apparatus 1000 reads the logical value of the boundary cell 420 on the receiver side of the signal path selected in step S100. For example, the test apparatus 1000 reads the logical value of the boundary cell 420 by scanning the boundary cell 420.

Next, in step S130, the test apparatus 1000 determines whether or not the logical value (reading value) read from the boundary cell 420 on the receiver side in step S120 is the logical value “1”. When the reading value is the logical value “1”, the operation of the test apparatus 1000 proceeds to step S140. On the other hand, when the read value is not the logical value "1", that is, when the read value is the logical value "0", the test apparatus 1000 causes a short failure of "0" fixed in the signal path selected in step S100. It is determined that the operation is performed, and the operation is moved to step S174.

In step S140, the test apparatus 1000 outputs a test signal having a logic value of “0” from the boundary cell 420 on the driver side to the receiver side using the signal path selected in step S100. For example, the test apparatus 1000 sets the initial values of all the boundary cells 420 to the logical value "1" by scanning the boundary cells 420. Then, the test apparatus 1000 sets the logical value “0” in the boundary cell 420a corresponding to the terminal 300d to be tested selected in step S100 by scanning the boundary cell 420. As a result, for example, the boundary cell 420a corresponding to the test target terminal 300d selected in step S100 transmits the test signal of the logical value “0” from the test target terminal 300d to the receiver side terminal via the output buffer 430. Output to 300r.

Next, in step S150, the test apparatus 1000 reads the logical value of the boundary cell 420 on the receiver side of the signal path selected in step S100. For example, the test apparatus 1000 reads the logical value of the boundary cell 420 by scanning the boundary cell 420.

Next, in step S160, the test apparatus 1000 determines whether or not the logical value (reading value) read from the boundary cell 420 on the receiver side in step S150 is the logical value “0”. When the reading value is the logical value “0”, the operation of the test apparatus 1000 proceeds to step S180. On the other hand, when the read value is not the logical value "0", that is, when the read value is the logical value "1", the test apparatus 1000 causes a short failure of "1" fixed in the signal path selected in step S100. It is determined that the operation is performed, and the operation is moved to step S176.

In step S172, the test apparatus 1000 determines that the type of failure occurring in the signal path selected in step S100 is an open failure, associates the determined failure type with the signal path, and registers it in the defective net list. After the process of step S172 is executed, the operation of the test apparatus 1000 shifts to step S180.

In step S174, the test apparatus 1000 determines that the type of failure that occurred in the signal path selected in step S100 is a short-circuit failure fixed at "0", and associates the determined failure type with the signal path to the defective netlist. to register. After the process of step S174 is executed, the operation of the test apparatus 1000 shifts to step S180.

In step S176, the test apparatus 1000 determines that the type of failure that occurred in the signal path selected in step S100 is a short-circuit failure fixed at "1", and associates the determined failure type with the signal path in the defective netlist. to register. After the process of step S176 is executed, the operation of the test apparatus 1000 shifts to step S180.

In step S180, the test device 1000 determines whether or not the test has been completed for all the signal paths of the failure detection targets among the signal paths between the semiconductor devices 206A and 206B. When the test is completed for all the signal paths, the operation of the test apparatus 1000 proceeds to step S190. On the other hand, if there is a signal path for which the test has not been completed, the operation of the test apparatus 1000 returns to step S100.

In step S190, the test apparatus 1000 determines whether the defective netlist is empty. If the bad netlist is empty, the operation of the test apparatus 1000 proceeds to step S200. On the other hand, when the defective netlist is not empty, that is, when the signal path in which the failure has occurred is registered in the defective netlist, the operation of the test apparatus 1000 shifts to step S302.

In step S200, the test device 1000 determines that the electronic device 106 is a non-defective product, and ends the test for detecting the failure of the signal path between the semiconductor devices 206A and 206B.

In step S302, the test apparatus 1000 determines the location where the failure has occurred. For example, the test apparatus 1000 executes the test shown in FIG. 19 to determine whether the location where the failure occurs is the receiver side or the driver side. When the process of step S302 is completed, the test for detecting the failure of the signal path between the semiconductor devices 206A and 206B is completed. The test method of the electronic device 106 is not limited to the example shown in FIG.

FIG. 19 shows an example of a method for determining a location where a failure occurs in the electronic device 106 shown in FIG. The test shown in FIG. 19 is the process of step S302 shown in FIG. 18, and is executed based on the control from the test device 1000 that tests the electronic device 106. Further, the test shown in FIG. 19 is executed for each signal path registered in the defective netlist in steps S172, S174, and S176 shown in FIG. The test shown in FIG. 19 is the same as or similar to the test shown in FIG. 14, except that step S313 is added to the test shown in FIG. Detailed description of the same or similar steps as those described with reference to FIG. 14 will be omitted.

The series of processes from step S322 to step S328 is a process of determining the location where a short failure occurs fixed at "0" or the location where an open failure occurs. Further, the series of processes from step S332 to step S338 is a process of determining the occurrence location of a short failure fixed at "1".

In step S313, the test apparatus 1000 selects pulse PLS1 from pulse PLS1 and PLS2 as the output of the selector 610 corresponding to the terminal 300d to be tested. Further, the test apparatus 1000 selects the comparison signal SIG3 from the comparison signals SIG1 and SIG3 as the output of the selector 550 of the comparison unit 504 corresponding to the terminal 300d to be tested. As a result, for example, the selector 610 corresponding to the terminal 300d to be tested outputs the pulse PLS1 of the pulses PLS1 and PLS2 received from the delay unit 602 to the holding unit 700. Further, the selector 550 of the comparison unit 504 corresponding to the terminal 300d to be tested outputs the comparison signal SIG3 among the comparison signals SIG1 and SIG2 to the holding unit 700.

That is, the pulse PLS1 and the comparison signal SIG3 received by the holding unit 700 are the same as or similar to the pulse and the comparison signal received by the holding unit 700 in the test shown in FIG. Therefore, the processing after step S314 is the same as or similar to the test shown in FIG. Therefore, also in the electronic device 106, the comparison signal SIG3 showing the magnitude relationship between the threshold value VTH and the propagated signal according to the type of failure without executing the process of switching the threshold value VTH according to the type of failure occurring in the signal path. Can be held by the holding unit 700. The method for determining the location where a failure occurs is not limited to the example shown in FIG.

As described above, even in the embodiments shown in FIGS. 15 to 19, the same effects as those in the embodiments shown in FIGS. 10 to 14 can be obtained. For example, the holding unit 700 takes in the comparison signal SIG3 received from the comparison unit 504 in synchronization with the pulse PLS1 received from the delay unit 600. The test device 1000 reads the comparison signal taken into the holding unit 700 at the determination timing determined based on the wiring length L, so that the failure in the signal path between the plurality of semiconductor devices 206 is performed without performing the visual inspection. Can be determined where the occurrence of

Further, the semiconductor device 206 controls the timing of capturing the comparison signal SIG by the holding unit 700 by using a pulse that delays the signal UpdataDR generated by the TAP controller 412. Therefore, the circuit scale can be reduced as compared with the case where the pulse generation unit 440 is provided.

Further, the comparison unit 504 sets the comparison signal SIG3 indicating the magnitude relationship between the threshold value VTH and the propagation signal according to the type of failure without executing the process of switching the threshold value VTH according to the type of failure occurring in the signal path. Can be generated. As a result, the control at the time of determining the occurrence location of the failure can be simplified as compared with the case of executing the process of switching the threshold value VTH according to the type of the failure.

Further, when determining the type of failure, the comparison unit 504 outputs a comparison signal SIG1 indicating a comparison result between the threshold value VTH2 associated with the open failure and the propagation signal to the holding unit 700. The logical value of the comparison signal SIG1 differs depending on whether or not the type of failure is an open failure after the timing at which the determination time TJ2 has elapsed from the time when the output of the boundary cell 420a changes from the ground voltage to the voltage VH. Therefore, when determining the type of failure, the holding unit 700 takes in the comparison signal SIG1 in synchronization with the pulse PLS2 received after the determination time TJ2 has elapsed. As a result, for example, the test apparatus 1000 can determine the type of failure by reading the comparison signal SIG1 taken into the holding unit 700 in synchronization with the pulse PLS2.

The inventions described in the above embodiments are organized and disclosed as an appendix as follows.
(Appendix 1)
In semiconductor devices connected to other semiconductor devices
A test signal output unit that outputs a test signal from the terminal to be tested to the other semiconductor device,
A comparison unit that receives the propagation signal propagated to the terminal to be tested, compares the threshold value according to the type of failure that occurred in the signal path with the propagation signal, and generates a comparison signal showing the comparison result.
A timing adjusting unit in which a determination timing determined based on the length of wiring connecting the terminal to be tested and the other semiconductor device is set, and a timing adjusting unit.
It is characterized by having a holding unit that holds the comparison signal as a signal used when determining the location where the failure has occurred by receiving the comparison signal from the comparison unit and taking in the comparison signal at the determination timing. Semiconductor device.
(Appendix 2)
In the semiconductor device described in Appendix 1,
Further, it has a pulse generation unit that generates a pulse in synchronization with the timing at which the test signal is output from the test signal output unit and outputs the generated pulse to the timing adjustment unit.
The timing adjusting unit delays the pulse received from the pulse generating unit by a delay time corresponding to the determination timing and outputs the pulse to the holding unit.
The holding unit is a semiconductor device that captures the comparison signal received from the comparison unit in synchronization with the pulse received from the timing adjusting unit.
(Appendix 3)
In the semiconductor device according to Appendix 1 or Appendix 2,
The comparison unit
A threshold selection unit that selects the threshold value to be compared with the propagated signal from the threshold values predetermined for each type of failure based on the type of the failure generated in the signal path.
A semiconductor device including a comparison signal generation unit that outputs a signal corresponding to the magnitude relationship between the threshold value selected by the threshold value selection unit and the propagation signal to the holding unit as the comparison signal.
(Appendix 4)
In the semiconductor device according to Appendix 1 or Appendix 2,
The types of failures include an open failure in which the signal path is in an open state and a short circuit failure in which the signal path is short-circuited to a power source.
The threshold value associated with the open failure is set to a voltage value larger than the threshold value associated with the short failure.
The comparison unit
A first signal generation unit that generates a first comparison signal according to the magnitude relationship between the threshold value associated with the open failure and the propagation signal.
A second signal generation unit that generates a second comparison signal according to the magnitude relationship between the threshold value and the propagation signal associated with the short failure.
A semiconductor device including a comparison signal generation unit that generates the comparison signal based on the first comparison signal and the second comparison signal and outputs the generated comparison signal to the holding unit.
(Appendix 5)
In the semiconductor device described in Appendix 4,
The first signal generation unit generates the first comparison signal indicating true when the propagated signal is larger than the threshold value associated with the open failure, and the propagated signal is associated with the open failure. The first comparison signal indicating false when it is smaller than the threshold value is generated.
The second signal generation unit generates the second comparison signal indicating false when the propagate signal is larger than the threshold value associated with the short failure, and the propagate signal is associated with the short failure. The second comparison signal indicating true when it is smaller than the threshold value is generated.
The semiconductor device is characterized in that the comparison signal generation unit calculates a NOR of the first comparison signal and the second comparison signal, and outputs the calculation result as the comparison signal to the holding unit.
(Appendix 6)
In an electronic device having a plurality of semiconductor devices connected to each other
The semiconductor device of any of the plurality of semiconductor devices
A test signal output unit that outputs a test signal from the terminal to be tested to another semiconductor device,
A comparison unit that receives the propagation signal propagated to the terminal to be tested, compares the threshold value according to the type of failure that occurred in the signal path with the propagation signal, and generates a comparison signal showing the comparison result.
A timing adjusting unit in which a determination timing determined based on the length of wiring connecting the terminal to be tested and the other semiconductor device is set, and a timing adjusting unit.
It is characterized by having a holding unit that holds the comparison signal as a signal used when determining the location where the failure has occurred by receiving the comparison signal from the comparison unit and taking in the comparison signal at the determination timing. Electronic device.
(Appendix 7)
In the electronic device described in Appendix 6,
The semiconductor device further includes a pulse generation unit that generates a pulse in synchronization with the timing at which the test signal is output from the test signal output unit and outputs the generated pulse to the timing adjustment unit. Have and
The timing adjusting unit delays the pulse received from the pulse generating unit by a delay time corresponding to the determination timing and outputs the pulse to the holding unit.
The holding unit is an electronic device that captures the comparison signal received from the comparison unit in synchronization with the pulse received from the timing adjusting unit.
(Appendix 8)
In the electronic device according to Appendix 6 or Appendix 7,
The comparison unit
A threshold selection unit that selects the threshold value to be compared with the propagated signal from the threshold values predetermined for each type of failure based on the type of the failure generated in the signal path.
An electronic device including a comparison signal generation unit that outputs a signal corresponding to the magnitude relationship between the threshold value selected by the threshold value selection unit and the propagation signal to the holding unit as the comparison signal.
(Appendix 9)
In the electronic device according to Appendix 6 or Appendix 7,
The types of failures include an open failure in which the signal path is in an open state and a short circuit failure in which the signal path is short-circuited to a power source.
The threshold value associated with the open failure is set to a voltage value larger than the threshold value associated with the short failure.
The comparison unit
A first signal generation unit that generates a first comparison signal according to the magnitude relationship between the threshold value associated with the open failure and the propagation signal.
A second signal generation unit that generates a second comparison signal according to the magnitude relationship between the threshold value and the propagation signal associated with the short failure.
An electronic device including a comparison signal generation unit that generates the comparison signal based on the first comparison signal and the second comparison signal and outputs the generated comparison signal to the holding unit.
(Appendix 10)
In the electronic device described in Appendix 9,
The first signal generation unit generates the first comparison signal indicating true when the propagated signal is larger than the threshold value associated with the open failure, and the propagated signal is associated with the open failure. The first comparison signal indicating false when it is smaller than the threshold value is generated.
The second signal generation unit generates the second comparison signal indicating false when the propagate signal is larger than the threshold value associated with the short failure, and the propagate signal is associated with the short failure. The second comparison signal indicating true when it is smaller than the threshold value is generated.
The electronic device is characterized in that the comparison signal generation unit calculates a logical sum of the first comparison signal and the second comparison signal, and outputs the calculation result as the comparison signal to the holding unit.
(Appendix 11)
In a test method for an electronic device having a plurality of semiconductor devices connected to each other,
The test signal output unit of any of the plurality of semiconductor devices outputs a test signal from the terminal to be tested to the other semiconductor device.
The comparison unit of any of the semiconductor devices receives the propagated signal propagated to the terminal to be tested, compares the threshold value according to the type of failure generated in the signal path with the propagated signal, and compares the result. Generate a comparison signal to show
The holding unit of any of the semiconductor devices receives the comparison signal from the comparison unit, and at a determination timing determined based on the length of the wiring connecting the terminal to be tested and the other semiconductor device. A method for testing an electronic device, which comprises capturing the comparison signal and holding the comparison signal as a signal used when determining a location where the failure has occurred.
(Appendix 12)
In the method for testing an electronic device according to Appendix 11,
The pulse generation unit of any of the semiconductor devices generates a pulse in synchronization with the timing at which the test signal is output from the test signal output unit, and the generated pulse is generated by the semiconductor device. Output to the timing adjustment unit that has
The timing adjusting unit delays the pulse received from the pulse generating unit by a delay time corresponding to the determination timing and outputs the pulse to the holding unit.
A test method for an electronic device, wherein the holding unit captures the comparison signal received from the comparison unit in synchronization with the pulse received from the timing adjusting unit.
(Appendix 13)
In the test method for the electronic device according to Appendix 11 or Appendix 12,
The threshold selection unit included in the comparison unit selects the threshold value to be compared with the propagation signal from the threshold values predetermined for each type of failure based on the type of the failure generated in the signal path.
An electron characterized in that the comparison signal generation unit included in the comparison unit outputs a signal corresponding to the magnitude relationship between the threshold value selected by the threshold value selection unit and the propagation signal to the holding unit as the comparison signal. How to test the device.
(Appendix 14)
In the test method for the electronic device according to Appendix 11 or Appendix 12,
The types of failures include an open failure in which the signal path is in an open state and a short circuit failure in which the signal path is short-circuited to a power source.
The threshold value associated with the open failure is set to a voltage value larger than the threshold value associated with the short failure.
The first signal generation unit included in the comparison unit generates a first comparison signal according to the magnitude relationship between the threshold value associated with the open failure and the propagation signal.
The second signal generation unit included in the comparison unit generates a second comparison signal according to the magnitude relationship between the threshold value associated with the short failure and the propagation signal.
An electron characterized in that a comparison signal generation unit included in the comparison unit generates the comparison signal based on the first comparison signal and the second comparison signal, and outputs the generated comparison signal to the holding unit. How to test the device.
(Appendix 15)
In the method for testing an electronic device according to Appendix 14,
The first signal generation unit generates the first comparison signal indicating true when the propagated signal is larger than the threshold value associated with the open failure, and the propagated signal is associated with the open failure. The first comparison signal indicating false when it is smaller than the threshold value is generated.
The second signal generation unit generates the second comparison signal indicating false when the propagate signal is larger than the threshold value associated with the short failure, and the propagate signal is associated with the short failure. The second comparison signal indicating true when it is smaller than the threshold value is generated.
A test method for an electronic device, wherein the comparison signal generation unit calculates a NOR of the first comparison signal and the second comparison signal, and outputs the calculation result as the comparison signal to the holding unit. ..
(Appendix 16)
A test signal output unit having a plurality of semiconductor devices connected to each other and one of the plurality of semiconductor devices outputs a test signal from a terminal to be tested to another semiconductor device, and the test. A comparison unit that receives the propagation signal propagated to the target terminal, compares the threshold value according to the type of failure that occurred in the signal path with the propagated signal, and generates a comparison signal showing the comparison result, and the test target. A timing adjustment unit in which a determination timing determined based on the length of the wiring connecting the terminal and the other semiconductor device is set, and the comparison signal is received from the comparison unit, and the comparison signal is received at the determination timing. In the test method of an electronic device having a holding unit that holds the comparison signal as a signal used when determining the location where the failure has occurred by incorporating the signal.
The test device for testing the electronic device is
By changing the logical value of the test signal,
The logical value of the comparison signal taken into the holding unit at the determination timing is read from the holding unit.
A method for testing an electronic device, which comprises determining a location where a failure occurs based on a logical value of the comparison signal read from the holding unit.

The above detailed description will clarify the features and advantages of the embodiments. It is intended that the claims extend to the features and advantages of the embodiments as described above, without departing from their spirit and scope of rights. Also, anyone with ordinary knowledge in the art should be able to easily come up with any improvements or changes. Therefore, there is no intention to limit the scope of the embodiments having invention to those described above, and it is possible to rely on suitable improvements and equivalents included in the scope disclosed in the embodiments.

10 Electronic device; 20 Semiconductor device; 30 Terminal; 40 Test signal output unit; 50 Comparison unit; 60 Timing adjustment unit; 70 Holding unit; 100, 102, 104, 106 Electronic device; 200, 202, 204, 206 ... Semiconductor device; 300 ... Terminal; 400, 402 ... Test circuit; 410, 412 ... TAP controller; 420 ... Boundary cell; 430 ... Output buffer; 440 ... Pulse generator; 500, 502, 504 ... Comparison Unit; 510 ... Threshold selection unit; 520 ... Signal comparison unit; 530 ... Inverter; 540 ... Noah circuit; 550 ... Selector; 600, 602 ... Delay part; 610 ... Selector; 700 ... Holding unit; 1000 ... Test device

Claims (7)

In semiconductor devices connected to other semiconductor devices
A test signal output unit that outputs a test signal from the terminal to be tested to the other semiconductor device,
A comparison unit that receives the propagation signal propagated to the terminal to be tested, compares the threshold value according to the type of failure that occurred in the signal path with the propagation signal, and generates a comparison signal showing the comparison result.
A timing adjusting unit in which a determination timing determined based on the length of the wiring connecting the terminal to be tested and the other semiconductor device is set, and a timing adjusting unit.
It is characterized by having a holding unit that holds the comparison signal as a signal used when determining the location where the failure has occurred by receiving the comparison signal from the comparison unit and taking in the comparison signal at the determination timing. Semiconductor device. In the semiconductor device according to claim 1,
Further, it has a pulse generation unit that generates a pulse in synchronization with the timing at which the test signal is output from the test signal output unit and outputs the generated pulse to the timing adjustment unit.
The timing adjusting unit delays the pulse received from the pulse generating unit by a delay time corresponding to the determination timing and outputs the pulse to the holding unit.
The holding unit is a semiconductor device that captures the comparison signal received from the comparison unit in synchronization with the pulse received from the timing adjusting unit. In the semiconductor device according to claim 1 or 2.
The comparison unit
A threshold selection unit that selects the threshold value to be compared with the propagated signal from the threshold values predetermined for each type of failure based on the type of the failure generated in the signal path.
A semiconductor device including a comparison signal generation unit that outputs a signal corresponding to the magnitude relationship between the threshold value selected by the threshold value selection unit and the propagation signal to the holding unit as the comparison signal. In the semiconductor device according to claim 1 or 2.
The types of failures include an open failure in which the signal path is in an open state and a short circuit failure in which the signal path is short-circuited to a power source.
The threshold value associated with the open failure is set to a voltage value larger than the threshold value associated with the short failure.
The comparison unit
A first signal generation unit that generates a first comparison signal according to the magnitude relationship between the threshold value associated with the open failure and the propagation signal.
A second signal generation unit that generates a second comparison signal according to the magnitude relationship between the threshold value and the propagation signal associated with the short failure.
A semiconductor device including a comparison signal generation unit that generates the comparison signal based on the first comparison signal and the second comparison signal and outputs the generated comparison signal to the holding unit. In the semiconductor device according to claim 4,
The first signal generation unit generates the first comparison signal indicating true when the propagated signal is larger than the threshold value associated with the open failure, and the propagated signal is associated with the open failure. The first comparison signal indicating false when it is smaller than the threshold value is generated.
The second signal generation unit generates the second comparison signal indicating false when the propagate signal is larger than the threshold value associated with the short failure, and the propagate signal is associated with the short failure. The second comparison signal indicating true when it is smaller than the threshold value is generated.
The semiconductor device is characterized in that the comparison signal generation unit calculates a NOR of the first comparison signal and the second comparison signal, and outputs the calculation result as the comparison signal to the holding unit. In an electronic device having a plurality of semiconductor devices connected to each other
The semiconductor device of any of the plurality of semiconductor devices
A test signal output unit that outputs a test signal from the terminal to be tested to another semiconductor device,
A comparison unit that receives the propagation signal propagated to the terminal to be tested, compares the threshold value according to the type of failure that occurred in the signal path with the propagation signal, and generates a comparison signal showing the comparison result.
A timing adjusting unit in which a determination timing determined based on the length of the wiring connecting the terminal to be tested and the other semiconductor device is set, and a timing adjusting unit.
It is characterized by having a holding unit that holds the comparison signal as a signal used when determining the location where the failure has occurred by receiving the comparison signal from the comparison unit and taking in the comparison signal at the determination timing. Electronic device. In a test method for an electronic device having a plurality of semiconductor devices connected to each other,
The test signal output unit of any of the plurality of semiconductor devices outputs a test signal from the terminal to be tested to the other semiconductor device.
The comparison unit of any of the semiconductor devices receives the propagated signal propagated to the terminal to be tested, compares the threshold value according to the type of failure generated in the signal path with the propagated signal, and compares the result. Generate a comparison signal to show
The holding unit of any of the semiconductor devices receives the comparison signal from the comparison unit, and at a determination timing determined based on the length of the wiring connecting the terminal to be tested and the other semiconductor device. A method for testing an electronic device, which comprises capturing the comparison signal and holding the comparison signal as a signal used when determining a location where the failure has occurred.

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