JP6781105B2 - Track and hold circuit - Google Patents

Description

The present invention relates to a track and hold circuit, and more particularly to a track and hold circuit in which the frequency of a clock signal is wide.

The track-and-hold circuit is one of the circuits used to convert an analog signal into a digital signal. The track-and-hold circuit switches between two modes, track mode and hold mode, depending on the level (High or Low) of the input clock signal.

In the track mode, the input voltage signal is output as it is as an output signal. In the hold mode, the voltage value input at the timing of switching from the track mode to the hold mode is held and output is continued.

The track-and-hold circuit is also called a sample-hold circuit, and is divided into oversampling and undersampling according to the magnitude relationship between the frequency of the input signal and the frequency of the clock signal. For example, Non-Patent Document 1 discloses an oversampling type track-and-hold circuit that samples and outputs at a frequency higher than the frequency of the input signal.

In the oversampling type track-and-hold circuit, a clock transmission circuit that operates at high speed is required because a higher-speed clock signal must be transmitted to the sampling unit. When the clock signal transmitted by the clock transmission circuit is a clock signal of a specific frequency, the band is extended by applying peaking using an inductor or the like, and even a high-speed signal is increased in gain and transmitted. (See, for example, Non-Patent Document 1).

However, when the frequency range of the signal input to the clock transmission circuit (hereinafter referred to as "input clock signal") covers a wide range from low speed to high speed (for example, 10 GHz to 40 GHz), peaking using a conventional inductor or the like. In this method, it is difficult to increase the gain in a wide range, that is, to make the amplitude of the clock signal (hereinafter, referred to as “sampling clock signal”) input to the sampling unit constant regardless of the frequency.

Further, in the switching operation between the track mode and the hold mode, it is necessary that not only the amplitude of the sampling clock signal is constant but also the rise time Tr and the fall time Tf of the sampling clock signal are constant.

However, if the rising time Tr and falling time Tf of the sampling clock signal fluctuate depending on the frequency of the input clock signal, the performance of the track-and-hold circuit such as the acquisition time and the droop rate changes, and the accuracy of the track-and-hold circuit deteriorates. There was a problem to do.

S. Shahramian, et al, "A40-GSSingle / Sec Track & Hold Amplifier in 0.18um SiGe BiCMOS Technology," CSICS, 2005.

An object of the present invention is to provide a track-and-hold circuit capable of obtaining a certain degree of accuracy even for input clock signals of various frequencies over a wider range.

In order to solve the above-mentioned problems, in the track and hold circuit according to the present invention, a first amplifier circuit that outputs an amplifier signal obtained by amplifying an input signal and a sampling clock signal having the amplified signal as a predetermined amplitude are output. A second amplifier circuit and a sampling circuit for sampling an analog input signal at the frequency of the sampling clock signal are provided, and the gain of the first amplifier circuit is larger than the gain of the second amplifier circuit. The load of the second amplifier circuit is smaller than the load of the amplifier circuit, and the first amplifier circuit amplifies the input signal to an amplitude larger than the predetermined amplitude of the sampling clock signal. It is a feature.

Further, in the track and hold circuit according to the present invention, the first amplifier circuit may include a plurality of amplifiers connected in multiple stages.

Further, in the track-and-hold circuit according to the present invention, in the plurality of amplifiers, the gain of the first stage amplifier may be larger than the gain of other amplifiers.

Further, in the track and hold circuit according to the present invention, the first amplifier circuit may include a variable gain amplifier circuit.

Further, in the track and hold circuit according to the present invention, the first-stage amplifier may be a variable gain amplifier.

Further, the track-and-hold circuit according to the present invention further includes an automatic gain control circuit that monitors the output of the variable gain amplifier circuit and controls the gain of the variable gain amplifier circuit so that a constant amplitude is output. You may.

According to the present invention, the first amplifier circuit is connected to the second amplifier circuit having a smaller load, the input clock signal is amplified to an amplitude larger than the amplitude of the predetermined sampling clock signal, and then the second amplifier is used. By adjusting the amplitude to a predetermined amplitude by the amplifier circuit of, it is possible to maintain a certain accuracy even for input clock signals of various frequencies over a wide range.

FIG. 1 is a block diagram showing a configuration example of a track-and-hold circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing the frequency characteristics of the clock signal amplifier circuit and the clock waveform adjustment circuit according to the first embodiment of the present invention. FIG. 3 is a diagram showing an output waveform of the clock signal amplifier circuit according to the first embodiment of the present invention. FIG. 4 is a diagram showing an output waveform of the clock waveform adjusting circuit according to the first embodiment of the present invention. FIG. 5 is a block diagram showing a configuration example of a track-and-hold circuit according to a second embodiment of the present invention. FIG. 6 is a diagram showing the frequency characteristics of the clock signal amplifier circuit according to the second embodiment of the present invention. FIG. 7 is a block diagram showing a configuration example of a track-and-hold circuit according to a third embodiment of the present invention. FIG. 8 is a block diagram showing a configuration example of a track-and-hold circuit according to a fourth embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 1 to 8. The components that are common to each figure are designated by the same reference numerals.

<First Embodiment>
The track-and-hold circuit 1 according to the first embodiment of the present invention adjusts the clock signal amplification circuit 152 for amplifying the input clock signal and the input clock signal amplified by the clock signal amplification circuit 152 to a predetermined amplitude. It has a clock waveform adjusting circuit 153 that outputs a sampling clock signal, and a sampling circuit 3 that samples an analog input signal at the frequency of the sampling clock signal output by the clock waveform adjusting circuit 153. The clock signal amplification circuit 152 amplifies the input clock signal to an amplitude larger than a predetermined amplitude for the sampling clock signal.

The track-and-hold circuit 1 is used, for example, in an AD converter that converts an analog signal into a digital signal. The track-and-hold circuit 1 discretizes (samples) the analog signal, holds the voltage of the sampled analog signal for a certain period in which the AD conversion is performed, and prevents an error during the AD conversion.

FIG. 1 is a block diagram showing a configuration example of the track and hold circuit 1 according to the first embodiment of the present invention. The track-and-hold circuit 1 includes a data input buffer 2, a sampling circuit 3, an output buffer 4, and a clock transmission circuit 5.

An analog signal is input to the data input buffer 2, and the input analog signal is transmitted to the sampling circuit 3. A data input buffer 2 having a low output impedance is used.

The sampling circuit 3 includes a switch such as an FET switch and a holding capacitance (hold capacitor), and when the sampling clock signal input from the clock transmission circuit 5 has a high potential (“H” level), the switch conducts. The analog signal transmitted from the data input buffer 2 is output as it is through the output buffer 4 (track mode).

Further, when the input sampling clock signal is at a low potential (“L” level), the switch becomes non-conducting, and the voltage level of the analog input signal immediately before the switch switches from the “H” level to the “L” level is the hold capacitor. The signal of the voltage level is output via the output buffer 4 (hold mode).

The output buffer 4 outputs an analog signal output according to each operation mode in the sampling circuit 3 to a circuit (not shown) such as a comparator in the subsequent stage. As the output buffer 4, a buffer having a large input impedance is used.

Next, the clock transmission circuit 5 will be described. The clock transmission circuit 5 includes a clock input buffer 151, a clock signal amplifier circuit 152 (first amplifier circuit), and a clock waveform adjustment circuit 153 (second amplifier circuit). The clock transmission circuit 5 generates a sampling clock signal having a predetermined amplitude based on the input clock signal, and inputs the sampling clock signal to the sampling circuit 3. It is assumed that input clock signals of various frequencies over a wide range, for example, a range of 10 GHz to 40 GHz, are input to the clock input buffer 151.

The clock signal amplification circuit 152 is a high-gain amplifier and amplifies the input clock signal input via the clock input buffer 151. The clock signal amplification circuit 152 amplifies the input clock signal to an amplitude larger than the amplitude of the predetermined sampling clock signal.

The clock waveform adjustment circuit 153 is an amplifier having a lower gain than the clock signal amplifier circuit 152, a wider band, and can cover various frequencies of the input clock signal. The clock waveform adjustment circuit 153 adjusts the amplitude of the input clock signal amplified by the clock signal amplification circuit 152 to a predetermined amplitude to generate a sampling clock signal, and outputs the sampling clock signal to the sampling circuit 3. The amplitude of the sampling clock signal input to the sampling circuit 3 is a preset value.

Next, the characteristics and operation of the clock signal amplifier circuit 152 and the clock waveform adjustment circuit 153 will be described. FIG. 2 is a diagram showing the frequency characteristics of the clock signal amplifier circuit 152 and the clock waveform adjustment circuit 153 according to the first embodiment. FIG. 3 is a diagram showing an output waveform of the clock signal amplifier circuit 152. Further, FIG. 4 is a diagram showing an output waveform of the clock waveform adjustment circuit 153.

As shown in FIG. 2, the clock signal amplification circuit 152 has a gain higher than that of the clock waveform adjustment circuit 153. On the other hand, the clock waveform adjustment circuit 153 is an amplifier in which the DC gain is lowered to, for example, 0 dB, and the -3 dB band is widened accordingly. In the present embodiment, for simplification, the case where the clock signal amplifier circuit 152 and the clock waveform adjustment circuit 153 both have the same -3 dB band at a predetermined upper limit frequency (for example, 40 GHz) will be described.

Further, as shown in FIG. 2, the output amplitude of the clock signal amplifier circuit 152 is higher than that of the output amplitude of the clock waveform adjustment circuit 153, in particular, the clock waveform adjustment circuit at the frequency upper limit (for example, 40 GHz) of the input clock signal. It is a large value by the loss of 153 (-3 dB). Specific values such as the cutoff frequency are determined by various trade-offs such as the withstand voltage of the transistor.

Next, the output of the signal amplified by the clock signal amplification circuit 152 to an amplitude larger than the amplitude of the sampling clock signal determined in advance has a rise time Tr and a fall time Tf as shown in FIG. It becomes a trapezoidal wave.

Further, FIG. 3 shows waveforms of an output signal when a high frequency input clock signal (for example, 40 GHz) is amplified and an output signal when a low frequency input clock signal (for example, 20 GHz) is amplified. It shows. In the clock signal amplification circuit 152, the amplitude of the output signal with respect to the high frequency input clock signal and the amplitude of the output signal with respect to the low frequency input clock signal have the same amplitude.

The reason why the output signal in the clock signal amplifier circuit 152 becomes a trapezoidal wave is that if the gain of the clock signal amplifier circuit 152 is sufficiently high, the through rate becomes high even if the input clock signal is, for example, a sine wave. This is because the amplitude of the output signal is limited to a certain value.

More specifically, when the clock signal amplifier circuit 152 is directly connected to the sampling circuit 3 without going through the clock waveform adjustment circuit 153, the band characteristics in the clock signal amplifier circuit 152 are affected by the influence of the sampling circuit 3 which is a large load capacitance. It gets worse, especially the high frequency input clock signal cannot be sufficiently amplified.

By connecting the clock waveform adjustment circuit 153 to the subsequent stage of the clock signal amplifier circuit 152 as in the present embodiment, the load on the clock signal amplifier circuit 152 is reduced, and the band characteristics of the clock signal amplifier circuit 152 are deteriorated. It can be suppressed. Therefore, the clock signal amplification circuit 152 can sufficiently amplify even a high frequency input clock signal.

For this reason, the output signal in the clock signal amplifier circuit 152 has a trapezoidal waveform, and the amplitude is the same as the amplitude of the output signal of the low frequency input clock signal even when the input clock signal has a high frequency. Become.

Further, in the trapezoidal waveform output from the clock signal amplifier circuit 152, the rise time Tr and the fall time Tf are constant regardless of the frequency of the input clock signal. The rise time Tr and the fall time Tf are determined by the output amplitude, frequency characteristics, and bandwidth of the clock signal amplifier circuit 152.

Next, the waveform of the output signal of the clock waveform adjustment circuit 153 under the same conditions as in FIG. 3 will be described. As shown in FIG. 4, the clock waveform adjustment circuit 153 adjusts the amplitude of the signal output from the clock signal amplification circuit 152 to a predetermined amplitude of the sampling clock signal. The output signal in the clock waveform adjusting circuit 153 becomes a trapezoidal waveform in which the amplitude of the output signal of the clock signal amplification circuit 152 is reduced.

The clock waveform adjustment circuit 153 is an amplifier in which the DC gain is lowered to 0 dB and the -3 dB band is widened by that amount as described above. Since the sampling circuit 3 which is a large load is connected to the subsequent stage of the clock waveform adjustment circuit 153, the high frequency component of the signal is attenuated in the clock waveform adjustment circuit 153, but the output amplitude is also lowered. Therefore, in the trapezoidal waveform of each output signal by the clock waveform adjusting circuit 153, the rising time Tr and the falling time Tf in the output signal of the clock signal amplification circuit 152 are maintained.

As described above, according to the first embodiment, the clock signal amplifier circuit 152 is provided in the front stage of the clock transmission circuit 5, and the clock waveform adjustment circuit 153 is provided in the rear stage. The gain of the clock signal amplifier circuit 152 is set to be higher than the gain of the clock waveform adjustment circuit 153, and the output amplitude of the clock signal amplifier circuit 152 is made larger than the output amplitude of the clock waveform adjustment circuit 153 in the subsequent stage.

Further, a clock waveform adjustment circuit 153 having a lower gain is provided in the final stage of the clock transmission circuit 5, and then connected to the sampling circuit 3 which is a large load. Then, the clock waveform adjusting circuit 153 limits the amplitude of the amplified signal input from the clock signal amplification circuit 152 in the previous stage so that the amplitude becomes a predetermined sampling clock signal.

With such a configuration, in the track and hold circuit 1, even if the frequency of the input clock signal is wide, a sampling clock signal having a constant amplitude, a constant rise time Tr, and a fall time Tf is generated. can do. As a result, the accuracy of the track-and-hold circuit 1 can be improved.

In the clock signal amplifier circuit 152, for example, impedance peaking may be used as a means for achieving both high gain and wide bandwidth. Further, as a means for lowering the gain of the clock waveform adjustment circuit 153 and widening the band, for example, source decoding may be used.

<Second Embodiment>
Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram showing a configuration example of the track-and-hold circuit 1a according to the second embodiment of the present invention. FIG. 6 is a diagram showing the frequency characteristics of the clock signal amplifier circuit 152. In the following description, the same components as those in the first embodiment described above are designated by the same reference numerals, and the description thereof will be omitted.

In the first embodiment, the case where the clock signal amplification circuit 152 is configured by a one-stage amplifier has been described. On the other hand, in the second embodiment, the clock signal amplifier circuit 152 is composed of a multi-stage amplifier. As shown in FIG. 5, the clock signal amplifier circuit 152 is composed of, for example, three-stage amplifiers 152A, 152B, and 152C connected in multiple stages.

The clock signal amplifier circuit 152 is required to have high gain and wide band characteristics. The load capacitance in the clock signal amplifier circuit 152 is smaller than that in the clock waveform adjustment circuit 153 connected to the sampling circuit 3, which is a large load. However, since the gain and band per stage are limited depending on the process node of the device used, it is sufficient to configure the clock signal amplifier circuit 152 with amplifiers 152A, 152B, and 152C connected in multiple stages. A clock signal amplifier circuit 152 having high gain and band characteristics can be obtained.

Further, in the amplifiers 152A, 152B and 152C connected in multiple stages, the gain and the band may not be set to the same value, respectively, but may be connected so that the gain gradually decreases in the order of the amplifiers 152A, 152B and 152C. More specifically, the first-stage amplifier 152A is set to have the highest gain, and the input clock signal is amplified by using the first-stage amplifier 152A so as to have a waveform as close to a trapezoidal wave as possible. Then, when the slew rate of the signal is improved in the order of the second stage amplifier 152B and the third stage amplifier 152C, the high frequency component of the amplified signal is maintained, and the final stage third stage amplifier 152C The higher the frequency component remains.

As shown in FIG. 6, the frequency characteristic of the clock signal amplification circuit 152 having the amplifiers 152A, 152B, and 152C connected in multiple stages has a lower gain as the latter stage amplifier and a wider band as the latter stage amplifier. ing. Therefore, according to the second embodiment, the high gain and wideband characteristics of the clock signal amplifier circuit 152 described with reference to FIG. 2 can be obtained more efficiently.

<Third embodiment>
Next, a third embodiment of the present invention will be described. FIG. 7 is a block diagram showing a configuration example of the track and hold circuit 1b according to the third embodiment. In the following description, the same components as those in the first and second embodiments described above are designated by the same reference numerals, and the description thereof will be omitted.

The track-and-hold circuit 1b in the third embodiment is different from the first and second embodiments in that the clock signal amplifier circuit 152 is composed of the variable gain amplifier circuit 252. In the first embodiment, the relationship between the gain and the band of the clock signal amplifier circuit 152 is simplified, and a flat frequency characteristic is assumed. However, when inductor peaking or the like is used to improve the band, a flat frequency characteristic may not be obtained in the amplifier.

In this case, due to the large waveform distortion of the clock signal amplifier circuit 152, the amplitude, rise time Tr, and fall time Tf of the sampling clock signal generated by the clock waveform adjustment circuit 153 may deviate and become unstable. is there.

Further, when the amplitude of the input clock signal changes significantly, the clock signal amplifier circuit 152 having a constant gain also has a larger waveform distortion, so that the amplitude of the sampling clock signal, the rise time Tr, and the fall are similarly large. The time Tf may be deviated and may not be constant.

In such a case, if the clock signal amplifier circuit 152 is configured by the variable gain amplifier circuit 252, the gain of the clock signal amplifier circuit 152 can be adjusted according to the frequency and amplitude of the input clock signal. Further, the amplitude of the sampling clock signal output from the clock waveform adjustment circuit 153, and the rise time Tr and the fall time Tf become constant.

In the present embodiment, the amplitude of the sampling clock signal and the rise time Tr and the fall time Tf are not adjusted directly by the clock waveform adjustment circuit 153 that generates the sampling clock signal. This is because the sampling circuit 3 which becomes a large load is connected to the subsequent stage of the clock waveform adjustment circuit 153, so that in addition to the function of the clock waveform adjustment circuit 153 to reduce the signal gain and widen the bandwidth. This is because it is considered difficult to provide another function in terms of design.

Further, in the clock signal amplifier circuit 152 having a plurality of amplifiers 152A, 152B, 152C connected in multiple stages described in the second embodiment, the first stage amplifier 152A having a particularly large gain is provided by the variable gain amplifier circuit 252. It may be configured. As a result, the gain of the first-stage amplifier 152A (variable gain amplification circuit 252) is adjusted to a large amplitude according to the frequency and amplitude of the input clock signal, and the second-stage and third-stage amplifiers 152B, The 152C makes it possible to more efficiently amplify the signal in which the high frequency component is maintained.

According to the third embodiment, since the clock signal amplifier circuit 152 is composed of the variable gain amplifier circuit 252, the gain of the clock signal amplifier circuit 152 is adjusted according to the frequency and amplitude of the input clock signal, and has a constant amplitude. , And a sampling clock signal having a constant rise time Tr and a fall time Tf is generated.

<Fourth Embodiment>
Next, a fourth embodiment of the present invention will be described. FIG. 8 is a block diagram showing a configuration example of the track-and-hold circuit 1c according to the fourth embodiment. In the following description, the same components as those in the first to third embodiments described above are designated by the same reference numerals, and the description thereof will be omitted.

The track-and-hold circuit 1c in the fourth embodiment is common in that the clock signal amplifier circuit 152 described in the third embodiment is composed of the variable gain amplifier circuit 252. However, unlike the first to third embodiments, an automatic gain control (AGC: Auto Gain Control) circuit 154 that monitors the output of the variable gain amplifier circuit 252 and performs feedback control so as to have a constant amplitude is added. Has the same configuration.

In the track-and-hold circuit 1b described in the third embodiment, the gain of the variable gain amplifier circuit 252 is preset according to the frequency and amplitude of the input clock signal, or the performance of the track-and-hold circuit 1b is evaluated. It is necessary to make adjustments based on this. However, in the fourth embodiment, the amplitude of the variable gain amplifier circuit 252 becomes constant due to the feedback control by the AGC circuit 154. Therefore, regardless of the frequency and amplitude of the input clock signal, a sampling clock signal having a more stable and constant amplitude and a constant rise time Tr and fall time Tf is generated.

In the present embodiment, the output of the variable gain amplifier circuit 252 is branched to be the input signal of the AGC circuit 154. This is because, if the output of the clock waveform adjustment circuit 153 is monitored, the load on the clock waveform adjustment circuit 153 becomes even larger, which may cause deterioration of the frequency characteristics.

Although the embodiments of the track-and-hold circuit of the present invention have been described above, the present invention is not limited to the described embodiments, and various types that can be assumed by those skilled in the art within the scope of the invention described in the claims. It is possible to transform.

1, 1a, 1b, 1c ... Track and hold circuit, 2 ... Data input buffer, 3 ... Sampling circuit, 4 ... Output buffer, 5 ... Clock transmission circuit, 151 ... Clock input buffer, 152 ... Clock signal amplifier circuit, 152A, 152B, 152C ... Amplifier, 252 ... Variable gain amplifier circuit, 153 ... Clock waveform adjustment circuit, 154 ... AGC circuit.

Claims (6)

The first amplifier circuit that outputs the amplified signal that amplified the input signal, and
A second amplifier circuit that outputs a sampling clock signal with the amplified signal as a predetermined amplitude, and
A sampling circuit that samples the analog input signal at the frequency of the sampling clock signal,
With
The gain of the first amplifier circuit is larger than the gain of the second amplifier circuit, and the load of the second amplifier circuit is smaller than the load of the sampling circuit.
The first amplifier circuit is a track-and-hold circuit that amplifies the input signal to an amplitude larger than the predetermined amplitude of the sampling clock signal. The track-and-hold circuit according to claim 1, wherein the first amplifier circuit includes a plurality of amplifiers connected in multiple stages. The track-and-hold circuit according to claim 2, wherein the plurality of amplifiers have a gain of a first-stage amplifier larger than that of another amplifier. The track-and-hold circuit according to claim 1, wherein the first amplifier circuit includes a variable gain amplifier circuit. The track-and-hold circuit according to claim 3, wherein the first-stage amplifier is a variable gain amplifier. The track-and-hand according to claim 4, further comprising an automatic gain control circuit that monitors the output of the variable gain amplifier circuit and controls the gain of the variable gain amplifier circuit so that a constant amplitude is output. Hold circuit.