JP6780678B2 - Electro-optics - Google Patents

Description

The present invention relates to an electro-optical device and an electronic device in which a flexible substrate such as TCP (tape carrier package), FPC (flexible printed circuit), COF (Chip On Film) is arranged in a terminal group provided on the substrate.

In an electro-optical device provided with a liquid crystal panel (liquid crystal light valve) or the like, the liquid crystal panel and the flexible substrate are generally connected, and a number of video signals corresponding to the number of data lines are supplied from the flexible substrate. In order to realize high resolution of the electro-optical device, it is necessary to increase the number of panel terminals. On the other hand, there is a limit to the pitch interval of the panel terminals. For this reason, as the resolution increases, it becomes difficult to secure a terminal arrangement area for connecting the panel terminal and the flexible substrate.
Conventionally, the securing of the terminal arrangement area has been dealt with by adopting a configuration in which a terminal group composed of a plurality of terminals is arranged in parallel on the electro-optical panel (see Patent Document 1).

Japanese Unexamined Patent Publication No. 2012-194242

By the way, in the above-mentioned electro-optical device, it is necessary to reduce the required area of the terminal group of each stage in order to avoid the increase in size of the element substrate. Therefore, it becomes difficult to reduce the resistance of the power supply path via the flexible substrate, and there is a problem that stable power supply becomes difficult. Further, in the conventional electro-optical device, it becomes difficult to adjust the transmission characteristics of the signal wiring on the flexible substrate and the element substrate between the signal wiring, and the timing control of the display control circuit for driving the display unit formed on the element substrate becomes difficult. There is a problem that makes it difficult. Further, in the above-mentioned electro-optical device, if the load balance of each supply circuit on a plurality of flexible substrates for supplying a signal to the display control circuit via the terminal group of each stage is not appropriate, the power consumption of some supply circuits is not appropriate. Occurs a problem that becomes excessive.

The present invention has been made in view of the circumstances described above, and one of the problems to be solved is to realize a stable supply of electric power in an electro-optical device provided with a plurality of terminal groups. Further, in an electro-optical device provided with a plurality of terminal groups, facilitating timing control is one of the solutions. Further, in an electro-optical device provided with a plurality of terminal groups, one of the solutions is to make the load balance of each supply circuit on a plurality of flexible substrates appropriate.

The present invention is an electro-optical device including a display unit for displaying an image and a substrate on which a display control circuit for driving the display unit is formed. The substrate is provided with a first flexible substrate in order from the display control circuit. A first terminal group for connecting and a second terminal group for connecting the second flexible substrate are sequentially formed, and the display control circuit includes a sequence circuit that transitions to a state according to a timing signal, and is a sequence circuit of the sequence circuit. A signal indicating the writing destination of the video signal in the display unit is generated based on the state, and the signal wiring for supplying the timing signal is one of the first terminal group and the second terminal group. Provided is an electro-optical device characterized in that it is connected to a group of terminals.

According to this electro-optic device, since the signal wiring for supplying the timing signal to the sequential circuit is connected to only one terminal of the first terminal group or the second terminal group, the timing signal supply timing can be adjusted. This makes it easier, and the timing control of the display control circuit can be facilitated.

In a preferred embodiment, in the electro-optic device, a power supply wiring for supplying power to the display control circuit is connected to both the terminal of the first terminal group and the terminal of the second terminal group. Further, in a more preferable embodiment, the same type of power supply wiring is connected to each terminal on both sides in the terminal arrangement direction in the first terminal group and each terminal on both sides in the terminal arrangement direction in the second terminal group. ..

According to these aspects, stable supply of electric power to the display control circuit can be realized.

In a preferred embodiment, the display unit comprises a plurality of scanning lines, a plurality of data lines, and a pixel matrix including pixels provided corresponding to each intersection of the plurality of scanning lines and the plurality of data lines. Then, the display control circuit is a video signal supply means that outputs the video signal to the plurality of data lines, and a writing destination of the video signal output to the plurality of data lines based on the state of the sequential circuit. It is provided with a scanning line driving means for selecting a scanning line corresponding to a pixel to be obtained from the plurality of scanning lines and outputting a scanning pulse to the selected scanning line.

In a more preferred embodiment, the video signal supply means switches the data line to which the video signal is output based on the select signal, and the terminal to which the signal wiring for supplying the select signal is connected is , It belongs to the same terminal group as the terminal group to which the terminal to which the signal wiring for supplying the timing signal is connected belongs.

According to this aspect, the signal wiring for the timing signal and the signal wiring for the select signal are connected to the same terminal group, and the supply circuit mounted on the flexible board connected to this terminal group synchronizes with the timing signal. The select signal is generated. According to this aspect, it becomes easy to transmit in the display control circuit without breaking the phase relationship between the timing signal and the select signal generated by the supply circuit.

In a preferred embodiment, the signal wiring for supplying the timing signal is connected to the terminals of the first terminal group.

According to this aspect, the delay time of the timing signal can be shortened, so that high-speed operation of the electro-optical device can be realized.

In a preferred embodiment, the scan line driving means outputs the scan pulse for the selected scan line based on an enable signal given to each group of the plurality of scan lines, and the enable. The signal wiring for supplying a signal is distributed and connected to the first terminal group and the second terminal group.

According to this aspect, the load capacitance per signal wiring for supplying the enable signal can be reduced by grouping. Further, since the connection destination of each signal wiring for supplying the enable signal is divided into the first terminal group and the second terminal group, the drive of each signal wiring is carried out on the supply circuit on the first flexible board and the second flexible board. Since the supply circuits are shared, it is possible to prevent the power consumption of one supply circuit from becoming excessive.

It is a left side view of the electro-optic device 1000 which is one Embodiment of this invention. It is a perspective view of the electro-optic device 1000. It is a circuit diagram which shows the electrical structure of the main part of the electro-optical device 1000. It is a circuit diagram which shows the structure of the Y driver 102_L (102_R) of the electro-optic device 1000. It is a time chart which shows the waveform of each part of the Y driver 102_L (102_R). It is a top view which shows the wiring layout around the 1st terminal group 31 and the 2nd terminal group 32 of the element substrate 10. It is a top view which shows the layout of the terminal in the 1st terminal group 31 and the 2nd terminal group 32. It is explanatory drawing for demonstrating the signal wiring which goes through the video signal terminal of the 1st terminal group 31 and the 2nd terminal group 32. It is a circuit diagram which shows the structure of the protection circuit of the same embodiment. It is a perspective view which shows the structure of the projection type display device 3000 which is an application example of the same embodiment. It is a perspective view which shows the structure of the information portable terminal 4000 which is an application example of the same embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(A. Embodiment)
FIG. 1 is a left side view showing the configuration of the electro-optical device 1000 according to the embodiment of the present invention, and FIG. 2 is a perspective view showing the configuration of the electro-optic device 1000. The electro-optical device 1000 constitutes an active matrix type liquid crystal display device that forms a display unit of a small electronic device such as a projection type projector. The electro-optical device 1000 includes an electro-optical panel 1, a first supply circuit 21, a second supply circuit 22, a first Flexible Printed Circuits board 51, and a second flexible board 52. The electro-optical device 1000 may have, for example, a full high-definition pixel number of 2 times in the vertical direction and 2 times in the horizontal direction, and has a pixel number of 3840 × 2160. Further, each of the first supply circuit 21 and the second supply circuit 22 is, for example, a drive integrated circuit. The electro-optical panel 1 has a configuration in which a facing substrate 20 is placed on an element substrate 10. A pixel matrix 101 for displaying an image is formed on a portion of the surface of the element substrate 10 that overlaps with the facing substrate 20.

The element substrate 10 is sequentially provided with a first terminal group 31 and a second terminal group 32 in the order of proximity to the opposing substrate 20 along the Y direction shown in FIG. Here, the first flexible substrate 51 is thermocompression bonded to the first terminal group 31 via the anisotropic conductive film 41, and the second flexible substrate 52 is thermocompression bonded to the second terminal group 32 via the anisotropic conductive film 42. Is thermocompression bonded. The first flexible substrate 51 and the second flexible substrate 52 are made of, for example, polyimide formed into a film. As shown in FIG. 1, the first flexible substrate 51 connected to the first terminal group 31 is arranged so as to be superimposed on the second flexible substrate 52 connected to the second terminal group 32.

The resin member 63 covers the side surface 32b of the second terminal group 32 that extends in the X direction and is far from the facing substrate 20. The resin member 63 is formed so as to cover a portion connected to each side surface 32b of the element substrate 10 and the second flexible substrate 52.

The resin member 62 has a side surface 32a closer to the facing substrate 20 among the two side surfaces extending in the X direction of the second terminal group 32 and two side surfaces extending in the X direction of the first terminal group 31. It covers the side surface 31b farther from the facing substrate 20. The resin member 62 is formed so as to cover a portion connected to each side surface 32a of the element substrate 10 and the second flexible substrate 52 and a portion connected to each side surface 31b of the element substrate 10 and the first flexible substrate 51. ing.

The resin member 61 covers the side surface 31a, which is the side surface of the first terminal group 31 that extends in the X direction and is closer to the facing substrate 20 among the two side surfaces 31a and 31b. The resin member 61 is formed so as to cover a portion connected to each side surface 31a of the element substrate 10 and the first flexible substrate 51.

As shown in FIG. 2, in the electro-optical device 1000, the first flexible substrate 51 and the second flexible substrate 52 are connected to one side of the electro-optical panel 1.
The first supply circuit 21 is mounted on the first flexible substrate 51 by COF (Chip On Film) technology. The second supply circuit 22 is mounted on the second flexible substrate 52 by COF technology. The first flexible substrate 51 is laminated on the second flexible substrate 52. The first supply circuit 21 is laminated on the second supply circuit 22. As described above, in the present embodiment, the first flexible substrate 51 and the second flexible substrate 52 are attached so as to partially overlap each other in the direction (z direction) perpendicular to the display surface of the electro-optical panel 1.

Various signals output by the first supply circuit 21 are supplied to the first terminal group 31 connected to the first flexible substrate 51. Further, various signals output by the second supply circuit 22 are supplied to the second terminal group 32 connected to the second flexible substrate 52. The electro-optical panel 1 displays an image based on various signals supplied to the first terminal group 31 and various signals supplied to the second terminal group 32.

The first flexible substrate 51 and the second flexible substrate 52 are provided with wiring (omitted in FIGS. 1 and 2) for transmitting signals.
One end of the wiring of the first flexible board 51 is connected to the first terminal group 31 of the electro-optical panel 1, and the other end is connected to a control board (not shown) provided with an upper control circuit. Has been done. The first supply circuit 21 is electrically connected to the electro-optical panel 1 and the host control circuit via the wiring of the first flexible substrate 51.

One end of the wiring of the second flexible board 52 is connected to the second terminal group 32 of the electro-optical panel 1, and the other end is connected to a control board (not shown) provided with an upper control circuit. Has been done. The second supply circuit 22 is electrically connected to the electro-optical panel 1 and the host control circuit via the wiring of the second flexible substrate 52.

FIG. 3 is a circuit diagram showing an electrical configuration of a main part of the electro-optical device 1000. As shown in FIG. 3, the electro-optical device 1000 has a pixel matrix 101, two Y drivers 102_L and 102_R, and 1040 demultiplexers (hereinafter, abbreviated as DMPX) 103_1 to 103_1040. The pixel matrix 101 functions as a display unit for displaying an image, and the Y drivers 102_L and 102_R and the DMPX103_1 to 103_1040 function as a display control circuit for driving the pixel matrix 101.

The pixel matrix 101 corresponds to 2176 scanning lines SL1 to SL2176 extending in the X direction, 4160 data lines DL1 to DL4160 extending in the Y direction, and each intersection of these scanning lines and data lines. It has a pixel PX provided in the above. Here, the pixel PX has a pixel electrode (not shown) and a TFT (Thin Film Transistor) element (not shown) in which one of the three terminals is connected to the pixel electrode. The remaining two terminals of the three terminals of the TFT element are connected to the scanning line SLi (i = 1 to 2176) and the data line DLj (j = 1 to 4160).

The facing substrate 20 is formed with facing electrodes 101C facing the pixel electrodes of all the pixels PX of the pixel matrix 101. An electro-optical substance such as a liquid crystal (not shown in FIGS. 1 and 2) is sandwiched between the counter electrode 101C and the pixel electrode of each pixel PX of the pixel matrix 101. The pixel matrix 101 is formed in the gap between the element substrate 10 and the facing substrate 20.

The Y drivers 102_L and 102_R are arranged on both sides of the pixel matrix 101 in the X direction. The Y drivers 102_L and 102_R sequentially output scanning pulses to the scanning lines SL1 to SL2176 during one vertical scanning period in synchronization with each other, and scans to indicate the scanning line corresponding to the pixel PX to which the video signal is written. It is a line driving means.

The Y drivers 102_L and 102R have a start pulse DY instructing the output start timing of the scanning pulse, a two-phase clock CLY and CLYB instructing the shift timing of the start pulse DY, and a shift direction signal instructing the shift direction of the start pulse DY. A timing signal such as SR and enable signals ENBY_1 to ENBY_8 are given.

FIG. 4 is a circuit diagram showing the configurations of Y drivers 102_L and 102R. As shown in FIG. 4, the Y driver 102_L (102R) has a shift register 1021 and a pair of 2176 sets of NAND gates 1022 and an inverter 1023 connected to scanning lines SL1 to SL2176, respectively.

The shift register 1021 is a sequential circuit that transitions to a state according to a timing signal including a start pulse DY, a clock CLY, a CLYB, and a shift direction signal SR. More specifically, the shift register 1021 shifts the start pulse DY in synchronization with the clocks CLY and CLYB in the first direction or in the second direction opposite to the first direction. Which direction to shift is determined by the shift direction signal SR. The 2176 sets of NAND gates 1022 and the inverter 1023 sets connected to the scanning lines SL1 to SL2176 are based on the state of the shift register 1021 which is a sequential circuit, specifically, the output signal of each stage of the shift register 1021. The enable signal given to each is output as a scanning pulse. In the present embodiment, the shift register 1021 is used as the sequence circuit that changes the state according to the timing signal, but the sequence circuit is not limited to this. For example, a counter may be used instead of the shift register 1021.

FIG. 5 is a time chart showing waveforms of each part of the Y driver 102_L (102_R) shown in FIG. The shift register 1021 repeats the operation of sequentially shifting the start pulse DY having a pulse width corresponding to one cycle of the clocks CLY and CLYB for each vertical scanning period. FIG. 5 shows how the first-stage output signals Q1 to the fourth-stage output signals Q4 of the shift register 1021 sequentially become active levels.

The enable signals ENBY_1 to ENBY_8 are 8-phase pulses in which the pulse generation timings are deviated from each other by a time corresponding to 1/2 of one cycle of the clocks CLY and CLYB.

The set of the NAND gate 1022 and the inverter 1023 connected to the scanning line SL1 outputs the enable signal ENBY_1 generated during the period when the first stage output signal Q1 of the shift register 1021 is at the active level as a scanning pulse for the scanning line SL1. ..

The set of the NAND gate 1022 and the inverter 1023 connected to the scanning line SL2 outputs the enable signal ENBY_2 generated during the period when the first stage output signal Q1 of the shift register 1021 is at the active level as a scanning pulse for the scanning line SL2. ..

The set of the NAND gate 1022 and the inverter 1023 connected to the scanning line SL3 outputs the enable signal ENBY_3 generated during the period when the second stage output signal Q2 of the shift register 1021 is at the active level as a scanning pulse for the scanning line SL3. ..

The set of the NAND gate 1022 and the inverter 1023 connected to the scanning line SL4 outputs the enable signal ENBY_4 generated during the period when the second stage output signal Q2 of the shift register 1021 is at the active level as a scanning pulse for the scanning line SL4. ..

The same applies hereinafter, and during the period when the i'stage output signal Qi'of the shift register 1021 is at the active level, the scanning lines SLi-1 and SLi (where i = 2i') are output destinations of the scanning pulse. At that time, the enable signal ENBY_k + 1 (k is the remainder obtained by dividing i by 8) is output as a scanning pulse for the scanning line SLi-1, and the enable signal ENBY_k + 2 is output as a scanning pulse for the scanning line SLi.

The DMPX103_m (m = 1 to 1040) constitutes a video signal supply means for outputting a video signal to the data line DLj (j = 1 to 4160). Select signals SEL_1 to SEL_4 are given to the DMPX103_m (m = 1 to 1040). The select signals SEL_1 to SEL_4 are supplied in synchronization with the clocks CLY and CLYB supplied to the Y drivers 102_L and 102_R. The DMPX103_m (m = 1-1040) distributes the video signal VIDm (m = 1-1040) to the data lines DLj (j = 1-4160) based on the select signals SEL_1 to SEL_14.

More specifically, for example, the DMPX103_1040 sets the output destination of the video signal VID1040 to the data line DL4157 when the select signal SEL_1 is at the active level. Further, the DMPX103_1040 sets the output destination of the video signal VIDEO signal VIDEO 1040 to the data line DL4158 when the select signal SEL_2 is at the active level. Further, the DMPX103_1040 sets the output destination of the video signal VIDEO signal VIDEO 1040 to the data line DL4159 when the select signal SEL_3 is at the active level. Further, the DMPX103_1040 sets the output destination of the video signal VIDEO signal VIDEO 1040 to the data line DL4160 when the select signal SEL_4 is at the active level. In this way, the DMPX103_1040 switches the output destination of the video signal VIDEO 1040 based on the select signals SEL_1 to SEL_4. The same applies to other DMPX103_m (m = 1 to 1039).
The above is an outline of the configuration of the main part of the electro-optical device 1000.

FIG. 6 is a plan view showing a wiring layout around the first terminal group 31 and the second terminal group 32 on the element substrate 10. Further, FIG. 7 is a plan view showing the layout of the terminals constituting the first terminal group 31 and the second terminal group 32.

As shown in FIGS. 3 and 6, a protection circuit region 72 for the second terminal group 32 is provided between the first terminal group 31 and the second terminal group 32 on the element substrate 10. The element board 10 has a signal wiring for connecting an input signal terminal in the second terminal group 32 and an input node of the protection circuit in the protection circuit area 72, an output node of the protection circuit, and an input node in the display control circuit. A signal wiring for connecting to and is formed (not shown in FIG. 6).

In the element substrate 10, a protection circuit region 71 for the first terminal group 31 is provided between the region facing the facing substrate 20 (that is, the region of the display unit) and the first terminal group 31. The element board 10 includes a signal wiring for connecting the input signal terminal in the first terminal group 31 and the input node of the protection circuit in the protection circuit area 71, and an output node of the protection circuit and an input node in the display control circuit. A signal wiring is formed to connect the two.

As shown in FIG. 7, the first terminal group 31 and the second terminal group 32 have a power supply terminal for supplying the counter electrode voltage LCCOM to the counter electrode 101C of the display unit, and a high potential to the Y drivers 102_L and 102_R. There is a power supply terminal for supplying the power supply voltage VDDY and a power supply terminal for supplying the low potential power supply voltage VSSY to the Y drivers 102_L and 102_R.

In the present embodiment, in order to stabilize the power supply, the power supply terminals for supplying one type of power supply voltage (for example, voltage LCCOM) are both ends in the X direction of the first terminal group 31 and the second terminal group 32. It is provided at four locations at both ends in the X direction. Further, one power supply terminal has a wide metal pattern in which a plurality of adjacent terminals are short-circuited with each other. Then, between the first terminal group 31 and the second terminal group 32, the power supply terminals of the same type arranged in the Y direction are short-circuited by a metal pattern.

Therefore, the power supply voltages LCCOM, VDDY, and VSSY of each type supplied via the first flexible board 51 or the second flexible board 52 are two corresponding to the power supply voltages at both ends in the X direction of the first terminal group 31. The power supply voltage supply terminal and the two power supply voltage supply terminals corresponding to the power supply voltage at both ends of the second terminal group 32 in the X direction are passed in parallel. Each type of power supply voltage LCCOM, VDDY, and VSSY is supplied to the display unit and the display control circuit via the four power supply wirings on the element board 10 connected to these four power supply voltage supply terminals. Therefore, a stable supply of power supply voltage can be realized.

In the element substrate 10, the signal wiring for supplying the timing signal for controlling the operation of the shift register 1021 in the Y driver 102L and 102R, such as the clock CLY, CLYB, shift direction signal SR, and start pulse DY, is the first terminal group. It is connected only to the terminals in 31. If the connection destination of the signal wiring for supplying various timing signals is divided into the first terminal group 31 and the second terminal group 32, the propagation delay of both signal wirings will be deviated, and the timing control of the display control circuit will be difficult. This is because it may become.

Further, the signal wiring for supplying the select signals SEL_1 to SEL_4 is connected only to the terminals of the first terminal group 31 like the signal wiring for supplying the timing signal. This is because it is necessary to synchronize the select signals SEL_1 to SEL_4 supplied to the DMPX103_m (m = 1 to 1040) with the timing signals, particularly the clocks CLY and CLYB.

In the present embodiment, the first supply circuit 21 mounted on the first flexible substrate 51 outputs timing signals and select signals SEL_1 to SEL_1 synchronized with each other. In the present embodiment, the timing signal and the select signals SEL_1 to SEL_4 are supplied to the display control circuit via the respective terminals in the same first terminal group 31.

More specifically, the element substrate 10 has an input path from the left side and an input path from the right side of the DMPX103_m (m = 1 to 1040) as input paths for the select signals SEL_1 to SEL4 with respect to the DMPX103_m (m = 1 to 1040). Is provided (see FIG. 3). On the other hand, the first supply circuit 21 mounted on the first flexible substrate 51 outputs each of the select signals SEL_1 to SEL4 to two signal wirings, and in the first terminal group 31 via these separate signal wirings. It is supplied to the terminals in the terminal group labeled SEL (left side) on the left side of the above and the terminals in the terminal group labeled SEL (right side) on the right side in the first terminal group 31. Then, on the element substrate 10, four signal wirings for supplying select signals SEL_1 to SEL4 supplied to the terminal group represented by SEL (left side) in FIG. 7 to DMPX103_m (m = 1 to 1040) from the left side are provided. It is formed. Further, the element substrate 10 is formed with four signal wirings that supply the select signals SEL_1 to SEL4 supplied to the terminal group indicated as SEL (right side) to DMPX103_m (m = 1 to 1040) from the left side. ing.

According to such a configuration, the load per circuit (or output buffer) that outputs the select signals SEL_1 to SEL4 in the first supply circuit 21 on the first flexible substrate 51 is lightened, and DMPX103_m (m = 1). The select signals SEL_1 to SEL_4 supplied to -1040) can be synchronized with the timing signals supplied by the first supply circuit 21 to the Y drivers 102_L and 102_R.
As shown in FIG. 3, in the first terminal group 31, the eight terminals to which the select signals SEL_1 to SEL_4 are supplied and the second terminal group 32 formed at positions corresponding to these eight terminals. The eight terminals may or may not be connected one-to-one using eight signal wirings. When connecting, no signal is supplied from the second supply circuit 22 to the eight terminals of the second terminal group 32.

Next, the terminal for supplying the enable signal ENBY_k (k = 1 to 8) and the signal wiring will be described. As described above, in the present embodiment, the 8-phase enable signal ENBY_k (k = 1 to 8) is supplied to the display control circuit. As shown in FIG. 7, the signal wiring for supplying the enable signal ENBY_odd having an odd index k among the enable signals ENBY_k (k = 1 to 8) is connected only to the terminals of the second terminal group 32 and has an index. The signal wiring for supplying the enable signal ENBY_even in which k is an even number is connected only to the terminals of the first terminal group 31. In this way, eight types of enable signals are supplied to the display control circuit, and the connection destinations of the signal wirings for the enable signal ENBY_k (k = 1 to 8) are set to the first terminal group 31 and the second terminal group 32. The reasons for the division are as follows.

As described above, the enable signal is a signal that is the source of the scanning pulse. In the present embodiment, the 8-phase enable signal ENBY_k (k = 1 to 8) is used, but it is also possible to generate a scanning pulse from the 1-phase enable signal having a frequency eight times that of the enable signal ENBY_k (k = 1 to 8). However, in doing so, the one-phase enable signal is given to the 2176 NAND gates 1022 corresponding to the 2176 scanning lines SL1 to SL2176, respectively, and the shift register 1021 controls to switch the NAND gate 1022 through which the enable signal is passed. Will be done. In this case, a load composed of 2176 NAND gates 1022 will be connected to the signal wiring for transmitting the enable signal. Such a load is excessive and hinders high-speed driving of the electro-optical device 1000.

Therefore, in the present embodiment, 2176 scanning lines SL1 to SL2176 are divided into eight groups, and one type of enable signal ENBY_k is connected to one group of scanning lines, that is, 2176/8 = 272 scanning lines. It is supplied to the 272 NAND gates 1022. In this way, when the 8-phase enable signal ENBY_k (k = 1 to 8) is used, the load per signal line for transmitting the enable signal is reduced to 1/8 of the case of one phase.

Here, it is also conceivable to connect eight signal wirings for the enable signal ENBY_k (k = 1 to 8) to only one of the first terminal group 31 and the second terminal group 32. However, if, for example, eight signal wirings for the enable signal ENBY_k (k = 1 to 8) are connected only to the first terminal group 31, the first supply circuit 21 mounted on the first flexible board 51 is these eight. The NAND gates 1022 corresponding to the 2176 scanning lines SL1 to SL2176 are driven via the signal wiring of the above, and the power consumption of the first supply circuit 21 becomes excessive.

Therefore, in the present embodiment, the signal wiring for supplying the enable signal ENBY_even is connected only to the terminals of the first terminal group 31 and driven by the first supply circuit 21 on the first flexible substrate 51 to drive the enable signal ENBY_odd. The signal wiring for supplying the signal is connected only to the terminals of the second terminal group 32, and is driven by the second supply circuit 22 of the second flexible board 52. As shown in FIG. 3, since the enable signals ENBY_1 to ENBY_8 are input from the left side in the first terminal group 31 and the second terminal group 32, they are first input to the left side via the signal wiring formed on the element substrate 10. It is supplied to the arranged Y driver 102_L. Then, it is supplied to the Y driver 102_R arranged on the right side via the signal wiring provided on the upper part of the element substrate 10.

Next, the terminal for supplying the video signal VIDm (m = 1 to 1040) and the signal wiring will be described. The number of signal wirings for supplying the video signal VIDm (m = 1 to 1040) is large, and it cannot be connected to only one of the first terminal group 31 or the second terminal group 32. Therefore, in the present embodiment, as shown in FIG. 7, the connection destinations of the signal wirings for supplying the video signal VIDm (m = 1 to 1040) are distributed to the first terminal group 31 and the second terminal group 32. I let you. Specifically, among the signal wirings of the video signal VIDm (m = 1 to 1040) arranged in the X direction in the display circuit 100, the signal wiring of the video signal VIDodd having an odd index m is the second terminal group 32. At each terminal, the signal wiring of the video signal SIDeven having an even index m is connected to each terminal of the first terminal group 31.

In order to realize high-speed operation, it is necessary to arrange the propagation delay time until the video signal VIDm (m = 1 to 1040) reaches DMPX103_m (m = 1 to 1040). In the present embodiment, in order to make the propagation delay time of the video signal VIDm (m = 1 to 1040) uniform in a state where the connection destinations of the signal wirings are dispersed in the first terminal group 31 and the second terminal group 32, they are used. The configuration of the signal wiring of is being improved.

FIG. 8 is a plan view showing signal wiring via terminals for video signals of the first terminal group 31 and the second terminal group 32. FIG. 8 shows terminals 311 for the video signals VID488, 486, ..., Which are a part of the video signal VIDm having an even index m in the first terminal group 31. Further, FIG. 8 shows terminals 321 for the video signals VID487, 485, ..., Which are a part of the video signal VIDm having an odd index m in the second terminal group 32. In the present embodiment, the positions of the video signal terminals 311 in the first terminal group 31 and the video signal terminals 321 in the second terminal group 32 are the same in the X direction.

A protection circuit region 72 is provided between the first terminal group 31 and the second terminal group 32. Further, a protection circuit area 71 is provided between the first terminal group 31 and the display unit. A plurality of protection circuits Q are formed in the protection circuit area 72 and the protection circuit area 71.
FIG. 9 shows a circuit diagram of the protection circuit Q. As shown in this figure, the protection circuit Q is a protection circuit 7R, a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a field effect transistor having a metal oxide semiconductor structure, hereinafter simply referred to as a transistor) P1 and N channels. It includes a transistor N1. The gate 7Pg of the transistor P1 and the source 7Ps are short-circuited, and a high potential power supply voltage VDDY is supplied to the short circuit. On the other hand, the gate 7Ng of the transistor N1 and the source 7Ns are short-circuited, and a low potential power supply voltage VSSY is supplied there.
A protection resistor 7R is connected to the common drain 7D of the transistor P1 and the transistor N1. The voltage of the drain 7D common by this protection circuit Q, that is, the voltage of the signal wiring for the video signal is lower than the low potential power supply voltage VSSY by the threshold voltage of the transistor N1, and the voltage of the transistor P1 is lower than the high potential power supply voltage VDDY. It is limited to the high voltage range by the voltage. As a result, even if a high voltage is applied to the first terminal group 31 or the second terminal group 32 due to static electricity or the like, it is possible to prevent the display control circuit from being electrostatically destroyed. In addition, a plurality of similar protection circuits Q are formed in the protection circuit region 71.

As shown in FIG. 8, a pair of transistors P1 and transistors N1 are formed for one terminal 321 in the protection circuit region 72. The common drain 7D of the two transistors in the OFF state occupies the same position as the terminal 321 in the X direction. This point is the same in the protection circuit region 71.

The configuration of the signal path for the video signals VID487, VIDEO485, ... Via the terminal 321 belonging to the second terminal group 32 is as follows. For example, the signal path for the video signal VID487 includes signal wiring 325, signal wiring 721, and signal wiring 722. The signal wiring 325 connects the terminal 321 for the video signal VID487 and one end of the protection resistor 7R. The signal wiring 721 connects the other end of the protection resistor 7R to the drain 7D of the transistors P1 and N1. The signal wiring 722 extends from the drain 7D toward the display circuit 100 along the Y direction.

Here, the terminal 321 for the video signal VIDEO 487, the signal wiring 325, the protection resistor 7R, the drain 7D of the transistor, and the signal wiring 722 are on a straight line along the Y direction.

Further, the signal path for the video signal VID487 includes a signal wiring 723. The signal wiring 723 has a first section extending in a first direction (Y direction) toward the display circuit 100 side from the connection portion with the signal wiring 722. Further, the signal wiring 723 has a second section connected to the first section and extending in the second direction bent with respect to the first direction. Further, the signal wiring 723 is connected to the second section and extends in the first direction (Y direction) toward the center between the two terminals 311 for the video signals VID488 and VID486 of the first terminal group 31. There is a third section. Further, the signal path for the video signal VID487 passes through the center between the two terminals 311 from the connection portion with the signal wiring 723 and extends in the first direction (Y direction) toward the display control circuit. including.

Further, the signal path for the video signal VID487 includes a signal wiring 322 extending from the terminal 321 for the video signal VID487 toward the end of the element substrate 10 on the opposite side of the display control circuit.

In the above signal path for the video signal VID487, the signal wirings 322 and 723 are metal layer wirings in the same layer as the terminal 321, and the signal wirings 325, 721, 722 and 314 are metal layer wirings in a layer lower than the terminal 321. Is. Further, the terminal 311 is a metal layer wiring of the same layer as the terminal 321. Therefore, the terminal 311 of the first terminal group 31 and the signal wiring 314 for transmitting the video signal from the second terminal group 32 are metal layer wirings having different layers.

The signal paths for the video signals VID485, VID483, ... Other than the video signal VID487 passing through the second terminal group 32 have the same configuration.

The configuration of the signal path for the video signals VID488, VID486, ... Via the terminal 311 belonging to the first terminal group 31 is as follows. For example, the signal path for the video signal VID486 includes a signal wiring 315 that connects the terminal 311 for the video signal VID486 and one end of the protection resistor 71R. The other end of the protection resistor 71R is connected to a signal wiring (not shown) extending to the display circuit 100 side via the drain 7D of the transistor in the OFF state, similarly to the signal path for the video signal VID487.

Further, the signal path for the video signal VID486 includes a signal wiring 724. The signal wiring 724 has a first section extending from the terminal 311 for the video signal VID486 to the end of the element substrate 10 along the first direction (Y direction). Further, the signal wiring 724 has a second section connected to the first section and extending along the second direction bent with respect to the first direction. Further, the signal wiring 724 is connected to the second section, passes through the upper layer of the source 72S of the transistor in the first direction (Y direction), and is the center between the two terminals 311 for the video signals VID487 and VID485. There is a third section extending in the first direction (Y direction) toward.

Further, the signal path for the video signal VID486 includes wirings 324 and 323 extending from the connection portion with the signal wiring 724 to the end portion of the element substrate 10 through the center between the two terminals 311 for the video signal VID487 and VID485. Including. In the manufacturing process of the electro-optical panel 1, the signal wirings 322 and 323 are connected to the guard ring, but in the finished product, they are not connected to the guard ring. The signal wirings 322 and 323 may form ends at predetermined positions or may be connected to inspection terminals.

Next, a cross section of the signal path AA'for the video signal VID486 will be described. The element substrate 10 has a four-layer structure. The first layer is a polysilicon layer, and the second to fourth layers are metal wiring layers. As the material of the second layer to the fourth layer, aluminum or an aluminum alloy (for example, ALTi) can be used.

The signal wiring 323 is formed of a first layer (polysilicon layer). Further, the wiring 324 is formed by the second layer. The signal wiring 724 is formed by the fourth layer. The power supply wiring for supplying the high potential power supply voltage VDDY and the low potential power supply voltage is formed by the second layer and the third layer.
Next, the terminal 311 is configured by connecting the first layer, the second layer, the third layer, and the fourth layer with through holes. In this way, all four layers are used in order to provide the strength required for crimping with the first flexible substrate 51 and to reduce the resistance of the terminal 311. It is preferable that an ITO (Indium Tin Oxide) film is formed on the upper surface of the terminal 311. Further, it does not necessarily have to be composed of four layers, and may be composed of at least two or more layers.

In the protection circuit region 71, the resistor 7R is formed by a first layer (polysilicon layer). The signal wiring 711 connecting the resistor 7R and the protection circuit Q is formed by the fourth layer.
Then, the protection circuit Q is configured by using the first layer, the third layer, and the fourth layer.
Further, the signal wiring 712 is formed by the fourth layer, and the signal wiring 713 is formed by the fourth layer.

Next, a cross section of the signal path BB'for the video signal VID486 will be described. The signal wiring 322 is formed of a first layer (polysilicon layer). The terminal 321 is configured by connecting the first layer, the second layer, the third layer, and the fourth layer with through holes. It is preferable that an ITO film is formed on the upper surface of the terminal 321.

In the protection circuit region 72, the resistor 7R is formed by a first layer (polysilicon layer). Then, the protection circuit Q is configured by using the first layer, the third layer, and the fourth layer.
Further, the signal wiring 722 is configured by using the fourth layer, and the signal wiring 723 and the signal wiring 314 are configured by using the second layer. Further, the wiring 714 is configured by using the fourth layer.

A second layer is used between the protection circuit area 72 and the first terminal group 31. The wiring 714 leading to the display control circuit uses the same fourth layer as the signal wiring 713. Further, between the first terminal group 31 and the second terminal group 32, the signal wiring 724 is formed by using the fourth layer, and the signal wiring 723 is formed by using the second layer different from the fourth layer. Here, the signal wiring 724 and the signal wiring 723 do not overlap when viewed in a plan view from a direction perpendicular to the element substrate 10.
Here, the thickness of the signal wiring 724 is preferably, for example, 0.2 μm to 0.4 μm, and the width thereof is preferably 5 to 10 μm. On the other hand, the thickness of the signal wiring 723 is preferably 0.25 μm to 0.45 μm, and the width thereof is preferably 15 to 30 μm. Further, the distance between the second layer and the fourth layer is preferably 1 μm to 1.5 μm.

The signal paths for the video signals VID488, VID485, ... Other than the video signals VID488 and VID487 that pass through the first terminal group 31 have the same configuration.

In the signal path for the video signal passing through the first terminal group 31, the signal wiring extending from the terminal 311 to the end of the element substrate 10 is provided with the capacitance connected to the signal path and the second terminal. This is to make the capacitance connected to the signal path for the video signal passing through the group 32 substantially equal.

In the present embodiment, the second terminal group 32 is farther from the display control circuit than the first terminal group 31. Therefore, if the wiring width of the signal wiring for supplying the video signal is the same for the second terminal group 32 and the first terminal group 31, the second terminal group 31 is compared with the resistance of the signal wiring passing through the first terminal group 31. The resistance of the signal wiring passing through the terminal group 32 increases. Therefore, in the present embodiment, by adjusting the width of the signal wiring and the like, the resistance of the signal wiring of the video signal VID_even from the first terminal group 31 to DMPX103_m and the signal of the video signal VID_odd from the second terminal group 32 to DMPX103_m. The resistance of the wiring is almost equal.

Further, in the present embodiment, since the signal wiring for the video signal passing through the second terminal group 32 is passed between the two adjacent terminals 311 of the first terminal group 31, the second terminal group The wiring length of the signal wiring for the video signal passing through the 32 can be shortened as much as possible.

Therefore, according to the present embodiment, the resistance of both the signal wiring passing through the first terminal group 31 and the signal wiring passing through the second terminal group 32 can be reduced.

Therefore, according to the present embodiment, the propagation delay time of the video signal VIDm (m = 1 to 1040) can be shortened as much as possible, and can be aligned to realize high-speed operation of the electro-optical device 1000.

Further, in the present embodiment, the wiring 314 passing between the adjacent terminals 311 of the first terminal group 31 is a wiring of a layer different from that of the terminal 311 and passes between the adjacent terminals 321 of the second terminal group 32. The wiring 324 is a different layer of wiring from the terminal 321. Therefore, in the present embodiment, it is possible to reduce the cross-coupling between the signal wirings for two adjacent video signals.

Further, according to the present embodiment, in order to direct the signal wiring for the video signal passing through the second terminal group 32 between the two adjacent terminals 311 of the first terminal group 31, the drain 7D of the transistor is used. A signal wiring 723 having an inclined section is provided in the region between the first terminal group 31 and the terminal group 31. According to this aspect, the electrostatic noise input to the terminal 321 is given to the signal wiring 723 in a state of passing through the protection resistor 7R and the drain 7D of the transistor and being sufficiently weakened, and thus is given to the signal wiring 723 in the Y direction of the signal wiring 723. It is possible to prevent discharge from the edge generated at the boundary between the section and the inclined section, and prevent the signal wiring 723 from being blown.

(B. Modification example)
Although the embodiment of the present invention has been described above, it is of course possible to add the following modifications to this embodiment.

(B-1) In the above-described embodiment, half of the eight signal wirings for supplying the enable signal are connected to the first terminal group 31, and the other half are connected to the second terminal group 32. However, this is an example, and the number of signal wirings for the enable signal connected to the first terminal group 31 and the number of signal wirings for the enable signal connected to the second terminal group 32 may be changed. That is, the first terminal group 31 is set so that both the power consumption of the first supply circuit 21 on the first flexible board 51 and the power consumption of the second supply circuit 22 on the second flexible board 52 are appropriate values. The number of signal wirings for the enable signal to be connected and the number of signal wirings for the enable signal to be connected to the second terminal group 32 may be adjusted.

(B-2) In the above-described embodiment, the case where a 3-terminal element represented by a TFT is used as the switching element of the pixel circuit has been described, but a 2-terminal element such as a diode may be used. .. However, when a two-terminal element is used as the switching element of the pixel circuit, the scanning line is formed on one substrate, the data line is formed on the other substrate, and the two-terminal element is either a scanning line or a data line. It is necessary to form between one of them and the pixel electrode. In this case, the pixel circuit is composed of a two-terminal element connected in series between the scanning line and the data line, and a liquid crystal.

(B-3) In the above-described embodiment, the active matrix type liquid crystal display device has been taken up as an example of the electro-optical device, but the present invention is not limited to this, and the passive type using an STN (Super Twisted Nematic) liquid crystal or the like is used. It is also applicable to. Further, the above-described embodiment may be applied to an electro-optical device having an organic light emitting diode element using an organic EL (Electro Luminescent) as an electro-optical material as an electro-optical device. The present invention also applies to an electro-optical panel using an electro-optical material other than an organic EL. An electro-optical substance is a substance whose optical characteristics such as transmittance and brightness change depending on the supply of an electric signal (current signal or voltage signal). For example, for a display panel using a liquid crystal or a luminescent polymer as an electro-optical material, or an electrophoretic display panel using microcapsules containing a colored liquid and white particles dispersed in the liquid as an electro-optical material. However, the present invention can be applied in the same manner as in the above-described embodiment. Further, the present invention can be applied to a twist ball display panel in which twist balls painted in different colors for regions having different polarities are used as an electro-optical material in the same manner as in the above-described embodiment. Further, the present invention can be applied to a toner display panel using black toner as an electro-optical substance in the same manner as in the above-described embodiment. Further, the present invention can be applied to various electro-optical panels such as a plasma display panel using a high-pressure gas such as helium or neon as an electro-optical substance, as in the above-described embodiment.

(C. Application example)
FIG. 10 is a schematic view of a projection type display device (three-panel projector) 3000 to which the electro-optical device 1000 is applied. The projection type display device 3000 is configured to include three electro-optical devices 1000 (1000R, 1000G, 1000B) corresponding to different display colors (red, green, blue). The illumination optical system 3001 supplies the red component r of the light emitted from the illumination device (light source) 3002 to the electro-optical device 1000R, supplies the green component g to the electro-optical device 1000G, and supplies the blue component b to the electro-optical device 1000B. Supply to. Each electro-optical device 1000 functions as an optical modulator (light valve) that modulates each monochromatic light supplied from the illumination optical system 3001 according to a display image. The projection optical system 3003 synthesizes the emitted light from each electro-optical device 1000 and projects it onto the projection surface 3004. By applying the above-mentioned electro-optical device 1000, a small projection type display device 3000 capable of high-definition display can be easily realized.

FIG. 11 is a diagram showing a configuration example of an information mobile terminal (PDA: Personal Digital Assistants) to which the electro-optical device 1000 is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001 and a power switch 4002, and an electro-optic device 1000 as a display unit. When the power switch 4002 is operated, various information such as an address book and a schedule book are displayed on the electro-optical device 1000.

In addition to the electronic devices shown in FIGS. 9 to 11, the electronic devices to which the electro-optical device 1000 is applied include digital still cameras, LCD TVs, viewfinder type, monitor direct view type video tape recorders, car navigation devices, pagers, and the like. Examples include electronic organizers, calculators, devices equipped with touch panels, and the like. The above-mentioned electro-optical device can be applied as a display unit of these various electronic devices.

1000 ... Electro-optical device, 1 ... Electro-optical panel, 10 ... Element board (board), 20 ... Opposed board, 21 ... 1st supply circuit, 22 ... 2nd supply circuit, 31 ... 1st terminal group, 32 ... 2nd Terminal group, 51 ... 1st flexible substrate, 52 ... 2nd flexible substrate, 41, 42 ... anisotropic conductive film, 61, 62, 63 ... resin member, 100 ... display circuit, 101 ... pixel matrix, 101C ... counter electrode , PX ... pixels, SL1-SL2176 ... scanning lines, DL1-DL4160 ... data lines, 102_L, 102_R ... Y drivers, 103_1 to 103_1040 ... DMPX, 1021 ... shift registers, 1022 ... NAND gates, 1023 ... inverters, 311,321 ... Terminals, 322-325, 721-724,314,315,712-714 ... Wiring, 7R, 7R ... Protection resistance, Q ... Protection circuit, 7Pg, 7Ng ... Gate, 7D ... Drain, 3000 ... Projection type display device, 4000 … Information mobile terminal.

Claims (8)

In an electro-optical device provided with a display unit for displaying an image and a substrate on which a display control circuit for driving the display unit is formed.
On the board, a first terminal group for connecting the first flexible board and a second terminal group for connecting the second flexible board are arranged in order from the display control circuit.
The display control circuit includes a sequential circuit that transitions to a state according to a timing signal, and generates a signal indicating a writing destination of a video signal in the display unit based on the state of the sequential circuit.
An electro-optical device, wherein the signal wiring for supplying the timing signal is connected only to the terminals of the first terminal group among the first terminal group and the second terminal group . The electro-optical device according to claim 1, wherein the power supply wiring for supplying power to the display control circuit is connected to both the terminal of the first terminal group and the terminal of the second terminal group. 2. The second aspect of the present invention is characterized in that the same type of power supply wiring is connected to each terminal on both sides in the terminal arrangement direction in the first terminal group and each terminal on both sides in the terminal arrangement direction in the second terminal group. The electro-optical device described in. The display unit
With multiple scan lines
With multiple data lines
A pixel matrix composed of pixels provided corresponding to each intersection of the plurality of scanning lines and the plurality of data lines is provided.
The display control circuit
A video signal supply means that outputs the video signal to the plurality of data lines, and
Based on the state of the sequential circuit, a scanning line corresponding to a pixel to which the video signal output to the plurality of data lines is written is selected from the plurality of scanning lines, and a scanning pulse is applied to the selected scanning line. The electro-optical device according to any one of claims 1 to 3, further comprising a scanning line driving means for outputting. The video signal supply means switches the data line to which the video signal is output based on the select signal.
4. The terminal to which the signal wiring for supplying the select signal is connected belongs to the same terminal group as the terminal group to which the terminal to which the signal wiring for supplying the timing signal is connected belongs. The electro-optical device described in. In an electro-optical device provided with a display unit for displaying an image and a substrate on which a display control circuit for driving the display unit is formed.
On the board, a first terminal group for connecting the first flexible board and a second terminal group for connecting the second flexible board are arranged in order from the display control circuit.
The display control circuit includes a sequential circuit that transitions to a state according to a timing signal, and generates a signal indicating a writing destination of a video signal in the display unit based on the state of the sequential circuit.
The signal wiring for supplying the timing signal is connected to the terminal of one of the first terminal group or the second terminal group.
The display unit
With multiple scan lines
With multiple data lines
A pixel matrix composed of pixels provided corresponding to each intersection of the plurality of scanning lines and the plurality of data lines is provided.
The display control circuit
A video signal supply means that outputs the video signal to the plurality of data lines, and
Based on the state of the sequential circuit, a scanning line corresponding to a pixel to which the video signal output to the plurality of data lines is written is selected from the plurality of scanning lines, and a scanning pulse is applied to the selected scanning line. It is equipped with a scanning line driving means for outputting.
The scanning line driving means outputs the scanning pulse for the selected scanning line based on an enable signal given to each group in which the plurality of scanning lines are grouped.
An electro-optical device characterized in that signal wiring for supplying the enable signal is distributed and connected to the first terminal group and the second terminal group. The electro-optical device according to claim 6, wherein the power supply wiring for supplying power to the display control circuit is connected to both the terminal of the first terminal group and the terminal of the second terminal group. 7. The claim 7 is characterized in that the same type of power supply wiring is connected to each terminal on both sides in the terminal arrangement direction in the first terminal group and each terminal on both sides in the terminal arrangement direction in the second terminal group. The electro-optical device described in.

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