JP6780542B2 - Manufacturing method of power converter - Google Patents

Description

The techniques disclosed herein relate to methods of manufacturing power converters.

The power conversion device uses a large number of semiconductor elements (semiconductor elements for power conversion) through which a large current flows. In order to reduce the load on each semiconductor element, semiconductor elements having the same specifications may be connected in parallel, and the parallel connection may be used as if it were one semiconductor element (for example, Patent Document 1).

JP-A-2016-163396

Even semiconductor devices with the same specifications have slightly different voltage characteristics (resistance characteristics) due to manufacturing errors. The voltage characteristic is, for example, a voltage drop when the semiconductor element is a diode, and an on-voltage when the semiconductor element is a transistor. When two semiconductor elements are connected in parallel, if the voltage characteristics are slightly different, a large amount of current will flow through one of the semiconductor elements. Therefore, even if two semiconductor elements are connected in parallel, the load of all the semiconductor elements is not simply halved. If the difference in voltage characteristics between the two semiconductor elements connected in parallel is large, the bias of the current flowing through the two semiconductor elements becomes large, and the load of one semiconductor element does not become as small as expected. In a power conversion device including parallel connection of two semiconductor elements, a technique for reducing the bias of the current flowing through the two semiconductor elements connected in parallel is desired.

The present specification discloses a method of manufacturing a power conversion device including a plurality of sets of parallel connections of two semiconductor elements. The manufacturing method includes a sorting step, an extraction step, and a connecting step. In the sorting process, a plurality of semiconductor elements for power conversion are divided into a first group in which the voltage characteristics of the semiconductor elements are within a predetermined range including a design value, a second group in which the voltage characteristics are larger than a predetermined range, and a voltage characteristic. Is sorted into a third group smaller than a predetermined range. In the extraction step, at least one semiconductor element is extracted from the first group, and the rest is extracted from the second group and the third group to collect a predetermined even number of semiconductor elements in total. The total number of semiconductor elements for power conversion is the total number of semiconductor elements required for one power conversion device. In other words, it is the total number of semiconductor elements used as if they were one element in a set of two. The connection step is a step of connecting two semiconductor elements collected in the extraction step in parallel. More specifically, in the connection step, the semiconductor element of the second group is connected in parallel with another semiconductor element of the second group or the semiconductor element of the first group. The semiconductor element of the third group is connected in parallel with another semiconductor element of the third group or the semiconductor element of the first group. According to the above manufacturing method, the semiconductor element belonging to the group having the largest voltage characteristic (second group) and the semiconductor element belonging to the group having the smallest voltage characteristic (third group) are not connected in parallel. Therefore, the current bias can be reduced in the two semiconductor elements connected in parallel. In the extraction step, "extracting the rest from the second group and the third group and collecting a predetermined even number of semiconductor elements in total" means that all the remaining semiconductor elements are extracted from the second group (or It may be extracted (from the third group).

Details of the techniques disclosed herein and further improvements will be described in the "Modes for Carrying Out the Invention" below.

It is a circuit diagram of an example of a power conversion device. It is a perspective view of a semiconductor module. It is a top view of the power conversion device. It is a schematic diagram explaining the sorting process. It is a figure explaining the extraction process. It is a figure explaining the connection process. It is a top view explaining the example of another combination of semiconductor modules. It is a top view of the power conversion apparatus composed of the semiconductor modules of another combination. It is a top view explaining the example of still another combination of semiconductor modules.

The manufacturing method of the Example will be described with reference to the drawings. First, the power conversion device that is the target of the manufacturing method of the embodiment will be described. FIG. 1 shows a circuit diagram of the power conversion device 2. The power conversion device 2 is an inverter that converts the DC power of the battery 80 into three-phase AC power suitable for driving the motor 83. The inverter includes a total of 12 transistors 6 and 12 diodes 7. The transistor 6 is, for example, an IGBT (Insulated Gate Bipolar Transistor), which is a semiconductor for power conversion. The 12 transistors 6 have the same specifications. The 12 diodes 7 have the same specifications. The power conversion device 2 includes the transistor 6 and the diode 7 shown in the drawing, and a control circuit for generating a drive signal of the transistor 6, but the drawing thereof is omitted.

The plurality of transistors 6 are a set of two, and two transistors 6 of each set are connected in parallel. Further, a diode 7 is connected to each transistor 6 in antiparallel. The same drive signal is supplied to the gates of the two transistors 6 connected in parallel, and the two transistors 6 are turned on and off at the same timing. The two transistors 6 connected in parallel operate as if they were one transistor. The parallel connection of two transistors 6 that operate as if they were one transistor is hereinafter referred to as a "parallel circuit" for convenience of explanation.

In the power conversion device 2, two sets of parallel circuits are connected in series. Three sets of series connections of the parallel circuit are connected in parallel. The three sets of series connections are connected in parallel between the positive electrode wire 81 and the negative electrode wire 82. The positive electrode wire 81 is connected to the positive electrode end of the battery 80, and the negative electrode wire 82 is connected to the negative electrode terminal of the battery 80. The transistor (parallel circuit) on the positive electrode wire 81 side is called the upper arm, and the transistor (parallel circuit) on the negative electrode wire 82 side is called the lower arm. Alternating current is output from the midpoint of each of the three sets of series connections. From the midpoint of the three sets of series connections, alternating current with a phase shift of 120 degrees is output. That is, three-phase alternating current is output from the midpoint of three sets of series connections. The generated three-phase alternating current is supplied to the motor 83.

One transistor 6 and one diode 7 connected in antiparallel to the transistor 6 are housed in one semiconductor module 3. The power conversion device 2 is composed of 12 semiconductor modules 3. When distinguishing each of the twelve semiconductor modules, reference numeral 3 is indicated by adding an alphabetic character of an. FIG. 2 shows a perspective view of the semiconductor module 3. The semiconductor module 3 is a device in which two semiconductor elements (transistor element 16 and diode element 17) are sealed in a resin package 14. The transistor element 16 corresponds to the transistor 6 of FIG. 1, and the diode element 17 corresponds to the diode 7 of FIG. That is, the transistor element 16 is a semiconductor element for power conversion.

Package 14 is a rectangular parallelepiped. For convenience of explanation, the Z-axis positive direction of the coordinate system in the figure is referred to as "upper". Two power terminals (positive electrode terminal 12 and negative electrode terminal 13) are provided on the upper surface of the package 14, and a plurality of control terminals 85 are provided on the lower surface of the package 14. The transistor element 16 and the diode element 17 are connected in antiparallel inside the package 14, the positive electrode terminal 12 is electrically connected to the high potential side of the antiparallel connection, and the negative electrode terminal 13 is connected to the low potential side of the antiparallel connection. It is conducting. The control terminal 85 is a sensor signal terminal connected to a gate terminal connected to the gate of the transistor element 16 and a temperature sensor (not shown) for measuring the temperature of the transistor element 16. Although not shown, the package 14 is flat, and heat radiating plates that release heat from the transistor element 16 and the diode element 17 to the outside are exposed on the wide surfaces on both sides.

The power conversion device 2 includes 12 semiconductor modules 3a-3n. FIG. 3 shows a plan view of the power conversion device 2. FIG. 3 is a view in which the cover of the housing 90 of the power conversion device 2 is removed. A part of the housing 90 (the part corresponding to the left side in FIG. 3) is not shown. The stacking unit 10 is housed in the housing 90. The stacking unit 10 is a device in which a plurality of semiconductor modules 3 and a plurality of coolers 4 are laminated. In FIG. 3, the semiconductor module 3 is painted in gray to make the figure easier to see.

The cooler 4 is flat, and the plurality of coolers 4 are arranged in parallel so that their wide surfaces face each other. Two semiconductor modules 3 are sandwiched between adjacent coolers 4. Six cooler spaces are formed by the seven coolers 4, and two semiconductor modules 3 are sandwiched in each cooler space. The two semiconductor modules 3 are sandwiched so that their respective wide surfaces on which the heat radiating plate is exposed are in contact with the cooler 4. Two refrigerant pipes 92 and 93 pass through the plurality of coolers 4. The inside of the cooler 4 is a cavity, and a liquid refrigerant flows through the cavity. One end of the refrigerant pipes 92 and 93 extends outside the housing 90. A refrigerant circulation device (not shown) is connected to one end of the refrigerant pipes 92 and 93. Refrigerant is distributed to each cooler 4 through one of the refrigerant pipes 92. The refrigerant absorbs heat from the semiconductor module 3 adjacent to the cooler 4 while passing through the cooler 4. The refrigerant that has absorbed heat is discharged to the outside through the other refrigerant pipe 93. The refrigerant discharged to the outside returns to the refrigerant circulation device, is cooled, and is sent to the stacking unit 10 again.

A spring 91 is inserted between one end of the stacking unit 10 and the side wall of the housing 90, and the spring 91 loads the stacking unit 10 in the stacking direction of the cooler 4 and the semiconductor module 3. Due to the load of the spring 91, the cooler 4 and the semiconductor module 3 are in close contact with each other to improve the heat transfer characteristics.

The two semiconductor modules 3 sandwiched between the adjacent coolers 4 are connected by a positive electrode bus bar 8a-8f and a negative electrode bus bar 9a-9f. The semiconductor modules 3a and 3b are connected in parallel by the positive electrode bus bar 8a and the negative electrode bus bar 9a. The semiconductor modules 3b and 3c, 3d and 3e, 3e and 3f, 3g and 3h, 3j and 3k, 3m and 3n are also connected in parallel by the corresponding positive electrode bus bar 8 and negative electrode bus bar 9, respectively.

The parallel connection of the two semiconductor modules 3 corresponds to the parallel circuit described above. The same drive signal is supplied to the transistor elements 16 of the two semiconductor modules 3 included in each parallel connection (parallel circuit). The transistor elements 16 of the two semiconductor modules 3 included in the parallel circuit are turned on and off at the same timing, and operate as if they were one transistor element.

All transistor elements 16 have the same specifications. However, due to manufacturing errors, the performance of the plurality of transistor elements 16 is slightly different. For example, the on-voltages of the plurality of transistor elements 16 are distributed in a predetermined range. The on-voltage distribution is, for example, a normal distribution centered on the design value. When two transistor elements 16 connected in parallel are turned on and off at the same timing, if the on-voltages are different, the current flowing through the two transistor elements 16 is biased. The permissible current of the power converter 2 is determined in consideration of the bias. The smaller the current bias, the larger the permissible current of the power converter 2. Hereinafter, a method of manufacturing the power conversion device 2 including a plurality of parallel circuits of the two semiconductor modules 3 (two transistor elements 16) will be described. The manufacturing method can reduce the bias of the current flowing through the two transistor elements 16 in the parallel circuit.

One transistor element 16 (and one diode element 17) is housed in one semiconductor module 3. In the following manufacturing method, a plurality of semiconductor modules 3 are sorted into three groups, but sorting the semiconductor modules 3 is equivalent to sorting the transistor elements 16.

First, a plurality of semiconductor modules 3 are manufactured. Since the plurality of semiconductor modules 3 are manufactured by a known method, the description thereof will be omitted. The main steps of the manufacturing method of the power conversion device 2 are a sorting step, an extraction step, and a connecting step.

(Sorting step) In this step, a plurality of semiconductor modules 3 are divided into a first group in which the on-voltage of the transistor element 16 is within a predetermined range including a design value, and a second group in which the on-voltage is larger than a predetermined range. Sort into a third group whose on-voltage is smaller than a predetermined range. The predetermined range is set within the range of the standard deviation (commonly known as sigma) of the normal distribution of the on-voltage. FIG. 4 shows a schematic diagram illustrating the sorting process. The upper view of FIG. 4 represents the entire group of the plurality of semiconductor modules 3. The on-voltage of each semiconductor module 3 (transistor element 16) of this overall group is measured, and each semiconductor module 3 (transistor element 16) is divided into corresponding groups according to the magnitude of the on-voltage. The lower side of FIG. 4 shows the semiconductor module after sorting. In FIGS. 4 and 4 and subsequent figures, the semiconductor modules belonging to the first group are represented by reference numeral 31, and the figures of the semiconductor modules are hatched in medium density gray to distinguish them from the other groups. Further, the semiconductor module belonging to the second group is represented by reference numeral 32, and the figure of the semiconductor module is hatched in light gray to distinguish it from other groups. Further, the semiconductor module belonging to the third group is represented by reference numeral 33, and the figure of the semiconductor module is hatched in dark gray to distinguish it from other groups. When distinguishing each of the plurality of semiconductor modules 31 of the first group, the letters a, b, etc. are added to the reference numerals 31. When distinguishing each of the plurality of semiconductor modules 32 of the second group, the letters a, b, etc. are added to the reference numerals 32. When distinguishing each of the plurality of semiconductor modules 33 of the third group, the letters a, b, etc. of reference numeral 33 are added. Further, when the semiconductor modules of the 1st to 3rd groups are expressed without distinction, they are referred to as "semiconductor module 3" as before.

(Extraction Step) In this step, the number of semiconductor modules 3 required for one power conversion device is extracted from the first to third groups. Here, at least one semiconductor module 3 (transistor element 16) is extracted from the first group, and the rest is extracted from the second group and the third group, for a total of 12 semiconductor modules 3 (transistor elements). 16) Collect. In this embodiment, one semiconductor module 31 is extracted from the first group. Five semiconductor modules 32a-32e are extracted from the second group. Six semiconductor modules 33a-33f are extracted from the third group. The laminated unit 10 is assembled with a total of 12 semiconductor modules 3 collected. FIG. 5 shows a plan view of the laminated unit 10 in which the semiconductor modules 3 collected in the extraction step are incorporated. When assembling the stacking unit 10, the semiconductor modules 32a-32e belonging to the second group are concentrated on one end in the stacking direction (X direction in the drawing). The semiconductor modules 33a-33f belonging to the third group are centrally arranged at the other end in the stacking direction. The semiconductor module 31 belonging to the first group is arranged between the first group and the second group. Further, two semiconductor modules 3 are sandwiched between two adjacent coolers 4.

(Connecting Step) In this step, the semiconductor modules 3 collected in the extraction step are made into a set of two and connected in parallel. At this time, the semiconductor modules 32a-32e of the second group are connected in parallel with another semiconductor module of the second group or the semiconductor module 31 of the first group. The semiconductor modules 33a-33f of the third group are connected in parallel with another semiconductor module of the third group or the semiconductor module 31 of the first group. For convenience of explanation, this connection relationship is referred to as a "bias reduction connection relationship".

FIG. 6 shows a laminated unit 10 in which two positive electrode bus bars 8a-8f and two negative electrode bus bars 9a-9f are connected in parallel. FIG. 6 is a plan view showing a state in which the laminated unit 10 to which the bus bars 8 and 9 are connected is housed in the housing 90.

As described above, the semiconductor modules 32a-32e belonging to the second group are concentrated on one end side in the stacking direction, and the semiconductor modules 33a-33f belonging to the third group are concentrated on the other end side in the stacking direction. A semiconductor module 31 belonging to the first group is arranged between them. With such an arrangement, the above-mentioned bias reduction connection relationship is realized by connecting the two semiconductor modules 3 arranged between the adjacent coolers 4 in parallel.

The semiconductor modules 32a and 32b belonging to the second group are connected in parallel by the positive electrode bus bar 8a and the negative electrode bus bar 9a. The semiconductor modules 32c and 32d belonging to the second group are connected in parallel by the positive electrode bus bar 8b and the negative electrode bus bar 9b. The semiconductor module 32e belonging to the second group is connected in parallel with the semiconductor module 31 belonging to the first group by the positive electrode bus bar 8c and the negative electrode bus bar 9c. The semiconductor modules 33a and 33b belonging to the third group are connected in parallel by the positive electrode bus bar 8d and the negative electrode bus bar 9d. The semiconductor modules 33c and 33d belonging to the third group are connected in parallel by the positive electrode bus bar 8e and the negative electrode bus bar 9e. The semiconductor modules 33e and 33f belonging to the third group are connected in parallel by the positive electrode bus bar 8f and the negative electrode bus bar 9f. The semiconductor modules 32a and 32b form the parallel circuit described above. The semiconductor modules 32c and 32d, 32e and 31, 33a and 33b, 33c and 33d, and 33e and 33f also form a parallel circuit, respectively.

The on-voltage of the semiconductor module 32 of the second group is larger than the predetermined range including the design value, and the on-voltage of the semiconductor module 33 of the third group is smaller than the predetermined range. Therefore, when the semiconductor module 32 belonging to the second group and the semiconductor module 33 belonging to the third group are connected in parallel, the current bias becomes large. In the connection step described above, the semiconductor module 32 belonging to the second group and the semiconductor module 33 belonging to the third group are not connected in parallel. Therefore, the current bias in the parallel circuit can be reduced as compared with the case where the semiconductor module is randomly selected to form the parallel circuit.

(Modification Example) In the previous extraction step, one semiconductor module (transistor element) was extracted from the first group. The number of semiconductor modules (transistor elements) extracted from the first group may be any number. A case where two semiconductor modules 31a and 31b are extracted from the first group will be described. In this modification, it is assumed that five semiconductor modules 32a-32e are extracted from the second group, five semiconductor modules 33a-33e are also extracted from the third group, and a total of 12 semiconductor modules 3 are collected. FIG. 7 shows a plan view of the laminated unit 10a assembled by using the 12 semiconductor modules 3. 7 and 8 also show that the light gray (semiconductor module 32a-32e) is a semiconductor module belonging to the second group. Dark gray (semiconductor modules 33a-33e) indicates that the semiconductor modules belong to the third group. The gray in the middle (semiconductor modules 31a, 31b) indicates that the semiconductor modules belong to the first group.

In this example, when assembling the stacking unit 10a, the semiconductor modules 32a-32e belonging to the second group are concentrated on one end in the stacking direction (X direction in the drawing). The semiconductor modules 33a-33e belonging to the third group are centrally arranged at the other end in the stacking direction. The semiconductor modules 31a and 31b belonging to the first group are arranged between the first group and the second group. By arranging in such a way, it becomes easy to allocate a bus bar that satisfies the above-mentioned bias reduction connection relationship.

In the connection step, the semiconductor modules 32a-32e of the second group are connected in parallel with another semiconductor module of the second group or the semiconductor modules 31a and 31b of the first group. The semiconductor modules 33a-33e of the third group are connected in parallel with another semiconductor module of the third group or the semiconductor modules 31a and 31b of the first group. FIG. 8 shows a plan view of a laminated unit 10a in which two positive electrode bus bars 8a-8f and two negative electrode bus bars 9a-9f are connected in parallel.

The connection relationship of the semiconductor modules 3 in the laminated unit 10a is as follows. The semiconductor modules 32a and 32b belonging to the second group are connected in parallel by the positive electrode bus bar 8a and the negative electrode bus bar 9a. The semiconductor modules 32c and 32d belonging to the second group are connected in parallel by the positive electrode bus bar 8b and the negative electrode bus bar 9b. The semiconductor module 32e belonging to the second group is connected in parallel with the semiconductor module 31a belonging to the first group by the positive electrode bus bar 8c and the negative electrode bus bar 9c. The semiconductor module 33a belonging to the third group is connected in parallel with the semiconductor module 31b belonging to the first group by the positive electrode bus bar 8d and the negative electrode bus bar 9d. The semiconductor modules 33b and 33c belonging to the third group are connected in parallel by the positive electrode bus bar 8e and the negative electrode bus bar 9e. The semiconductor modules 33d and 33e belonging to the third group are connected in parallel by the positive electrode bus bar 8f and the negative electrode bus bar 9f.

Also in the examples of FIGS. 7 and 8, the semiconductor module 32 of the second group having a large on-voltage and the semiconductor module 33 of the third group having a small on-voltage are not connected in parallel. Therefore, the current bias becomes small in the parallel circuit of the two semiconductor modules 3 (transistor elements).

In the examples of FIGS. 7 and 8, two semiconductor modules 31a and 31b were extracted from the first group, and five (that is, odd number) semiconductor modules 3 were extracted from the second group and the third group, respectively. .. An even number of each may be extracted from the second group and the third group. For example, when two semiconductor modules 31a and 31b are extracted from the first group, four semiconductor modules 32a-32d are extracted from the second group, and six semiconductor modules 33a-33f are extracted from the third group. Is assumed. FIG. 9 shows a plan view of the laminated unit 10b composed of the extracted 12 semiconductor modules 3. Also in FIG. 9, light gray (semiconductor modules 32a-32d) indicates that the semiconductor modules belong to the second group. Dark gray (semiconductor modules 33a-33f) indicates that the semiconductor modules belong to the third group. The gray in the middle (semiconductor modules 31a, 31b) indicates that the semiconductor modules belong to the first group.

The four semiconductor modules 32a-32d of the second group are arranged so that two of them are sandwiched between adjacent coolers 4 and both sides of each are in contact with the coolers 4. The six semiconductor modules 33a-33f of the third group are also sandwiched between the adjacent coolers 4 by two, and both sides of each are arranged so as to be in contact with the cooler 4. The two semiconductor modules 31a and 31b of the first group are also arranged so that both sides of each of the adjacent coolers 4 are in contact with the cooler 4. Also in this case, the semiconductor module 32 of the second group is connected in parallel with another semiconductor module 32 of the same second group by connecting the positive electrode bus bar 8a-8f and the negative electrode bus bar 9a-9f shown in FIG. .. The semiconductor module 33 of the third group is connected in parallel with another semiconductor module 32 of the same third group. The semiconductor module 31a of the first group is connected in parallel with another semiconductor module 31b of the same group. In this example as well, the semiconductor module 32 of the second group having a large on-voltage and the semiconductor module 33 of the third group having a small on-voltage are not connected in parallel. Therefore, the current bias becomes small in the parallel circuit of the two semiconductor modules 3.

When manufacturing one power converter, the same effect can be obtained by extracting at least one semiconductor module from the first group and extracting the rest from the second and third groups. All the rest may be extracted from the second group, or all may be extracted from the third group.

The points to be noted regarding the technique described in the examples will be described. In the embodiment, one transistor element 16 is housed in one semiconductor module 3. Therefore, extracting the semiconductor module 3 of a specific group is equivalent to extracting the transistor element 16 of the specific group. A plurality of transistor elements may be housed in one semiconductor module. It is sufficient that the electrode terminals of the plurality of transistor elements contained therein extend from the package of one semiconductor module. In that case, the on-voltage of each transistor element is measured, and each is classified into one of the first, second, and third groups described above. In the sorting here, for example, the terminals of each transistor element are colored to indicate the group to which they belong. Even a plurality of transistor elements physically contained in one package can be grouped into separate groups. Then, when extracting a predetermined even number of transistor elements required for one power conversion device, the semiconductor module may be selected so that at least one semiconductor module includes the transistor elements belonging to the first group.

In the embodiment and the modification, when assembling the stacking unit, the semiconductor modules 32 belonging to the second group are concentrated on one end in the stacking direction (X direction in the drawing). The semiconductor modules 33 belonging to the third group are concentrated on the other end in the stacking direction. Then, the semiconductor module 31 belonging to the first group is arranged between the first group and the second group. By arranging in such a way, it is possible to simplify the wiring of the bus bar when connecting two in parallel. However, the arrangement of the plurality of semiconductor modules is not limited to the above. Semiconductor modules (transistor elements) belonging to each group may be randomly arranged in the laminated unit.

The transistor element 16 of the embodiment corresponds to an example of a semiconductor element. The on-voltage corresponds to an example of voltage characteristics. When selecting a diode as a semiconductor element, the voltage characteristic of interest may be forward voltage.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

2: Power converters 3, 3a-3n: Semiconductor module 4: Cooler 6: Transistor 7: Diode 8a-8f: Positive electrode bus bar 9a-9f: Negative electrode bus bar 10, 10a, 10b: Laminated unit 12: Positive electrode terminal 13: Negative electrode Terminal 14: Package 16: Transistor element (semiconductor element)
17: Diode element 20: Laminated units 31, 31a, 31b: Semiconductor module (first group)
32, 32a-32e: Semiconductor module (second group)
33, 33a-33f: Semiconductor module (3rd group)
80: Battery 81: Positive electrode wire 82: Negative electrode wire 83: Motor 85: Control terminal 90: Housing 91: Spring 92, 93: Refrigerant pipe

Claims (1)

A plurality of semiconductor elements for power conversion are included in a first group in which the voltage characteristics of the semiconductor elements are within a predetermined range including a design value, a second group in which the voltage characteristics are larger than the predetermined range, and the voltage characteristics. In the sorting process of sorting into a third group in which is smaller than the predetermined range,
An extraction step of extracting at least one of the semiconductor elements from the first group, extracting the rest from the second group and the third group, and collecting a predetermined even number of the semiconductor elements in total.
In a step of connecting two semiconductor elements collected in the extraction step in parallel, the semiconductor elements of the second group are combined with another semiconductor element of the second group or a semiconductor element of the first group. A connection step of connecting in parallel and connecting the semiconductor element of the third group in parallel with another semiconductor element of the third group or the semiconductor element of the first group.
A method of manufacturing a power converter comprising.