JP6780443B2 - Storage control device and storage device - Google Patents

Description

The present invention relates to a storage control device and a storage device.

In the scale-out type storage device, a plurality of storage control devices may be linked to operate as one system. By adding a control device, the system can be easily expanded and the performance of the system can be improved.

Such a storage device may be provided with a monitoring system module (hereinafter, may be referred to as “monitoring device”) of the system of the storage device.

In the storage device, the monitoring devices in each control device are started simultaneously or substantially simultaneously according to the AC ON (power ON) of the device, so that the initial processing for the monitoring device is performed simultaneously or substantially simultaneously. The initial process may include, for example, an authentication process for incorporating the control device into the storage device.

Japanese Unexamined Patent Publication No. 2000-131004 Japanese Unexamined Patent Publication No. 2012-143017

As the number of control devices increases, the number of authentication processes required by the monitoring device increases. Depending on the processing capacity of the firmware (Firmware; hereinafter referred to as FW) of the monitoring device, it may not be possible to cope with the increase in the communication processing load due to the increase in the number of authentication processes. In this case, the process following the authentication process cannot be executed, and the plurality of control devices cannot be started, which may make the storage device unusable.

When the monitoring device is started before the monitoring device, the monitoring device performs an authentication process on the monitoring device after the FW is started. However, the monitoring device cannot respond to the requested authentication process because it is in an unstarted state. Therefore, even when the monitoring device is started before the monitoring device, the storage device may not be available because the control device cannot be started depending on the FW processing procedure of the monitoring device.

In one aspect, the present invention aims to improve the availability of storage devices.

It should be noted that the other object of the present invention is not limited to the above-mentioned object, but is an action and effect derived by each configuration shown in the embodiment for carrying out the invention described later, and exerts an action and effect which cannot be obtained by the conventional technique. It can be positioned as one of.

In one aspect, the storage control device is any one of a plurality of storage control devices that control the storage device, and may include a processing unit, a measurement unit, and a timing control unit. .. The processing unit may execute the initial processing after the power of the storage control device is turned on for the monitoring device that monitors the storage device. The measuring unit may measure the delay time based on the length of the cable connecting the storage control device and the monitoring device after the power is turned on. The timing control unit may control the start timing of the initial processing by the processing unit after the power is turned on based on the delay time measured by the measuring unit.

On one side, the availability of storage devices can be improved.

It is a block diagram which shows the structural example of the storage apparatus which concerns on the comparative example of one Embodiment. It is a flowchart explaining the operation example of the Controller Module (CM) which concerns on the comparative example of one Embodiment. It is a flowchart explaining the operation example of the service controller (SVC) which concerns on the comparative example of one Embodiment. It is a figure explaining an example of the operation timing of the authentication process when the SVC is started before the Micro Controller (MC) of CM. It is a figure explaining an example of the operation timing of the authentication process when the SVC is started before the MC of the CM. It is a figure explaining an example of the operation timing of the authentication process when MC of CM starts before SVC. It is a figure which shows an example of the relationship between the cable length and the round trip time of a step pulse. It is a figure explaining an example of the start timing of the authentication process of each MC. It is a block diagram which shows the structural example of the storage device which concerns on one Embodiment. It is a block diagram which shows the detailed configuration example of the storage device which concerns on one Embodiment. It is a figure which shows an example of the operation mode of Termination Circuit (TC), and the switching timing by Mode Selector (MS). It is a figure which shows an example of the operation after the step pulse detection by a Reflection Detector (RD). It is a flowchart explaining the operation example of CM which concerns on one Embodiment. It is a figure explaining an example of the operation timing of the authentication process when the SVC is started before the MC of the CM. It is a figure explaining an example of the operation timing of the authentication process when MC of CM starts before SVC. It is a flowchart explaining operation example of SVC which concerns on one Embodiment. It is a block diagram which shows the detailed configuration example of the storage device which concerns on the modification of one Embodiment. It is a flowchart explaining the operation example of SVC which concerns on the modification of one Embodiment. It is a figure which shows an example of the operation sequence of the storage device which concerns on the modification of one Embodiment. It is a block diagram which shows the configuration example of the storage device which concerns on application example of one Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments described below are merely examples, and there is no intention of excluding the application of various modifications and techniques not specified below. For example, the present embodiment can be variously modified and implemented without departing from the spirit of the present embodiment. In the drawings used in the following embodiments, the parts having the same reference numerals represent the same or similar parts unless otherwise specified.

[1] One Embodiment [1-1] Comparative Example FIG. 1 is a block diagram showing a configuration example of a storage device 100 according to a comparative example of one embodiment. As shown in FIG. 1, the storage device 100 is exemplified by one or more service controllers (SVC) 200 and a plurality of controller modules (CM) (m; m is an integer of two or more in the example of FIG. 1). 300 (denoted as CM # 0 to CM # m-1) may be provided.

The SVC200 is an example of a monitoring device that monitors the storage device 100. The SVC200 may optionally include a Field Programmable Gate Array (FPGA) 210 and a Micro Controller (MC) 220. Hereinafter, the FPGA and MC provided by the SVC200 may be referred to as "FPGA" and "SVC MC", respectively.

The SFPGA210 is an example of a logic circuit capable of reconstructing logic. The MC 220 is an example of a processor that executes firmware (FW). The MC 220 performs initial processing in response to a request from the CM 300, for example. The initial process may include a CM300 authentication process.

The CM 300 is an example of a storage control device or controller that controls access to a plurality of storage devices from a host device (not shown) and controls the storage device 100. The CM300 may optionally include the FPGA 310 and the MC320. Hereinafter, the FPGA and MC provided by the CM 300 may be referred to as "CFPGA" and "CM MC", respectively.

CFPGA310 is an example of a logic circuit capable of reconstructing logic. The CFPGA 310 controls the communication between the CM300 and the SVC200 by the communication between the FPGAs and the SFPGA210.

The MC320 is an example of a processor that executes FW. The MC320 performs initial processing with, for example, the SVC200.

The SVC200 and each CM300 may be provided with a power supply unit, and the power supply unit may be connected to an AC outlet box (hereinafter, referred to as “ACS”) via an AC cable. AC ON (power ON) of the SVC 200 and each CM 300 may be carried out by turning on the corresponding breaker switch of the ACS.

By the way, the order of AC ON performed in each CM 300 may not be controlled. For example, when an operator turns on the breaker switches in sequence, a plurality of CM 300s may AC on each other at short time intervals (simultaneously or substantially simultaneously).

As described above, between the SVC200 and the CM300, there is an initial process performed immediately after AC ON, for example, an authentication process in a comparative example. The authentication process is exemplarily positioned as a series of processes indicating (associating) that each module (for example, CM300) is a member of the scale-out type storage device 100.

As an example, when the device is AC ON, each FW of the SVC MC220 and the CM MC320 is activated, and a process for authenticating each module is performed. For example, the CM MC 320 sends an authentication command to the SVC 200 after the FW has been started, and starts the authentication process. In the storage device 100, after this authentication process is performed, normal monitoring system communication becomes possible.

Hereinafter, the authentication process according to the comparative example of one embodiment will be described with reference to FIGS. 2 and 3.

(Authentication processing on the CM side)
First, the authentication process on the CM300 side will be described. As illustrated in FIG. 2, when the CM 300 is AC ON (step A110), the FW of the CM MC 320 is activated (step A120). The MC320 carries out an authentication process for the SVC200 (step A130). For example, the MC320 sends an authentication command to the SVC200.

The MC 320 receives the response to the authentication request from the SVC 200 and performs a series of processes. After the series of processes is completed, the authentication is established (step A140). The CM 300 is incorporated in the storage device 100 and starts communication of the monitoring system with the SVC 200 (step A150).

(Processing up to authentication on the SVC side)
Next, the process up to the authentication on the SVC200 side will be described. As illustrated in FIG. 3, when the SVC200 is AC ON (step B110), the FW of the SVC MC220 is activated (step B120).

The MC 220 waits for the SFPGA 210 to receive an authentication request (for example, an authentication command) from each CM MC 320 (step B130), and when it receives an authentication request from the MC 320, notifies the MC 320 of the result of whether or not the authentication is possible (step B140). The SVC200 starts the monitoring process for the authenticated CM300 (step B150).

By performing the authentication process in the above procedure, the processing of the monitoring system and the control system can be performed in cooperation between the SVC200 and the CM300.

Here, as described above, the storage device 100 may have the following inconveniences.

(A) Occurrence of insufficient processing resource of FW of monitoring device Authentication processing is performed by each FW of SVC MC220 and CM MC320. However, if the number of CM300s increases and authentication requests are transmitted from a large number of CM300s to the SVC200 at the same time or substantially simultaneously, the FW resource shortage of the SVC MC220 may occur.

As a result, processing following the authentication, for example, DC ON to a module such as the Central Processing Unit (CPU) in the CM 300 cannot be executed, and the CM 300 may not be started. If the FW processing resource of the MC 220 is to be increased, an expensive CPU and memory will be installed, which will increase the cost.

(B) Immediately after AC ON, the activation sequence of the monitoring device cannot be controlled by the FW. In order to avoid the above (a), it is conceivable to control the activation sequence of each CM300. However, immediately after AC ON, the FW of MC220 cannot recognize each CM300, so sequence control cannot be performed.

The above (a) and (b) may occur, for example, when the following SVC200 is started before the CM MC320.

(When SVC starts before CM MC)
As shown in FIG. 4, when the authentication process is performed one by one from the MC320, the SVC200 can normally respond to the request for the authentication process, and the CM300 starts normally.

On the other hand, as shown in FIG. 5, when the authentication process is performed from a plurality of MC320s at the same time, the amount of the authentication command transmitted increases as the number of connected CMs increases. Therefore, for example, when the authentication command is transmitted from each MC320 of CM # 0 to CM # 2, the authentication command may not be received due to insufficient reception buffer capacity in the SVC200 or the like. In this case, the FW of the SVC200 fails in the authentication response, the response times out, and the CM300, which cannot proceed to the subsequent processing, cannot be started when the DC ON is executed.

On the other hand, when the CM MC 320 is started before the SVC 200, the following inconveniences may occur in addition to the above (a) and (b).

(When CM MC starts before SVC)
As shown in FIG. 6, the CM MC320 issues an authentication command to the SVC200, but the SVC200 has not started and is not in the authentication waiting state (authentication request cannot be received), so an authentication response is received from the SVC200. Not sent. Therefore, the CM 300 cannot proceed to the subsequent processing, and the plurality of CM 300s cannot be started when the DC ON is executed.

As described above, depending on the timing of performing the authentication process, a plurality of CM300s in the storage device 100 may become unbootable.

[1-2] Storage device according to one embodiment Therefore, the storage device according to one embodiment is subjected to the authentication order of the storage control device (for example, the processing order of the initial processing after the power is turned on) by the method exemplified below. To control. Hereinafter, the authentication order control method according to the embodiment will be briefly described.

(When SVC starts before MC)
As described above, when the authentication process from the CM MC is executed at the same time, the SVC may not be able to respond and the CM may not be able to start. Therefore, in one embodiment, the SVC reliably performs the authentication process from the CM MC by controlling the authentication timing to be shifted so that the authentication process from each CM MC is executed by one unit or a predetermined number of units. Be able to respond.

As an example, each CM transmits a signal having a predetermined waveform (for example, a step pulse) to the SVC, and measures the time until the signal reaches the SVC, is reflected, and returns to the CM again.

Here, the length of the cable between each CM and SVC is different for each connection. That is, in one embodiment, if the cable length between each CM and SVC is different, the time until the signal is transmitted and returned is different for each CM, so that the authentication timing is shifted for each CM. is there.

For example, as shown in FIG. 7, if the relationship between cable lengths is d ₀ <d ₁ <d ₂ , the longer the distance of the transmission line through which the signal passes, the longer it takes for the signal to be reflected and returned. , The relationship of the time until the signal returns is t ₀ <t ₁ <t ₂ .

Then, the time t ₀ , t ₁ , t ₂ ... t _m-1 for returning the above-mentioned step pulse is assigned to the power-on timing (for example, reset release timing) of each CM-MC. As shown in FIG. 8, after the rise of power supply V _MC to CM MC, by shifting the timing of the reset release of the CM MC, shifting the start timing of each MC, it can be shifted timing of the authentication processing start It becomes. In FIG. 8, the MC reset signal is referred to as “Reset M”. The reset signal is, for example, a signal in which the Low (L) level indicates the reset (stop) of the MC and the High (H) level indicates the reset release (start) of the MC.

In this way, utilizing the fact that the measured time of the CM depends on the cable length between the CM and the SVC, the authentication process is performed by starting the MC in order from the CM in which the step pulse is reflected earlier. In other words, the priority by the cable length connecting the SVC2 and the CM3 determines the time when the CM3 starts authentication with the SVC2, and this priority is the impedance mismatch when each CM3 transmits a pulse. Measure based on the round-trip time of the reflected wave.

As a result, the authentication command is transmitted from each CM to the SVC with a time difference according to the measurement time, so that the SVC can normally return an authentication response to each authentication command. Therefore, the CM can normally execute the authentication process and the subsequent processes, and can avoid the storage control device from becoming unstartable, so that the availability of the storage device can be improved.

(When CM MC starts before SVC)
Even when the CM MC is activated before the SVC, each CM waits for the SVC to be activated by transmitting a signal having a predetermined waveform (for example, a step pulse) in the same manner as described above, and detects the activation of the SVC. In that case, the authentication process may be started.

For example, the CM may detect the activation of the SVC based on the waveform of the returned signal. For example, the SVC may change the reflection waveform depending on whether the authentication process is not ready (for example, before or during startup) or when the authentication process is ready. As an example, the SVC may change the waveform (for example, the amplitude of the step pulse; the detected voltage in the CM) by changing the impedance of the cable according to its own starting state.

In this way, by controlling the impedance of the cable by the SVC, the CM can detect that the SVC has been activated based on the waveform of the returned signal, and can send an authentication command after the SVC is activated. Therefore, the CM can normally execute the authentication process and the subsequent processes, and can avoid the storage control device from becoming unstartable, so that the availability of the storage device can be improved.

[1-3] Configuration Example of Storage Device According to One Embodiment Hereinafter, a configuration example of the storage device according to one embodiment will be described. The storage device according to the embodiment may be a scale-out type storage device. FIG. 9 is a block diagram showing a configuration example of the storage device 1 according to the embodiment. As shown in FIG. 9, the storage device 1 includes, for example, one or more SVC2s and a plurality of CM3s (denoted as CM # 0 to CM # m-1 in the example of FIG. 9). Good.

The SVC 2 is an example of a monitoring device that monitors the storage device 1. The SVC2 may optionally include the SFPGA21, the MC22, and a plurality of (m in the example of FIG. 9) Termination Circuit (TC) 23 (denoted as TC # 0 to TC # m-1). In addition, in SVC2, for example, the same number of TC23 as CM3 (MC32) may exist.

The SFPGA 21 is an example of a logic circuit capable of reconstructing logic, and controls communication between CM3-SVC2 by communication between FPGAs and CFPGA31 provided by CM3.

Cable 10 may be used for FPGA-to-FPGA communication between SFPGA21 and CFPGA31. The cable 10 may be various serial cables having at least one coaxial line and electrically transmitting signals. Examples of the cable 10 include cables conforming to standards such as RS422 and RS232C. As the cable 10, for example, a Local Area Network (LAN) cable may be used. In the example of FIG. 1, CM # 0-TC # 0 is connected by a cable 10-0, CM # 1-TC # 1 is connected by a cable 10-1, and CM # 2-TC # 2 is connected by a cable. It is connected by 10-2, and CM # m-1 and TC # m-1 are connected by a cable 10- [m-1].

Further, the SFPGA21 according to the embodiment monitors the signal input from the CM3 to the TC23 via the cable 10, and controls the TC23 based on the state of the SVC2 and the monitoring result.

The MC 22 is an example of a processor that executes firmware (FW). The MC 22 performs initial processing in response to a request from, for example, CM3. The initial process may include a CM3 authentication process.

The TC23 is an example of a termination circuit interposed between the SFPGA21 and the CFPGA31 and terminating the cable 10 connected to the CM3. The TC 23 may have a plurality of (for example, three types) impedance modes (hereinafter, referred to as “operating modes”) applied to the cable 10 connected to the CFPGA 31. The operation mode will be described later.

The CM3 is an example of a storage control device or controller that controls access to a plurality of storage devices from a host device (not shown) and controls the storage device 1. The CM3 may optionally include an FPGA 31, an MC32, a Switch (SW; switch) 33, and a reset signal output unit (denoted as “RESET” in FIG. 9) 34.

CFPGA31 is an example of a logic circuit capable of reconstructing logic. The CFPGA 31 transmits / receives information used for monitoring control with the SVC2 via FPGA communication via the cable 10.

Further, the CFPGA 31 according to the embodiment performs various processes for controlling the execution timing of the authentication process. For example, the CFPGA 31 transmits a signal having a predetermined waveform to the SVC 2 via the cable 10 and monitors the waveform of the reflected signal from the SVC 2. Further, the CFPGA 31 measures the time from the transmission of the signal to the reception of the reflected signal.

Further, the CFPGA 31 transmits a control signal for activating the MC 32 to the SW 33 based on the monitoring result of the waveform of the reflected signal and the measured time. Hereinafter, it is assumed that a step pulse is used as a signal having a predetermined waveform.

In other words, CFPGA31 is an example of a measuring unit that measures a delay time based on the length of a cable 10 connecting CM3 and SVC2 after the power of CM3 is turned on.

The MC 32 is an example of a processing unit that executes the initial processing after the power of the CM 3 is turned on for the SVC 2. The MC 32 may be, for example, a processor that executes FW and functions as a monitoring device in the CM3.

The SW 33 sends an activation signal, which is a trigger for activating the MC 32, to the MC 32 based on the reset signal input from the reset signal output unit 34 and the control signal input from the CFPGA 31.

In other words, the SW33 is an example of a timing control unit that controls the start timing of the initial processing by the MC32 after the power of the CM3 is turned on based on the delay time measured by the CFPGA31.

The reset signal output unit 34 is a circuit that switches the reset signal supplied to the SW 33 from “L” to “H” level when the MC 32 can be activated by AC ON of the CM3. The timing of switching the reset signal may be, for example, the timing at which it is detected that the voltage VMC supplied to the _MC 32 has reached a predetermined level or higher. The reset signal output unit 34 may be provided in the CFPGA 31.

Each of the SVC2 and the plurality of CM3s may include a processor and memory such as a CPU (not shown) and a power supply unit connected to the ACS via an AC cable. By turning on the breaker switch corresponding to the ACS, AC ON (power ON) of each of the SVC 2 and the plurality of CM3s may be carried out. The reset signal output unit 34 may be provided in the power supply unit of the CM3.

Further, a plurality of CM3s may be provided in the Controller Enclosure (CE) as an example of the control housing, and may control the Drive Enclosure (DE) which is an example of the storage housing in which a plurality of storage devices are mounted. In the example of FIG. 9, the illustration of CE and DE is omitted.

The storage device 1 can be expanded with CE and DE, and can operate as one system by linking CM3 by communication between CM3 and / or CM3-SVC2. In the storage device 1, the system can be easily expanded by adding CM3 (or CE), and the performance of the system can be improved.

[1-4] Description of Execution Timing Control of Authentication Process Next, a method of execution timing control of authentication processing by SVC2 and CM3 will be described. FIG. 10 is a diagram showing a detailed configuration example of the storage device 1 according to the embodiment.

As shown in FIG. 10, the SFPGA 21 may optionally be provided with a Mode Selector (MS) 212 (denoted as MS # 0, MS # 1) and a buffer 214 for each CM MC32 or TC23. The buffer 214 may be a buffer common to a plurality of CM3s.

The MS212 is an example of a control circuit that controls the impedance of the TC23 according to the activation state of the SVC2. For example, the MS212 monitors the voltage in the front stage of the corresponding TC23 (cable 10 side of the TC23), and controls to switch the operation mode of the TC23 according to the monitored voltage and the state of the SVC2. FIG. 11 shows an example of the operation mode of TC23 and the switching timing by MS212.

As shown in FIG. 11, as the operation mode of the TC23, when the impedance Z of the cable 10 is 50Ω, the following modes can be exemplified as examples.

-Open This is an operation mode in which the end of the cable 10 in the TC23 is opened.

The MS212 controls the TC23 in the open state until the SVC2 is activated, for example, until the MC22 can execute the authentication process. In the open state, the step pulse output from the CM3 to the cable 10 is totally reflected by the TC23, and the CM3 detects a voltage twice the voltage of the output step pulse.

-75Ω termination This is an operation mode in which the impedance of the TC23 is set to the impedance between the impedance of the cable 10 and the impedance in the open state. When the impedance Z of the cable 10 is 50Ω, the impedance of the TC23 is, for example, 75Ω in this operation mode.

Immediately after starting SVC2, MS212 switches and controls TC23 from open to 75Ω termination operation mode. At the 75Ω termination, the step pulse output from the CM3 to the cable 10 is reflected by the TC23 at a predetermined ratio, and the CM3 detects a voltage between each voltage of the open state and the 50Ω matched termination described later (for example, intermediate). To.

50Ω matching termination This is an operation mode in which the TC23 is impedance-matched with the cable 10. When the impedance Z of the cable 10 is 50Ω, the impedance of the TC23 is 50Ω in this operation mode.

When the MS212 detects the reflected voltage from the TC23 (or the input voltage to the TC23) from the cable 10 in the monitoring of the cable 10 after the activation of the SVC2, the operation of the TC23 from the 75Ω termination to the 50Ω matching termination. Switch to mode and control. Communication between CM3-SVC2 including authentication processing is performed in the operation mode of 50Ω matched termination. At the 50Ω matching termination, the step pulse output from the CM3 to the cable 10 is not reflected by the TC23, so that the CM3 detects the same voltage as the original step pulse voltage.

Returning to the description of FIG. 10, the buffer 214 is a storage device that temporarily stores the information received from the CM3. The information stored in the buffer 214 is output to the MC32. Although not shown, the SFPGA21 may include a transmission buffer for temporarily storing information to be transmitted to the CM3. Alternatively, buffer 214 may be used for both reception and transmission.

CFPGA31 of CM3 may optionally include a signal generator 312, a buffer 314, and a Reflection Detector (RD) 316.

The signal generator 312 is an example of a transmission unit that generates a signal having a predetermined waveform and transmits the generated signal to the cable 10. In one embodiment, the signal generator 312 generates a step pulse after the CM3 is activated and before the authentication process is performed.

The buffer 314 is a storage device that temporarily stores information to be transmitted to the SVC 2. Information output from the MC 32, such as an authentication command and information used for monitoring control, is stored in the buffer 314 and then sent to the cable 10. Although not shown, the CFPGA 31 may include a reception buffer for temporarily storing information received from the SVC 2. Alternatively, buffer 314 may be used for both reception and transmission.

The RD316 is an example of a detection unit that detects a reflected signal of the above signal reflected by the SVC2. For example, the RD 316 detects a step pulse (hereinafter, may be referred to as an “input step pulse”) transmitted from the signal generator 312, passed through the cable 10, reflected by the SVC2 side, and returned.

The RD 316 measures the time t _n (n is an integer of 0 to m-1) from when the step pulse is transmitted from the signal generator 312 to when it is reflected by the SVC 2 and returned. Then, the RD 316 issues a “Reset R” signal based on the time t _n and the voltage of the input step pulse that is reflected and returned. FIG. 12 shows an example of the operation after the step pulse detection in the RD316.

As shown in FIG. 12, the RD316 performs the following processing according to the voltage level of the detected input step pulse.

-When a voltage level twice the original step pulse voltage is detected (in the case of total reflection)
The RD 316 obtains the time t _n from the transmission of the step pulse to the detection of the reflected step pulse by the RD 316 from the reflected waveform. At this time, the output of the "Reset R" signal from the RD316 holds the reset state (e.g. "L" level), RD316 is reflected in "Reset R" signals obtained time _{t n} is not performed.

When a voltage level between 1 and 2 times the original step pulse voltage (for example, intermediate) is detected, the RD 316 reflects the time t _n from the transmission of the step pulse to the detection of the reflected step pulse by the RD 316. Obtained from the waveform. At this time, the output of the "Reset R" signal from the RD316 is switched to the reset release from the timing of detecting the reflected waveform after a time t _n state (e.g. "H" level). That is, the RD 316 reflects the obtained time t _n in the “Reset R” signal.

In other words, the CFPGA 31 notifies the SW 33 of a signal indicating the delay time when it detects that the voltage level of the signal in the cable 10 has reached a voltage level within a predetermined range by controlling the impedance by the SVC 2. In this case, the activation state of SVC2 is immediately after activation (TC23 ends at 75Ω). Therefore, CFPGA31 can start MC32 according to the time difference for each CM3 at the timing when SVC2 is started.

・ When the same voltage level as the original step pulse voltage is detected (impedance matching state)
When the RD316 detects the same voltage level as the original step pulse voltage, the authentication process or the like can already be performed, so that nothing needs to be done. Further, the output of the "Reset R" signal from the RD 316 holds the reset release state (for example, "H" level).

As described above, the RD 316 may determine that the reflected signal has been detected when the voltage level of the signal in the cable 10 is higher than the voltage level of the signal of the predetermined waveform transmitted from the signal generator 312. As a result, the reflected signal can be reliably detected.

Returning to the description of FIG. 10, SW33 performs an AND calculation of the “Reset R” signal from the reset signal output unit 34 and the “Reset R” signal from the RD 316, and converts the calculation result into the MC 32 as the “Reset M” signal. This is an example of an AND circuit that outputs.

"Reset" signal goes "H" level after startup of CM3, "Reset R" for signal becomes "H" level after time t _n from the detection predetermined reflected waveform starts SVC2 is, "Reset M The "signal is at the" H "level if both of these conditions are met. As described above, since the "Reset M" signal triggers the activation of the MC 32, the MC 32 is activated when both of these conditions are satisfied.

As described above, in the storage device 1, the CM3 measures the difference in the reflection time of the step pulse generated by the cable length between the CM3-SVC2, and thus the initial processing performed between the CM3-SVC2 when the power of the CM3 is turned on. The order of can be shifted between CM3s.

Further, by performing the above-mentioned control with the hardware of CM3 and SVC2, it is possible to control the activation sequence of CM MC32 even when the FW of SVC MC22 or CM MC32 is not activated.

Further, a circuit (TC23) for operating the termination state of the transmission line is provided on the SVC2 side, and the SFPGA21 changes the mode of the circuit depending on the situation, so that the activation state of the SVC2 and the initial state at the time of AC ON with another CM3 are performed. The order of processing can be transmitted to the CM3 side.

[1-5] Operation Example Next, an operation example of the storage device 1 configured as described above will be described with reference to FIGS. 13 to 16.

[1-5-1] CM operation example (when SVC is started before CM MC)
First, an operation example of CM3 when SVC2 is started before CM MC32 will be described. As illustrated in FIG. 13, when CM3 is AC ON (step A1), CFPGA31 is activated (step A2). The signal generator 312 of CFPGA31 generates a step pulse and transmits it to the cable 10 (step A3; see timing T1 in FIG. 14). At this time, the operation mode of TC23 is 75Ω termination.

The RD316 of CFPGA31, detecting a step pulse having returned reflected by SVC2 side (step A4; detection voltage _{V RD} is V2 at RD316 at timing T2 of FIG. 14). At the time of timing T1 in FIG. 14, the operation mode of TC23 is 75Ω termination, but since it is before the reflected step pulse returns, the period of timings T1 to T2 is the voltage of the original step pulse in RD316. Has been detected (see V1 in FIG. 14).

Then, the RD 316 obtains the time t _n from the transmission of the step pulse to the detection of the reflected and returned step pulse (step A5; see t _{n in} FIG. 14). Further, the RD316 determines whether the voltage of the reflected and returned step pulse is twice the original voltage, in other words, whether the operation mode of the TC23 is open or 75Ω termination (step A6).

When the voltage of the reflected and returned step pulse is not twice the original voltage, in other words, when the operation mode of the TC23 is 75Ω termination (No in step A6), the process shifts to step A7.

In step A7, RD316, since step pulse voltage _{V RD} of FIG. 14 is changed from the timing T4 V2 to V1, issue a "Reset R" signal reflecting the timing _{t n} reset release (T4 in FIG. 14 And T5, see the arrow of reference numeral A). In FIG. 14, a “Reset” signal (“H”) is issued from the reset signal output unit 34 at the timing T3. Further, after the timing T4, the TC23 holds a 50Ω matched termination.

The SW33 performs an AND operation on the “Reset” signal and the “Reset R” signal, and outputs a “Reset M” signal (“H”) (step A8). As a result, the activation timing of the MC32 of the corresponding CM3 is delayed by t _n times after the activation of the SVC2 is detected (after the step pulse reflected and returned is detected), and the activation of the MC32 is started (step A9; See reference numeral B in FIG. 14).

Then, the activated MC32 starts the authentication process (step A10; see reference numeral C in FIG. 14). The process from the authentication process by the MC32 to the start of monitoring may be performed in the same manner as in steps A130 to A150 of FIG.

By executing the above processing by each CM3, when the SVC2 is started before the CM MC32, the SVC2 can surely respond to the authentication processing from the CM MC32. As a result, all CM3s can be started normally.

(When CM MC is started before SVC)
Next, an operation example of CM3 when the CM MC32 is started before the SVC2 will be described. In this case, step A3 in FIG. 13 is performed when the operation mode of TC23 is open (see timing T11 in FIG. 15).

The RD 316 detects the step pulse reflected and returned on the SVC2 side (step A4; the detection voltage V _RD is V3 at the timing T12 in FIG. 15). Although the operation mode of TC23 is open at the time of timing T11 in FIG. 15, since the reflected step pulse is before returning, the voltage of the original step pulse in RD316 is set during the period of timings T11 to T12. It has been detected (see V1 in FIG. 15).

Then, the RD 316 obtains the time t _n from the transmission of the step pulse to the detection of the reflected and returned step pulse (step A5; see t _{n in} FIG. 15). Further, the RD316 determines whether the voltage of the reflected and returned step pulse is twice the original voltage, in other words, whether the operation mode of the TC23 is open or 75Ω termination (step A6).

In the example of FIG. 15, since the operation mode of TC23 is open and the voltage of the reflected and returned step pulse is twice the original voltage (Yes in step A6), the process shifts to step A11.

In step A11, the reset signal output unit 34 stops transmitting the step pulse (see timing T13 in FIG. 15) and waits for a certain period of time t _w (step A12; t _{w in} FIG. 15 (timing T13 to T14)). reference). Then, the process proceeds to step A3.

In the example of FIG. 15, since the operation mode of TC23 is open during the timings T14 to T17, in step A6 after passing through step A11 of FIG. 14, the route of Yes is passed again and steps A10 and A11 are executed. After that, the process proceeds to step A3.

In FIG. 15, when SVC2 is activated and the operation mode of TC23 is switched from open to 75Ω termination, the RD316 detects the reflected voltage at 75Ω termination at timing T19 by the step pulse transmitted at timing T18 (step A3). , A4). Further, RD316 obtains t _n at this time (step A5).

The voltage of the step pulse that is reflected and returned is not twice the original voltage. In other words, since the operation mode of TC23 is 75Ω termination, the process shifts to step A7 through the route No in step A6. To do. Since the processing of steps A7 to A10 is the same as the description with reference to FIG. 13, the description will be omitted.

By executing the above processing by each CM3, even if the SVC2 is not started, the completion of the activation of the SVC2 is awaited, and the MC32 is started at the timing of each CM3 after the SVC2 is started (see the timing T20 in FIG. 15). As a result, the authentication process of the CM MC 32 can be started at the timing when the SVC 2 can respond.

In the above description, in step A7, the RD 316 issues a “Reset R” signal that reflects the reset release timing t _n , but the present invention is not limited to this.

When the time required for one authentication process and the time order with the time t _n are different, for example, when the difference in t _n calculated by each CM3 is smaller than the time required for one authentication process by SVC2, FIG. It is also conceivable that the SVC2 will not be able to receive the authentication request, as in the example of. Thus, RD316 only issues a "Reset R" signal reflecting the _{t n,} if the control of the startup sequence is insufficient, RD316 each CM3 is the time multiplied by a constant time _{t n} " By reflecting it in "Reset R", it may be adjusted so that the time order matches.

[1-5-2] Operation example of SVC Next, an operation example of SVC2 will be described. As illustrated in FIG. 16, the operation mode of TC23 is in the open state when SVC2 is AC OFF (step B1). When SVC2 is AC ON (step B2), SFPGA21 is activated (step B3).

Each of the plurality of MS212s of the SFPGA21 switches the operation mode of the corresponding TC23 from the open state to the 75Ω termination (step B4). Then, each MS212 observes the reflected voltage from the corresponding TC23 (75Ω termination) (step B5).

The MS212 that has detected the reflected voltage switches the operation mode of the corresponding TC23 from the 75Ω termination to the 50Ω matched termination (step B6). Then, it waits for the authentication from the SVC MC22 whose firmware has started with the AC ON (step B7). The process from the authentication process by the MC22 to the start of monitoring may be performed in the same manner as in steps B130 to B150 of FIG.

[1-6] Modification Example In one embodiment, the cable lengths between the CM3-SVC2s are different from each other, but it is also possible that the lengths of the cables 10 are the same in a plurality of CM3s. In this case, since the step pulses transmitted from each CM3 return to the CM3 almost at the same time, the authentication process from the CM MC32 may compete with the SVC2. Therefore, when the authentication processing conflicts, it may be controlled so that the SVC2 is not started in a pseudo manner.

FIG. 17 is a diagram showing a detailed configuration example of the storage device 1 according to the modified example of the embodiment. As shown in FIG. 17, the SFPGA21A of the SVC2A according to the modified example may optionally include a mask circuit 216 in addition to the SFPGA21 shown in FIG. Further, the SFPGA21A may include the MS212A having some functions different from those of the MS212.

The MS212A controls the switching of the operation mode of the TC23, similarly to the MS212. Further, when the MS212A according to the modified example detects a signal (for example, a step pulse) from the CM3, it notifies the mask circuit 216 that the step pulse from the CM3 is detected (observed). Then, when the mask circuit 216 gives a mask instruction to be described later in response to the notification, the MS212A switches the operation mode of the TC23 (switching from the 75Ω end to the 50Ω matched end) according to the detection of the reflected voltage from the TC23. Deter.

The mask circuit 216 detects the input of the step pulse to each TC23 based on the notification from each MS212A, and outputs a mask instruction to the MS212A other than the MS212A that first detects the input of the step pulse. The mask instruction is, for example, an instruction to switch the operation mode of the TC23 from the 75Ω end to the open state and hold the open state.

On the other hand, the mask circuit 216 does not output a mask instruction to the MS212A that first detects the input of the step pulse. As a result, the MS212A switches the operation mode of the TC23 from the open state to the 75Ω termination, similarly to the MS212 according to the embodiment. Therefore, with respect to the source CM3 of the step pulse detected first, the processing up to the authentication is performed by the method according to the above-described embodiment.

The mask circuit 216 masks all MS212A that transmit the mask instruction after a certain period of time has elapsed since the operation mode of the TC23 was switched to the 50Ω matched termination by the MS212A that first detected the input of the step pulse. Output the release instruction. The fixed time t may be, for example, about the same as the time required for the authentication process. Further, the start point of the fixed time t may be the timing at which the MS212A that first detects the input of the step pulse observes the reflected voltage from the TC23.

Then, the mask circuit 216 does not output a mask instruction to the MS212A that first detects the input of the step pulse after the mask is released, and the other authentication process is not completed for the MS212A on the CM3 path. , The mask instruction is output in the same manner as above.

By repeating the above processing, the authentication request from any one of the plurality of CM3s is sequentially input to the SVC2A, so that the conflict of the authentication processing in the SVC2A can be avoided and the plurality of CM3s can be stored. It can be started normally.

In other words, the mask circuit 216 is an example of a limiting unit that individually controls the MS212A for each CM3 so as to limit the number of CM3s that perform initial processing at the same time.

For example, when the mask circuit 216 detects the input of the step pulse to the TC23 connected to the first CM3, the mask circuit 216 corresponds to the TC23 corresponding to the SFPGA21A corresponding to the second CM3 different from the first CM3. To control the impedance of. This control is such that the CM MC32 of the second CM3 determines that the voltage level of the signal in the cable 10 connected to the second CM3 is a voltage level outside the predetermined range.

When the SVC2A can process a plurality of authentication requests in parallel, the mask circuit 216 may control the output of the mask instruction based on the upper limit of parallel processing that the SVC2A can process the authentication requests in parallel. For example, the mask circuit 216 can control the MS212A that has detected the input of the step pulse so that the mask instruction is not output to the MS212A up to the upper limit of parallel processing on a first-come-first-served basis.

As described above, in the mask circuit 216, the SVC2A is activated for one or more second CM3s other than the first CM3 until the authentication process related to the first CM3 which is the source of the first detected step pulse is completed. Mask the state of being. In other words, the mask circuit 216 causes the MS212A on the path to the second CM3 to control the TC23 so as to indicate a state in which the SVC2A is not activated in a pseudo manner.

The SVC2A controls the activation state of the SVC2A recognized by the CM3 by observing the reflection waveform by mask control for each CM3. Therefore, although the timing for detecting that the SVC2A has been activated (the timing when No in step A6 of FIG. 13) is different for each CM3, each CM3 may perform the process illustrated in the flowchart of FIG.

Next, an operation example of SVC2A according to a modified example of one embodiment will be described with reference to FIG. As shown in FIG. 18, steps B1 to B4 are the same as the process of FIG. In the following step B11, in the SFPGA21A, the MS212A on the path of the CM3 detects a step pulse from any CM3. The detected MS212A (hereinafter referred to as the detected MS212A) notifies the mask circuit 216 that the step pulse from the CM3 (hereinafter referred to as the detected CM3) corresponding to the mask circuit 216 has been observed (step B12).

In response to the notification from the detection MS212A, the mask circuit 216 determines whether or not there is an unauthenticated CM3 other than the detection CM3 (step B13). When there is no unexecuted CM3 (No in step B13), the SVC MC22 executes an authentication process with the MC32 of the detected CM3 (step B14), and the process ends.

On the other hand, when the unexecuted CM3 is present (Yes in step B13), the mask circuit 216 issues a mask instruction for the unexecuted CM3 to each of one or more MS212A on the path of the unexecuted CM3 (step B15). Upon receiving the mask instruction, the MS212A switches the operation mode of the corresponding TC23 from the 75Ω termination to the open (step B16).

The detection MS212A on the path of the detection CM3 observes the reflected voltage from the 75Ω termination (step B17) and switches the corresponding TC23 from the 75Ω termination to the 50Ω matched termination (step B18).

The mask circuit 216 waits for a certain period of time t. Further, the SVC MC22 performs an authentication process with the MC32 of the detection CM3 within a certain period of time t (step B19).

After a lapse of a certain time t, the mask circuit 216 outputs an instruction to release the mask to the unexecuted CM3 to each MS212A on the path of the unexecuted CM3 (step B20). Upon receiving the mask release instruction, the MS212A switches the operation mode of the corresponding TC23 from open to 75Ω termination (step B21) in response to the mask release instruction, and the process shifts to step B11.

By executing the above operation by the SVC2A and by each CM3 executing the process illustrated in FIG. 13, it is possible to avoid the authentication process from each CM MC32 from competing with the SVC2A, and the authentication process is started one by one CM3. Is possible.

The process from the authentication process of CM3 in steps B14 and B19 to the start of monitoring of each CM3 may be performed in the same manner as in steps B130 to B150 of FIG.

Next, with reference to FIG. 19, the operation sequence of the storage device 1 according to the modified example of the embodiment will be described. In the following description, it is assumed that SVC2A is connected to CM # 0 and CM # 1 by cables 10-0 and 10-1, respectively, and the cable lengths of cables 10-0 and 10-1 are equal (d0 = d1). ). Further, it is assumed that the SVC2A is activated before the CM3 MC32.

As illustrated in FIG. 19, when SVC2A is AC ON (process P1), MS # 0 and MS # 1 switch the operation modes of TC # 0 and TC # 1 to 75Ω termination (processes P2 and P3), respectively.

Next, CM # 0 and CM # 1 are activated (processes P4 and P5), respectively, and each CFPGA31 is activated (processes P6 and P7). When the signal generator 312 of CM # 0 transmits a step pulse at a timing earlier than that of CM # 1 (process P8), MS # 0 observes the input and notifies the mask circuit 216 (process P9).

The mask circuit 216 instructs MS # 1 to mask CM # 1 (process P10), and MS # 1 switches the operation mode of TC # 1 to open (process P11). After that, the signal generator 312 of CM # 1 transmits a step pulse (process P12).

When MS # 0 detects the reflected voltage from TC # 0 after the process P9, the MS # 0 switches the operation mode of the TC # 0 to the 50Ω matched termination (process P13).

In CM # 0, the reflection waveform of the step pulse transmitted by the RD 316 in the process P8 is detected (process P14). After that, CM # 0 performs the processes of Nos. A7 to A9 of steps A5 and A6 of FIG. 13, and performs the authentication process by CM MC32 with the SFPGA21A (process P15).

The mask circuit 216 of the SVC2A waits for a certain period of time t after the instruction of the process P10 (process P16). During the standby, the SVC MC 22 performs an authentication process with the CM MC 32 in the process P15.

On the other hand, in CM # 1, the reflected waveform of the step pulse transmitted in the process P12 is detected (process P17). Since the operation mode of TC # 1 is an open, CM # 1 performs a process of Yes in step A5, A6 of FIG. 13, waits a predetermined time _{t w} stops the transmission of the step pulse (processing P18 ).

In the SVC2A, when the standby of the process P16 for a certain period of time ends and the mask circuit 216 instructs the mask to be released (process P19), the MS # 1 switches the operation mode of the TC # 1 to the 75Ω termination (process P20).

Thereafter, CM # 1 to wait for a predetermined time _{t w} has finished processing P18 is the sending step pulses (processing P21), MS # 1 is notified to the mask circuit 216 observes the input (process P22). Since there is no other CM3 for which the authentication process has not been completed, the mask instruction is not transmitted in the mask circuit 216 (process P23).

Further, when MS # 1 detects the reflected voltage from TC # 1 after the process P22, the MS # 1 switches the operation mode of the TC # 1 to the 50Ω matched termination (process P24). It should be noted that each of MS # 0 and MS # 1 keeps the operation modes of TC # 0 and TC # 1 at the 50Ω matched termination while the processes P13 and P24 are transferred and SVC2A or CM3 is activated.

In CM # 1, the reflection waveform of the step pulse transmitted by the RD 316 in the process P21 is detected (process P25). After that, CM # 1 performs the processes of Nos. A7 to A9 of steps A5 and A6 of FIG. 13, and performs the authentication process by CM MC32 with the SFPGA21A (process P26). The SVC MC22 performs an authentication process with the CM MC32 in the process P26 (process P27).

In FIG. 19, the operation (for example, monitoring control, etc.) after the authentication process in the SVC2A and each CM3 is not shown.

[1-7] Application Example Next, an application example of the storage device 1 described above will be described with reference to FIG. The storage device 1A shown in FIG. 20 may optionally include a plurality of CE4s, a plurality of DE5s, and a relay device 6. The relay device 6 may be, for example, a Front-End Enclosure (FE).

The storage device 1A mounts a plurality of storage devices on the DE5 and provides a storage area of the storage device to the host device (not shown). For example, the storage device 1A may store data in a plurality of storage devices in a distributed or redundant state by using Redundant Arrays of Inexpensive Disks (RAID). The CE4 may have a storage device inside.

The CE4 is an example of a control housing that is connected to the relay device 6 and the DE5, respectively, and performs various controls. The CE4 may optionally include a plurality of CM3s (two in FIG. 1). In the example of FIG. 20, the CM3 is made redundant (for example, duplicated) with other CM3s in the CE4. Further, each CM3 in the CE4 is directly or indirectly connected to each of the DE5s corresponding to the CE4, so that the access route is made redundant. Further, the CM3 may be provided with a host interface for communicating with a host device (not shown).

At least one of the CFPGA31, MC32, SW33, and reset signal output unit 34 of the CM3 according to the embodiment and the modified example may be provided, for example, in the interface circuit with the SVC2 in the CM3 shown in FIG. ..

The relay device 6 is an example of a device connected to a plurality of CM3s and relaying communication between the CM3s. The relay device 6 may optionally include a plurality of redundant (two in FIG. 20) Midplane (MP) 7s and an MP bridge 9 connecting these MP7s.

The MP7 may optionally include an SVC2 and a plurality of redundant Front End Routers (FRTs) 8 (two in FIG. 1).

The FRT 8 is an example of a connection unit that connects each of the plurality of CM3s so as to be able to communicate with each other. The FRT 8 may be provided with, for example, a plurality of adapters compliant with Peripheral Component Interconnect (PCI) Express (PCIe), and may be connected to each of the plurality of CM3s by a cable corresponding to the PCIe.

The SVC2 is provided with, for example, a plurality of interfaces for connecting to the CM3, and is connected to each of the plurality of CM3s by a cable (cable 10 illustrated in FIGS. 10 and 17).

At least one of the SFPGA21, MC22, and TC23 of the SVC2 according to the embodiment and the modification may be provided in the interface circuit between the SVC2 and the CM3 shown in FIG. 20, for example.

The MP bridge 9 is an example of a bridge unit that connects a plurality of MP7s in a communicable manner. The SVC2 may monitor other systems (for example, modules connected to the other MP7 and MP7) via the MP bridge 9.

The storage device 1A may be provided with, for example, a rack (not shown) in order to mount the CE4, DE5, and the relay device 6 described above, and the CE4, DE5, and the relay device 6 may be detachably mounted. Good.

In addition to the circuit blocks shown in FIGS. 10 and 17, each of the CM3 and the SVC2 has a processor such as a CPU and a memory such as a Random Access Memory (RAM) in order to perform various controls in the storage device 1A. And may be equipped with a communication interface.

In the storage device 1A, the execution order of the initial processing executed at the time of AC ON is different between each of the plurality of SVC2s (or the master SVC2) and each of the plurality of CM3s in the plurality of CE4s. , It may be controlled by the method described above according to the embodiment.

[2] Others The technology according to the above-described embodiment can be modified or modified as follows.

For example, the circuit blocks of CM3 or SVC2 shown in FIGS. 10 and 17 may be merged or divided in any combination.

Further, in one embodiment and a modification, the CFPGA 31 can measure t _{n a} plurality of times depending on whether the operation mode of the TC 23 of the SVC 2 is in the open state or at the end of 75Ω, but the present invention is limited to this. It's not a thing. t _n is a time that depends on the cable length, and once it is obtained by measurement, the value does not change significantly in subsequent measurements. Therefore, the CFPGA 31 may transmit a step pulse to determine the activation state of the SVC2 after measuring t _n at least once, while skipping the measurement of t _n .

[3] Additional notes The following additional notes will be further disclosed with respect to the above embodiments.

(Appendix 1)
A storage control device that is one of a plurality of storage control devices that control a storage device.
A processing unit that executes initial processing after the power of the storage control device is turned on for the monitoring device that monitors the storage device, and a processing unit.
A measuring unit that measures the delay time based on the length of the cable connecting between the storage control device and the monitoring device after the power is turned on.
A storage control device including a timing control unit that controls the start timing of the initial processing by the processing unit after the power is turned on based on the delay time measured by the measuring unit.

(Appendix 2)
The measuring unit
A transmission unit that sends a signal of a predetermined waveform to the cable,
It is equipped with a detection unit that detects the reflected signal of the signal reflected by the monitoring device.
The storage control device according to Appendix 1, wherein the delay time is a time from when the transmitting unit transmits the signal until the detecting unit detects the reflected signal.

(Appendix 3)
The detection unit is characterized in that it determines that the reflected signal has been detected when the voltage level of the signal in the cable is higher than the voltage level of the signal of the predetermined waveform transmitted from the transmission unit. The storage control device according to Appendix 2.

(Appendix 4)
The monitoring device controls the impedance at the end of the cable according to the activation state of the monitoring device.
When the measuring unit detects that the voltage level of the signal in the cable has reached a voltage level within a predetermined range by controlling the impedance by the monitoring device, the measuring unit sends a signal indicating the delay time to the timing control unit. The storage control device according to any one of Items 1 to 3, wherein the storage control device is characterized by notifying.

(Appendix 5)
It's a storage device
A control device for controlling the storage device and a monitoring device for monitoring the storage device are provided.
Each of the control devices
A processing unit that executes initial processing after the power of the control device is turned on for the monitoring device, and
A measuring unit that measures the delay time based on the length of the cable connecting the control device and the monitoring device after the power is turned on.
A storage device including a timing control unit that controls the start timing of the initial processing by the processing unit after the power is turned on based on the delay time measured by the measuring unit.

(Appendix 6)
The measuring unit
A transmission unit that sends a signal of a predetermined waveform to the cable,
It is equipped with a detection unit that detects the reflected signal of the signal reflected by the monitoring device.
The storage device according to Appendix 5, wherein the delay time is a time from when the transmitting unit transmits the signal until the detecting unit detects the reflected signal.

(Appendix 7)
The detection unit is characterized in that it determines that the reflected signal has been detected when the voltage level of the signal in the cable is higher than the voltage level of the signal of the predetermined waveform transmitted from the transmission unit. The storage device according to Appendix 6.

(Appendix 8)
The monitoring device controls the impedance at the end of each of the cables connected to the plurality of control devices according to the activation state of the monitoring device.
When the measuring unit detects that the voltage level of the signal in the cable has reached a voltage level within a predetermined range by controlling the impedance by the monitoring device, the timing control unit outputs a signal indicating the delay time. The storage device according to any one of Supplementary note 5 to 7, wherein the storage device is notified to.

(Appendix 9)
The monitoring device is
A terminating circuit that terminates the cable connected to the control device,
Each control device is provided with a control circuit that controls the impedance of the termination circuit according to the activation state of the monitoring device.
The storage device according to Appendix 8, wherein a limiting unit for individually controlling the control circuit for each control device is provided so as to limit the number of control devices that simultaneously perform the initial processing.

(Appendix 10)
When the limiting unit detects the input of the signal of the predetermined waveform to the termination circuit connected to the first control device, the limiting unit becomes a control circuit corresponding to a second control device different from the first control device. On the other hand, the corresponding termination so that the measurement unit of the second control device determines that the voltage level of the signal in the cable connected to the second control device is a voltage level outside the predetermined range. The storage device according to Appendix 9, wherein the impedance of the circuit is controlled.

1,1A storage device 10,10-0-10- [m-1] cable 2,2A SVC
21 SFPGA
212, 212A MS
214, 314 buffer 216 mask circuit 22, 32 MC
23 TC
3 CM
31 CFPGA
312 signal generator 316 RD
33 SW
34 Reset signal output unit 4 CE
5 DE
6 Relay device 7 MP
8 FRT
9 MP bridge

Claims (8)

A storage control device that is one of a plurality of storage control devices that control a storage device.
A processing unit that executes initial processing after the power of the storage control device is turned on for the monitoring device that monitors the storage device, and a processing unit.
A measuring unit that measures the delay time based on the length of the cable connecting between the storage control device and the monitoring device after the power is turned on.
A storage control device including a timing control unit that controls the start timing of the initial processing by the processing unit after the power is turned on based on the delay time measured by the measuring unit. The measuring unit
A transmission unit that sends a signal of a predetermined waveform to the cable,
It is equipped with a detection unit that detects the reflected signal of the signal reflected by the monitoring device.
The storage control device according to claim 1, wherein the delay time is a time from when the transmitting unit transmits the signal to when the detecting unit detects the reflected signal. The detection unit is characterized in that it determines that the reflected signal has been detected when the voltage level of the signal in the cable is higher than the voltage level of the signal of the predetermined waveform transmitted from the transmission unit. The storage control device according to claim 2. The monitoring device controls the impedance at the end of the cable according to the activation state of the monitoring device.
When the measuring unit detects that the voltage level of the signal in the cable has reached a voltage level in a predetermined range by controlling the impedance by the monitoring device, the measuring unit sends a signal indicating the delay time to the timing control unit. The storage control device according to any one of claims 1 to 3, wherein the storage control device is characterized by notifying. It's a storage device
A control device for controlling the storage device and a monitoring device for monitoring the storage device are provided.
Each of the control devices
A processing unit that executes initial processing after the power of the control device is turned on for the monitoring device, and
A measuring unit that measures the delay time based on the length of the cable connecting the control device and the monitoring device after the power is turned on.
A storage device including a timing control unit that controls the start timing of the initial processing by the processing unit after the power is turned on based on the delay time measured by the measuring unit. The monitoring device controls the impedance at the end of each of the cables connected to the plurality of control devices according to the activation state of the monitoring device.
When the measuring unit detects that the voltage level of the signal in the cable has reached a voltage level within a predetermined range by controlling the impedance by the monitoring device, the timing control unit outputs a signal indicating the delay time. 5. The storage device according to claim 5, further comprising notifying. The monitoring device is
A terminating circuit that terminates the cable connected to the control device,
Each control device is provided with a control circuit that controls the impedance of the termination circuit according to the activation state of the monitoring device.
The storage device according to claim 6, further comprising a limiting unit that individually controls the control circuit for each control device so as to limit the number of control devices that simultaneously perform the initial processing. When the limiting unit detects the input of the signal of the predetermined waveform to the termination circuit connected to the first control device, the limiting unit becomes a control circuit corresponding to a second control device different from the first control device. On the other hand, the corresponding termination so that the measurement unit of the second control device determines that the voltage level of the signal in the cable connected to the second control device is a voltage level outside the predetermined range. The storage device according to claim 7, wherein the impedance of the circuit is controlled.

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