JP6777204B2 - Image sensor - Google Patents

Description

The present invention relates to an image sensor.

In recent years, CMOS type image pickup devices have attracted attention in image pickup devices such as electronic cameras. On the light receiving surface of these image pickup devices, pixel portions that perform photoelectric conversion and output an electric signal are arranged. Further, a signal line for reading an electric signal to the outside, a control line for driving the pixel unit, and the like are also provided close to the light receiving surface.

In addition, Patent Document 1 discloses a configuration in which an electric signal is generated on the light receiving surface and the electric signal is output to an electrode on the opposite surface.

Further, Patent Document 2 discloses a back surface incident type image sensor that reads out an electric signal generated on the light receiving surface by a wiring layer on the opposite surface. This backside incident type image sensor is connected to another signal processing chip via an electrode on the wiring layer side.

Japanese Patent Application No. 2003-543107 Japanese Unexamined Patent Publication No. 2006-49361

In the above-mentioned conventional technique, it is necessary to complicatedly integrate the pixel portion, the wiring structure, and the like on the light receiving surface of the semiconductor substrate. Therefore, the manufacturing process of the image sensor has many steps and is complicated. Therefore, in the prior art, there is a problem that it is difficult to implement a design rule or a manufacturing process that gives the highest priority to the imaging performance of the image sensor.

An image pickup device of an example of the present invention is an image pickup device having a first chip on which light is incident and a second chip connected to the first chip, and is a photoelectric conversion unit and a photoelectric conversion unit that convert light into charges. A plurality of pixels having a read circuit including a transistor for reading a signal based on the charge converted by the photoelectric conversion unit to the read line, and a control connected to the gate of the transistor to control the transistor. A control line from which a signal is output is provided, a photoelectric conversion unit is arranged on the first chip, and a transistor and a control line are arranged on the second chip.

According to an example of the present invention, it is possible to provide a structure of an image pickup device suitable for improving image pickup performance.

It is sectional drawing of the image sensor 10. It is a figure which shows the equivalent circuit of the image sensor 10. It is a top view of the 1st chip 11 and the 2nd chip 12. It is sectional drawing of the pixel part of the image sensor 10a. It is an equivalent circuit diagram for one pixel of the image pickup element 10a. It is a top view of the 1st chip 11a and the 2nd chip 12a. It is a figure which shows the structure of the image sensor 10b. It is a figure which shows the structure of the image sensor 10c. It is a figure which shows the structure of the image sensor 10d. It is a figure which shows the structure of the image sensor 10f. It is an equivalent circuit diagram of the image sensor 10f. It is a figure which shows the element structure of the image sensor 10h.

<< First Embodiment >>
In the first embodiment, the light receiving element is arranged on the first chip, and the transfer transistor or the like is arranged on the second chip.

FIG. 1 is a diagram showing a pixel cross section of the image sensor 10. FIG. 2 is an equivalent circuit diagram for one pixel of the image sensor 10. FIG. 3 is a top view of the first chip 11 and the second chip 12. The pixel cross section shown in FIG. 1 is a cross section of a dotted line portion shown in FIG.

As shown in these figures, the first chip 11 is formed on the basis of the semiconductor substrate 11x. The light receiving pixel 1 is formed on the light receiving surface 16x side of the substrate 11x. A light receiving element PD is provided on the light receiving pixel 1. A microlens 23 is formed above the light receiving element PD via the interlayer film 11y. The light receiving element PD is electrically connected to the through wiring 20 via the wiring layer 17. The through wiring 20 is formed in a through hole provided in the element separation region 22. The through wiring 20 is composed of a conductive embedded wiring 18 and an insulating film 19 that insulates the inner peripheral wall of the through hole. An insulating film 11z is formed on the opposite surface 16y of the substrate 11x. The through wiring 20 penetrates the insulating film 11z and appears on the opposite surface 16y. A micro pad 13 is formed at this penetrating portion.

The second chip 12 is formed on the basis of the semiconductor substrate 12x. A read circuit 30 is formed on at least one surface (forming surface) of the substrate 12x corresponding to the through wiring 20. Micropads 14 are formed on the forming surface by aligning with the opposing micropads 13. A through hole 25 is formed directly below the micro pad 14. An insulating film 26 is formed on the inner peripheral wall of the through hole 25. Through the through hole 25, the micropad 14 makes ohmic contact with the source / drain region 27 of the transfer transistor QT. A gate 28 of the transfer transistor QT is provided between the source / drain region 27 and the floating diffusion FD region via an insulating film. Further, a gate 29 of the reset transistor QR is provided between the floating diffusion FD and the reset drain 31 to which the reference voltage VDD is applied via an insulating film. The voltage of the floating diffusion FD is supplied to the gate 32 of the amplification element QA via a wiring layer (not shown). A gate 34 of the selection transistor QS is provided between the source 33 of the amplification element QA and the source / drain region 35 of the selection transistor QS via an insulating film. The source / drain region 35 is connected to the read line 36.

In addition to the above-described configuration, the second chip 12 mainly includes a vertical scanning circuit that gives a control signal to the read circuit 30, a correlated double sampling circuit for removing reset noise, and an output (image signal) of the read circuit 30. A horizontal scanning circuit for sequentially reading in the scanning direction, an output amplifier for amplifying an image signal, and the like are also formed.

The first chip 11 and the second chip 12 described above are completed through independent manufacturing processes. The opposite surface 16y of the first chip 11 and the read circuit 30 of the second chip 12 are arranged so as to face each other. In this state, the micro pad 13 of the through wiring 20 and the micro pad 14 of the read circuit 30 are electrically joined by the micro bump 15.

(Procedure for reading image signal)
The light receiving element PD on the first chip 11 side photoelectrically converts the incident light to generate a signal charge. At this time, by keeping the transfer transistor QT non-conducting, the light receiving element PD accumulates signal charges.

On the other hand, the reference potential VDD is applied to the floating diffusion FD on the second chip 12 side by conducting the reset transistor QR. After that, when the reset transistor QR is cut off, the floating diffusion FD is put into a floating state, and the potential at the time of cutoff is held as the reset potential.

The selection transistor QS is conduction-controlled according to the selection timing of the read line. At this time, a current is supplied to the amplification element QA via the read line 36 and the selection transistor QS to form a source follower circuit. As a result, the reset potential of the floating diffusion FD is output to the read line 36. The correlated double sampling circuit holds this reset potential.

Next, the transfer transistor QT temporarily conducts on the second chip 12 side. As a result, the light receiving element PD on the first chip 11 side and the floating diffusion FD on the second chip 12 side are electrically connected. At this time, the signal charge accumulated in the light receiving element PD is attracted by the potential difference with the floating diffusion FD. Then, the signal charge on the first chip 11a side passes through the path of the wiring layer 17, the through wiring 20, the micro pad 13, the micro bump 15, the micro pad 14, and the transfer transistor QT, and the floating diffusion on the second chip 12a side. Transferred to FD.

The reset potential of the floating diffusion FD changes by the amount of this signal charge, and becomes a signal potential. This signal potential is output to the read line 36 via the amplification element QA and the selection transistor QS. The correlated double sampling circuit generates a difference between this signal potential and the reset potential held earlier, and outputs it as a true image signal. This image signal is read out to the outside through a horizontal scanning circuit and an output amplifier.

(Effects of the first embodiment, etc.)
In the first embodiment, the light receiving element PD and the through wiring 20 are arranged on the first chip 11, and the readout circuit 30 is arranged on the second chip 12. By dividing the element structure into two in this way, the step of forming the readout circuit 30 becomes unnecessary in the manufacturing process of the first chip 11. Therefore, it becomes possible to adopt a design rule and a manufacturing process specialized for the element performance of the light receiving element PD. Therefore, it becomes possible to realize an image pickup device 10 having high imaging performance.

Further, on the second chip 12 side, the space of the light receiving element PD becomes unnecessary. Therefore, there is a wide margin in circuit design, and it is possible to improve the yield by relaxing the design rules. Further, by utilizing the margin of this space and providing a memory area for signal charges for each pixel, it is possible to realize a global electronic shutter. Further, by adding an AD conversion circuit for each pixel or line, it is possible to realize an image sensor 10 that outputs a digital image signal.

In particular, in the first embodiment, it is not necessary to give a control signal related to signal reading to the light receiving element PD of the first chip 11. Therefore, it is not necessary to provide the first chip 11 with a wiring layer for giving a control signal. Therefore, it is not necessary to provide a wiring layer on the layer above the light receiving element PD, and there is no adverse effect such as light receiving eclipse due to the wiring layer.

Further, by omitting the wiring layer for the control signal from the first chip 11, the layer structure of the light receiving surface can be thinned. As a result, the microlens 23 and the light receiving element PD can be brought closer to each other, and the obliquely incident light of the microlens 23 can be efficiently incident on the light receiving element PD. In particular, in a large image sensor for a single-lens reflex camera, the luminance shading at the peripheral edge of the imaging area is improved, and the peripheral image quality of the captured image can be improved.

A read circuit 30 exists on the second chip 12 side. Therefore, it is preferable to shield the reading circuit 30 from light. However, since the upper part of the readout circuit 30 is covered with the first chip 11, the light-shielding layer can be omitted or thinned.

Further, in the first embodiment, since the readout circuit 30 conventionally arranged on the light receiving surface 16x is moved to the second chip 12, there is a margin in the mounting space of the light receiving pixel 1. Therefore, the area of the light receiving element PD can be expanded to improve the light receiving performance of the image sensor 10. On the contrary, by reducing the light receiving pixel 1, it is possible to further increase the number of pixels.

Further, by improving the isotropic shape of the light receiving element PD, it is possible to improve the light receiving performance of the image sensor 10.

Further, on the second chip 12 side, there is a margin in the mounting space because there is no light receiving element PD. The signal line in the readout circuit 30 can be shortened by utilizing the margin of the mounting space. As a result, it is possible to reduce signal delay, reduce noise, improve operating speed, and the like.

Further, by selecting and assembling the characteristics and compatibility of the first chip 11 and the second chip 12, the yield of the image pickup device 10 can be further increased.

<< Second Embodiment >>
In the second embodiment, the light receiving element and the transfer transistor are arranged on the first chip, and the reset transistor and the like are arranged on the second chip. Since the procedure for reading the image signal is the same as that in the first embodiment, the description thereof will be omitted here.

FIG. 4 is a diagram showing a pixel cross section of the image sensor 10a. FIG. 5 is an equivalent circuit diagram for one pixel of the image sensor 10a. FIG. 6 is a top view of the first chip 11a and the second chip 12a. The pixel cross section shown in FIG. 4 is a cross section of the dotted line portion shown in FIG.

Hereinafter, the configuration of the image pickup device 10a will be described with reference to these figures.

A light receiving element PD and a transfer transistor QT are formed on the light receiving pixel 1a of the first chip 11a. The gate 28a of the transfer transistor QT is provided between the light receiving element PD and the diffusion region FDx via an insulating film. This diffusion region FDx is connected to the through wiring 20 via the wiring layer 17a. The through wiring 20 penetrates to the opposite surface 16y through a through hole provided in the element separation region 22 of the light receiving pixel 1a. A micro pad 13 is formed at the penetrating portion of the opposite surface 16y.

A read-out circuit 30a is formed on the forming surface of the second chip 12a corresponding to the through wiring 20. The reading circuit 30a is provided with micropads 14 so as to align with the opposing micropads 13. The micropad 14 makes ohmic contact with the diffusion region FDy via the through hole 25. These diffusion region FDx, through wiring 20, and diffusion region FDy are electrically integrally connected and function as a floating diffusion FD. A gate 29a of the reset transistor QR is provided between the diffusion region FDy and the reset drain 31 to which the reference voltage VDD is applied via an insulating film. The voltage of the diffusion region FDy is supplied to the gate 32a of the amplification element QA via a wiring layer (not shown). A gate 34a of the selection transistor QS is provided between the source 33a of the amplification element QA and the source / drain region 35a of the selection transistor QS via an insulating film. The source / drain region 35a is connected to the read line 36.

The first chip 11a is provided with a drive circuit for giving a control signal to the gate 28a of the transfer transistor QT.

Further, the second chip 12a sequentially reads out a vertical scanning circuit that gives a control signal to the reading circuit 30a, a correlated double sampling circuit for removing reset noise, and an output (image signal) of the reading circuit 30a in the main scanning direction. A horizontal scanning circuit for this purpose, an output amplifier for amplifying an image signal, and the like are also formed.

The micropad 13 of the through wiring 20 described above and the micropad 14 of the readout circuit 30a are electrically joined via the microbump 15.

Also in the second embodiment, by dividing the element structure into the first chip 11a and the second chip 12a, the same effects as those in the first embodiment can be obtained.

Further, in the second embodiment, since the light receiving element PD and the transfer transistor QT are arranged on the first chip 11a, it is possible to prevent the remaining transfer of the signal charge.

<< Third Embodiment >>
In the third embodiment, a light receiving element, a transfer transistor, and a reset transistor are arranged on the first chip, and an amplification element or the like is arranged on the second chip. Since the procedure for reading the image signal is the same as that in the first embodiment, the description thereof will be omitted here.

FIG. 7A is a top view (for one pixel) of the first chip 11b, which is a component of the image sensor 10b. FIG. 7B is a top view (for one pixel) of the second chip 12b, which is a component of the image sensor 10b. FIG. 7C is an equivalent circuit diagram for one pixel of the image sensor 10b.

Hereinafter, the configuration of the image pickup device 10b will be described with reference to these figures.

A light receiving element PD, a transfer transistor QT, and a reset transistor QR are formed on the light receiving pixel 1b of the first chip 11b. The gate 28b of the transfer transistor QT is provided between the region of the light receiving element PD and the floating diffusion FD via an insulating film. A gate 29b of the reset transistor QR is provided between the floating diffusion FD and the reset drain 31b to which the reference voltage VDD is applied via an insulating film. Further, the floating diffusion FD is connected to the through wiring 20. The through wiring 20 penetrates to the opposite surface through the through hole. A micro pad 13 is provided at this penetrating portion.

On the other hand, a read-out circuit 30b is formed on the second chip 12b corresponding to the through wiring 20. The micro pad 14 of the readout circuit 30b is electrically joined to the micro pad 13 of the first chip 11b by a micro bump. The micropad 14 is connected to the gate 32b of the amplification element QA. On the other hand, a power supply voltage is applied to the drain of the amplification element QA. A gate 34b of the selection transistor QS is provided between the source 33b of the amplification element QA and the source / drain region 35b of the selection transistor QS via an insulating film. The source / drain region 35b is connected to the read line 36.

The first chip 11b is provided with a drive circuit for giving control signals to the gates 28b and 29b.

Further, the second chip 12b sequentially reads out a vertical scanning circuit that gives a control signal to the reading circuit 30b, a correlated double sampling circuit for removing reset noise, and an output (image signal) of the reading circuit 30b in the main scanning direction. A horizontal scanning circuit for this purpose, an output amplifier for amplifying an image signal, and the like are also formed.

Also in the third embodiment, the same effect as that of the second embodiment can be obtained by dividing the element structure into the first chip 11b and the second chip 12b.

Further, in the third embodiment, since the light receiving element PD and the reset transistor QR are arranged on the first chip 11a, it is possible to prevent the remaining reset of the signal charge.

<< Fourth Embodiment >>
In the fourth embodiment, a light receiving element, a transfer transistor, a reset transistor, and an amplification element are arranged on the first chip, and a selection transistor or the like is arranged on the second chip. Since the procedure for reading the image signal is the same as that in the first embodiment, the description thereof will be omitted here.

FIG. 8A is a top view (for one pixel) of the first chip 11c, which is a component of the image sensor 10c. FIG. 8B is a top view (for one pixel) of the second chip 12c, which is a component of the image sensor 10c. FIG. 8C is an equivalent circuit diagram for one pixel of the image sensor 10c.

Hereinafter, the configuration of the image pickup device 10c will be described with reference to these figures.

A light receiving element PD, a transfer transistor QT, a reset transistor QR, and an amplification element QA are formed on the light receiving pixel 1c of the first chip 11c. The gate 28c of the transfer transistor QT is provided between the region of the light receiving element PD and the floating diffusion FD via an insulating film. A gate 29c of the reset transistor QR is provided between the floating diffusion FD and the reset drain 31c to which the reference voltage VDD is applied via an insulating film. The voltage of the floating diffusion FD is supplied to the gate 32c of the amplification element QA via a wiring layer (not shown). The source 33c of the amplification element QA is connected to the through wiring 20. The through wiring 20 penetrates to the opposite surface through the through hole. A micro pad 13 is provided at the penetrating portion on the opposite surface.

On the other hand, a read circuit 30c is formed on the second chip 12c corresponding to the through wiring 20. The micro pad 14 of the readout circuit 30c is electrically joined to the micro pad 13 of the first chip 11c by a micro bump. The micropad 14 is connected to one source / drain region 38 of the selection transistor QS. A gate 34c of the selection transistor QS is provided between the source / drain region 38 and the other source / drain region 35c via an insulating film. The source / drain region 35c is connected to the read line 36.

The first chip 11c is provided with a drive circuit for giving control signals to the gates 28c and 29c.

Further, the second chip 12c sequentially reads out a vertical scanning circuit that gives a control signal to the reading circuit 30c, a correlated double sampling circuit for removing reset noise, and an output (image signal) of the reading circuit 30c in the main scanning direction. A horizontal scanning circuit for this purpose, an output amplifier for amplifying an image signal, and the like are also formed.

Also in the fourth embodiment, the same effect as that of the third embodiment can be obtained by dividing the element structure into the first chip 11c and the second chip 12c.

Further, in the fourth embodiment, the light receiving element PD to the amplification element QA are arranged close to each other on the first chip 11a. Therefore, it is possible to convert the signal charge into the source hollower output with a short wiring distance, and it is possible to reduce the adverse effect of noise.

<< Fifth Embodiment >>
In the fifth embodiment, the light receiving element, the transfer transistor, the reset transistor, the amplification element, and the selection transistor are arranged on the first chip, and the processing circuit of the subsequent stage is arranged on the second chip. Since the procedure for reading the image signal is the same as that in the first embodiment, the description thereof will be omitted here.

FIG. 9A is a top view (for one pixel) of the first chip 11d, which is a component of the image sensor 10d. FIG. 9B is a top view (for one pixel) of the second chip 12d, which is a component of the image sensor 10d. FIG. 9C is an equivalent circuit diagram for one pixel of the image sensor 10d.

Hereinafter, the configuration of the image pickup device 10d will be described with reference to these figures.

A light receiving element PD, a transfer transistor QT, a reset transistor QR, an amplification element QA, and a selection transistor QS are formed on the light receiving pixel 1d of the first chip 11d. The gate 28d of the transfer transistor QT is provided between the region of the light receiving element PD and the floating diffusion FD via an insulating film. A gate 29d of the reset transistor QR is provided between the floating diffusion FD and the reset drain 31d to which the reference voltage VDD is applied via an insulating film. The voltage of the floating diffusion FD is supplied to the gate 32d of the amplification element QA via a wiring layer (not shown). A gate 34d of the selection transistor QS is provided between the source 33d of the amplification element QA and the source / drain region 35d of the selection transistor QS via an insulating film. The source / drain region 35d is connected to the read line 36. The read line 36 is connected to the through wiring 20. The through wiring 20 penetrates to the opposite surface through the through hole. A micro pad 13 is provided at the penetrating portion on the opposite surface.

On the other hand, a read circuit 30d is formed on the second chip 12d corresponding to the through wiring 20. The micro pad 14 of the readout circuit 30d is electrically joined to the micro pad 13 of the first chip 11d by a micro bump. The read circuit 30d includes a correlated double sampling circuit (CDS), a column amplifier (CA), a column AD conversion circuit, and the like in units of pixel rows. Further, the readout circuit 30d may include a preprocessing circuit for an image signal and the like.

In the fifth embodiment, a correlated double sampling circuit, an AD conversion circuit, and the like can be mounted on the second chip 12d side with a margin. Further, by providing a plurality of readout circuits 30d and processing the image signals in parallel, it is possible to increase the number of channels of the image signal output. As a result, it becomes possible to shorten the reading time of the image signal and the signal processing time.

<< 6th Embodiment >>
The sixth embodiment is an embodiment in which a plurality of light receiving pixels are commonly connected to the through wiring.

FIG. 10A is a top view (for 4 pixels) of the first chip 11f, which is a component of the image sensor 10f. FIG. 10B is a top view (for 4 pixels) of the second chip 12f, which is a component of the image sensor 10f. FIG. 11 is an equivalent circuit diagram for four pixels of the image sensor 10f.

Hereinafter, the configuration of the image pickup device 10f will be described with reference to these figures.

The light receiving pixel 1f of the first chip 11f is divided into sections for each of a plurality of pixels (here, 2 horizontal pixels × 2 vertical pixels). Four light receiving elements PD1 to PD4 are provided in this section. Transfer transistors QT1 to QT4 are provided on each of these light receiving elements PD1 to PD4. The drains of the transfer transistors QT1 to QT4 are commonly connected to the through wiring 20 via the common wiring 71. The through wiring 20 penetrates to the opposite surface through the through hole. A micro pad 13 is provided at the penetrating portion on the opposite surface.

On the other hand, a read circuit 30f is formed on the second chip 12f corresponding to the through wiring 20. The micro pad 14 of the readout circuit 30f is electrically joined to the micro pad 13 of the first chip 11f by a micro bump. The read-out circuit 30f has the same circuit configuration as the read-out circuit 30a of the second embodiment. In addition, the read circuit 30f may be provided with a pixel memory unit, an AD conversion circuit, or the like.

In such a configuration, the signal charges of the light receiving elements PD1 to PD4 can be given to the readout circuit 30f in a time-division manner by sequentially conducting the transfer transistors QT1 to QT4 using the control signals φTx1 to φTx4. The readout circuit 30f takes in these signal charges in a time-division manner and sequentially outputs them as image signals.

In the sixth embodiment, one read circuit 30f is provided for each section of a plurality of pixels. Therefore, the number of reading circuits 30f installed can be reduced to a fraction of the total number of pixels.

In particular, in the sixth embodiment, since the division is 2 horizontal pixels x 2 vertical pixels, the minimum color array of the Bayer array can be processed by one readout circuit 30f. Therefore, it is also possible to mount a processing circuit (color difference conversion circuit, pixel number conversion circuit, etc.) between adjacent signals in the readout circuit 30f.

In the sixth embodiment, the layout of the section can be flexibly designed. For example, it is also possible to divide the light receiving pixel 1f in a row unit and provide a read circuit 30f in a row unit. In this case, by providing the AD conversion circuit in the read circuit 30f, the AD conversion can be performed in column units.

In the sixth embodiment, the output of the transfer transistor QT is commonly connected to the through wiring 20. However, the present invention is not limited to this. For example, in the element structures of the third to fifth embodiments, a plurality of light receiving pixels may be set as one section and commonly connected to the through wiring 20. In this case, by sequentially conducting the transfer transistors QT in the compartment, the readout circuit can take in the electric signals of the light receiving pixels in the compartment in a time division manner.

<< 7th Embodiment >>
The seventh embodiment is an embodiment in which an interposer is provided between the layers of the first chip and the second chip.

FIG. 12 is a diagram showing an element structure of the seventh embodiment.

In the seventh embodiment, an interposer 81 extending the through wiring 20 is arranged between the first chip 11h and the second chip 12h constituting the image sensor 10h. The through wiring 82 of the interposer 81 and the micro pad 13 of the first chip 11h are electrically joined by the micro bump 15x. Further, the through wiring 82 of the interposer 81 and the micro pad 14 of the second chip 12h are electrically joined by the micro bump 15y.

It should be noted that such a configuration can be realized in any of the element structures of the first to sixth embodiments. The through wiring 20 can be extended by using the interposer 81.

By inserting the interposer 81 between the layers in this way, the heat generated on the second chip 12h side can be insulated by the interposer 81. Further, by using the interposer 81 as a heat sink, the heat generated on the second chip 12h side can be efficiently exhausted. Therefore, deterioration of image quality such as thermal noise caused by the temperature rise of the light receiving element PD can be suppressed.

Further, by inserting the interposer 81 between the layers, it is possible to increase the mechanical strength of the image pickup device 10h.

PD ... light receiving element, QT ... transfer transistor, FD ... floating diffusion, QR ... reset transistor, QA ... amplification element, QS ... selection transistor, 1 ... unit pixel, 11 ... first chip, 12 ... second chip, 13 ... micro Pad, 14 ... Micro pad, 15 ... Micro bump, 16x ... Light receiving surface, 20 ... Through wiring, 23 ... Micro lens, 30 ... Read circuit, 81 ... Interposer, 82 ... Through wiring

Claims (18)

An image sensor having a first chip into which light is incident and a second chip connected to the first chip.
A plurality of pixels having a photoelectric conversion unit that converts light into electric charges and a reading circuit that is connected to the photoelectric conversion unit and includes a transistor for reading a signal based on the electric charge converted by the photoelectric conversion unit to a reading line. ,
A control line connected to the gate of the transistor and outputting a control signal for controlling the transistor is provided.
The photoelectric conversion unit is arranged on the first chip.
The transistor and the control line are image pickup devices arranged on the second chip. The photoelectric conversion units are arranged side by side at least in the row direction.
The image pickup device according to claim 1, wherein the transistors are arranged side by side at least in the row direction. The read circuit has a transfer transistor for transferring the electric charge converted by the photoelectric conversion unit as the transistor.
The image pickup device according to claim 1 or 2, wherein the control line is connected to the gate of the transfer transistor. The read circuit has a reset transistor as the transistor that resets the potential of the floating diffusion to which the electric charge converted by the photoelectric conversion unit is transferred.
The image pickup device according to claim 1 or 2, wherein the control line is connected to the gate of the reset transistor. The read circuit has a selection transistor as the transistor that controls the connection between the pixel and the read line.
The image pickup device according to claim 1 or 2, wherein the control line is connected to the gate of the selection transistor. The second chip, according to any one of claims 1 to 5 conversion circuit for converting the signal read out to the readout line by the reading circuit into a digital signal is assigned Image sensor. The image pickup device according to claim 6, wherein the conversion circuit is arranged for each pixel in the second chip. The image pickup device according to any one of claims 1 to 7, wherein the reading circuit has a holding unit that holds a charge from the photoelectric conversion unit. The image pickup device according to any one of claims 1 to 8 , wherein the first chip is provided with a through wiring for electrically connecting the photoelectric conversion unit and the read circuit. The image pickup device according to claim 9 , wherein the through wiring is formed in a through hole provided in the first chip, and has a conductive portion and an insulating portion that insulates an inner peripheral wall of the through hole. The first chip has a first surface on which light is incident and a second surface opposite to the first surface.
The second chip has a third surface facing the second surface of the first chip.
The first chip and the second chip are arranged on the second surface and electrically connected to the photoelectric conversion unit, and are arranged on the third surface and electrically with the read circuit. The image pickup device according to any one of claims 1 to 10 , which is electrically connected to a second pad connected to. The image pickup device according to any one of claims 1 to 11 , wherein the first chip is arranged so as to overlap the second chip so as to cover the read circuit. The image pickup device according to any one of claims 1 to 12 , wherein the first chip is arranged so as to overlap the second chip so as to block the reading circuit. An image sensor having a first chip into which light is incident and a second chip connected to the first chip.
A plurality of pixels having a photoelectric conversion unit that converts light into electric charges and a reading circuit including a plurality of transistors for reading a signal based on the electric charge converted by the photoelectric conversion unit to a reading line.
A first control line that is connected to the gate of the first transistor among the plurality of transistors and outputs a control signal for controlling the first transistor.
A second control line, which is connected to the gate of the second transistor among the plurality of transistors and outputs a control signal for controlling the second transistor, is provided.
The photoelectric conversion unit is arranged on the first chip.
The first transistor, the second transistor, the first control line, and the second control line are image pickup devices arranged on the second chip. The read circuit includes a transfer transistor that transfers the charge converted by the photoelectric conversion unit as the first transistor, and includes a reset transistor that resets the potential of the floating diffusion to which the charge transferred from the photoelectric conversion unit is transferred. The image pickup device according to claim 14, which includes two transistors. The read circuit includes a reset transistor as the first transistor that resets the potential of the floating diffusion to which the electric charge from the photoelectric conversion unit is transferred, and includes a selection transistor that controls the connection between the pixel and the read line. The image pickup device according to claim 14, which is included as the second transistor. The image pickup device according to claim 14 or 15, wherein the second chip is provided with a conversion circuit for converting the signal read on the read line by the read circuit into a digital signal. The image pickup device according to claim 17, wherein the conversion circuit is arranged for each pixel in the second chip.

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