JP6769662B2 - Hardware timers, control methods and programs - Google Patents

Description

The present invention relates to hardware timers, control methods and programs.

Patent Document 1 discloses a technique for preventing omission of notification of a timer that has timed out when the time-out buffer is in the full state, and for acquiring information on the time when the original time-out should occur for the timer.
Further, in Patent Document 2, when an access request to the memory is generated from the CPU (Central Processing Unit), the access to the memory is permitted from the CPU, and the CPU reads the timer value (Read) to the memory. It discloses a technology for processing write.

Further, Patent Document 3 discloses a technique for releasing the timer buffer by deleting the information of the timer buffer from a predetermined table when the timer value stored in the timer buffer times out. There is.
Further, Patent Document 4 discloses that counting processing of a plurality of timer values stored in a timer memory is performed in a time division manner.

Japanese Unexamined Patent Publication No. 2013-229671 Japanese Unexamined Patent Publication No. 2001-273049 JP-A-11-143723 Japanese Patent Application Laid-Open No. 08-190517

However, in Patent Documents 1 to 4, when the first time in which the CPU can access the timer memory and the second time in which the timer can access the timer memory are allocated, during the second time. The CPU could not access the timer memory until after the second time had elapsed, even when the timer was off.
Therefore, when the access to the timer memory is performed by the CPU and the timer on a time-division basis, even if the timer memory is off during the time allotted to the timer, the access to the timer memory is performed. The timer memory could not be accessed by the CPU, and the usage time of the timer memory of the CPU could not be increased.

Therefore, an object of the present invention is to provide a hardware timer, a control method, and a program that solve the above-mentioned problems.

Some aspects of the present invention have been made to solve the above-mentioned problems, and the hardware timer according to the first aspect of the present invention is a device.
A selection unit that selects either a first state in which the central processing unit can access the timer memory and a second state in which the timer can access the timer memory.
Of the first time allocated as the time that the central processing unit can access the timer memory and the second time allocated as the time that the timer can access the timer memory, the second time. A control unit that causes the selection unit to select the first state when the timer is off even within the time period.
To be equipped.

Further, the method for controlling the hardware timer according to the second aspect of the present invention is as follows.
One of the first state in which the central processing unit can access the timer memory and the second state in which the timer can access the timer memory is selected.
Of the first time allocated as the time that the central processing unit can access the timer memory and the second time allocated as the time that the timer can access the timer memory, the second time. Even within the time, if the timer is off, the first state is selected.

Further, the program according to the third aspect of the present invention has either a first state in which the central processing unit can access the timer memory and a second state in which the timer can access the timer memory. Selection means to select,
Of the first time allocated as the time that the central processing unit can access the timer memory and the second time allocated as the time that the timer can access the timer memory, the second time. A control means that causes the selection means to select the first state even within the time when the timer is off.
To function as.

According to the present invention, when the timer memory is accessed by the CPU and the timer in a time-division manner, the usage time of the timer memory by the CPU can be increased.

It is a block diagram which shows the structure of the CPU and the hardware timer by 1st Embodiment of this invention. It is a block diagram which shows the structure of the bus selection part by 1st Embodiment of this invention. It is a block diagram which shows the structure of the timer-on control part by 1st Embodiment of this invention. It is a timing chart which shows the operation of the hardware timer by 1st Embodiment of this invention. It is a flowchart which shows the operation of the timer by 1st Embodiment of this invention. It is a flowchart which shows the operation of the register part of the timer-on control part by 1st Embodiment of this invention. It is a flowchart which shows the operation of the signal selection part of the timer-on control part by 1st Embodiment of this invention. It is a block diagram which shows the structure of the timer-on control part by 2nd Embodiment of this invention. It is a block diagram which shows the structure of the timer-on control part by the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the timer-on control part by 4th Embodiment of this invention. It is a block diagram which shows the structure of the hardware timer which has the minimum structure. It is a flowchart which shows the processing of the hardware timer which has the minimum configuration.

[First Embodiment]
First, the first embodiment of the present invention will be described.
FIG. 1 is a block diagram showing a configuration of a CPU 10 and a hardware timer 20 according to the first embodiment of the present invention.
For example, the hardware timer 20 is a base station device for a mobile phone, and is used as a timer included in a base station device that manages time for each user in controlling communication with a plurality of users (slave units).
The hardware timer 20 includes a timer 21, a timeout buffer 22, a bus selection unit 23 (also referred to as a selection unit), a timer memory 24, a timer-on control unit 25a (also referred to as a control unit), and a bus 26.

The CPU 10 writes the initial timer value to the storage area of the timer memory 24 which is a RAM (Random Access Memory) via the bus 26.
The CPU 10 reads the timer value decremented by the timer 21 from the timer memory 24 via the bus 26. The CPU 10 obtains the passage of time from the difference between the timer value written to the address x (integer of x = 0 to n) and the timer value read from the address x.

When the interrupt signal from the timeout buffer 22 becomes active, the CPU 10 reads the timeout buffer 22 and acquires the timer number that has timed out.
Since the cycle of decrementing by one timer is equal to or greater than the value of (clock cycle) × (number of timers) × (number of timer cycles), it is equal to or greater than the value of (clock cycle) × (n + 1) × (r + 1). Become. For example, when the clock cycle is 10 ns (nanoseconds), the number of timers is 4096 (n = 4095), and the number of timer cycles is 10 (r = 9), the cycle in which one timer decrements is 10 ns × 4096. × 10 = 0.4096 ms or more.

The timer 21 reads a timer value from the timer memory 24, and determines whether the timer is in a time-out state, a timer not used, or a decrement state based on the read timer value. Specifically, the timer 21 determines that the timer is not used when the timer value read from the timer memory 24 is "0", and determines that the timer is timed out when the timer value is "1", and determines that the timer is unused. If the value is a value other than '0' or '1', it is determined to be decrement.
When the timer 21 determines that the timer is not used, the timer 21 does not perform any processing.

If the timer 21 determines that a timeout has occurred and there is space in the storage area of the timeout buffer 22, the timeout buffer write signal is activated and output to the timeout buffer 22 with the timeout timer number as the timeout number. At the same time, the timer 21 sets the write data to '0' and writes to the timeout buffer 22.
The timer 21 does not perform any processing when it is determined that a timeout has occurred and there is no free space in the storage area of the timeout buffer 22.
When the timer 21 determines that the decrement is determined, the timer 21 writes the decremented value to the same address as the read timer value.

The timeout buffer 22 is a generally used FIFO (First In First Out). When the write signal output from the timer 21 becomes active, the timeout buffer 22 stores the time-out timer number, negates the empty signal, and sends an interrupt signal to the CPU 10. Output.
The timeout buffer 22 can store m (m is a positive integer) timer numbers that have timed out, and when there is no free space in the storage area of the timeout buffer 22, the timer 21 activates the full signal. , Do not write to the timeout buffer 22.

The timeout buffer 22 can receive read access only from the CPU 10. When the timeout buffer 22 is read from the CPU 10, the timeout buffer 22 outputs the timer numbers to the CPU 10 in the order of being written from the timer 21.
The timeout buffer 22 is read from the CPU 10, and when the storage area of the timeout buffer 22 becomes empty, the timeout buffer 22 activates the empty signal and stops the interrupt to the CPU 10.

The bus selection unit 23 converts the access signal to the timer memory 24 from the CPU 10 and the access signal to the timer memory 24 from the timer 21 into the cycle count signal from the timer 21 and the selection timer-on signal from the timer-on control unit 25a. Select based on and output to the timer memory 24.
When the selection timer on signal is active, the bus selection unit 23 fixedly determines the usage ratio of the CPU 10 and the timer 21 by time division based on the value of the cycle count signal from the timer 21. The bus selection unit 23 alternately selects the output signal of the CPU 10 and the output signal of the timer 21 based on the time-division time, and outputs the output signal to the timer memory 24.

When the selection timer on signal is non-active, the bus selection unit 23 outputs an access signal from the CPU 10 to the timer memory 24 and with respect to the timer memory 24 regardless of the time-division time. The read data is masked with "0" indicating that the timer is not used and output.
When the bus selection unit 23 receives an access from the CPU 10 at the time allocated to the CPU 10, the bus selection unit 23 immediately returns the CPU Ac signal to the CPU 10. On the other hand, when the bus selection unit 23 receives an access from the CPU 10 outside the time allocated to the CPU 10, the bus selection unit 23 causes the CPU 10 to stand by without immediately returning the CPU ack signal, and the time allocated to the CPU 10. When becomes, the CPU ack signal is returned to the CPU 10.

The timer memory 24 stores the timer value. The timer memory 24 is subjected to write and read processing by the CPU 10 and the timer 21 via the bus selection unit 23.
The address '0' of the timer memory 24 is associated with the timer number '0' on a one-to-one basis, and the address n of the timer memory 24 is the timer number n.

Whether the timer-on control unit 25a snoops the signal that the CPU 10 accesses the timer memory 24, the timeout number to the timeout buffer 22, and the timeout buffer write signal to perform the timer value decrementing operation. Judge whether or not. The case where the timer value decrement operation is performed is defined as timer on.
When the CPU 10 writes to the timer number x (integer of x = 0 to n) of the timer memory 24, the timer-on control unit 25a has the timer number x the timer off if the write data value is '0'. Is determined.

Further, the timer-on control unit 25a determines that the timer number x is timer-on when the CPU 10 writes to the timer number x of the timer memory 24 and the write data value is other than '0'.
Further, the timer-on control unit 25a determines that the timer number x is timer-off when the timer 21 writes the timer number x to the timeout buffer 22.
Further, the timer-on control unit 25a includes a 1-bit register that holds timer on / off information for the number of timers, and holds the timer on / off determination result in the register assigned to each timer number.
Further, the timer-on control unit 25a selects a register of the corresponding timer number according to the timer number output from the timer 21, and outputs the value of the selected register as a selection timer-on signal to the bus selection unit 23.

The bus 26 is a signal line connected to the CPU 10, the timer 21, the timeout buffer 22, the bus selection unit 23, and the timer-on control unit 25a, and for exchanging data between them.

FIG. 2 is a block diagram showing a configuration of a bus selection unit 23 according to the first embodiment of the present invention. The bus selection unit 23 includes a timer selection signal generation unit 231, a CPU control unit 232, a selector 233, and a mask control unit 234.

The timer selection signal generation unit 231 generates a timer selection signal that is fixedly determined by time-dividing the usage ratio of the timer memory 24 by the CPU 10 and the timer 21 based on the timer cycle count signal from the timer 21, and mask control. Output to unit 234.

The CPU control unit 232 detects access to the timer memory 234 from the CPU 10, and if the mask timer selection signal is '0', immediately outputs a CPU ack signal to the CPU 10. On the other hand, when the mask timer selection signal is '1', the CPU control unit 232 waits until the mask timer selection signal becomes '0', and then outputs the CPU ack signal to the CPU 10.
The CPU control unit 232 detects a write access from the CPU 10 to the timer memory 234, and outputs a CPU retiming write signal whose timing is matched to the CPU ack signal to the selector 233.
The CPU control unit 232 detects read access from the CPU 10 to the timer memory 24, and outputs the input RAM read data as CPU read data whose timing is adjusted to the CPU ack signal.

When the value of the mask timer selection signal is '0', the selector 233 outputs the address and data of the CPU 10 and the CPU retiming write signal to the timer memory 24.
When the value of the mask timer selection signal is '1', the selector 233 outputs the timer number of the timer 21, the timer write data, and the timer write signal to the timer memory 24.

The mask control unit 234 performs '0' mask control of the timer read data output to the timer 21 and mask control of the mask timer selection signal based on the timer selection signal and the selection timer on signal from the timer on control unit 25a. The control result is output to the CPU control unit 232 and the selector 233.
The mask control unit 234 sets the timer read data to '0' when the selection timer on signal is '0'. Further, the mask control unit 234 sets the mask timer selection signal to '0'.
When the selection timer on signal is '1', the mask control unit 234 outputs RAM read data as timer read data. Further, the mask control unit 234 outputs a timer selection signal as a mask timer selection signal.

FIG. 3 is a block diagram showing a configuration of a timer-on control unit 25a according to the first embodiment of the present invention. The timer-on control unit 25a includes a CPU set pulse generation unit 251, a CPU clear pulse generation unit 252, a register unit 253a, a signal selection unit 254, a timeout clear pulse generation unit 255, and a clear pulse synthesis unit 256.

The CPU setup pulse generation unit 251 refers to the timer number x (an integer of x = 0 to n) of the timer memory 24 based on the CPU address and CPU data from the CPU 10 and the CPU retiming write signal from the bus selection unit 23. When the light data is written other than '0', the set pulse x is activated.

The CPU clear pulse generation unit 252 refers to the timer number x (integer of x = 0 to n) of the timer memory 24 based on the CPU address and CPU data from the CPU 10 and the CPU retiming write signal from the bus selection unit 23. When the write data is '0', the clear pulse x is activated.

The register unit 253a is composed of registers 253a-0, ..., 253a-n corresponding to the number of timers, and when the corresponding clear pulse is active, the register value is set to "0". On the other hand, the register unit 253a sets the register value to '1' when the corresponding set pulse is active. The register unit 253a outputs the register value to the signal selection unit 254 as a timer-on signal.

The signal selection unit 254 selects the timer-on signal from the register unit 253a based on the timer number from the timer 21, and outputs it to the bus selection unit 23 as the selection timer-on signal.

The timeout clear pulse generation unit 255 clears the timer number x (integer of x = 0 to n) of the timer memory 24 based on the timeout number from the timer 21 and the timeout buffer write signal. Activate pulse x.

The clear pulse synthesis unit 256 takes the logical sum of the clear pulse x of the CPU clear pulse generation unit 252 and the clear pulse x from the timeout clear pulse generation unit 255, and outputs the logical sum to the register unit 253a.

FIG. 4 is a timing chart showing the operation of the hardware timer 20 according to the first embodiment of the present invention.
The signal of reference numeral (a) in FIG. 4 indicates a clock signal. Here, the clock period is 10 ns (nanoseconds).
The signal of reference numeral (b) in FIG. 4 indicates a RAM address (timer number). Here, it consists of a total of n + 1 timer numbers from 0 to n. One clock is assigned to each timer number, and when the timer number advances to n, the timer number returns to 0.
The signal of reference numeral (c) in FIG. 4 indicates a timer selection signal. The timer selection signal indicates whether the timer corresponding to the RAM address (timer number) is ON (ON) or OFF (OFF). Here, the case where the timer with the timer number 0 is turned on, the timer with the timer number 1 is turned off, and the timers with the timer numbers 2 to n are turned on is shown.

The signal of reference numeral (d) in FIG. 4 indicates a RAM address (timer number).
The signal of reference numeral (e) in FIG. 4 indicates a timer selection signal.
The signal of reference numeral (f) in FIG. 4 indicates a timer cycle count signal. The timer cycle count signal increases from 0 to r, and then repeats the process of counting from 0 to r.
The signal of reference numeral (g) in FIG. 4 indicates a bus selection operation signal. The bus selection operation signal is a signal for selecting either the CPU 10 or the timer (TIMER) 21. Here, when the RAM address (timer number) is 1, the timer 21 is selected when the timer cycle count is between 1 and 4, and the CPU 10 is selected when the timer cycle count is between 5 and r. It shows the case where it is selected.
The signals of reference numerals (d) to (g) in FIG. 4 are mainly shown by enlarging the portion where the RAM address (timer number) of the signal of reference numeral (b) is 1.

The signal of reference numeral (h) in FIG. 4 indicates a case where the RAM address (timer number) of reference numeral (d) is 1 and the timer cycle count is 1 to 4, and the timer 21 sets the signal. Indicates the processing to be performed. Here, when the RAM address (timer number) is 1, and the timer cycle count is 1 to 4, the timer 21 reads the timer value, determines the timer value, decrements the timer value, and writes the decrement value (decrement value write). Timeout buffer write) is processed.

FIG. 5 is a flowchart showing the operation of the timer 21 according to the first embodiment of the present invention. The timer 21 determines whether or not the CPU 10 has instructed the timer operation to be turned on (step S101). If the timer 21 has not received an instruction from the CPU 10 to set the timer operation to ON (No in step S101), the timer 21 again performs the process of step S101.
When the timer 21 receives an instruction from the CPU 10 to set the timer operation on (Yes in step S101), the timer 21 performs the process of step S102.
That is, the timer 21 starts timer access from the timer number 0 (step S102). Then, the timer 21 reads the timer value from the timer memory 24 (step S103). When the timer operation corresponding to the timer number is stopped, the timer 21 outputs '0' as a timer cycle count signal to prohibit the timer 21 from accessing the timer memory 24.

Next, the timer 21 determines whether or not the timer value is 0 (step S104). That is, the timer 21 determines whether or not the timer value is in an unused state. When the timer 21 determines that the timer value is 0 (Yes in step S104), the timer 21 performs the process of step S105.
That is, the timer 21 adds (increments) 1 to the timer number (step S105).

Then, the timer 21 determines whether or not the timer number is n, which is the maximum number (step S106). When the timer 21 determines that the timer number is not n (No in step S106), the timer 21 performs the process of step S103 described above. On the other hand, when the timer 21 determines that the timer number is n (Yes in step S106), the timer 21 performs the process of step S107.
That is, the timer 21 determines whether or not the CPU 10 has instructed the timer operation to be turned off (step S107). When the timer 21 receives an instruction from the CPU 10 to set the timer operation to off (Yes in step S107), the timer 21 ends the processing of the flowchart shown in FIG. 5 and stops the operation. In this case, the timer 21 sets the timer cycle count signal to '0'.

On the other hand, when the timer 21 has not received the instruction of the timer operation off setting from the CPU 10 (No in step S107), the timer 21 performs the process of step S108.
That is, the timer 21 determines whether or not the timer update cycle has been reached (step S108). If it is determined that the timer 21 has not reached the timer update cycle (No in step S108), the timer 21 again performs the process of step S108.
On the other hand, when the timer 21 determines that the timer update cycle has been reached (Yes in step S108), the timer 21 sets the timer number to '0' and performs the process of step S102 described above.

On the other hand, when the timer 21 determines that the timer value is not 0 (No in step S104), the timer 21 performs the process of step S109.
That is, the timer 21 determines whether or not the timer value is 1 (step S109). When the timer 21 determines that the timer value is 1 (Yes in step S109), the timer 21 performs the process of step S110.
That is, the timer 21 determines whether or not the timeout buffer 22 is full (step S110). When the timer 21 determines that the timeout buffer 22 is full (Yes in step S110), the timer 21 performs the process of step S105 described above.

On the other hand, when the timer 21 determines that the timeout buffer 22 is not full (No in step S110), the timer 21 performs the process of step S111.
That is, the timer 21 subtracts (decrements) 1 from the timer value (step S111).
Then, the timer 21 writes the timer value to the timer memory 24, writes the timer number to the timeout buffer 22 (step S112), and performs the process of step S105 described above.

On the other hand, when the timer 21 determines that the timer value is not 1 (No in step S109), the timer 21 performs the process of step S113.
That is, the timer 21 subtracts 1 from the timer value (step S113).
Then, the timer 21 writes the timer value to the timer memory 24 (step S114), and performs the process of step S105 described above.

FIG. 6 is a flowchart showing the operation of the register unit 253a of the timer-on control unit 25a according to the first embodiment of the present invention.
First, the register unit 253a determines whether or not the timer number has been updated (step S201). When the register unit 253a determines that the timer number has not been updated (No in step S201), the register unit 253a again performs the process of step S201.
On the other hand, when the register unit 253a determines that the timer number has been updated (Yes in step S201), the register unit 253a performs the process of step S202.

That is, the register unit 253a determines whether or not the CPU 10 has updated the timer memory 24 (step S202).
When the register unit 253a determines that the timer memory 24 has been updated from the CPU 10 (Yes in step S202), the register unit 253a performs the process of step S203.

That is, the register unit 253a determines from the CPU 10 whether or not there is a write other than the write data value '0' (step S203).
When the register unit 253a determines from the CPU 10 that there is a write other than the write data value '0' (Yes in step S203), the register unit 253a sets the timer number x register to timer on (step). S204).
On the other hand, when the register unit 253a determines from the CPU 10 that there is no write other than the write data value '0' (No in step S203), the register unit 253a sets the timer number x register to timer off. (Step S206).

If the register unit 253a determines that the CPU 10 has not updated the timer memory 24 (No in step S202), the register unit 253a performs the process of step S205.
That is, the register unit 253a determines whether or not the timer 21 has updated the timeout buffer 22 (step S205).
When the register unit 253a determines that the timer 21 has updated the timeout buffer 22 (Yes in step S205), the register unit 253a performs the process of step S206 described above.
On the other hand, when the register unit 253a determines that the timer 21 has not updated the timeout buffer 22 (No in step S205), the register unit 253a performs the process of step S201 described above.

FIG. 7 is a flowchart showing the operation of the signal selection unit 254 of the timer-on control unit 25a according to the first embodiment of the present invention.
First, the signal selection unit 254 determines whether or not the timer number x has been updated (step S301). When the signal selection unit 254 determines that the timer number x has not been updated (No in step S301), the signal selection unit 254 performs the process of step S301 again.
On the other hand, when the signal selection unit 254 determines that the timer number x has been updated (Yes in step S301), the signal selection unit 254 performs the process of step S302.

That is, the signal selection unit 254 determines whether the register value indicated by the timer number x is on or off (step S302).
When the signal selection unit 254 determines that the register value indicated by the timer number x is on (on in step S302), the signal selection unit 254 allows the timer 21 to access the timer memory 24. The bus selection unit 23 is switched (step S303), and the process of step S301 described above is performed.
On the other hand, when the signal selection unit 254 determines that the register value indicated by the timer number x is off (off in step S302), the signal selection unit 254 allows the CPU 10 to access the timer memory 24. , The bus selection unit 23 is switched (step S304), and the process of step S301 described above is performed.

The operation of the hardware timer 20 according to this embodiment will be described below.
First, the CPU 10 sets a timer initial value in the timer number x of the timer memory 24 having an address area corresponding to the number of timers.
The maximum value of the timer value is determined by the data width of the timer memory 24. For example, when the data width of the timer memory 24 is 16 bits, the maximum value of the timer value is 65535, so that the hardware timer 20 can count up to the value of (timer update cycle) × (65535).

The bus selection unit 23 detects write access from the CPU 10 to the timer memory 24, generates a CPU ack signal only for the time when the CPU 10 can access the timer memory 24, and causes the timer memory 24 to have a CPU address and CPU data. , Outputs a retimed light signal. The address and data output from the bus selection unit 23 and the initial timer value are written to the timer memory 24.
After the write of the initial value of the timer is finished, the CPU 10 sets the timer operation on (Yes in step S101 of FIG. 5). The timer 21 detects the timer operation on setting from the CPU 10 and starts incrementing the timer cycle count. In the timer cycle count, the values 0 to r are repeated.

Every time the timer cycle count returns to 0, the timer number (RAM address) is incremented.
The timer numbers from timer 0 to timer n are output for each timer update cycle (steps S103 to S106 in FIG. 5). As shown by the reference numerals (f) and (h) of FIG. 4, the timer 21 has a timer value read, a timer value determination, a timer value decrement, and a decrement value write (during the four clocks of the timer cycle counts 1 to 4). Timeout buffer write) is processed.
The timer-on control unit 25a snoops the signal that the CPU 10 accesses the timer memory 24, the timeout number to the timeout buffer 22, and the timeout buffer write signal, and determines whether or not the timer value decrement operation is performed. judge. Here, the case where the timer value decrement operation is performed is defined as timer on. A case other than timer on is defined as timer off.

When the CPU 10 writes to the timer number x (x = 0 to n) of the timer memory 24 and the write data value is '0', the timer-on control unit 25a is in the timer-off state. Is determined.
When the CPU 10 writes to the timer number x of the timer memory 24, the timer-on control unit 25a determines that the timer number x is in the timer-on state when the write data value is other than '0'.
When the timer 21 writes the timer number x to the timeout buffer 22, the timer-on control unit 25a determines that the timer number x is in the timer-off state.
The timer-on control unit 25a includes a 1-bit register that holds timer on / off information for the number of timers, and records the timer on / off determination result in the register of the corresponding timer number.

The timer-on control unit 25a selects a register having a corresponding timer number based on the timer number from the timer 21, and outputs the value of the selected register to the bus selection unit 23 as a selection timer-on signal.
When the selection timer on signal is '1', the bus selection unit 23 determines that the timer 21 is in the on state, and gives the timer 21 access to the timer memory 24 within 1 to 4 times of the timer cycle count. to approve. On the other hand, when the selection timer on signal is '0', the bus selection unit 23 determines that the timer 21 is in the off state, and even if the time is 1 to 4 of the timer cycle count, the timer memory 24 is stored in the CPU 10. (Section of timer number 1 of reference numerals (b) and (d) in FIG. 4).
In this case, the time when the CPU 10 is allowed to access the timer memory 24 masks the read data of the timer memory 24 to '0' in order to make the timer 21 appear to be reading the timer memory 24. To do.

After reading the timer value, if the timer value is '1' and the timeout buffer 22 is not full, the timer 21 determines that the timer has timed out, decrements the timer value, and writes the decremented timer value to the timer memory 24. At the same time, the timer number is written to the timeout buffer 22.
After reading the timer value, the timer 21 times out when the timer value is '1' and the timeout buffer 22 is full, and when the next timer value having the same timer number is read without performing any processing. Check if the buffer 22 is in the full state.

The timeout buffer 22 activates an interrupt to the CPU 10 when the timer number is written.
When the timeout interrupt becomes active, the CPU 10 can acquire the timer number by reading the timeout buffer 22.
Here, the case where the timer initial value is written to the timer memory 24 and then the timer operation is set to be turned on for the timer 21 has been described. The initial value of the timer may be written after the start of.

As another method of using the timer 21, a method of observing the passage of time without timing out will be described. Here, the process of time measurement by the CPU 10 is defined as process y.
During the timer operation, the CPU 10 writes an initial value to the address x (timer number x) of the timer memory 24, performs processing y, and then reads the address x of the timer memory 24 to read the initial value. By taking the difference from the timer value, the time of processing y can be measured in units of timer update cycles.

According to the first embodiment of the present invention, when the timer memory 24 is accessed by the CPU 10 and the timer 21 in a time-divided manner, and the timer memory 24 is in the off state, the CPU 10 determines the timer memory 24. The timer memory 24 can be accessed without waiting for the time allotted to the timer memory 24 to elapse. Therefore, the usage time of the timer memory 24 by the CPU 10 can be increased.

Further, by performing mask control by the timer on control unit 25a and the bus selection unit 23, '0' is read from the timer 21 at the address where the timer value is not written, so that the initialization of the timer memory 24 is unnecessary. Can be.
Further, when a large-scale hardware timer 20 having a large number of timers is used, the CPU 10 writes or reads the timer value from the timer memory 24, and it takes time to write or read the timer value. Even in this case, the usage time of the timer memory 24 by the CPU 10 can be increased, so that the performance deterioration of the bus 26 can be avoided.

Next, a second embodiment of the present invention will be described. In addition, about the part where the 2nd Embodiment is the same as the 1st Embodiment, those processings will be described.
In the first embodiment, the hardware timer 20 includes a timer-on control unit 25a, but the hardware timer 20 according to the second embodiment is different in that it includes a timer-on control unit 25b.

FIG. 8 is a block diagram showing a configuration of a timer-on control unit 25b according to a second embodiment of the present invention. The timer-on control unit 25b includes a CPU set pulse generation unit 251, a CPU clear pulse generation unit 252, a register unit 253a, and a signal selection unit 254.
In the timer-on control unit 25b (FIG. 8), the timeout clear pulse generation unit 255 and the clear pulse synthesis unit 256 are omitted in the timer-on control unit 25a (FIG. 3) according to the first embodiment. In the second embodiment, the timeout number from the timeout buffer 22 and the timeout buffer write signal are not used.

In the hardware timer 20 according to the second embodiment, although the time during which the CPU 10 can access the timer memory 24 is reduced, it is not necessary to provide a configuration for determining the timer off of the timer number that has timed out, so that the hardware timer 20 is compared with the first embodiment. Therefore, the active section of the selection timer on signal increases. Therefore, the hardware timer 20 according to the second embodiment can be applied to a circuit that does not have a timeout buffer 22.

Next, a third embodiment of the present invention will be described. In addition, about the part where the 3rd Embodiment is the same as the 1st Embodiment, those processings will be described.
In the first embodiment, the hardware timer 20 includes a timer-on control unit 25a, but the hardware timer 20 according to the third embodiment is different in that it includes a timer-on control unit 25c.

FIG. 9 is a block diagram showing a configuration of a timer-on control unit 25c according to a third embodiment of the present invention. The timer-on control unit 25c includes a CPU set pulse generation unit 251, a register unit 253c, and a signal selection unit 254.
In the timer-on control unit 25c (FIG. 9), the CPU clear pulse generation unit 252 is omitted in the timer-on control unit 25b (FIG. 8) according to the second embodiment. Further, the timer-on control unit 25c (FIG. 9) includes a register unit 253c instead of the register unit 253a (FIG. 8) according to the second embodiment.

The timer-on control unit 25c (FIG. 9) according to the third embodiment includes register units 253c for the number of timers, which can be set to turn on / off the timer by write access from the CPU 10. The register unit 253c is provided in an address area other than the timer memory 24, and when the CPU data register setting is "1", the timer is turned on, and when the register setting is "0", the timer is turned off.

In the hardware timer 20 according to the third embodiment, although it is necessary to provide the same address area as the timer 21 separately from the timer 21, the timer number (address) set as the timer off can be used for the data stack. it can.

In the third embodiment, the CPU set pulse generates set pulses of the register unit 253c corresponding to the number of timers mapped to the address area other than the timer memory 24. When the CPU write is '1' and the CPU address is an arbitrary address x (an integer of x = 0 to n), the set pulse x is activated.
The registers 253c-0 to 253cn constituting the register unit 253c record one bit of CPU data in the register 253c-x when the set pulse x is active. The set value of the register 253c-x is output to the signal selection unit 254 as a timer-on signal.
The signal selection unit 254 selects a timer-on signal corresponding to the value of the timer number x from the timer 21 and outputs it to the bus selection unit 23 as a selection timer-on signal.

Next, a fourth embodiment of the present invention will be described. In addition, about the part where the 4th Embodiment is the same as the 1st Embodiment, those processings will be described.
In the first embodiment, the hardware timer 20 includes a timer-on control unit 25a, but the hardware timer 20 according to the fourth embodiment is different in that it includes a timer-on control unit 25d.

FIG. 10 is a block diagram showing a configuration of a timer-on control unit 25d according to a fourth embodiment of the present invention. The timer-on control unit 25d includes a CPU set pulse generation unit 251, an upper limit register 301, a lower limit register 302, and a comparator 303.
The upper limit register 301 stores the upper limit of the timer number. Further, the lower limit register 302 stores the lower limit value of the timer number.

In the first to third embodiments, registers corresponding to the number of timers are provided, but the timer on control unit 25d according to the fourth embodiment does not hold on / off of each timer, but has a timer number. An upper limit register 301 and a lower limit register 302 in which an upper limit and a lower limit can be set are provided in an address area other than the timer memory 24. Then, the timer-on control unit 25d activates the selection timer-on signal when the timer number from the timer 21 is within the range from the lower limit to the upper limit.
According to the fourth embodiment, as compared with the first to third embodiments, it is not necessary to provide registers for the number of timers, so that the circuit scale of the hardware timer 20 can be reduced and the timer is turned off. Area can be used for the data stack.
In the fourth embodiment, the timer-on area needs to be initialized, but the efficiency of access from the CPU 10 during the operation of the timer 21 to the timer memory 24 can be improved.

In FIG. 10, the CPU set pulse generation unit 251 activates the lower limit set pulse when it is the address of the lower limit set pulse based on the CPU address and the CPU write signal from the CPU 10.
The CPU set pulse generation unit 251 activates the upper limit set pulse when it is the address of the upper limit set pulse based on the CPU address from the CPU 10 and the CPU write signal.

The upper limit register 301 captures and holds CPU data from the CPU 10 when the upper limit set pulse is active.
The lower limit register 302 captures and holds CPU data from the CPU 10 when the lower limit set pulse is active.
The comparator 303 uses the value held by the lower limit register 302 as the lower limit value and the value held by the upper limit register 301 as the upper limit value. The comparator 303 activates the selection timer on signal when the timer number from the timer 21 is within the range from the lower limit value to the upper limit value. When the timer number from the timer 21 is out of the range from the lower limit value to the upper limit value, the selection timer on signal is deactivated.
By combining the first embodiment and the fourth embodiment, it is not necessary to initialize the timer-on area, and by snooping the state of each timer in the timer-on area, the timer can be started from the CPU 10. The efficiency of access to the memory 24 can be maximized.

FIG. 11 is a block diagram showing the configuration of the hardware timer 400 having the minimum configuration. The hardware timer 400 includes a selection unit 401 and a control unit 402.

FIG. 12 is a flowchart showing the processing of the hardware timer 400.
First, the selection unit 401 has either a first state in which the CPU (Central Processing Unit) 10 can access the timer memory 24 or a second state in which the timer 21 can access the timer memory 24. Is selected (step S401).
Then, the control unit 402 is the second of the first time allocated as the time that the CPU 10 can access the timer memory 24 and the second time allocated as the time that the timer 21 can access the timer memory 24. If the timer 21 is off even within the time of 2, the selection unit 401 is made to select the first state (step S402).

A program for realizing the functions of each part in FIG. 1 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system and executed to process each part. You may. The term "computer system" as used herein includes hardware such as an OS and peripheral devices. Further, the "computer-readable recording medium" refers to a portable medium such as a flexible disk, a magneto-optical disk, a ROM, or a CD-ROM, or a storage device such as a hard disk built in a computer system. Furthermore, a "computer-readable recording medium" is a volatile memory (RAM) inside a computer system that serves as a server or client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line. In addition, it shall include those that hold the program for a certain period of time.

In some aspects of the present invention, a hardware timer, a control method, and a program that require an increase in the usage time of the timer memory by the CPU when the timer memory is accessed by the CPU and the timer in a time-divided manner. It can be applied to.

10 ... CPU
20 ... Hardware timer 21 ... Timer 22 ... Timeout buffer 23 ... Bus selection unit 24 ... Timer memory 25a, 25b, 25c, 25d ... Timer on control unit 26 ... Bus 231 ... Timer selection signal generation unit 232 ... CPU control unit 233 ... Selector 234 ... Mask control unit 251 ... CPU set pulse generation unit 252 ... CPU clear pulse generation unit 253a ... Register Unit 253c ... Register unit 253a-0 to 253an ... Register 253c-0 to 253cn ... Register 254 ... Signal selection unit 255 ... Timeout clear Pulse generation unit 256 ... Clear Pulse synthesis unit 301 ... Upper limit register 302 ... Lower limit register 303 ... Comparer 400 ... Hardware timer 401 ... Selection unit 402 ... Control unit

Claims (10)

A selection unit that selects either a first state in which the central processing unit can access the timer memory and a second state in which the timer can access the timer memory.
Of the first time allocated as the time that the central processing unit can access the timer memory and the second time allocated as the time that the timer can access the timer memory, the second time. A control unit that causes the selection unit to select the first state when the timer is off even within the time period.
Hardware timer with. When the timer is on and the selection unit selects the second state, the control unit permits the timer to access the timer memory. The hardware timer according to claim 1, which does not allow access to the timer memory by the central processing unit. The control unit determines whether or not the timer has timed out and whether or not the timer has been unused, and when the timer has timed out or the timer has not yet been used. The hardware timer according to claim 1 or 2, wherein the timer is determined to be off when it is in use. The control unit determines whether or not the timer has timed out and whether or not the timer has not been used, and if the timer has not timed out or the timer has not yet been used. The hardware timer according to claim 1 or 2, wherein the timer is determined to be on when not in use. The hardware timer according to any one of claims 1 to 4, wherein the selection unit alternately selects the first state and the second state in a time division manner. When the timer is off, and the selection unit selects the first state, and the read process of the timer occurs, the selection unit uses the timer. The hardware timer according to any one of claims 1 to 5, which outputs a signal indicating that the timer is unused. Of the plurality of timer numbers stored in the timer memory, a timeout buffer for storing the timer number that has timed out is further provided.
The hardware timer according to any one of claims 1 to 6, wherein the control unit causes the selection unit to select the first state for the time allocated to the timer number that has timed out. The present invention according to any one of claims 1 to 7, which is a register that stores a plurality of timer numbers in association with each other and whether the state is on or off, and further includes registers equal to or less than the number of the plurality of timer numbers. The described hardware timer. One of the first state in which the central processing unit can access the timer memory and the second state in which the timer can access the timer memory is selected.
Of the first time allocated as the time that the central arithmetic processing device can access the timer memory and the second time allocated as the time that the timer can access the timer memory, the second time. A method of controlling a hardware timer that selects the first state when the timer is off even within a time period. A selection means for selecting either a first state in which the central processing unit can access the timer memory and a second state in which the timer can access the timer memory.
Of the first time allocated as the time that the central processing unit can access the timer memory and the second time allocated as the time that the timer can access the timer memory, the second time. A control means that causes the selection means to select the first state even within the time when the timer is off.
A program that functions as.

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