JP6763754B2 - Manufacturing method of substrate terminal board for mounting semiconductor elements - Google Patents

Manufacturing method of substrate terminal board for mounting semiconductor elements Download PDF

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JP6763754B2
JP6763754B2 JP2016224339A JP2016224339A JP6763754B2 JP 6763754 B2 JP6763754 B2 JP 6763754B2 JP 2016224339 A JP2016224339 A JP 2016224339A JP 2016224339 A JP2016224339 A JP 2016224339A JP 6763754 B2 JP6763754 B2 JP 6763754B2
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terminal portion
substrate
electrode
electrode terminal
lower substrate
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JP2018082093A (en
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雅也 中川
雅也 中川
正二郎 若林
正二郎 若林
真擁 湯浅
真擁 湯浅
稔文 渡辺
稔文 渡辺
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SANCALL CORPORATION
Stanley Electric Co Ltd
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Stanley Electric Co Ltd
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本発明は、半導体素子、例えば消費電力の大きく発熱量が多いLEDチップ、LSI、CPUなどの素子を取り付けるための部分を有するとともに、電極線との接続を行なう端子部分も有する取付用基板端子板を、簡易な構成で製造できるようにした製造方法に関するものである。 The present invention has a mounting substrate terminal board having a portion for mounting a semiconductor element, for example, an element such as an LED chip, LSI, or CPU that consumes a large amount of power and generates a large amount of heat, and also has a terminal portion for connecting to an electrode wire. It is related to the manufacturing method which made it possible to manufacture with a simple structure.

従来から消費電力が大きいLED素子においては、チップをガラスエポキシ基板に封じ込めて端子を表出した構成としているものがある。そしてこの種のLED素子では発熱量が大きいなどの理由から、他の素子類や装置と同じ回路基板に並べ設けることはせずに、LED素子への専用の電極線を設けてLED素子へ給電を行なっていて、LED素子の接点と電極線との間は、導電性を有する金属板を所定形状に折り曲げた接続部品を用いて導通させるようにしていた。 Conventionally, some LED elements that consume a large amount of power have a configuration in which a chip is enclosed in a glass epoxy substrate to expose terminals. Since this type of LED element generates a large amount of heat, it is not provided side by side on the same circuit board as other elements and devices, but a dedicated electrode wire for the LED element is provided to supply power to the LED element. The contact between the contact point of the LED element and the electrode wire was made conductive by using a connecting component in which a conductive metal plate was bent into a predetermined shape.

例えば特許文献1、2に示されているようにLED素子を保持することのできるボックス部分を備えてLED素子の端子と接続できる接続部品と、LED素子の他方の接点と接続することのできる接続部品とを対にして用意している。そしてLED素子の前記他方の接点に接続できる接続部品を電極線であるケーブルに取り付けたのち、もう一つの接続部品をケーブルに取り付け、ボックス部分にLED素子を嵌め入れることで、各接続部品がLED素子の接点に接触するようにしていた。 For example, as shown in Patent Documents 1 and 2, a connection component having a box portion capable of holding an LED element and capable of connecting to a terminal of the LED element and a connection capable of connecting to the other contact of the LED element. It is prepared as a pair with the parts. Then, after attaching a connection component that can be connected to the other contact of the LED element to the cable that is the electrode wire, another connection component is attached to the cable, and the LED element is fitted into the box portion, so that each connection component is an LED. It was designed to come into contact with the contacts of the element.

また対の接続部品とLED素子とをデバイスホルダーに組み入れることで、デバイスホルダーの内部でLED素子の接点と接続部品とが接触し、デバイスホルダーで電極線のケーブルを挟むことで接続部品がケーブルと接触するようにした点も示されている。 In addition, by incorporating the pair of connecting parts and the LED element into the device holder, the contacts of the LED element and the connecting parts come into contact with each other inside the device holder, and by sandwiching the electrode wire cable between the device holders, the connecting parts become the cable. The points of contact are also shown.

特許第4934545号公報Japanese Patent No. 4934545 特許第5203035号公報Japanese Patent No. 5203035

しかしながら、ケーブルなどの電極線からLED素子側に給電を行なえるようにするために、二つの接続部品を独立させて電極線に取り付けたりデバイスホルダーに組み付けるようにしなければ、接続部品間の絶縁を保った状態でのLED素子側への接続が行なえない。このようにLED素子への給電には二つの接続部品が必要でそれぞれ単独で取り扱うものとなる。ましてやLEDチップへの給電に対してこのような構成を採用すると接続部品それぞれの構造が非常に複雑になり、接続部品の管理が煩雑になるという欠点がある。 However, in order to be able to supply power from the electrode wire such as a cable to the LED element side, if the two connecting parts are not attached to the electrode wire independently or attached to the device holder, the insulation between the connecting parts must be provided. It is not possible to connect to the LED element side while maintaining it. As described above, two connecting parts are required to supply power to the LED element, and each of them is handled independently. Furthermore, if such a configuration is adopted for supplying power to the LED chip, the structure of each connecting component becomes very complicated, and there is a drawback that the management of the connecting component becomes complicated.

上述した点はLED素子やLEDチップ用のものに限られた欠点ではなく、発熱するLSI、CPUなどの半導体素子製品用のものの場合でも同様の欠点であった。 The above-mentioned points are not limited to those for LED elements and LED chips, but also have the same drawbacks for semiconductor element products such as LSIs and CPUs that generate heat.

そこで本発明は上記事情に鑑み、複数の独立した部品を用いることなしに半導体素子への電気の供給が行えるようにすることを課題とし、半導体素子が取り付けられる取り扱い容易な基板端子板を提供することを目的とするものである。 Therefore, in view of the above circumstances, it is an object of the present invention to make it possible to supply electricity to a semiconductor element without using a plurality of independent parts, and to provide an easy-to-handle substrate terminal board to which the semiconductor element is attached. The purpose is to do that.

(請求項1の発明)
本発明は上記課題を考慮してなされたもので、端子板上面中央に、半導体素子に接続するための第一素子接続端子部と第二素子接続端子部とを対にして備えて半導体素子を配置可能にした素子取付部を有し、端子板辺部に、電極線を接続するための第一電極端子部と第二電極端子部とからなる電極端子部を有している半導体素子取付用基板端子板を製造する方法であって、
導電性金属板から、上面中央に前記第一素子接続端子部が設けられ、一隅に前記第一電極端子部が設けられ、この第一電極端子部の近傍に電極線拘束部が配されている下基板を形成するとともに、
導電性金属板から、前記下基板と重ね合わせたときの前記第一素子接続端子部に対応する部分にして透孔が開口され、この透孔の周辺に前記第二素子接続端子部が設けられ、下基板と重ね合わせたときの前記第一電極端子部と対向する位置に前記第二電極端子部が設けられ、この第二電極端子部の近傍に電極線拘束部が配されている上基板を形成し、
前記下基板と上基板とを、耐熱性と絶縁性とを有する電着塗料を用いた電着塗装を施してなる樹脂被覆膜で被覆して、前記各電極線拘束部を樹脂被覆膜で覆われた状態とし、
前記下基板の第一素子接続端子部に前記上基板の透孔を対応させるとともに、下基板の第一電極端子部と電極拘束部とが上基板の第二電極端子部と電極線拘束部とに重ならない非重合状態となるようにして、下基板の上に上基板を重ね合わせ、
この重ね合わされた状態での下基板と上基板とに対して加圧加熱処理を施すことにより、下基板と上基板との間の樹脂被覆膜同士を接着させ、
この接着による下基板と上基板との連結により、第一素子接続端子部と第二素子接続端子部とを備えた前記素子取付部を有するとともに、それぞれが電極線拘束部を近傍に配した第一前記電極端子部と第二電極端子部とを配した前記電極端子部を有する一つの基板端子板を形成することを特徴とする半導体素子取付用基板端子板の製造方法を提供して、上記課題を解消するものである。
(Invention of claim 1)
The present invention has been made in consideration of the above problems, and a semiconductor element is provided in the center of the upper surface of a terminal plate by providing a pair of a first element connection terminal portion and a second element connection terminal portion for connecting to a semiconductor element. For mounting a semiconductor device having an element mounting portion that can be arranged and having an electrode terminal portion composed of a first electrode terminal portion and a second electrode terminal portion for connecting an electrode wire on the side portion of the terminal plate. It is a method of manufacturing a board terminal board.
From the conductive metal plate, the first element connection terminal portion is provided in the center of the upper surface, the first electrode terminal portion is provided in one corner, and an electrode wire restraint portion is arranged in the vicinity of the first electrode terminal portion. While forming the lower substrate
A through hole is opened from the conductive metal plate at a portion corresponding to the first element connection terminal portion when superposed on the lower substrate, and the second element connection terminal portion is provided around the through hole. The upper substrate is provided with the second electrode terminal portion at a position facing the first electrode terminal portion when superposed on the lower substrate, and the electrode wire restraint portion is arranged in the vicinity of the second electrode terminal portion. Form and
The lower substrate and the upper substrate are coated with a resin coating film obtained by electrodeposition coating using an electrodeposition coating having heat resistance and insulating properties, and each electrode line restraint portion is covered with a resin coating film. Covered with
The first element connection terminal portion of the lower substrate is made to correspond to the through hole of the upper substrate, and the first electrode terminal portion and the electrode restraint portion of the lower substrate are the second electrode terminal portion and the electrode wire restraint portion of the upper substrate. Lay the upper substrate on the lower substrate so that it does not overlap with the lower substrate.
By applying pressure and heat treatment to the lower substrate and the upper substrate in this superposed state, the resin coating films between the lower substrate and the upper substrate are adhered to each other.
By connecting the lower substrate and the upper substrate by this adhesion, the element mounting portion provided with the first element connecting terminal portion and the second element connecting terminal portion is provided, and each of them has an electrode wire restraining portion arranged in the vicinity. (I) A method for manufacturing a substrate terminal plate for mounting a semiconductor element, which comprises forming one substrate terminal plate having the electrode terminal portion in which the electrode terminal portion and the second electrode terminal portion are arranged, is provided. It solves the problem.

(請求項2の発明)
そして、本発明において、上記電極線拘束部は、基板厚さ方向に貫通した透孔、または基板厚さ方向での上方に向けて凸となる隆起形状物であることが良好である。
(Invention of claim 2)
In the present invention, the electrode wire restraint portion is preferably a through hole penetrating in the substrate thickness direction or a raised shape that is convex upward in the substrate thickness direction.

(請求項3の発明)
また、本発明において、上記下基板における電極線拘束部と第一電極端子部とを配する部分と上記上基板の電極線拘束部と第二電極端子部とを配する部分とが、それぞれギボシ端子とされていて、下基板の前記ギボシ端子に電極線拘束部と第一電極端子部とが形成されているとともに、上基板の前記ギボシ端子に電極線拘束部と第二電極端子部とが形成されていることが良好である。
(Invention of claim 3)
Further, in the present invention, the portion of the lower substrate where the electrode wire restraint portion and the first electrode terminal portion are arranged and the portion of the upper substrate where the electrode wire restraint portion and the second electrode terminal portion are arranged are respectively. It is a terminal, and an electrode wire restraint portion and a first electrode terminal portion are formed on the Giboshi terminal on the lower substrate, and an electrode wire restraint portion and a second electrode terminal portion are formed on the Giboshi terminal on the upper substrate. It is good that it is formed.

(請求項4の発明)
また、本発明において、上記電着塗料を施す前に、上記第一素子接続端子部と上記第二素子接続端子部と上記第一電極端子部と上記第二電極端子部とのそれぞれにマスキングを施し、
下基板と上基板との上記連結後に前記マスキングを除去して、第一素子接続端子部と第二素子接続端子部と第一電極端子部と第二電極端子部と外方に表出させることが良好である。
(Invention of claim 4)
Further, in the present invention, before applying the electrodeposition paint, masking is applied to each of the first element connection terminal portion, the second element connection terminal portion, the first electrode terminal portion, and the second electrode terminal portion. Alms,
After the connection between the lower substrate and the upper substrate, the masking is removed so that the first element connection terminal portion, the second element connection terminal portion, the first electrode terminal portion, the second electrode terminal portion, and the outside are exposed. Is good.

(請求項5の発明)
また、本発明において、下基板と上基板との上記連結後に、第一素子接続端子部と第二素子接続端子部と第一電極端子部と第二電極端子部との部分を被覆する樹脂被覆膜を除去して、第一素子接続端子部と第二素子接続端子部と第一電極端子部と第二電極端子部とを外部に表出させることが可能である。
(Invention of claim 5)
Further, in the present invention, after the connection between the lower substrate and the upper substrate, the resin coating that covers the first element connection terminal portion, the second element connection terminal portion, the first electrode terminal portion, and the second electrode terminal portion. It is possible to remove the covering film so that the first element connection terminal portion, the second element connection terminal portion, the first electrode terminal portion, and the second electrode terminal portion are exposed to the outside.

(請求項1の発明の効果)
請求項1の発明によれば、下基板と上基板との樹脂被覆膜同士の接着によって、一つの半導体素子取付用基板端子板が形成され、その一つの半導体素子取付用基板端子板に、素子取付部と、それぞれ電極線拘束部が近接している第一電極端子部と第二電極端子部とを備える電極端子部とが設けられているので、半導体素子取付用基板端子板にて、従来のように対の接続部品をそれぞれ単独で取り扱うような取り扱いや管理の煩雑さを解消することができる。また絶縁層となる樹脂被覆膜同士の接着を利用して半導体素子取付用基板端子板を得るようにしているので、安価に製造することができて、コストを引き上げることも無いという優れた効果を奏するものである。
(Effect of the invention of claim 1)
According to the invention of claim 1, one semiconductor element mounting substrate terminal plate is formed by bonding the resin coating films of the lower substrate and the upper substrate to each other, and the one semiconductor element mounting substrate terminal plate is formed. Since the element mounting portion and the electrode terminal portion including the first electrode terminal portion and the second electrode terminal portion in which the electrode wire restraining portions are close to each other are provided, the semiconductor element mounting substrate terminal plate can be used. It is possible to eliminate the complexity of handling and management in which each pair of connecting parts is handled independently as in the conventional case. In addition, since the substrate terminal board for mounting the semiconductor element is obtained by utilizing the adhesion between the resin coating films as the insulating layer, it can be manufactured at low cost and does not raise the cost, which is an excellent effect. It plays.

また下基板と上基板との二つの基板を重ね合わせた簡単な構造であり、上下基板間の熱抵抗による熱損失が少なくなって良好な放熱を行なうことができるという効果を奏する。 Further, it has a simple structure in which two substrates, a lower substrate and an upper substrate, are superposed, and has an effect that heat loss due to thermal resistance between the upper and lower substrates is reduced and good heat dissipation can be performed.

(請求項2の発明の効果)
請求項2の発明によれば、電極線拘束部の形状が簡易なものであり、製造に係るコストを引き上げることなしに、電極線の接続がより確実になる半導体素子取付用基板端子板が得られるようになるという効果を奏する。
(Effect of the invention of claim 2)
According to the invention of claim 2, the shape of the electrode wire restraint portion is simple, and a substrate terminal plate for mounting a semiconductor element can be obtained in which the electrode wire connection is more reliable without increasing the manufacturing cost. It has the effect of being able to be used.

(請求項3の発明の効果)
請求項3の発明によれば、半導体素子取付用基板端子板が対のギボシ端子を有するものとなり、従来から公知の工具を用いて電極線の取付が確実に行えるようになる。
(Effect of the invention of claim 3)
According to the invention of claim 3, the substrate terminal plate for mounting the semiconductor element has a pair of giboshi terminals, and the electrode wire can be reliably mounted using a conventionally known tool.

(請求項4の発明の効果)
請求項4の発明によれば、第一素子接続端子部と第二素子接続端子部と第一電極端子部と第二電極端子部を、予め定められた位置に正確に設けることができるという優れた効果を奏する。
(Effect of the invention of claim 4)
According to the invention of claim 4, the first element connection terminal portion, the second element connection terminal portion, the first electrode terminal portion, and the second electrode terminal portion can be accurately provided at predetermined positions. Has an effect.

(請求項5の発明の効果)
請求項5の発明によれば、第一素子接続端子部と第二素子接続端子部と第一電極端子部と第二電極端子部での導体の表面が表出する部分の広さを適宜変更することができるという優れた効果を奏する。
(Effect of the invention of claim 5)
According to the invention of claim 5, the width of the portion where the surface of the conductor is exposed in the first element connection terminal portion, the second element connection terminal portion, the first electrode terminal portion, and the second electrode terminal portion is appropriately changed. It has an excellent effect of being able to do it.

本発明に係る半導体素子取付用基板端子板の製造方法の一例からなる半導体素子取付用基板端子板を示す説明図である。It is explanatory drawing which shows the substrate terminal board for semiconductor element mounting which comprises an example of the manufacturing method of the board terminal board for mounting a semiconductor element which concerns on this invention. 半導体素子取付用基板端子板を下基板と上基板とを分離した状態で示す説明図である。It is explanatory drawing which shows the substrate terminal board for mounting a semiconductor element in a state where the lower substrate and the upper substrate are separated. 本発明の半導体素子取付用基板端子板の製造方法で用いる下基板を図1A−A線に沿った断面で示す説明図である。It is explanatory drawing which shows the lower substrate used in the manufacturing method of the substrate terminal board for mounting a semiconductor element of this invention in the cross section along the line AA. 同じく第一の実施の形態で用いる上基板を図1A−A線に沿った断面で示す説明図である。It is explanatory drawing which also shows the upper substrate used in 1st Embodiment in the cross section along the line AA. 上下基板の重ね合わせ状態で上基板の樹脂被覆膜を完全硬化させた状態を断面で示す説明図である。It is explanatory drawing which shows the state in which the resin coating film of the upper substrate is completely hardened in the state of superimposing the upper and lower substrates in the cross section. 電極線拘束部がブリッジ状とされている例を示す説明図である。It is explanatory drawing which shows the example which the electrode wire restraint part has a bridge shape. 電極線拘束部が透孔とされている例を示す説明図である。It is explanatory drawing which shows the example which the electrode line restraint part is a through hole. 電極線拘束部がギボシ端子とされている例を示す説明図である。It is explanatory drawing which shows the example which the electrode wire restraint part is a Giboshi terminal.

つぎに本発明を図1から図8に示す実施の形態に基づいて詳細に説明する。なお、LEDチップを配するための例を実施の形態として挙げて本発明を説明するが、本発明はLEDチップを配するものに限定されず、LSIやCPUなどの半導体素子を配するものとすることもできる。 Next, the present invention will be described in detail based on the embodiments shown in FIGS. 1 to 8. The present invention will be described by giving an example for arranging LED chips as an embodiment. However, the present invention is not limited to arranging LED chips, and semiconductor elements such as LSIs and CPUs are arranged. You can also do it.

図中1は半導体素子取付用基板端子板で、図1と図2に示されているように下基板2と上基板3とを重ね合わせて一体化して形成されているものである。この半導体素子取付用基板端子板1にあっては、端子板上面中央にしてLEDチップを配置可能にした素子取付部4を有するとともに、端子板辺部で離間する配置にして、素子取付部に配されるLEDチップに電気を供給するために電気ケーブルなどの電極線を接続できるようにした電極端子部5を有している。 In the figure, reference numeral 1 denotes a substrate terminal board for mounting a semiconductor element, which is formed by superimposing and integrating the lower substrate 2 and the upper substrate 3 as shown in FIGS. 1 and 2. The semiconductor element mounting substrate terminal plate 1 has an element mounting portion 4 in which the LED chip can be arranged in the center of the upper surface of the terminal plate, and is arranged so as to be separated from the terminal plate side portion in the element mounting portion. It has an electrode terminal portion 5 capable of connecting an electrode wire such as an electric cable to supply electricity to the arranged LED chips.

(下基板、第一素子接続端子部)
半導体素子取付用基板端子板1を形成している上下基板の内の下基板2は、銅材などの導電性金属板からなる下基板用導体板6の導体板表面を、絶縁性の樹脂被覆膜7で被覆したものである。そして中央には凸面があり、その凸面を、樹脂被覆膜が存在せずに下基板用導体板6の導体板表面が表出する部分にしてLEDチップを接続するための第一素子接続端子部8として設けている。
(Lower board, first element connection terminal)
The lower substrate 2 of the upper and lower substrates forming the semiconductor element mounting substrate terminal plate 1 covers the surface of the conductor plate 6 of the lower substrate conductor plate 6 made of a conductive metal plate such as a copper material with an insulating resin. It is coated with a cover film 7. Then, there is a convex surface in the center, and the convex surface is used as a portion where the conductor plate surface of the lower substrate conductor plate 6 is exposed without the presence of the resin coating film, and the first element connection terminal for connecting the LED chip. It is provided as a part 8.

(下基板、第一電極端子部)
また下基板2での端子板辺部一隅側の表面に、樹脂被覆膜が存在せずに下基板用導体板6の導体板表面が長方形状にして表出する上記電極端子部5の一方である第一電極端子部9が設けられている。
(Lower board, first electrode terminal)
Further, one of the electrode terminal portions 5 which is exposed in a rectangular shape on the surface of the conductor plate 6 for the lower substrate without the presence of the resin coating film on the surface of the lower substrate 2 on the one corner side of the terminal plate side portion. The first electrode terminal portion 9 is provided.

(下基板、電極線拘束部)
さらに図1と図2とに示すように第一電極端子部9の近傍に、この下基板用導体板6の導体板表面(第一素子接続端子部が存在する表面)を、導体板厚さ方向での上方に凸となるように隆起させた平面形状四角形の隆起形状物からなる電極線拘束部10が設けられており、この電極線拘束部10も樹脂被覆膜7にて覆われている。
(Lower substrate, electrode wire restraint)
Further, as shown in FIGS. 1 and 2, the conductor plate surface (the surface where the first element connection terminal portion exists) of the lower substrate conductor plate 6 is formed in the vicinity of the first electrode terminal portion 9 to have a conductor plate thickness. An electrode wire restraining portion 10 made of a flat, square raised object that is raised so as to be convex upward in the direction is provided, and the electrode wire restraining portion 10 is also covered with the resin coating film 7. There is.

(上基板、第二素子接続端子部)
上記上基板3は、下基板2と同じく銅材などの導電性金属板からなる上基板用導体板11の導体板表面を、絶縁性の樹脂被覆膜7で被覆したものである。そして上記下基板用導体板6の第一素子接続端子部8に対応して開口している透孔12の周辺の薄板状とした板部の表面に、前記樹脂被覆膜が存在せずに上基板用導体板11の導体板表面が表出する部分にしてLEDチップを接続するための第二素子接続端子部13が設けられている。
(Upper board, second element connection terminal)
The upper substrate 3 is formed by coating the surface of a conductor plate 11 for an upper substrate, which is made of a conductive metal plate such as a copper material like the lower substrate 2, with an insulating resin coating film 7. Then, the resin coating film does not exist on the surface of the thin plate-shaped plate portion around the through hole 12 that is opened corresponding to the first element connection terminal portion 8 of the lower substrate conductor plate 6. A second element connection terminal portion 13 for connecting the LED chip is provided in a portion where the surface of the conductor plate 11 for the upper substrate is exposed.

半導体素子取付用基板端子板1では、下基板2の上に上基板3を重ね合わせて一体とすることで、この半導体素子取付用基板端子板1の中央にして、第一素子接続端子部8と第二素子端子部12とが表出した上記素子取付部4が形成されている。 In the semiconductor element mounting substrate terminal plate 1, the upper substrate 3 is superposed on the lower substrate 2 and integrated so that the semiconductor element mounting substrate terminal plate 1 is centered on the first element connecting terminal portion 8. The element mounting portion 4 in which the surface and the second element terminal portion 12 are exposed is formed.

(上基板、第二電極端子部)
また上基板3の端子板辺部一隅側であって上記第一電極端子部9とは反対側となる隅部の表面に、第一電極端子部9と同様に樹脂被覆膜が存在せずに上基板用導体板11の導体板表面が長方形状にして表出して、対の電極端子部5の内の他方である第二電極端子部14が設けられている。
(Upper board, second electrode terminal)
Further, as with the first electrode terminal portion 9, the resin coating film does not exist on the surface of the corner portion of the upper substrate 3 on the one corner side of the terminal plate side portion and opposite to the first electrode terminal portion 9. The surface of the conductor plate 11 for the upper substrate is exposed in a rectangular shape, and a second electrode terminal portion 14 which is the other of the pair of electrode terminal portions 5 is provided.

半導体素子取付用基板端子板1では、下基板2の上に上基板3を重ね合わせて一体とすることで、この半導体素子取付用基板端子板1の端子板辺部において、上記第一電極端子部9と第二電極端子部14とからなる対の電極端子部5が対向して配置されている。 In the semiconductor element mounting substrate terminal plate 1, the upper substrate 3 is superposed on the lower substrate 2 and integrated, so that the first electrode terminal is formed on the terminal plate side portion of the semiconductor element mounting substrate terminal plate 1. A pair of electrode terminal portions 5 composed of a portion 9 and a second electrode terminal portion 14 are arranged so as to face each other.

さらにこの上基板3の上記第二電極端子部14の近傍に電極線拘束部10が設けられている。この電極線拘束部10も上記下基板2の電極線拘束部10と同じように、上基板用導体板11の導体板表面(第二素子接続端子部が存在する表面)を、導体板厚さ方向での上方に凸となるように隆起させた隆起形状物からなるものであり、樹脂被覆膜7にて覆われている。 Further, an electrode wire restraint portion 10 is provided in the vicinity of the second electrode terminal portion 14 of the upper substrate 3. Similar to the electrode wire restraint portion 10 of the lower substrate 2, the electrode wire restraint portion 10 also has the conductor plate thickness of the conductor plate surface (the surface where the second element connection terminal portion exists) of the conductor plate 11 for the upper substrate. It is made of a raised shape that is raised so as to be convex upward in the direction, and is covered with a resin coating film 7.

(上下基板、樹脂被覆膜)
下基板2と上基板3とのそれぞれの樹脂被覆膜7は、後述するように上記導体板表面に耐熱性と絶縁性とを有する電着塗料を用いた電着塗装を施して、電着塗料を析出させて形成したものである。そして電着塗料として、優れた耐熱性及び絶縁性を有するポリイミド樹脂、ポリアミド樹脂、エポキシ樹脂、好ましくはポリアミドイミド樹脂などを用いてなるものであり、耐熱性及び絶縁性を有する樹脂被覆膜7が樹脂層として形成されている。
(Upper and lower substrates, resin coating film)
As will be described later, each of the resin coating films 7 of the lower substrate 2 and the upper substrate 3 is electrodeposited on the surface of the conductor plate by electrodeposition coating using an electrodeposition coating material having heat resistance and insulating properties. It is formed by precipitating paint. As the electrodeposition coating material, a polyimide resin, a polyamide resin, an epoxy resin, preferably a polyamideimide resin or the like having excellent heat resistance and insulating properties is used, and a resin coating film 7 having heat resistance and insulating properties is used. Is formed as a resin layer.

下基板2の上に上基板3を重ね合わせて一体化した状態においても、下基板2の上面側の樹脂被覆膜7と上基板3の下面側の樹脂被覆膜7が、下基板用導体板6と上基板用導体板11との間に存在して、下基板用導体板6と上基板用導体板11との間の絶縁を行なっているものである。 Even when the upper substrate 3 is superposed on the lower substrate 2 and integrated, the resin coating film 7 on the upper surface side of the lower substrate 2 and the resin coating film 7 on the lower surface side of the upper substrate 3 are used for the lower substrate. It exists between the conductor plate 6 and the conductor plate 11 for the upper substrate, and insulates between the conductor plate 6 for the lower substrate and the conductor plate 11 for the upper substrate.

(製造方法)
つぎに上記半導体素子取付用基板端子板1の製造方法について第一の実施の形態を説明する。なお、図示の各断面は、図1におけるA−A線に沿った位置と同一部分での断面である。
(Production method)
Next, a first embodiment of the method for manufacturing the semiconductor element mounting substrate terminal plate 1 will be described. It should be noted that each cross section shown in the drawing is a cross section at the same portion as the position along the line AA in FIG.

(下基板、上基板の製造)
まず、打ち抜き用のプレス金型を用いた打ち抜き加工などによって所定の形状とされた下基板用導体板6と上基板用導体板11とを準備する。この時点で下基板用導体板6と上基板用導体板11とに隆起形状物として上記電極線拘束部10が形成される。
(Manufacturing of lower board and upper board)
First, a conductor plate 6 for a lower substrate and a conductor plate 11 for an upper substrate having a predetermined shape by punching using a press die for punching are prepared. At this point, the electrode wire restraint portion 10 is formed as a raised shape on the lower substrate conductor plate 6 and the upper substrate conductor plate 11.

つぎに下基板用導体板6と上基板用導体板11とに電着塗料の電着塗装を行なう。また電着塗料の塗工を行なう前に、下基板用導体板6には、第一素子接続端子部8と第一電極端子部9とする部分についてマスキング15を施し、上基板用導体板11には、第二素子接続端子部13と第二電極端子部14とする部分にマスキングを施しておく。そして必要部分にマスキングが施された下基板用導体板6と上基板用導体板11とに電着塗料を電着塗装にて施し、下基板用導体板6と上基板用導体板11との全面に樹脂被覆膜7を析出形成させる。 Next, electrodeposition coating of the electrodeposition paint is performed on the lower substrate conductor plate 6 and the upper substrate conductor plate 11. Further, before applying the electrodeposition paint, the lower substrate conductor plate 6 is masked at the portions to be the first element connection terminal portion 8 and the first electrode terminal portion 9, and the upper substrate conductor plate 11 is provided. The second element connection terminal portion 13 and the second electrode terminal portion 14 are masked. Then, an electrodeposition paint is applied to the lower substrate conductor plate 6 and the upper substrate conductor plate 11 whose necessary parts are masked by electrodeposition coating, and the lower substrate conductor plate 6 and the upper substrate conductor plate 11 are combined. A resin coating film 7 is precipitated and formed on the entire surface.

なお、図示の断面にて第一素子接続端子部8にマスキング15を施している点のみが示されているが、第二素子接続端子部12、第一電極端子部9、第二電極端子部13に対するマスキングも同様である。 Although only the point that the masking 15 is applied to the first element connection terminal portion 8 is shown in the cross section shown in the figure, the second element connection terminal portion 12, the first electrode terminal portion 9, and the second electrode terminal portion are shown. The same applies to masking for 13.

(下基板、図3)
全面に樹脂被覆膜7が析出形成された下基板用導体板6については、適宜な温度で加熱処理(焼付)を施して、図3に示すように樹脂被覆膜7を焼付乾燥して樹脂被覆膜7を完全硬化した状態にする。これにより所定の厚みでかつ厚さが均一とされた完全硬化の樹脂被覆膜7を有した下基板2を得ることができる。析出形成した時点で樹脂被覆膜7にピンホールがある場合、そのピンホールは加熱処理時に周囲の電着塗料によって埋め合わされて充足されるため、厚みの均一性が確保される。
(Lower board, Fig. 3)
The conductor plate 6 for the lower substrate having the resin coating film 7 deposited on the entire surface is heat-treated (baked) at an appropriate temperature, and the resin coating film 7 is baked and dried as shown in FIG. The resin coating film 7 is completely cured. As a result, it is possible to obtain a lower substrate 2 having a completely cured resin coating film 7 having a predetermined thickness and a uniform thickness. If there are pinholes in the resin coating film 7 at the time of precipitation formation, the pinholes are filled with the surrounding electrodeposition paint during the heat treatment, so that the thickness uniformity is ensured.

(上基板、図4)
一方、全面に樹脂被覆膜7が形成された上基板用導体板11については適宜な温度で加熱処理(焼付)を施して、樹脂被覆膜7を半硬化させて軟質状態に形成し、半硬化の樹脂被覆膜7を有した上基板3を得る。
(Upper board, Fig. 4)
On the other hand, the conductor plate 11 for the upper substrate on which the resin coating film 7 is formed on the entire surface is heat-treated (baked) at an appropriate temperature to semi-cure the resin coating film 7 to form a soft state. An upper substrate 3 having a semi-cured resin coating film 7 is obtained.

(重ね合わせ、図5)
つぎに、完全硬化の樹脂被覆膜7を有する下基板2の上面に、上述したように半硬化の樹脂被覆膜7を有する上基板3を重ね合わせる。このとき下基板2のマスキング15されている第一素子接続端子部8の部分が上基板3の透孔12を通して外部に位置するようにし、共にマスキングされている第一素子接続端子部8(下基板2)と第二素子接続端子部13(上基板3)とが外部に表われるようにしている。またマスキングされている第一電極端子部9の部分と電極線拘束部10、およびマスキングされている第二電極端子部14の部分と電極線拘束部10も外部に表われる状態にして下基板2と上基板3との重ね合わせが行われる。
(Superposition, Fig. 5)
Next, the upper substrate 3 having the semi-cured resin coating film 7 is superposed on the upper surface of the lower substrate 2 having the completely cured resin coating film 7 as described above. At this time, the masked first element connection terminal portion 8 of the lower substrate 2 is located outside through the through hole 12 of the upper substrate 3, and the first element connection terminal portion 8 (lower) is masked together. The substrate 2) and the second element connection terminal portion 13 (upper substrate 3) are made to appear to the outside. Further, the masked first electrode terminal portion 9 and the electrode wire restraint portion 10, and the masked second electrode terminal portion 14 and the electrode wire restraint portion 10 are also exposed to the outside of the lower substrate 2. And the upper substrate 3 are superposed.

(加圧加熱)
重ね合わされた下基板2と上基板3に対して、上下方向から適宜な圧力で加圧しながら適宜な温度で加熱する加圧加熱処理を施し、上基板3の半硬化の樹脂被覆膜7を完全硬化させる。重ね合わせによって下基板2の完全硬化している樹脂被覆膜7と上基板3の半硬化の樹脂被覆膜7とが相対して密着しており、加圧加熱処理を施すことにより半硬化の樹脂被覆膜7が完全硬化する。
(Pressurized heating)
The superposed lower substrate 2 and upper substrate 3 are subjected to a pressure heating treatment in which the upper substrate 3 is heated at an appropriate temperature while being pressurized at an appropriate pressure from above and below, and the semi-cured resin coating film 7 of the upper substrate 3 is formed. Fully cure. The completely cured resin coating film 7 of the lower substrate 2 and the semi-cured resin coating film 7 of the upper substrate 3 are in close contact with each other due to superposition, and are semi-cured by applying pressure heat treatment. The resin coating film 7 of the above is completely cured.

そして半硬化の樹脂被覆膜7が完全硬化する過程で、下基板2の樹脂被覆膜7と上基板3の樹脂被覆膜7とが接着して、下基板2と上基板3とが強固に貼り合わされて一体となる。図5においては、共に樹脂被覆膜7が完全硬化して接着している状態を示している。 Then, in the process of completely curing the semi-cured resin coating film 7, the resin coating film 7 of the lower substrate 2 and the resin coating film 7 of the upper substrate 3 adhere to each other, and the lower substrate 2 and the upper substrate 3 come together. It is firmly bonded and becomes one. FIG. 5 shows a state in which the resin coating film 7 is completely cured and adhered to each other.

図5に示されているように、上記加圧加熱処理によって貼り合わされて一体となる下基板2と上基板3との間には絶縁性を有する樹脂被覆膜7が存在しており、下基板2と上基板3とは電気的に絶縁された積層状態で連結されている。 As shown in FIG. 5, a resin coating film 7 having an insulating property exists between the lower substrate 2 and the upper substrate 3 which are bonded and integrated by the pressure heat treatment. The substrate 2 and the upper substrate 3 are connected in an electrically insulated laminated state.

(マスキング除去)
加圧加熱処理を施して下基板2と上基板3とを樹脂被覆膜7同士の接着で積層状態で連結した後、マスキングを除去すると、半導体素子取付用基板端子板1が完成する。
(Masking removal)
After applying pressure heat treatment to connect the lower substrate 2 and the upper substrate 3 in a laminated state by adhering the resin coating films 7 to each other, and then removing the masking, the substrate terminal board 1 for mounting the semiconductor element is completed.

これによって、一つの半導体素子取付用基板端子板1は、第一素子接続端子部8と第二素子接続端子部12とが外方に表出した素子取付部4を有するとともに、上方に凸の電極線拘束部10を近接させた第一電極端子部9と同じく上方に凸の電極線拘束部10を近接させた第二電極端子部14とが外方に表出した対の電極端子部5を有するものとなっている。 As a result, one semiconductor element mounting substrate terminal plate 1 has an element mounting portion 4 in which the first element connecting terminal portion 8 and the second element connecting terminal portion 12 are exposed to the outside, and is convex upward. A pair of electrode terminal portions 5 in which the first electrode terminal portion 9 having the electrode wire restraint portion 10 in close proximity and the second electrode terminal portion 14 in which the electrode wire restraint portion 10 convex upward is brought close to each other are exposed to the outside. It is supposed to have.

(重ね合わせの他の例)
上述した重ね合わせでは、下基板2の完全硬化した樹脂被覆膜7に上基板3の半硬化した樹脂被覆膜7が接するように下基板2に上基板3を重ね合わせていて、その重ね合わされた状態での下基板2と上基板3とに加圧加熱処理を施しているが、重ね合わせ前の下基板2の樹脂被覆膜7を半硬化の状態としておき、その下基板2の半硬化した樹脂被覆膜7と上基板3の半硬化した樹脂被覆膜7との間に、ガラスビーズやシリカビーズ、或いは電着塗料と同一の素材からなる樹脂シートからなる空間保持部材(図示せず)を介在させた状態にして、下基板2の半硬化した樹脂被覆膜7に上基板3の半硬化した樹脂被覆膜7が接するように下基板2に上基板3を重ね合わせ、この後に下基板2と上基板3とに加圧加熱処理を施して、前記空間保持部材を介在させて下基板2と下基板3とを一体とするようにしてもよい。
(Other examples of superposition)
In the above-mentioned superposition, the upper substrate 3 is superposed on the lower substrate 2 so that the semi-cured resin coating film 7 of the upper substrate 3 is in contact with the completely cured resin coating film 7 of the lower substrate 2. The lower substrate 2 and the upper substrate 3 are subjected to pressure heating treatment in this state, but the resin coating film 7 of the lower substrate 2 before being overlapped is left in a semi-cured state, and the lower substrate 2 is subjected to a semi-cured state. A space-retaining member (a space-retaining member made of glass beads, silica beads, or a resin sheet made of the same material as the electrodeposition coating material) between the semi-cured resin coating film 7 and the semi-cured resin coating film 7 of the upper substrate 3. The upper substrate 3 is overlaid on the lower substrate 2 so that the semi-cured resin coating film 7 of the lower substrate 2 is in contact with the semi-cured resin coating film 7 of the upper substrate 3 with an interposition (not shown). After that, the lower substrate 2 and the upper substrate 3 may be subjected to a pressure heating treatment so that the lower substrate 2 and the lower substrate 3 are integrated with the space holding member interposed therebetween.

(マスキング無しのレーザ加工)
また上述した実施の形態においてはマスキングを行なっているが、第一素子接続端子部8、第二素子接続端子部13、第一電極端子部9、第二電極端子部14を表出させる手法としては、マスキングを行なわずに上記下基板2と上基板3との連結を行ない、その後に第一素子接続端子部8、第二素子接続端子部13、第一電極端子部9、第二電極端子部14を覆っている樹脂被覆膜7をレーザ加工によって除去するようにしてもよい。
(Laser processing without masking)
Further, although masking is performed in the above-described embodiment, as a method of exposing the first element connection terminal portion 8, the second element connection terminal portion 13, the first electrode terminal portion 9, and the second electrode terminal portion 14. Connects the lower substrate 2 and the upper substrate 3 without masking, and then connects the first element connection terminal portion 8, the second element connection terminal portion 13, the first electrode terminal portion 9, and the second electrode terminal. The resin coating film 7 covering the portion 14 may be removed by laser processing.

(電極線拘束部の他の例)
上記実施の形態での電極線拘束部10については平面形状を四角形状にした隆起形状物からなるものを示したが、本発明はこの例に限定されるものではなく、図6に示すように基板厚さ方向での上方に向けて凸のブリッジ状とされた隆起形状物からなるものや、図7に示すように基板厚さ方向に貫通する貫通孔からなるものとすることができる。
(Other examples of electrode wire restraint)
The electrode wire restraint portion 10 in the above embodiment is shown to be a raised object having a quadrangular planar shape, but the present invention is not limited to this example, and as shown in FIG. It may consist of a raised object having a bridge shape that is convex upward in the substrate thickness direction, or a through hole that penetrates in the substrate thickness direction as shown in FIG. 7.

さらには上記第一電極端子部9と電極線拘束部10を配する下基板2の一隅全体、及び上記第二電極端子部14と電極線拘束部10とを配する上基板3の一隅全体を、図8に示すようにそれぞれギボシ端子16とし、下基板2のギボシ端子16にて第一電極端子部9と電極線拘束部10とが連続した状態で形成され、上基板3のギボシ端子16にて第二電極端子部14と電極線拘束部10とが連続した状態で形成されるようにすることも可能である。 Further, the entire corner of the lower substrate 2 on which the first electrode terminal portion 9 and the electrode wire restraint portion 10 are arranged, and the entire corner of the upper substrate 3 on which the second electrode terminal portion 14 and the electrode wire restraint portion 10 are arranged are covered. As shown in FIG. 8, each of the Giboshi terminals 16 is formed, and the first electrode terminal portion 9 and the electrode wire restraint portion 10 are formed in a continuous state by the Giboshi terminal 16 of the lower substrate 2, and the Giboshi terminal 16 of the upper substrate 3 is formed. It is also possible to form the second electrode terminal portion 14 and the electrode wire restraint portion 10 in a continuous state.

ギボシ端子16を備えるものである場合、ギボシ全体をマスキングしてから下基板2と上基板3との一体化後にマスキング除去を行なったり、或いはマスキング無しで樹脂被覆膜にて覆い、上述したようにレーザ加工にて樹脂被覆膜を除去するようにしても構わない。 When the Giboshi terminal 16 is provided, the entire Giboshi is masked and then the masking is removed after the lower substrate 2 and the upper substrate 3 are integrated, or the masking is covered with a resin coating film without masking, as described above. The resin coating film may be removed by laser processing.

上述したように電極線拘束部10は、樹脂被覆膜を形成する前の下基板2と上基板3とに設けるようにしており、下基板用導体板6と上基板用導体板11とのそれぞれに対して加工を施して形成するものである。この電極線拘束部10を得るための加工方法自体は特に限定されるものではないが、例えば平面形状四角形の隆起形状物からなる電極線拘束部やブリッジ状の隆起形状物からなる電極線拘束部を得るときには、プレスの型打ち加工にて対応することが可能である。また貫通孔からなる電極線拘束部を得るときには、打ち抜き加工にて対応することが可能である。上記ギボシ端子にて電極端子部と連続する電極線拘束部を得るときには、ギボシ用として形成された部位を曲げ起こし加工することにて対応することが可能である。 As described above, the electrode wire restraint portion 10 is provided on the lower substrate 2 and the upper substrate 3 before forming the resin coating film, and the conductor plate 6 for the lower substrate and the conductor plate 11 for the upper substrate are provided. It is formed by processing each of them. The processing method itself for obtaining the electrode wire restraint portion 10 is not particularly limited, but for example, an electrode wire restraint portion made of a flat quadrangular raised shape object or an electrode wire restraining portion made of a bridge-shaped raised shape object. It is possible to deal with this by stamping the press. Further, when obtaining an electrode wire restraint portion formed of a through hole, it is possible to deal with it by punching. When obtaining an electrode wire restraint portion continuous with the electrode terminal portion at the above-mentioned Giboshi terminal, it is possible to cope with the process by bending and raising the portion formed for Giboshi.

そして、下基板用導体板と上基板用導体板との隆起形状物や貫通孔からなる電極線拘束部は、超音波溶着にて接続する電極線の掛け留め部位を電極接続端子部と同一面側(即ち、電極線を超音波溶着に際して重ね置く側)に孔や凸部として表われるようにして形成されているものである。 The electrode wire restraint portion formed of the raised shape and the through hole between the conductor plate for the lower substrate and the conductor plate for the upper substrate has the electrode wire fastening portion to be connected by ultrasonic welding on the same surface as the electrode connection terminal portion. It is formed so as to appear as a hole or a convex portion on the side (that is, the side on which the electrode wires are superposed during ultrasonic welding).

1…半導体素子取付用基板端子板
2…下基板
3…上基板
4…素子取付部
5…電極端子部
6…下基板用導体板
7…樹脂被覆膜
8…第一素子接続端子部
9…第一電極端子部
10…電極線拘束部
11…上基板用導体板
12…透孔
13…第二素子接続端子部
14…第二電極端子部
16…ギボシ端子
1 ... Substrate terminal plate for mounting semiconductor elements 2 ... Lower board 3 ... Upper board 4 ... Element mounting part 5 ... Electrode terminal part 6 ... Conductor plate for lower board 7 ... Resin coating film 8 ... First element connection terminal part 9 ... 1st electrode terminal part 10 ... Electrode line restraint part 11 ... Conductor plate for upper substrate 12 ... Through hole 13 ... 2nd element connection terminal part 14 ... 2nd electrode terminal part 16 ... Giboshi terminal

Claims (5)

端子板上面中央に、半導体素子に接続するための第一素子接続端子部と第二素子接続端子部とを対にして備えて半導体素子を配置可能にした素子取付部を有し、端子板辺部に、電極線を接続するための第一電極端子部と第二電極端子部とからなる電極端子部を有している半導体素子取付用基板端子板を製造する方法であって、
導電性金属板から、上面中央に前記第一素子接続端子部が設けられ、一隅に前記第一電極端子部が設けられ、この第一電極端子部の近傍に電極線拘束部が配されている下基板を形成するとともに、
導電性金属板から、前記下基板と重ね合わせたときの前記第一素子接続端子部に対応する部分にして透孔が開口され、この透孔の周辺に前記第二素子接続端子部が設けられ、下基板と重ね合わせたときの前記第一電極端子部と対向する位置に前記第二電極端子部が設けられ、この第二電極端子部の近傍に電極線拘束部が配されている上基板を形成し、
前記下基板と上基板とを、耐熱性と絶縁性とを有する電着塗料を用いた電着塗装を施してなる樹脂被覆膜で被覆して、前記各電極線拘束部を樹脂被覆膜で覆われた状態とし、
前記下基板の第一素子接続端子部に前記上基板の透孔を対応させるとともに、下基板の第一電極端子部と電極拘束部とが上基板の第二電極端子部と電極線拘束部とに重ならない非重合状態となるようにして、下基板の上に上基板を重ね合わせ、
この重ね合わされた状態での下基板と上基板とに対して加圧加熱処理を施すことにより、下基板と上基板との間の樹脂被覆膜同士を接着させ、
この接着による下基板と上基板との連結により、第一素子接続端子部と第二素子接続端子部とを備えた前記素子取付部を有するとともに、それぞれが電極線拘束部を近傍に配した第一前記電極端子部と第二電極端子部とを配した前記電極端子部を有する一つの基板端子板を形成することを特徴とする半導体素子取付用基板端子板の製造方法。
In the center of the upper surface of the terminal plate, there is an element mounting portion in which a semiconductor element can be arranged by providing a pair of a first element connection terminal portion and a second element connection terminal portion for connecting to a semiconductor element, and the terminal plate side. This is a method for manufacturing a substrate terminal plate for mounting a semiconductor element, which has an electrode terminal portion including a first electrode terminal portion and a second electrode terminal portion for connecting an electrode wire.
From the conductive metal plate, the first element connection terminal portion is provided in the center of the upper surface, the first electrode terminal portion is provided in one corner, and an electrode wire restraint portion is arranged in the vicinity of the first electrode terminal portion. While forming the lower substrate
A through hole is opened from the conductive metal plate at a portion corresponding to the first element connection terminal portion when superposed on the lower substrate, and the second element connection terminal portion is provided around the through hole. The upper substrate is provided with the second electrode terminal portion at a position facing the first electrode terminal portion when superposed on the lower substrate, and the electrode wire restraint portion is arranged in the vicinity of the second electrode terminal portion. Form and
The lower substrate and the upper substrate are coated with a resin coating film obtained by electrodeposition coating using an electrodeposition coating having heat resistance and insulating properties, and each electrode line restraint portion is covered with a resin coating film. Covered with
The first element connection terminal portion of the lower substrate is made to correspond to the through hole of the upper substrate, and the first electrode terminal portion and the electrode restraint portion of the lower substrate are the second electrode terminal portion and the electrode wire restraint portion of the upper substrate. Lay the upper substrate on the lower substrate so that it does not overlap with the lower substrate.
By applying pressure and heat treatment to the lower substrate and the upper substrate in this superposed state, the resin coating films between the lower substrate and the upper substrate are adhered to each other.
By connecting the lower substrate and the upper substrate by this adhesion, the element mounting portion provided with the first element connecting terminal portion and the second element connecting terminal portion is provided, and each of them has an electrode wire restraining portion arranged in the vicinity. (I) A method for manufacturing a substrate terminal plate for mounting a semiconductor element, which comprises forming one substrate terminal plate having the electrode terminal portion in which the electrode terminal portion and the second electrode terminal portion are arranged.
上記電極線拘束部は、基板厚さ方向に貫通した透孔、または基板厚さ方向での上方に向けて凸となる隆起形状物である請求項1に記載の半導体素子取付用基板端子板の製造方法。 The substrate terminal plate for mounting a semiconductor element according to claim 1, wherein the electrode wire restraint portion is a through hole penetrating in the substrate thickness direction or a raised shape that is convex upward in the substrate thickness direction. Production method. 上記下基板における電極線拘束部と第一電極端子部とを配する部分と上記上基板の電極線拘束部と第二電極端子部とを配する部分とが、それぞれギボシ端子とされていて、下基板の前記ギボシ端子に電極線拘束部と第一電極端子部とが形成されているとともに、上基板の前記ギボシ端子に電極線拘束部と第二電極端子部とが形成されている請求項1に記載の半導体素子取付用基板端子板の製造方法。 The portion of the lower substrate where the electrode wire restraint portion and the first electrode terminal portion are arranged and the portion where the electrode wire restraint portion and the second electrode terminal portion of the upper substrate are arranged are designated as Giboshi terminals, respectively. A claim that an electrode wire restraint portion and a first electrode terminal portion are formed on the Giboshi terminal of the lower substrate, and an electrode wire restraint portion and a second electrode terminal portion are formed on the Giboshi terminal of the upper substrate. The method for manufacturing a substrate terminal plate for mounting a semiconductor element according to 1. 上記電着塗料を施す前に、上記第一素子接続端子部と上記第二素子接続端子部と上記第一電極端子部と上記第二電極端子部とのそれぞれにマスキングを施し、
下基板と上基板との上記連結後に前記マスキングを除去して、第一素子接続端子部と第二素子接続端子部と第一電極端子部と第二電極端子部と外方に表出させる請求項1から3の何れか一項に記載の半導体素子取付用基板端子板の製造方法。
Before applying the electrodeposition paint, masking is applied to each of the first element connection terminal portion, the second element connection terminal portion, the first electrode terminal portion, and the second electrode terminal portion.
A claim that removes the masking after the connection between the lower substrate and the upper substrate so that the first element connection terminal portion, the second element connection terminal portion, the first electrode terminal portion, the second electrode terminal portion, and the outside are exposed. Item 8. The method for manufacturing a substrate terminal board for mounting a semiconductor element according to any one of Items 1 to 3.
下基板と上基板との上記連結後に、第一素子接続端子部と第二素子接続端子部と第一電極端子部と第二電極端子部との部分を被覆する樹脂被覆膜を除去して、第一素子接続端子部と第二素子接続端子部と第一電極端子部と第二電極端子部とを外部に表出させる請求項1から3の何れか一項に記載の半導体素子取付用基板端子板の製造方法。 After the above connection between the lower substrate and the upper substrate, the resin coating film covering the first element connection terminal portion, the second element connection terminal portion, the first electrode terminal portion, and the second electrode terminal portion is removed. The semiconductor element mounting according to any one of claims 1 to 3, wherein the first element connection terminal portion, the second element connection terminal portion, the first electrode terminal portion, and the second electrode terminal portion are exposed to the outside. Substrate Terminal plate manufacturing method.
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