JP6746543B2 - Signal processor - Google Patents

Description

Embodiments of the present invention relate to a signal processing device.

2. Description of the Related Art There is known a signal processing device that forms a reception beam based on respective reception signals output by a plurality of antenna elements of an array antenna device. When performing an operation test of such a signal processing device, for example, a test signal is distributed by a distributor, the distributed signal is supplied to each signal processing device, and a signal output from each signal processing device is supplied. If they match, it is determined that each signal processing device is operating normally. However, as the number of antenna elements of the array antenna device increases, the number of distributions by the distributor increases, which may cause a deviation between test signals or it may be difficult to monitor the deviation. Further, when performing an operation test of the signal processing device, it was necessary to stop the signal processing in operation.

JP, 2013-242151, A

The problem to be solved by the present invention is to provide a signal processing device capable of more accurately performing an operation test of a signal processing device while continuing operational signal processing.

The signal processing device according to the embodiment has a plurality of channels, a plurality of operation monitoring units, a distributor, and a plurality of mixing units. Each of the plurality of channels includes an AD converter that converts a mixed signal including an analog signal received from the antenna element into a digital signal, and a first orthogonal demodulator that orthogonally demodulates the digital signal output by the AD converter. Have. The plurality of operation monitoring units monitor the operation of each of the plurality of channels based on the digital signal output by the AD conversion unit. The distributor is a clock signal that serves as a reference for operating the plurality of channels and the plurality of operation monitoring units, and a reference timing signal that serves as a reference for outputting signals from the plurality of channels and the plurality of operation monitoring units. A frequency-divided signal is generated by dividing the clock signal into a frequency corresponding to a signal processed by the plurality of operation monitoring units while outputting to the plurality of channels and the plurality of operation monitoring units. The plurality of mixing units are interposed between the distributor and each of the plurality of AD conversion units, and the mixed signal obtained by mixing the divided signal generated by the distributor and the analog signal is output. Output to AD converter. Each of the plurality of operation monitoring units monitors the operation related to the frequency-divided signal extracted by suppressing the analog signal input to the mixing unit among the mixed signals converted into the digital signal by the AD conversion unit. To do.

1 is a configuration diagram of a DBF signal processing system 1 including a signal processing device 100 according to an embodiment. The figure for demonstrating the frequency band of the signal processed by the main process part 140, and the frequency band of the signal processed by the operation monitoring part 150. The figure for demonstrating the output level of an analog signal and a test signal.

Hereinafter, a signal processing device according to an embodiment will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a DBF (Digital Beam Forming) signal processing system 1 including a signal processing device 100 of the embodiment. The DBF signal processing system 1 includes, for example, a plurality of antenna elements 10-1 to 10-n (1>n), a plurality of pre-stage signal processing units 20-1 to 20-n, a reference timing signal generation unit 30, and The distributor 40, the signal processing device 100, and the beam combining unit 50 are provided. In the following description, the plurality of antenna elements 10-1 to 10-n have the same configuration, and when it is not distinguished which antenna element, a reference numeral after the hyphen indicating which antenna element is used. The description will be omitted and will be referred to as "antenna element 10". The same applies to other configurations described using hyphens. Further, the numbers of the pre-stage signal processing units 20 and the channels ch in the DBF signal processing system 1 are associated with the numbers of the antenna elements 10.

The antenna element 10 receives a radio wave coming from the space and generates a reception signal. Further, the antenna element 10 supplies the generated reception signal to the pre-stage signal processing unit 20. The received signal is, for example, an analog signal.

The pre-stage signal processing unit 20 includes a signal processing circuit such as a limiter, a bandpass filter, an amplifier, and a phase shifter. The limiter limits the signal level of the reception signal input from the antenna element 10. The bandpass filter suppresses unnecessary signal components included in the received signal. The amplifier amplifies the amplitude of the reception signal that has passed through the reception bandpass filter. The phase shifter changes the phase of the received signal to a desired phase. The phase shift of the phase shifter is set for each antenna element 10. The pre-stage signal processing unit 20 outputs the signal-processed analog signal to the signal processing device 100.

The reference timing signal generator 30 generates the clock signal CLK and the reference timing signal SYSREF. The clock signal CLK is a timing signal serving as a reference for operating each of the plurality of channels ch of the signal processing device 100. The reference timing signal SYSREF is, for example, information serving as a reference for outputting a signal in which a plurality of channels ch are synchronized. The reference timing signal generation unit 30 outputs the generated clock signal CLK and reference timing signal SYSREF to the distributor 40.

The distributor 40 supplies the clock signal CLK and the reference timing signal SYSREF input from the reference timing signal generation unit 30 according to the number of the antenna elements 10 to a plurality of channel channels included in the signal processing device 100 connected to the distributor 40. Output to. Here, the distributor 40 can be connected in multiple stages according to the number of the antenna elements 10 that receive the signal from which the beam combiner 50 combines the beams. Thereby, even when the number of distributions of the distributor 40 or the number of channels of the signal processing device 100 is limited, signals can be distributed according to the number of antenna elements 10. Also, the DBF signal processing system 1 includes one or more signal processing devices according to the number of antennas. Therefore, the distributor 40 outputs the clock signal CLK and the reference timing signal SYSREF to each signal processing device 100. The “signal processing device 100” and the “other signal processing device” in the figure have the same configuration.

The signal processing device 100, based on the clock signal CLK and the reference timing signal SYSREF input from the distributor 40, outputs the analog signals input from the respective preceding signal processing units 20 for each of the plurality of channels ch-1 to ch-n. Convert the signal to a digital signal. Further, the signal processing device 100 orthogonally demodulates the converted digital signal to generate an I (In-phase) signal and a Q (Quadrature-phase) signal with a phase shifted by 90 degrees with respect to the I signal, and generates the signal. The output I signal and Q signal are output to the beam combining unit 50. The above-described processing is an example of operational signal processing of the signal processing apparatus 100. Further, the signal processing device 100 generates a test signal based on the clock signal CLK and the reference timing signal SYSREF input from the distributor 40 while continuing the operation processing, and for each channel ch based on the generated test signal. The operation of is monitored. The operation monitoring is to confirm the operation such as synchronization and amplitude by an operation test using a test signal, for example. Details of the function of the signal processing device 100 will be described later.

The beam combiner 50 forms a beam based on the I signal and the Q signal output from the plurality of channels ch of the signal processing device 100 and the plurality of channels of another signal processing device, and combines the formed beams. Further, the beam combining unit 50 outputs the combined beam as a reception beam obtained from the antenna element 10.

Next, details of the functions of the signal processing apparatus 100 described above will be described. The signal processing device 100 includes, for example, a distributor 110, a plurality of mixing units 120-1 to 120-n, a plurality of AD conversion units 130-1 to 130-n, and a plurality of main processing units 140-1 to 140. -N and a plurality of operation monitoring units 150-1 to 150-n. These components are realized, for example, by a hardware processor such as a CPU (Central Processing Unit) executing a program (software). Further, some or all of these components are hardware (circuit section) such as LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array), and GPU (Graphics Processing Unit). (Including circuitry), or by cooperation of software and hardware. Further, these constituent elements may be realized by one processor or may be realized by a plurality of processors. A combination of one AD conversion unit 130 and one main processing unit 140 constitutes one channel ch.

The distributor 110 receives the clock signal CLK and the reference timing signal SYSREF, which are input from the reference timing signal generation unit 30 via the distributor 40, from a plurality of channels ch1 to chn included in the signal processing device 100 connected to the distributor 110. Distribute to.

The distributor 110 also generates a test signal to be input to the operation monitoring unit 150. In this case, the distributor 110 generates, as a test signal, a divided signal obtained by dividing the clock signal CLK into a frequency corresponding to the signal processed by the operation monitoring unit 150. Further, the distributor 110 sets, for example, the center frequency of the test signal to a frequency that does not affect the mixed signal of the analog signal output from the pre-stage signal processing unit 20 and the test signal. No influence is, for example, that the analog signal and the test signal do not interfere during mixing.

For example, if it is assumed that the center frequency of the analog signal output from the pre-stage signal processing unit 20 is 1/4 times the frequency of the clock signal CLK, the distributor 110 divides the frequency of the clock signal CLK by 16. The divided signal (CLK/16 [Hz]) is generated as a test signal. The bandwidth of the test signal at this time is a bandwidth that does not overlap with the frequency band of the analog signal output from the preceding signal processing unit 20. For example, the distributor 110 may acquire the analog signal output from the pre-stage signal processing unit 20 to acquire the information about the center frequency and the bandwidth. Further, the distributor 110 may generate a test signal divided by a frequency division ratio preset by the administrator of the signal processing device 100 or the like.

FIG. 2 is a diagram for explaining a frequency band of a signal processed by the main processing unit 140 and a frequency band of a signal processed by the operation monitoring unit 150. The horizontal axis of FIG. 2 represents the frequency f [Hz] of the signal, and the vertical axis represents the output level [dB]. Further, FIG. 2 shows a filter frequency characteristic 200f of the first quadrature demodulation unit 142 of the main processing unit 140 and a filter frequency characteristic 202f of the second quadrature demodulation unit 152 of the operation monitoring unit 150. As described above, in the embodiment, by adjusting the frequency bands of the signals to be processed so as not to interfere with each other, the operation monitoring unit 150 monitors the operation while continuing the operation signal processing by the main processing unit 140. Processing can be performed.

Further, the distributor 110 can synchronize the clock signal CLK and the reference timing signal SYSREF with the test signal by using the divided signal (CLK/16 [Hz]) as the test signal. Further, even when the analog signal (CLK/4) output from the pre-stage signal processing unit 20 by the mixing unit 120 is mixed with the test signal by using the divided signal (CLK/16 [Hz]) as the test signal. , Do not interfere with each other's signals without interfering with each other's signals. Further, by using the divided signal (CLK/16) as the test signal, filtering processing such as noise removal is facilitated, and signal processing suitable for the characteristics of quadrature demodulation can be performed. Further, the distributor 110 may generate a divided signal (CLK/8 [Hz]) obtained by dividing the frequency of the clock signal CLK by 8 as a test signal, and divides the frequency of the clock signal CLK by 32. The signal (CLK/32 [Hz]) may be generated as the test signal.

The mixing unit 120 is interposed between the distributor 110 and the plurality of channels ch1 to chn of the signal processing device 100. Mixing section 120 mixes the test signal output from distributor 110 with the analog signal generated by pre-stage signal processing section 20, and outputs the mixed signal to a plurality of channels of signal processing apparatus 100.

The mixing unit 120 includes, for example, a filter unit 122, an attenuator 124, and a signal mixing unit 126. The filter unit 122 passes a predetermined frequency band in order to suppress the harmonic component of the test signal output from the distributor 110. The filter unit 122 is, for example, a BPF (Band Pass Filter) or an LPF (Low Pass Filter). As a result, the square wave of the test signal input to the filter unit 122 is output from the filter unit 122 as a sine wave.

The attenuator 124 attenuates the output level of the test signal output by the filter unit 122. FIG. 3 is a diagram for explaining the output levels of the analog signal and the test signal. The horizontal axis of FIG. 3 represents the frequency f [Hz] of the signal, and the vertical axis represents the output level [dB]. For example, the attenuator 124 attenuates the output level of the test signal so that the output level L2 is lower than the output level L1 of the analog signal output by the pre-stage signal processing unit 20. Further, the attenuator 124 may attenuate the output level L2 of the test signal so as to be equal to or lower than a preset threshold value. As a result, it is possible to easily filter the test signal from the mixed signal in the main processing unit 140, and it is possible to suppress noise due to the test signal. Further, by adjusting the output level of the test signal by the attenuator 124, it is possible to suppress the variation in the output level.

The signal mixing unit 126 mixes the signal output by the attenuator 124 and the analog signal output by the pre-stage signal processing unit 20, and outputs the mixed signal to the AD conversion unit 130 of the channel ch.

The AD conversion unit 130 converts the mixed signal output by the signal mixing unit 126 into a digital signal, and outputs the converted digital signal X(n) to the main processing unit 140 and the operation monitoring unit 150.

The main processing unit 140 includes, for example, a first quadrature demodulation unit 142. The first orthogonal demodulation unit 142 generates an I signal and a Q signal from the digital signal X(n) AD-converted by the AD converter 130. The first quadrature demodulation unit 142 is, for example, a DDC (Digital Down Converter) including an NCO (Numerical Controlled Oscillator), a multiplier (Mixer), and an LPF (Low Pass Filter).

Here, a specific process of the first orthogonal demodulation unit 142 will be described. For example, the digital signal X(n) can be expressed as “X(n)=XI(n)cosωn+jXQ(n)sinωn” as the sum of orthogonal components whose phases are shifted by 90 degrees. XI(n) and XQ(n) represent the I component and Q component of the input signal, respectively, and ωn represents the carrier angular frequency of the signal. In this case, the multiplier of the first orthogonal demodulation unit 142 multiplies the digital signal X(n) by the complex phase (cosωn-jsinωn) to convert X(n) into a desired frequency band. At this time, the NCO of the first quadrature demodulation unit 142 outputs a numerical control signal having cos ωn={1,0,-1,0} and sin ωn={0,1,0,-1}, for example, a sampling frequency of 1 It oscillates at a frequency (fs/4) multiplied by /4. This frequency corresponds to, for example, 1/4 times the clock signal CLK (CLK/4). As a result, the digital signal X(n) can be expressed in quadrature, and I component and Q component signals (that is, I signal and Q signal) can be generated. Further, the first quadrature demodulation unit 142 removes the frequency component of CLK/16 from the I signal and the Q signal by band limitation (filter characteristic) by the LPF. As a result, of the mixed signals input from the AD conversion unit 130, the test signal is suppressed, the signal output by the pre-stage signal processing unit 20 can be extracted, and the I signal and Q signal corresponding to the extracted signal can be output. it can. The first quadrature demodulation unit 142 outputs the generated I signal and Q signal to the beam combining unit 50.

The operation monitoring unit 150 includes, for example, a second orthogonal demodulation unit 152, a phase angle calculation unit 154, and an operation determination unit 156. The second quadrature demodulation unit 152 is, for example, a DDC including an NCO, a multiplier, and an LPF. The NCO of the second quadrature demodulation unit 152 uses a numerical control signal for cos ωn={1,0,−1,0} and sin ωn={0,1,0,−1} It oscillates at the specified frequency (fs/16). This frequency corresponds to, for example, 1/16 times the clock signal CLK (CLK/16 [Hz]). As a result, the digital signal X(n) can be expressed in quadrature, and the I signal and the Q signal can be generated. Further, the second quadrature demodulation unit 152 removes the frequency component of CLK/4 from the I signal and the Q signal by band limitation by the LPF. As a result, of the mixed signals input from the AD conversion unit 130, the signal output by the pre-stage signal processing unit 20 is suppressed, and the I signal and Q signal corresponding to the extracted test signal can be output.

The phase angle calculator 154 calculates the phase angle of the I signal and the Q signal output by the second quadrature demodulator 152.

The operation determination unit 156 determines the operation of the channel ch based on the phase angle calculated by the phase angle calculation unit 154. For example, since the test signal is generated as a frequency-divided signal of CLK/16 [Hz] and the timing of numerical control of the NCO is set to CLK/16 [Hz], the IQ signal after the orthogonal demodulation by the second orthogonal demodulation unit 152 is , NCO (origin 0 degree) represents the angle of deviation (so-called phase angle). Therefore, the motion determination unit 156 performs a subtraction process on the phase angle calculated by the phase angle calculation unit 154 with a predetermined angle, and if the result (angle difference) of the subtraction is near a preset angle, the motion determination unit 156 performs the motion. It is determined that the channel ch to be determined is operating normally. The vicinity of the preset angle is, for example, a range within a threshold of about ±10 degrees with reference to the preset angle. In addition, the operation determination unit 156 determines that the channel for which the operation is to be performed is performing an abnormal operation when the subtracted result exceeds the preset angle. In addition, the operation determination unit 156 may determine that the device (for example, the antenna element 10, the previous stage signal processing unit 20, etc.) related to the channel ch determined to be abnormal is performing an abnormal operation.

The operation determination unit 156 stores the determination result in a storage unit (not shown) provided in the signal processing device 100, for example. The operation determination unit 156 may also transmit the determination result to an external device from a communication unit (not shown) provided in the signal processing device 100.

Further, the signal processing device 100 may include light emitting elements (not shown) such as LEDs (Light Emitting Diodes) according to the number of the operation determination units 156. In this case, the operation determination unit 156 causes the light emitting element corresponding to the channel determined to be abnormal in operation to emit light. As a result, the administrator of the signal processing apparatus 100 and the like can easily see the abnormality of the channel ch and the portion determined to be abnormal.

According to at least one embodiment described above, an AD converter 130 that converts an analog signal into a digital signal, and a first orthogonal demodulator 142 that orthogonally demodulates the digital signal output by the AD converter 130 are provided. A plurality of channel ch having a plurality of channels ch, and a plurality of operation monitoring units 150 for monitoring the operation of each of the plurality of channel ch based on the digital signal output by the AD conversion unit 130, a plurality of channel ch and a plurality of operation monitoring units. A clock signal CLK serving as a reference for operating 150 and a reference timing signal SYSREF serving as a reference for outputting signals from a plurality of channel ch and a plurality of operation monitoring units 150 are provided to a plurality of channel ch and a plurality of operation monitoring units 150. A distributor 110 that outputs a frequency-divided signal (test signal) obtained by dividing the clock signal CLK into a frequency corresponding to a signal processed by the plurality of operation monitoring units 150, a distributor 110, and a plurality of AD conversions. The plurality of mixing units 120 that intervene between each of the units 130 and mix the divided signal generated by the distributor 110 with the analog signal and output the mixed signal to the AD conversion unit 130 are provided. The operation test of the signal processing device can be performed more accurately while continuing the signal processing of 1.

Further, according to at least one embodiment, a test signal synchronized with the clock signal CLK and the reference timing signal SYSREF is generated in the signal processing device 100, and the entire test signal is processed by the first quadrature demodulation unit 142. By not affecting the signal, the operation test by the operation monitoring unit 150 can be performed while continuing the signal processing in the first quadrature demodulation unit 142. Further, according to at least one embodiment, the operation monitoring unit 150 can determine whether the signal processing device 100 is operating normally or abnormally. Further, according to at least one embodiment, it is possible to determine normality or abnormality for each of a plurality of channel ch, so that it becomes easy to search for a failure at the time of abnormality.

The applicant of the present application has confirmed that the signal processing device 100 according to the above-described embodiment is implemented to efficiently determine the operation shift in each channel. Further, the applicant has set the NCO of the first quadrature demodulation unit 142 in the signal processing apparatus 100 to 612.79 [MHz] and the NCO of the second quadrature demodulation unit 152 to 876.4648 [MHz], and set the frequency to 600 [ The output from each quadrature demodulation unit was simulated using a mixed signal obtained by mixing two signals of [MHz] and 880 [MHz]. As a result, with respect to the signal having the frequency of 600 [MHz], the output of the first quadrature demodulation unit 142 was a specified output, and the output of the second quadrature demodulation unit 152 was suppressed by the filter and became almost zero. Further, for a signal having a frequency of 880 [MHz], the output of the first quadrature demodulation unit 142 was suppressed to almost 0 by the filter, and the output of the second quadrature demodulation unit 152 was a specified output.

While some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. The embodiments and their modifications are included in the scope of the invention and the scope thereof, as well as in the invention described in the claims and the scope of equivalents thereof.

DESCRIPTION OF SYMBOLS 1... DBF signal processing system, 10... Antenna element, 20... Pre-stage signal processing part, 30... Reference timing signal generation part, 40, 110... Distributor, 50... Beam combining part, 100... Signal processing device, 120... Mixing part , 130... AD conversion section, 140... Main processing section, 142... First quadrature demodulation section, 150... Operation monitoring section, 152... Second quadrature demodulation section, 154... Phase angle calculation section, 156... Operation determination section, ch... channel

Claims (5)

A plurality of channels each including an AD conversion unit that converts a mixed signal including an analog signal received from the antenna element into a digital signal, and a first orthogonal demodulation unit that orthogonally demodulates the digital signal output by the AD conversion unit. When,
A plurality of operation monitoring units that monitor the operation of each of the plurality of channels based on the digital signal output by the AD conversion unit;
The plurality of channels and the reference timing signal serving as a reference for outputting signals from the plurality of channels and the plurality of operation monitoring units, and the plurality of channels And a distributor that outputs to the plurality of operation monitoring units and generates a divided signal by dividing the clock signal to a frequency corresponding to a signal processed by the plurality of operation monitoring units,
A plurality of units intervening between the distributor and each of the plurality of AD conversion units and outputting the mixed signal obtained by mixing the divided signal generated by the distributor and the analog signal to the AD conversion unit. It includes a mixing section, and
Each of the plurality of operation monitoring units monitors the operation related to the frequency-divided signal extracted by suppressing the analog signal input to the mixing unit among the mixed signals converted into the digital signal by the AD conversion unit. To do
Signal processing device. The distributor is set to the center frequency of the divided signal, a frequency that does not interfere during the mixing of the previous SL-divided signal and the analog signal,
The signal processing device according to claim 1. The mixing unit further includes an attenuator that attenuates the divided signal,
Mixing the divided signal attenuated by the attenuator and the analog signal,
The signal processing device according to claim 1. The operation monitoring unit,
A second quadrature demodulator for outputting the I and Q signals to digital signal converted by the front Symbol A D converting section orthogonal demodulation to the basis of the divided signal,
A plurality of phase angle calculation units for calculating orthogonal phase angles of the I signal and the Q signal output by the second quadrature demodulation unit;
Based on the phase angle calculated by the plurality of phase angle calculation unit, an operation determination unit that performs the operation determination of each of the plurality of channels,
The signal processing device according to claim 1, further comprising: When the difference between the phase angle calculated by the phase angle calculation unit and the predetermined angle is within a threshold value, the operation determination unit determines that the operation determination target channel is operating normally, and the phase If the difference between the angle and the predetermined angle exceeds a threshold value, it is determined that the channel of the operation determination target is abnormal,
The signal processing device according to claim 4.

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