JP6742635B2 - Sink device and control method - Google Patents

Description

The present invention relates to a technique suitable when, for example, a source device and a sink device in the DisplayPort interface standard are connected via a signal line based on the standard.

<First background technology>
An external video interface for connecting an image data output device and a display device has started from the VGA (Video Graphics Array) standard as an analog external interface and has been developed mainly as an interface between a personal computer and the display device. There are DVI (Digital Visual Interface) standards for both analog and digital, and HDMI (High-Definition Multimedia Interface) (registered trademark) standards developed mainly for AV devices.
Further, as the internal video interface used when the display device (device) is incorporated in the image data processing device, the LVDS (Low Voltage Differential Signaling) standard has been the mainstream.

<DP interface standard>
In addition, recently, the DisplayPort (hereinafter referred to as “DP”) standard, which is a video interface for serially transferring as micropackets using an internal clock without using an external clock, has become widespread.
According to this interface standard, since the clock is generated from the data to be transferred, there are advantages that the data transfer is high speed and the function expansion is easy.
Also, the DP interface standard specifies that audio can be transferred at the same time as the HDMI interface. Furthermore, what defines the DP interface standard as an internal interface is embedded DP (hereinafter referred to as "eDP").

FIG. 10 is a schematic diagram for explaining the outline of the DP interface standard.
As shown in the figure, in the DP interface standard, an image signal transmission path is provided between the source device 100, which is a logical device on the image data output side, and the sink device 200, which is a logical device on the display device side. A certain main link ML is logically connected to two sub-channels, an auxiliary (AUX) channel AC and a hot plug detect (Hot Plug Detect) HPD.

<Hot plug detection HPD>
Here, the hot plug detection HPD is a signal for notifying the source device 100 side when the power of the sink device 200 side is initially turned on, and for some reason during transmission, the source device 100 and the sink device 200 are also notified. This is a signal for requesting re-linking from the sink device 200 side when the link status between and is down (also referred to as link loss or unlock).
The AUX channel AC is a low-speed bidirectional side channel and is a signal for link setup and management by link training described later, control of status and functional configuration, operation support of main link, and the like. ..

<DPCD, EDID>
The sink device 200 also includes a configuration parameter information storage unit (DPCD: Display Port Configuration Data) 2001 and a display device function information storage unit (EDID: Extended Display Identification Data) 2002.
The configuration parameter information storage unit 2001 stores the link speed, the number of corresponding lanes, the determined number of lanes, the link speed, the down spread control, the main link channel code, and the like.
In addition, the display device function information storage unit 2002 stores function information (resolution, size, timing information (frequency, sync signal parameter), etc.) of physical display devices that configure the sink device 200.

Therefore, in the DP interface standard, the signal of the hot plug detection HPD becomes active by the initial operation such as power-on of the sink device 200 side, and the source device 100 side detects it. Thereby, thereafter, the initial link establishing process for determining the condition for transmitting the frame signal such as an image from the source device 100 side to the sink device 200 side via the main link ML is performed.

<Procedure for initial link establishment>
11A and 11B are flowcharts showing the procedure at the time of establishing the initial link.
First, when the power of the sink device 200 is turned on, the signal of the hot plug detection HPD becomes active (High in the standard) (step S251), and the source device 100 side detects it (step S151).
Note that, even when a link loss described later is performed, the sink device 200 activates the signal of the hot plug detection HPD in exactly the same manner, but a new power-on (new device connection and simple re-power supply) is performed on the source device 100 side. (Including both input) or a link loss is determined based on how long there was inactivity before the signal detection. That is, when there is a period of inactivity for a predetermined time or longer, it is determined that the power is newly turned on, and the following initial link establishment time procedure is executed.

Specifically, first, each process of sink device characteristic detection (Sink Capabilities Discovery) and sink device function configuration (Sink Configuration) is performed using the AUX channel AC.
That is, the source device 100 reads the link speed, the number of corresponding lanes, and the like from the configuration parameter information storage unit 2001 of the sink device 200 via the AUX channel AC, and from the display device function information storage unit 2002, the resolution of the liquid crystal display. , Size, timing information (frequency, sync signal parameter, etc.) is read (step S152).
Then, the source device 100 determines the number of lanes, the link speed, the down spread control, and the main link channel code based on the transmission request (the data amount of the image data to be transmitted, etc.), and through the AUX channel AC, On the contrary, the determined information is sent to the sink device 200 and stored in a predetermined area of the configuration parameter information storage unit 2001 (step S252). For example, in the DPv1.1a standard, the transmission of image/audio data via the main link ML is configured by selecting one, two, or four lanes, and the bandwidth of each lane is 2.7 Gbps or 1.62. Since it is selectable at Gbps, the maximum bandwidth is 10.8Gbps.

<Link training>
Next, link training is performed between the source device 100 and the sink device 200 (steps S153 and S253). 11C and 11D are flowcharts for explaining the flow and contents of link training. As shown in the figure, the link training is generally composed of a clock recovery process (steps S1531, S2531) and an equalization process (steps S1532, S2532).

In the clock recovery process (steps S1531, S2531), (a1) pre-emphasis level (a1), and (a2) voltage swing level (Voltage swing Level) by the exchange between the source device 100 and the sink device 200. , And (a3) while adjusting the sync-side equalization parameter (Rx equalizer parameter), (a4) clock recovery (ClockRecovery) is attempted.
Here, the clock recovery simply means to secure necessary synchronization when converting an image signal as an analog signal on the main link ML into a digital signal.
Specifically, the training pattern for clock recovery (D10.2 data symbol (0101010...) in transmission method 8b/10b) is sent from the source device 100 to the sink device 200 via the main link ML and the AUX channel AC. In the sink device 200, for example, clock recovery is realized by phase shifting the VCO output by the PLL circuit and locking the data symbols.
Whether or not the clock recovery is successful in the sink device 200 is determined by the source device 100 via the AUX channel AC, which is information indicating whether or not the sink device 200 has written in a predetermined area of the configuration parameter information storage unit 2001. Is recognized by the source device 100.

<Pre-emphasis level>
Here, the pre-emphasis level refers to the transition part (rising edge) of the signal in order to cope with the increase in bit error due to the frequency-dependent attenuation of the transmission signal according to the attenuation characteristic peculiar to the transmission path. Part and falling part) is emphasized with respect to the non-transition signal period, and is determined according to the success or failure result of the clock recovery while being adjusted by the source device 100. Information on the determined pre-emphasized level is held in the source device 100.

<Voltage amplitude level>
The voltage swing level is a parameter indicating how much voltage amplitude a signal is transmitted according to the attenuation characteristic of the transmission path, and whether the clock recovery is successful or not while the source device 100 adjusts. Determine according to the result. The information on the determined voltage amplitude level is held in the source device 100.

<Sink side equalization parameter>
The sync-side equalization parameter (Rx equalizer parameter) is a parameter that represents a filtering characteristic for returning the input transmission signal to a waveform suitable for decoding, and is determined by the sync device 200. The information of the determined sync-side equalization parameter is held in the sync device 200.

<Symbol lock, time adjustment between lanes>
Next, in the equalization processing (steps S1532 and S2532), (b1) symbol lock (Symbol Lock) and (b2) inter-lane time adjustment (Inter-) are performed by the exchange between the source device 100 and the sink device 200. lane de-skewing) is held.
The symbol lock is simply establishing synchronization so that serial data received from the source device 100 can be converted into parallel data.
The time adjustment between lanes means eliminating a signal time difference (skew) between signal lines (lanes) due to a difference in wiring length of signal lines or relative permittivity between PCB layers.
Specifically, the training pattern for symbol lock (K28.5(0011111010/1100000101)+D11.6(1101000110)+D10.2 in the transmission system 8b/10b from the source device 100 via the main link ML and the AUX channel AC. (0101010101)) is sent, the sink device 200 searches for K28.5, locks the position where the K28.5 is found as a symbol boundary, and deserializes the serial data based on the locked boundary position ( De-serialize) to lock the symbol.
In addition, the sink device 200 searches for K28.5 for each lane and locks the position of K28.5 found for each lane as a time difference (skew) adjustment position to perform inter-lane time adjustment. Whether or not the equalization process is completed in the sink device 200 is read by the source device 100 via the AUX channel AC from the status information written in a predetermined area of the configuration parameter information storage unit 2001 by the sink device 200. Be recognized by

<Idol pattern/scrambler reset>
Returning to FIGS. 11A and 11B, after the link training, the idle pattern/scrambler reset process is performed (steps S154 and S254).
In the process, the source device 100 sends an idle pattern to the sink device 200. The idle pattern consists of a BS symbol sequence (BS+BF+BF+BS, followed by one VB-ID set No VideoStream_Frag bit being set). The 512th BS symbol sequence is replaced with a scrambler reset symbol sequence (SR+BF+BF+SR).

<Stream transmission>
After the above initial processing, the source device 100 serializes, scrambles, and encodes the image data (frame data), and then stream-transmits it to the sink device 200 via the main link ML (steps S155 and S255). ).

<Link loss>
By the way, after the link of the main link ML is established between the source device 100 and the sink device 200, the link state of the main link ML is lost due to the influence of noise or the like caused by the operating environment in the image signal transmission process. , A so-called link loss (also referred to as link down or unlock) state may occur.
The unlocked state is simply a state in which the source device 100 transmits the image signal to the sink device 200 but the sink device 200 cannot receive the image signal. Specifically, it means a state in which the sink device 200 cannot convert the above-described analog signal into a digital signal, or a state in which even if the conversion can be performed, serial data cannot be converted into parallel data. Therefore, in the unlocked state, on the side of the sink device 200, an image is not displayed on the display device, which is a so-called blackout (darkening) or whiteout state.

<Relink establishment processing>
When such a link loss state occurs, link training is performed again between the source device 100 and the sink device 200. FIG. 12 is a flowchart showing a processing procedure at the time of such a link loss.
That is, when the sink device 200 detects a link loss (step S172, Yes) while the source device 100 is performing stream transmission of image data to the sink device 200 (steps S161 and S171), the sink device 200 The signal of the hot plug detection HPD is activated (step S173).
In this case, the sink device 200 activates the signal of the hot plug detection HPD after being inactive for less than the predetermined time.
Therefore, the source device 100 side recognizes it as an HPD_IRQ (Interrupt ReQuest) signal. That is, it is recognized that the link loss has occurred on the sink device 200 side even when it is not at the time of initial connection or power-on (step S162, Yes).
At that time, the source device 100 interrupts the stream transmission of the image data via the main link ML (step S163), and then performs the link training again with the sink device 200 (steps S164 and S174). ).
The link training here is the same process as the link training at the time of initial connection (step S153).

As described above, in the DP interface standard, every time the main link ML falls into the state of link loss, the stream transmission of the image data via the main link ML is temporarily interrupted, and the main link ML and the AUX channel AC are transmitted. Is configured to perform the linked training.
Here, the AUX channel AC has a disadvantage that the link training requires a relatively long time because it is relatively slow.
In particular, since the link training period corresponds to the period of darkening as described above, the longer the link training period, the longer the darkening period, which affects the effectiveness of image display. In particular, in devices operated in a noisy environment (for example, gaming machines such as pachinko machines and pachislot machines), the frequency of darkening tends to increase, but if the darkening period is long, the effectiveness of display (gaming machines In this case, it may have a great impact on entertainment. Therefore, it is desirable to complete the link training corresponding to the dark period in a short time.

<Patent Document 1>
Patent Document 1 discloses a technique that solves such a drawback. Differences between the relinking method described in the document and the relinking method based on the DP interface standard will be described below.
(1) The source device 100 always embeds the training pattern in the blanking period in the video signal format including the image data and sends the training pattern.
(2) Even if a link loss occurs, the sink device 200 does not notify the source device 100 of the fact and autonomously performs link training by using the training pattern embedded in the blanking period in the video signal format. I do. However, the sink device 200 also does not confirm the success/failure result with the source device 100.
(3) The source device 100 continues the stream transmission of the image data regardless of the occurrence of the link loss on the side of the sink device 200 (which is inevitable because the fact that the link loss has occurred is not notified).

From the above, even in the invention of Patent Document 1, image data cannot be received in the link loss state, and the image is in a dark state.
At this time, the source device 100 continues the stream transmission of the image data despite the occurrence of the link loss on the side of the sink device 200, and the source device 100 operates at low speed in the process of recovering from the link loss. Since the success or failure of relinking via the AUX channel AC is not confirmed, the dark period due to the link loss is shorter than the processing based on the DP interface standard.

<Second background technology>
When an apparatus adopting the DP interface standard is used in an environment where a lot of noise is generated due to a metal collision such as a pachinko machine, there is a possibility that a communication error may occur due to the noise.
In addition to the initial link establishment described in the first background art, negotiation is performed when a cable is inserted/removed or a communication error occurs. Generally, a display device such as a liquid crystal display is in a blackout or whiteout state during the negotiation. Target.
When a serious communication error has occurred, blackout or whiteout may occur during negotiation for recovering the communication error. On the other hand, when a slight communication error occurs, the display screen on the liquid crystal display of the gaming machine may be disturbed.

<MSA>
According to the DP interface standard, information such as an image size for one frame and synchronization timing is transmitted in a packet called Main Stream Attribute (hereinafter referred to as MSA) in the blanking period.
The MSA is transmitted from the source device 10 to the sink device 20 for each frame, and the sink device 20 generates display data based on the received MSA.
According to the DP interface standard, not all MSA data is transmitted, but at least the total number of pixels in a horizontal line (Htotal) and the total number of lines in a video frame (Vtotal) are transmitted as essential information from the source device 10 to the sink device 20. It

Japanese Patent No. 5799320

<First issue>
However, in Patent Document 1, there is a drawback in that the source device 100 is forced to perform a new process in which the training pattern is embedded in the blanking period in the video signal format and must be continuously sent.

<Second task>
In addition, when the data of the MSA packet is changed to an incorrect value and transmitted due to the influence of the above-described noise, an error occurs in the data such as the total number of pixels of the horizontal line and the total number of lines of the video frame. appear.
Specifically, as shown in FIG. 13B, the image data itself can be decoded with almost no problem, whereas the total number of horizontal line pixels transmitted by the MSA packet (Htotal) and the total number of video frame lines ( If Vtotal) is incorrect for one frame, the screen will flicker momentarily.
For example, when the screen resolution is VGA, the total number of horizontal line pixels (Htotal) and the total number of video frame lines (Vtotal) sent in an MSA packet are 640 and 480, respectively. Then, for example, if the total number of pixels in the horizontal line (Htotal) and the total number of lines in the video frame (Vtotal) change to 800, 500, etc., respectively, as shown in FIG. Is displayed from point P, and the situation is such that it is stretched in the lower right direction.
Although it depends on the number of frames forming the moving image, if the quality of the moving image deteriorates so that the flicker due to stretching or shrinking of the screen can be visually confirmed by the viewer, the image becomes annoying to the viewer.

The present invention has been made in view of the above, and an object thereof is to quickly return from a link loss state to a normal state in a sink device connected to a source device via a signal line, influence of noise and the like. This is to prevent the flickering of the screen due to.

In order to solve the above-mentioned problems, the invention of claim 1 is a sink device connected to a source device via a signal line, wherein a hot plug detection signal indicating that a link loss has occurred after the initial link is established. Control means for controlling the output to the source device to be in an invalid state; link loss detection means for detecting occurrence of a link loss during reception of a data stream continuously transmitted from the source device; Clock recovery means for extracting a clock signal embedded in the data stream when the occurrence of loss is detected, and a blanking start symbol embedded in the data stream when the occurrence of the link loss is detected. A blanking start signal detecting means for detecting a signal, and a storage means for storing a signal receiving condition at the time of link establishment, the extracted clock signal, the signal receiving condition stored in the storing means, and the detected signal. The re-link is established by the blanking start signal.

According to the present invention, in a sink device connected to a source device via a signal line, a link loss state is quickly restored to a normal state, and screen flicker due to an influence of noise or the like is prevented.

It is a block diagram which shows the structure of the data transmission system which concerns on 1st Embodiment of this invention. FIG. 3 is a block diagram showing a layer configuration of a DP interface standard for providing video information from the source device 10 to the sink device 20 according to the first exemplary embodiment of the present invention. 6 is a flowchart for explaining a processing procedure by the control method according to the first embodiment of the present invention. 6 is a flowchart for explaining a processing procedure when a link loss occurs during transmission of image data in the data transmission system according to the first embodiment of the present invention. It is a block diagram for explaining the internal configuration of the sink device of the data transmission system according to the second embodiment of the present invention. It is a figure which shows the frame structure of DisplayPort standard. It is a figure which shows the definition of an MSA packet. It is a functional block diagram for demonstrating the internal structure of DPRX and AV processor of the sink device which concerns on 2nd Embodiment of this invention. 7 is a flowchart showing operations of the DPRX and the AV processor of the sink device according to the second embodiment of the present invention. It is an outline figure for explaining the outline of the conventional DP interface standard. It is a flowchart for demonstrating the process in the conventional DP interface standard, (a) is a flowchart which shows the procedure at the time of initial link establishment of a source device, (b) shows the procedure at the time of initial link establishment of a sink device. It is a flowchart, (c) is a flowchart for demonstrating the flow and the content of the link training of a sink device, (d) is a flowchart for demonstrating the flow and the content of the link training of a sink device. It is a flowchart which shows the processing procedure at the time of the conventional link loss, (a) is a flowchart which shows the processing procedure at the time of a link loss of a source device, (b) is a flowchart which shows the processing procedure at the time of a link loss of a sink device. is there. It is a schematic diagram which shows the screen which the conventional sink device displays, (a) is a schematic diagram which shows the screen at the time of normal, (b) is a schematic diagram which shows the screen when abnormality generate|occur|produced in MSA data. ..

Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings.
The present invention has the following configuration in order to quickly return from a link loss state to a normal state in a sink device connected to a source device via a signal line.
That is, the sink device of the present invention is a sink device connected to the source device via a signal line, and outputs a hot plug detection signal HPD indicating that a link loss has occurred to the source device after the initial link is established. When the occurrence of a link loss is detected, the control means for controlling so as to be in an invalid state, the link loss detection means for detecting the occurrence of the link loss during the reception of the data stream continuously transmitted from the source device, In, the clock recovery means for extracting the clock signal embedded in the data stream, and the blanking start signal detection means for detecting the blanking start symbol embedded in the data stream when the occurrence of a link loss is detected, Storage means for storing a signal reception condition at the time of establishing the link, wherein the re-link is established by the extracted clock signal, the signal reception condition stored in the storage means, and the detected blanking start signal. And
With the above configuration, in the sink device connected to the source device via the signal line, the link loss state can be quickly restored to the normal state.
The features of the present invention described above will be described in detail below with reference to the drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1 is a block diagram showing the configuration of a data transmission system according to the first embodiment of the present invention.

<Hardware configuration>
Referring to FIG. 1, a data transmission system 1 according to a first embodiment of the present invention has a configuration in which a source device 10 and a sink device 20 are connected via a plurality of signal lines, and the sink device 20 is a source. This is a so-called built-in system that is fixedly configured with respect to the device 10.
<Structure of source device>
The source device 10 is a so-called transmission side graphic controller, and includes an AV processor 2, a display port transmitter DPTX4, and a CPU 6.
The AV processor 2 outputs the video data, the audio data, and the control signal to the display port transmitter DPTX4.
The display port transmitter DPTX4 encrypts the main link data (video data, audio data) and sends it to the display port receiver DPRX22.
The CPU 6 controls the AV processor 2 and the display port transmitter DPTX4 via I2C. The CPU 6 has a ROM and a RAM inside, reads the operating system OS from the ROM, expands it on the RAM and activates the OS, and reads the program from the ROM to execute various processes under the OS management.
The DPTX 4 of the source device 10 has a register (not shown) that stores data such as a pre-emphasized level and a voltage amplitude level, which are signal reception conditions necessary for data transmission with the sink device 20.

<Structure of sink device>
The sink device 20 is a so-called receiving-side graphic controller, and includes a display port receiver DPRX 22, an AV processor 24, a Video_I/F 25, an Audio_I/F 26, an EDID 27, and a CPU 28.
The display port receiver DPRX22 has a DPCD 22a, an HPD driver 22b, and an HPD register 22c, receives the main links ML0 to ML3 and the AUX channel AC transmitted from the display port transmitter DPTX4, and receives a video signal, an audio signal, and a control signal. Output to the AV processor 24.
The DPCD 22a is a register that stores information such as the number of main link lanes and the bit rate, which is the capability of the sink device.
The DPRX 22 has a physical layer that transmits and receives signals of the main links ML0 to ML3, signals of the AUX channel, and HPD signals, and a link layer that performs functions related to data generation of the main link, communication of the AUX channel, and link of the AUX channel. doing. The main link physical layer has functions such as descramble, decoding, link training, equalization processing, clock data recovery, and deserializer of received signals, and the main link link layer has various symbols for creating frame data from received signals. Of the main link, setting timing skew between lanes of the main link, and generating MSA (Main Stream Attribute) data. In the claims, "control means" is a function of the CPU 28, "clock recovery means" is a function in the physical layer of the DPRX22, "blanking start signal detecting means" is a function in the link layer of the DPRX22, and "link loss detecting means". "Indicates a physical layer and a link layer of the DPRX 22, or a physical layer or a link layer.
The AV processor 24 outputs a video signal to the display device 34 and a voice signal to the speaker 36 via the Video_I/F 25 and the Audio_I/F 26.
The EDID 27 stores function information (resolution, size, timing information (frequency, sync signal parameter), etc.) of a physical display device that constitutes the sink device 20.
The CPU 28 controls the DPRX 22, the AV processor 24, and the EDID 27 via I ² C. The CPU 28 has a ROM and a RAM inside, reads the operating system OS from the ROM, expands it on the RAM, and activates the OS. Under the control of the OS, the program is read from the ROM to execute various processes.
The HPD driver 22b is, for example, a tri-state driver circuit, and when the HPD register 22c is set to the enable state (enabled), outputs the hot plug detection signal HPD indicating that the link loss has occurred to the source device 10. On the other hand, the HPD driver 22b cannot output the hot plug detection signal HPD to the source device 10 when the HPD register 22c is set to the disable state (invalid).
The HPD register 22c stores data according to the control by the CPU 28 and sets the HPD driver 22b in the enabled state or the disabled state.

FIG. 2 is a block diagram showing a layer structure of the DP interface standard for providing video information from the source device 10 to the sink device 20.
The DP interface standard provides as AC coupled voltage differential interfaces three different channels consisting of a main link 10P1, 20P1, auxiliary channels 10P2, 20P2, and a hot plug detect HPD 10P3, 20P3.
The main links 10P1 and 20P1 have one, two, or four pairs of scalable lanes that can operate at different speeds (Gbit/sec), and are implemented by settings in the physical layers 10P and 20P. .. The main links 10P1 and 20P1 are used to transmit a stream from the stream source source 10SS.
The main link speed is determined by several factors including the capabilities of the source device 10, the capabilities of the sink device 20, the quality of the cable, and the noise generated in the system. The stream transmitted from the source device 10 is finally supplied to the stream sink 20SS in the sink device 20.

Since the DPCD 22a and the EDID 27 have been described above, the description thereof will be omitted.
The stream policy makers 10SP and 20SP manage the transmission of streams, respectively. The stream policy makers 10SP and 20SP initialize stream transmission using the auxiliary channel device services 10R3 and 20R3, obtain necessary link information from the link policy makers 10LP and 20LP, and prepare for stream transmission.
The link policy makers 10LP and 20LP manage the establishment and maintenance of links, respectively, as operations conforming to the DP interface standard. The link policy makers 10LP and 20LP use the auxiliary channel link services 10R2 and 20R2 to perform link initialization, link detection, and link maintenance.

On the other hand, the link policy maker 20LPb provided only in the sink device 20 manages the establishment and maintenance of links, respectively, as a non-standard operation that is a feature of the present invention. The link policy maker 20LPb uses the auxiliary channel link services 10R2 and 20R2 to perform link initialization, link detection, and link maintenance.
The RT register 32 stores at least the sync-side equalization parameter among the pre-emphasized level as a signal reception condition used in the clock recovery process, the voltage amplitude level, and the sync-side equalization parameter as a parameter managed by the link policy maker 20LPb. Is stored.
As described above, the sink device 20 includes the RT register 32 that stores the sync-side equalization parameter that is a part of the signal reception condition. Therefore, if data is read from the RT register 32 and used, normal link training is performed. The clock signal embedded in the data stream can be extracted by omitting the processes of determining the pre-emphasized level, determining the voltage amplitude level, and determining the sink-side equalization parameter in the clock recovery process executed in. Note that the parameters such as the pre-emphasized level and the voltage amplitude level included in the signal reception condition are stored in the register of the source device 10, and it is not necessary to determine these parameters again.
As a result, re-linking can be quickly established from the state of link loss by the extracted clock signal.
As described above, the signal reception conditions are the pre-enhancement level, the voltage amplitude level, and the sink-side equalization parameter. Therefore, in the sink device that is connected to the source device through the signal line, the state of the link loss is detected. Can quickly establish a relink.
The control unit 20c is configured by the CPU 28, and controls the non-standard operation when the contact of the switch SW1 is switched to the closed state.

The link layer is involved in the services of isochronous transport services 10R1, 20R1, auxiliary channel link services 10R2, 20R2 and auxiliary channel device services 10R3, 20R3.
At the source device 10, the isochronous transport service 10R1 maps the video and audio streams to a format that has a set of rules that the main links 10P1, 20P1 understand so that the data within the main links 10P1, 20P1. Configure to allow scaling beyond the number of lanes available.
Also, when the data arrives at sink device 20, the rule reconstructs the stream in its original form.

Auxiliary channel link services 10R2, 20R2 are used to discover, configure and maintain links with connected devices. The auxiliary channel link services 10R2, 20R2 do this using the DPCD 22a via the auxiliary channels 10P2, 20P2.
If a hot plug is detected via the hot plug channel, the source device 10 reads, via the DPCD 22a, the capabilities of the sink device 20 at least partially embodied in the EDID 27.

Link training is a signal output from the source device 10 so that the data output from the source device 10 can be properly received by the sink device 20 by grasping the characteristics of the transmission path between the source device 10 and the sink device 20. Is a process performed in order to determine the voltage amplitude and so on, extract the data bit from the data transmitted by the main link in the sink device 20, and reproduce the clock in the PLL.

<Procedure for initial link establishment>
FIG. 3 is a flowchart for explaining a processing procedure by the data transmission system according to the first embodiment of the present invention.
In the processing procedure shown in FIG. 3, when the power is turned on, the CPU 28 of the sink device 20 first sets the HPD signal to be valid (step S50). At this time, the CPU 28 sets the value “1” indicating validity in the HPD register 22c in order to set the output state of the driver 22b to the enable state (valid).
Next, in steps S51 to S55, the CPU 28 performs the same initial link establishment procedure as the processing (steps S251 to S255) shown in FIG. 11B, and thus the description thereof will be omitted.
Therefore, the sink device 20 outputs the HPD signal to the source device 10 (step S51).
Therefore, after the initial link is established, the DPTX 4 of the source device 10 stores the appropriate (a1) pre-enhancement level and (a2) voltage amplitude level appropriate for the transmission path characteristics. Further, the RT register 32 of the sink device 20 stores an appropriate (a3) sink side equalization parameter.
If the (a1) pre-enhancement level, (a2) voltage amplitude level, and (a3) sink side equalization parameter are known in advance at the time of mode setting included in the stage of initial setting, the clock recovery processing of the link training is performed. Some become unnecessary.
In this way, in step S50, the CPU 28 controls the output of the hot plug detection signal HPD to be in the valid state when the power is turned on. Therefore, between the source device 10 and the self sink device 20, the display port interface standard is set. It is possible to perform the processing relating to the initial link establishment conforming to.
Here, if the control unit 20c configured by the CPU 28 stores the signal reception condition acquired at the time of establishing the initial link in the RT register 32, it can be used when re-establishing the link from the state of the link loss. it can.

<Switch SW1>
The control unit 20c illustrated in FIG. 2 includes a switch SW1 that is configured by an external pin and that switches at least two voltage states. The control unit 20c controls when the switch SW1 switches the voltage state to the first voltage state. The clock recovery may be performed using the information about the signal reception condition acquired from the RT register 32.
Switch SW1 switches between at least two voltage states. The control unit 20c can cause the physical layer of the DPRX 22 to perform clock recovery using the information acquired from the RT register 32 when the switch SW1 switches the voltage state to the first voltage state.
As a result, re-linking can be quickly established from the state of link loss by the extracted clock signal.

<Link loss>
Next, in the data transmission system according to the first embodiment of the present invention, a processing procedure when a link loss occurs during transmission of image data will be described. FIG. 4 is a flowchart for explaining a processing procedure when a link loss occurs during transmission of image data in the data transmission system according to the first embodiment of the present invention.
The CPU 28 first sets the HPD signal to be invalid (step S91). At this time, the CPU 28 sets a value "0" indicating invalidity in the HPD register 22c in order to set the output state of the driver 22b to the disabled state (invalidity).
That is, in the state where the stream transmission of the image data is being performed from the source device 10 to the sink device 20 via the main link ML (step S81, step S92), if a link loss occurs due to the influence of noise or the like, The sink device 20 detects the link loss (step S93, Yes), and proceeds to the next step S94.
In the embodiment of the present application, unlike the normal DP interface standard, relinking is established by the following procedure without performing link training with a training pattern.
Since the HPD signal is set to be invalid in step S91, when the link loss is detected (step S93, Yes), the sink device 20 does not activate the hot plug detection HPD signal.

Therefore, since the HPD signal is not output from the sink device 20 to the source device 10, the source device 10 sends a stream of image data and audio data to the sink device 20 even after detecting the link loss on the sink device 20 side. Continue transmission.

<Clock recovery processing>
On the other hand, the link policy maker 20LPb of the sink device 20 performs the clock recovery process in step S94, but the source device 10 performs the (a1) pre-emphasized level and (a2) voltage amplitude level, which are performed in the normal clock recovery process. Does not enter into the link training state, continues stream transmission of image data and audio data at (a1) pre-enhancement level and (a2) voltage amplitude level determined at initial link establishment, and (a3) sync side equalization parameter With regard to the above, it is assumed that one determined at the time of initial link processing according to the pin state of the switch SW1 or one stored in advance in the RT register 32 is read and used as it is, and these parameters are redetermined at the time of this link loss. Absent.
In the case of (a4) clock recovery itself, if the transmission method is 8b/10b, the clock signal is embedded in the serial data itself. Therefore, the clock signal can be extracted and reproduced from the serial data received by the physical layer of the DPRX 22.
As described above, since the clock signal embedded in the data stream is extracted using the signal reception condition determined in the process related to the initial link establishment according to the transmission line characteristic and the functional characteristic of the own sink device, the extraction is performed. The re-link can be quickly established from the state of the link loss by the generated clock signal.

<Equalization processing>
Next, the equalization processing shown in step S95 is performed in the physical layer 20P of the sink device 20, and the control code K28. which is necessary for both processing of (b1) symbol lock and (b2) time adjustment between lanes. Since 5 is included in the BS symbol which is the blanking start symbol in the stream transmission format regardless of the training symbol pattern, the control code K28.5 is detected from the serial data string received in the stream and used. ..
That is, in (b1) symbol lock, the position of K28.5 detected from the serial data string is locked as a symbol boundary, and the serial data is deserialized based on the locked boundary position. In (b2) time adjustment between lanes, the position of each K28.5 detected for each lane is locked as a time difference (skew) adjustment position.

As described above, in the embodiment of the present invention, the clock recovery process and the equalization process are performed under a predetermined condition without using the training pattern, and the re-link is realized from the state of the link loss. When re-linking is realized on the sink device 20 side, at that stage, the source device 10 is in a state of continuously transmitting serial data, so that the sink device 20 can immediately recognize the serial data. Can be received at (step S92).

It should be noted that at the time of link loss, the above-described processing may be performed in principle, and the switch SW1 may be switched to perform the normal processing of the DP interface standard, if necessary.

As described above, according to the first embodiment, even if a link loss occurs, the sink device 20 sets the HPD signal for notifying the fact to the source device 10, so that the source device is disabled. 10 continues the stream transmission of the image serial data.
In the link recovery process, (a1) pre-enhancement level, (a2) voltage amplitude level, and (a3) sink-side equalization parameters that have been determined during initial connection are read from the RAM and used.
Also, (a4) clock recovery itself uses the clock signal embedded in the serial data itself, regardless of the training pattern of link training.
Furthermore, since the control code K28.5 required for both (b1) symbol lock and (b2) lane time adjustment processing is used for the BS symbol of stream-received serial data, it does not depend on the training pattern. Further, the sink device 20 does not transmit the result of the link recovery to the source device 10.
In this way, even if a link loss occurs, there is no communication between the source device 10 and the sink device 20, and the sink device 20 autonomously restores the link, so that relinking can be secured quickly, and the darkness etc. The time of can be shortened as much as possible.

In addition, since the source device 10 does not interact with the sink device 20 at the time of link loss, the load is reduced, and further, it is only necessary to continue the stream transmission of image data, so that the DPTX of the source device 10 is customized. There is no need and no new burden is imposed.

<Second Embodiment>
The present invention has the following configuration in a sink device connected to a source device via a signal line in order to prevent screen flicker due to the influence of noise or the like.
That is, the sink device of the present invention is a sink device connected to the source device via a signal line, and decodes the MSA packet received in the vertical blanking period after the initial link establishment or the relink establishment. MSA decoding means, MSA data storage means for storing decoded MSA data, and whether or not the MSA data related to the current frame and the MSA data related to the previous frame acquired from the MSA data storage means are the same or not. MSA determining means, and control means for controlling whether or not to provide MSA data to the video processor based on the determination result by the MSA determining means. If it is determined that the MSA data is provided to the video processor as new MSA data.
With the above configuration, it is possible to prevent the flicker of the screen due to the influence of noise or the like in the sink device connected to the source device via the signal line.

The sink device of the data transmission system according to the second embodiment of the present invention will be described.
In the first embodiment, in the situation where the link loss occurs due to the influence of noise or the like in the situation where the data stream can be normally transmitted from the source device 10 to the sink device 20 after the initial link is established, the non-linkage The standard processing method has been described.
On the other hand, in the second embodiment, after the initial link is established, under the situation where the data stream can be normally transmitted from the source device 10 to the sink device 20, the MSA data is converted to the MSA data due to the influence of noise or the like. A non-standard processing method when an error occurs will be described.

<Function block diagram of sink device>
FIG. 5 is a block diagram for explaining the internal configuration of the sink device of the data transmission system according to the second embodiment of the present invention.
As shown in FIG. 5, the sink device 20 includes a DPRX 22, an EDID 27, a CPU 28, an AV processor 24, a Video_I/F 25, and an Audio_I/F 26.
The DPRX 22 exchanges information such as link management and link training with the source device 10 via the AUX channel AC. On the other hand, the DPRX 22 receives information such as video data, audio data, video format, screen size, and video timing information transmitted from the source device 10 via the main link ML, and the DPRX 22 decodes the received data to obtain various data. Is output to the AV processor 24.
In the second embodiment, the DPRX 22 described in the first embodiment shown in FIG. 1 will be described in detail.
Specifically, the DPRX 22 includes a video data decoding unit 22d, an audio data decoding unit 22e, an InfoFrame packet decoding unit 22f, an MSA decoding unit 22g, a VBID decoding unit 22h, and a DPCD 22a.
The video data decoding unit 22d decodes the input video data. The audio data decoding unit 22e decodes the input audio data.
The InfoFrame packet decoding unit 22f decodes the InfoFrame packet received during the data island period.
The MSA decoding unit 22g decodes and outputs the MSA from the MSA packet received during the vertical blanking period.
The VBID decoding unit 22h decodes a vertical blanking ID (Vertical Blanking ID) to generate VBID decoded data. This vertical blanking ID includes a vertical blanking flag.
Since the DPCD 22a has been described above, its explanation is omitted.

The AV processor 24 processes the video data based on the InfoFrame decoded data, the packet decoded data, the MSA decoded data, and the VBID decoded data (MSA data is as described above), and the video data is displayed on the display device via the Video_I/F 25. 34 is displayed.

<Frame structure of DP interface standard>
FIG. 6 is a diagram showing a frame structure of the DP interface standard.
According to the DP interface standard, information such as image size and synchronization timing is transmitted for each frame by using MSA packets in the vertical blanking period.
The MSA packet is transmitted from the source device 10 to the sink device 20 frame by frame, and the sink device 20 generates display data based on the received MSA packet.

<MSA packet>
FIG. 7 is a diagram showing the definition of the MSA packet.
As shown in FIG. 7, Mvid and Nvid are used to reproduce the video stream clock of the display.
Htotal is the total number of pixels in the horizontal line, and Vtotal is the total number of lines in the video frame.
HSP/HSW represents HSYNC polarity/HSYNC width in number of pixels. VSP/VSW represents VSYNC polarity/VSYNC width by the number of lines. Hstart represents the start of the active video pixel for HSYNC. Vstart represents the start of the active video line for VSYNC. MISC1:0 represents other video related information.
Note that in the DP interface standard, not all MSA data is transmitted, but some data is optional, but at least the total number of pixels for horizontal lines (Htotal) and the total number of lines for video frames (Vtotal) are mandatory. It is information.

<DPRX>
FIG. 8 is a functional block diagram for explaining internal configurations of the DPRX and the AV processor of the sink device according to the second embodiment of the present invention.
In the second embodiment, as shown in FIG. 8, the MSA decoding unit 22g provided in the DPRX 22 includes an MSA register 22gr.
The MSA decoding unit 22g decodes the MSA from the MSA packet received in the vertical blanking period and updates the MSA data in the MSA register 22gr. The MSA decoding unit 22g enables the update completion status ST indicating that the MSA register 22gr has been updated, and outputs the update completion status ST to the MSA determination unit 24a.
The update completion status ST is output as High at the time when the data from SS to SE (FIG. 6) forming the MSA data is completed in the vertical blanking period, and during the period when the vertical blanking flag is valid. The state is maintained, and Low is output when the active video period is started. In the claims, "MSA decoding means" means the MSA decoding section 22g, "MSA data storage means" means the MSA register 22gr, "MSA judging means" means the MSA judging section 24a, and "control means" means the control section 24b. Shown respectively. Further, the DPRX 22 of the second embodiment is described by including the driver 22b and the HPD register 22c as in the first embodiment, but in order to prevent the flicker of the screen due to the error of the MSA data, the driver 22b is included. The HPD register 22c may not be included.

<AV processor>
The AV processor 24 includes an MSA determination unit 24a, a control unit 24b, and a video processor 24c. The MSA determination unit 24a and the control unit 24b are configured by the CPU 28 of the sink device 20.
When the update completion status ST of the MSA decoding unit 22g becomes High, the MSA determining unit 24a reads MSA data from the MSA register 22gr of the MSA decoding unit 22g and stores it in the memory 24ar. As a result, each data forming the MSA data shown in FIG. 7 is stored in the memory 24ar. The memory 24ar has a capacity to store MSA data for two frames, and by dividing the capacity of the memory 24ar into ½ units in units of one frame, the received MSA data is alternately stored in units of one frame. It is configured to store the MSA data (t) of the current frame and the MSA data (t-1) of the previous frame, but the MSA data (t-2) of the last-previous frame disappears. To do. The capacity of the memory 24ar may be increased to store three or more frames of MSA data.
Further, the MSA determination unit 24a reads the MSA data (t) of the current frame and the MSA data (t-1) of the previous frame from the memory 24ar in the vertical blanking period, compares them, and compares them for two or more frames. When the same MSA data is detected, information indicating that the determination results are the same is output to the control unit 24b.
Note that the MSA determination unit 24a reads the MSA data (t) of the current frame and the MSA data (t-1) of the previous frame from the memory 24ar and compares them, and when the MSA data differs for only one frame. Does not output information indicating that the above determination results are the same.

When the control unit 24b receives the information indicating that the above determination results are the same, the control unit 24b receives the MSA data (t) of the current frame or the MSA data (t-1 of the previous frame from the memory 24ar of the MSA determination unit 24a. ) Is read out and the acquired MSA data is stored in the MSA register 24br.
The video processor 24c reads the MSA data for each frame from the MSA register 24br of the control unit 24b in the vertical blanking period, and configures the angle of view for one frame based on the acquired MSA data.

<Operation explanation>
FIG. 9 is a flowchart showing the operations of the DPRX and AV processor of the sink device according to the second embodiment of the present invention.
<MSA decoding section>
The MSA decoding unit 22g provided in the DPRX22 decodes the MSA from the MSA packet received in the vertical blanking period, stores the MSA data in the MSA register 22gr, and updates the MSA register 22gr with an update completion status ST. The state is changed from the Low state to the High state and output to the MSA determination unit 24a.
At this time, the update completion status ST (High state) output from the MSA decoding unit 22g is High when the reception of data from SS to SE (FIG. 6) forming the MSA data is completed in the vertical blanking period. Therefore, it may be configured to switch to the Low state and be released when the vertical blanking period ends.

<MSA determination unit>
The MSA determination unit 24a provided in the AV processor 24 reads the update completion status ST output from the MSA decoding unit 22g (step S101).
The MSA determination unit 24a determines whether or not the update completion status ST of the MSA decoding unit 22g has switched from the Low state (0) to the High state (1) during the vertical blanking period (step S102).
When the update completion status ST is switched to the high state (1) (step S102, Yes), the MSA determination unit 24a adds 1 to the counter X. Note that X is a natural number.
Next, the MSA determination unit 24a determines whether or not the value of the counter X is an even number (step S104).
When the value of the counter X is an even number (Yes in step S104), the MSA data is read from the MSA register 22gr of the MSA decoding unit 22g and the MSA data is stored in the memory A of the memory 24ar (step S105).
On the other hand, when the value of the counter X is an odd number (step S104, No), the MSA data is read from the MSA register 22gr of the MSA decoding unit 22g and the MSA data is stored in the memory B of the memory 24ar (step S106).
Next, the MSA determination unit 24a determines whether the data values read from both the memories A and B of the memory 24ar are the same (step S107). When the MSA determination unit 24a determines that the data values of the two are not the same (No in step S107), the process proceeds to step S112. As a result, even if the MSA packet being transmitted changes to different data for one frame due to noise, the changed MSA data is not used but the MSA data stored in the MSA register 24br of the control unit 24b is used. A video signal can be generated to remove MSA data errors.
The control unit 24b maintains the data in the MSA register 24br unless it determines that the MSA data different from the currently used MSA data is received multiple times.

<Control part>
On the other hand, when it is determined that the data values stored in the memories A and B of the MSA determination unit 24a are the same (step S107, Yes), the control unit 24b causes the memory 24ar provided in the MSA determination unit 24a. The data values stored in the memory A and the memory (C) 24bc of the control unit 24 are acquired (step S108).
In step S108, the control unit 24b stores the MSA data provided to the video processor 24c up to the previous time in the memory 24bc.

Next, the control unit 24b determines whether the data values read from both the memories A and C are the same (step S109). When the control unit 24b determines that the two data values are the same (Yes in step S109), the process proceeds to step S112.
On the other hand, when it is determined that the data values of the memories A and C are not the same (No in step S109), the control unit 24b obtains the data value from the memory A of the memory 24ar provided in the MSA determination unit 24a. It is acquired and stored in the memory C of the memory 24bc (step S110).
Next, the control unit 24b obtains the data value of the memory C and stores the data value in the MSA register (D) 24br, so that the video processor 24c stores the latest MSA data stored in the register (D) 24br. Is provided (step S111). Then, it progresses to step S112.
During the vertical blanking period, the video processor 24c reads (polling) the MSA data for each frame from the MSA register 24br of the control unit 24b, and configures the angle of view for one frame based on the acquired MSA data.
In this way, the control unit 24b determines that the MSA determination unit 24a determines the same MSA data multiple times, and determines that the MSA data is different from the MSA data provided to the video processor 24c until the previous time. To the video processor 24c as new MSA data.
As a result, in the sink device connected to the source device via the signal line, the image of a desired size (Htotal, Vtotal) is displayed on the display device 34 without being affected by the MSA packet data corruption due to noise or the like. , It is possible to prevent the flickering of the screen.

<Display period operation elimination processing>
The control unit 24b reads the update completion status ST output from the MSA decoding unit 22g (step S112).
The control unit 24b determines whether or not the update completion status ST output from the MSA decoding unit 22g has switched from the High state (1) to the Low state (0) (step S102). When the update completion status ST is in the high state (1), it is determined that the vertical blanking period is in progress (No in step S113), the process returns to step S112, and the process is repeated.
On the other hand, when the update completion status ST is switched to the Low state (0), it is determined that the display period is in progress (Yes in step S113), the process returns to step S101, and the process is repeated.

During the vertical blanking period, the video processor 24c reads (polling) the MSA data for each frame from the register 24br of the control unit 24b, and configures the angle of view for one frame based on the acquired MSA data.
Conventionally, when the data of the MSA packet is changed to an incorrect value and transmitted due to the influence of noise or the like, an error occurs in the data such as the total number of pixels in the horizontal line and the total number of lines in the video frame. Had occurred.
For example, when the screen resolution is VGA, the total number of horizontal line pixels (Htotal) and the total number of video frame lines (Vtotal) sent in an MSA packet are 640 and 480, respectively. Then, for example, if the total number of pixels in a horizontal line (Htotal) and the total number of lines in a video frame (Vtotal) change to 800, 500, etc., as shown in FIG. Is stretched to the lower right.
On the other hand, in the second embodiment, when the AV processor 24 includes the MSA determination unit 24a, the data values of the received MSA packet are compared between two frames, and different MSA data are continuously received for two or more frames. Only, it was decided to reflect the information of the MSA data on the display.
Therefore, even if the data of the MSA packet is changed to an erroneous value and transmitted due to the influence of noise or the like, as shown in FIG. It is possible to suppress the occurrence of flicker on the screen due to the data error for one frame that occurred in 1).
Accordingly, it is possible to remove the data error of the MSA packet including the total number of pixels and/or the total number of lines related to the horizontal line that configures the video frame.

In step S107, the control unit 24b may be configured to provide the MSA data as new MSA data to the video processor 24c when the MSA determination unit 24a determines that the same MSA data is obtained a plurality of times. ..
As a result, in the sink device connected to the source device via the signal line, it is possible to prevent screen flicker due to the influence of noise or the like.

<Structure, Action, and Effect of Embodiment of the Present Invention>
<First aspect>
The sink device 20 of this aspect is a sink device 20 connected to the source device 10 via a signal line,
After the initial link is established, the CPU 28 that controls the output of the hot plug detection signal HPD indicating that a link loss has occurred to the source device 10 to be in an invalid state, and the data stream that is continuously transmitted from the source device 10. In the physical layer and/or link layer of the DPRX22 that detects the occurrence of link loss during reception, and in the physical layer of the DPRX22 that extracts the clock signal embedded in the data stream when the occurrence of link loss is detected. The function, the function in the link layer of the DPRX 22 that detects the blanking start symbol embedded in the data stream when the occurrence of the link loss is detected, and the RT register 32 that stores the signal reception condition when the link is established. It is characterized in that the re-link is established by the extracted clock signal and the detected blanking start signal.
According to this aspect, the CPU 28 controls so that the output of the hot plug detection signal HPD indicating that a link loss has occurred to the source device 10 becomes invalid after the initial link is established. The function in the physical layer and/or the link layer of the DPRX 22 detects the occurrence of the link loss during the reception of the data stream continuously transmitted from the source device 10. The physical layer function of the DPRX 22 extracts the clock signal embedded in the data stream when the occurrence of the link loss is detected. The function in the link layer of the DPRX 22 detects the blanking start symbol embedded in the data stream when the occurrence of the link loss is detected. The RT register 32 stores the signal reception condition when the link is established. Then, the re-link is established by the extracted clock signal, the signal reception condition stored in the RT register 32, and the detected blanking start signal.
In this way, in the sink device connected to the source device via the signal line, the link loss state can be quickly restored to the normal state.
Specifically, even if a link loss occurs, the sink device autonomously recovers the link without exchanging between the source device and the sink device, so that relinking can be secured quickly and the time of darkening etc. Can be shortened as much as possible. Further, the source device does not have to impose a new burden because it simply continues to stream the image data.

<Second mode>
The signal reception condition of this aspect is characterized in that it is a sync-side equalization parameter.
According to this aspect, the signal reception condition is the equalization parameter on the sink side, so that the sink device connected to the source device via the signal line so as to face each other quickly establishes the relink from the state of the link loss. can do.

<Third aspect>
The control unit 20c according to this aspect controls the output of the hot plug detection signal HPD to be in the valid state when the power is turned on, and complies with the display port interface standard between the source device 10 and the own sink device 20. It is characterized in that processing relating to initial link establishment is performed.
According to this aspect, the control unit 20c controls the output of the hot plug detection signal HPD to be in the valid state when the power is turned on, and the display port interface standard is set between the source device 10 and the own sink device 20. It is possible to perform the processing relating to the initial link establishment conforming to.

<Fourth aspect>
The sink device 20 of this aspect includes a switch unit that switches at least two voltage states, and the control unit 20c displays the information acquired from the RT register 32 when the switch unit switches the voltage state to the first voltage state. It is characterized in that the function in the physical layer of the DPRX 22 is used to perform clock recovery.
According to this aspect, the switch SW1 switches at least two voltage states. When the switch SW1 switches the voltage state to the first voltage state, the control unit 20c can cause the function in the physical layer of the DPRX 22 to perform the clock recovery by using the information acquired from the register 32.
As a result, re-linking can be quickly established from the state of link loss by the extracted clock signal.

<Fifth aspect>
The sink device 20 of the present aspect, the MSA decoding unit 22g that decodes the MSA packet received in the vertical blanking period after the initial link establishment or after the relinking establishment, the MSA register 22er that stores the decoded MSA data, The MSA determination unit 24a that determines whether or not the MSA data related to the current frame and the MSA data related to the previous frame, which are acquired from the MSA register 22er, are the same. A control unit 24b for controlling whether or not to provide the processor 24c, and the control unit 24b determines that the MSA data is new MSA data when the MSA determination unit 24a determines the same MSA data a plurality of times. It is provided to the video processor 24c.
According to this aspect, the MSA decoding unit 22g decodes the MSA packet received in the vertical blanking period after the initial link establishment or the relink establishment. The MSA register 22er stores the decoded MSA data. The MSA determination unit 24a determines whether or not the MSA data regarding the current frame and the MSA data regarding the previous frame acquired from the MSA register 22er are the same. The control unit 24b controls whether to provide the MSA data to the video processor 24c based on the determination result of the MSA determination 24a. When the MSA determination unit 24a determines that the MSA data is the same MSA data multiple times, the control unit 24b provides the MSA data as new MSA data to the video processor 24c.
As a result, in the sink device connected to the source device via the signal line, it is possible to prevent screen flicker due to the influence of noise or the like.

<Sixth aspect>
The sink device 20 of this aspect is the sink device 20 connected to the source device 10 via a signal line, and decodes the MSA packet received in the vertical blanking period after initial link establishment or relink establishment. The MSA decoding unit 22g, the MSA register 22er that stores the decoded MSA data, and the MSA that determines whether the MSA data related to the current frame and the MSA data related to the previous frame acquired from the MSA register 22er are the same. The control unit 24b includes a determination unit 24a and a control unit 24b that controls whether or not to provide the MSA data to the video processor 24c based on the determination result by the MSA determination unit 24a. When it is determined that the same MSA data is obtained, the MSA data is provided to the video processor 24c as new MSA data.
According to this aspect, the MSA decoding unit 22g decodes the MSA packet received in the vertical blanking period after the initial link establishment or the relink establishment. The MSA register 22er stores the decoded MSA data. The MSA determination unit 24a determines whether the MSA data related to the current frame and the MSA data related to the previous frame acquired from the MSA register 22er are the same. The control unit 24b controls whether to provide the MSA data to the video processor 24c based on the determination result by the MSA determination unit 24a. When the MSA determination unit 24a determines that the same MSA data is obtained a plurality of times, the control unit 24b provides the MSA data as new MSA data to the video processor 24c.
As a result, in the sink device connected to the source device via the signal line, it is possible to prevent screen flicker due to the influence of noise or the like.

<Seventh mode>
When the MSA determination unit 24a determines the same MSA data multiple times and when the MSA data is different from the MSA data provided to the video processor 24c up to the previous time, the control unit 24b of the present aspect determines the MSA data. It is characterized in that it is provided to the video processor 24c as new MSA data.
According to this aspect, when the MSA determination unit 24a determines that the MSA data is the same MSA data multiple times, and when the MSA data is different from the MSA data provided to the video processor 24c until the last time, The MSA data is provided to the video processor 24c as new MSA data.
As a result, in the sink device connected to the source device via the signal line, it is possible to prevent screen flicker due to the influence of noise or the like.

<Eighth mode>
The control unit 24b of this aspect is characterized in that, when the MSA determination unit 24a determines that the same MSA data does not exist multiple times, the control unit 24b maintains the MSA data provided to the video processor 24c until the last time.
According to this aspect, the control unit 24b maintains the MSA data provided to the video processor 24c until the previous time when the MSA determination unit 24a determines that the same MSA data does not exist a plurality of times.
As a result, in the sink device connected to the source device via the signal line, it is possible to remove the data error of the MSA packet being transmitted due to the influence of noise.

<Ninth aspect>
The MSA data of this aspect is characterized in that it is the total number of pixels and/or the total number of lines related to horizontal lines that form a video frame.
According to this aspect, the MSA data is the total number of pixels, and/or the total number of lines, of the horizontal lines that make up the video frame.
As a result, it is possible to remove the data error of the MSA packet, which is the total number of pixels and/or the total number of lines related to the horizontal lines that form the video frame.

<Tenth aspect>
The control method of this aspect is a control method by the sink device 20 connected to the source device 10 via a signal line, and is a source device of a hot plug detection signal HPD indicating that a link loss has occurred after the initial link is established. A control step (S91) for controlling the output to 10 to be in an invalid state, and a link loss detection step (S93) for detecting occurrence of a link loss during reception of the data stream continuously transmitted from the source device 10. And a clock recovery step (S94) of extracting a clock signal embedded in the data stream when the occurrence of the link loss is detected, and a block recovery step embedded in the data stream when the occurrence of the link loss is detected. A blanking start signal detection step (S95) of detecting a ranking start symbol and a storage step (S53) of storing a signal reception condition at the time of link establishment are executed, and the extracted clock signal and RT register are executed. The re-link is established by the signal reception condition stored in 32 and the detected blanking start signal.
The actions and effects of the tenth aspect are similar to those of the first aspect, and therefore their explanations are omitted.

<Eleventh mode>
The control method according to the present aspect is a control method by the sink device 20 connected to the source device 10 via a signal line, and includes an MSA packet received in a vertical blanking period in a data stream transmitted from the source device 10. The MSA decoding step of decoding by the MSA decoding section 22e, the storing step of storing the decoded MSA data in the MSA register 22gr by the MSA decoding section 22e, the MSA data of the current frame and the previous frame acquired from the MSA register 22gr. MSA determination step (S107) for determining whether the MSA data is the same as the above, and a control step (S109) for controlling whether or not to provide the MSA data to the video processor based on the determination result by the MSA determination step. And the control step provides the video processor with new MSA data as new MSA data when the MSA determination step determines that the same MSA data is obtained a plurality of times.
The actions and effects of the eleventh aspect are the same as those of the sixth aspect, and therefore description thereof will be omitted.

The sink device and the control method of the present invention can be adopted or mounted in a game machine such as a pachinko machine, for example.

2... AV processor, 4... Display port transmitter DPTX, 6... CPU, 10... Source device, 10SP, 20SP... Stream policy maker, 10R1, 20R1... Isochronous transport service, 10R2, 20R2... Auxiliary channel link service, 10R3 , 20R3... Auxiliary channel device service, 10LP, 20LP... Link policy maker, 10P2, 20P2... Auxiliary channel, 10P1, 20P1... Main link, 20... Sink device, 22... Display port receiver DPRX, 22a... DPCD, 22d... Video data Decoding unit, 22e... Audio data decoding unit, 22f... InfoFrame packet decoding unit, 22g... MSA decoding unit, 22gr... MSA register, 22h... VBID decoding unit, 24... AV processor, 24a... MSA judging unit, 24ar... Memory, 24b ... control unit, 24br... register, 24c... video processor, 26... EDID, 28... CPU, 30... driver, 32... RT register, 34... display device, 36... speaker, SW1... switch

Claims (11)

A sink device connected to the source device via a signal line,
After the initial link is established, control means for controlling the output of the hot plug detection signal indicating that a link loss has occurred to the source device to be in an invalid state,
Link loss detection means for detecting the occurrence of link loss during the reception of the data stream continuously transmitted from the source device,
Clock recovery means for extracting a clock signal embedded in the data stream when the occurrence of the link loss is detected,
Blanking start signal detection means for detecting a blanking start symbol embedded in the data stream when the occurrence of the link loss is detected,
Storage means for storing the signal reception condition at the time of link establishment,
A sink device for establishing a relink by the extracted clock signal, the signal reception condition stored in the storage means, and the detected blanking start signal. The sink device according to claim 1, wherein the signal reception condition is a sync-side equalization parameter. When the power is turned on, the control means controls the output of the hot plug detection signal to be in an effective state, and establishes an initial link between the source device and its own sink device in accordance with the DisplayPort interface standard. The sink device according to claim 1, wherein the sink device performs the process. A switch means for switching between at least two voltage states,
The control means causes the clock recovery means to perform clock recovery using the information acquired from the storage means when the switch means switches the voltage state to the first voltage state. The sink device according to 1. MSA decoding means for decoding the MSA packet received in the vertical blanking period after the initial link establishment or after the relink establishment,
MSA data storage means for storing the decoded MSA data,
MSA determination means for determining whether or not the MSA data for the current frame and the MSA data for the previous frame acquired from the MSA data storage means are the same;
Control means for controlling whether or not to provide the MSA data to the video processor based on the determination result by the MSA determining means,
5. The control unit provides the MSA data to the video processor as new MSA data when the MSA determination unit determines that the same MSA data is obtained a plurality of times. The sink device according to item 1. A sink device connected to the source device via a signal line,
And MSA decoding means for decoding the MSA packets received in the initial link establishment after or vertical blanking period after re link establishment,
MSA data storage means for storing the decoded MSA data,
MSA determination means for determining whether or not the MSA data for the current frame and the MSA data for the previous frame acquired from the MSA data storage means are the same;
Control means for controlling whether or not to provide the MSA data to the video processor based on the determination result by the MSA determining means,
The sink device, wherein the control unit provides the MSA data as new MSA data to the video processor when the MSA determination unit determines that the MSA data is the same MSA data a plurality of times. When the MSA determination unit determines that the same MSA data is obtained a plurality of times and when the MSA data is different from the MSA data that has been provided to the video processor until the last time, the control unit updates the MSA data. The sink device according to claim 5 or 6, wherein the sink device is provided as MSA data to the video processor. 7. The control unit maintains the MSA data provided to the video processor until the last time, when the MSA determination unit determines that the same MSA data does not exist multiple times. The sink device described in. The sink device according to claim 5 or 6, wherein the MSA data is the total number of pixels and/or the total number of lines in a horizontal line for forming a video frame. A control method by a sink device connected to a source device via a signal line,
After the initial link is established, a control step of controlling the output of the hot plug detection signal indicating that a link loss has occurred to the source device to an invalid state,
A link loss detecting step of detecting the occurrence of link loss during reception of a data stream continuously transmitted from the source device;
A clock recovery step of extracting a clock signal embedded in the data stream when the occurrence of the link loss is detected,
A blanking start signal detecting step of detecting a blanking start symbol embedded in the data stream when the occurrence of the link loss is detected,
Performing a storage step of storing the signal reception condition at the time of link establishment in the storage means,
A control method characterized in that a relink is established by the extracted clock signal, the signal reception condition stored in the storage means, and the detected blanking start signal. A control method by a sink device connected to a source device via a signal line,
An MSA decoding step of decoding an MSA packet received during a vertical blanking period in a data stream transmitted from the source device;
A storage step of storing the decoded MSA data in an MSA data storage means;
An MSA determination step of determining whether or not the MSA data related to the current frame and the MSA data related to the previous frame acquired from the MSA data storage means are the same;
A control step of controlling whether or not to provide the MSA data to a video processor based on the determination result of the MSA determination step,
The control method, wherein the control step provides the MSA data to the video processor as new MSA data when the MSA determination step determines that the same MSA data is obtained a plurality of times.

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