JP6738874B2 - Analog-to-digital converter device and test signal generation method - Google Patents

Description

The present disclosure relates to an analog-digital converter device, and more particularly, to a time interleaved analog-digital converter and a method for generating a signal under test thereof.

BACKGROUND Analog-to-digital converters (eg, US Pat. No. 6,037,097) are commonly used in various electronic devices to convert analog signals to digital signals for signal processing.

US Pat. No. 8,730,072

The higher the resolution and speed of operation of the analog-to-digital converter, the higher the cost and difficulty of measuring the performance of the analog-to-digital converter. For example, the higher the resolution and the more pins the analog-to-digital converter needs to measure, the larger the circuit area. Alternatively, the faster the operating speed, the faster the data transmission rate of the converted digital signal and the higher the specification requirements of the measuring device.

In order to solve the above problems, one aspect of the present disclosure is to convert an input signal based on a plurality of interleaved clock signals respectively corresponding to a plurality of channels to generate a plurality of quantized outputs. A plurality of analog-to-digital converter circuit systems each having a sampling frequency used for the clock signal, and a down-sampling operation coupled to the analog-to-digital converter circuit system based on a first control signal and the quantized output. And a data output circuit system used to output a first digital signal, said first digital signal being used to determine the performance of said analog-to-digital converter circuit system, It is to provide an analog-digital converter device in which the frequency of the first digital signal is N/M times the sampling frequency and N is a positive integer and the number of the channels.

One aspect of the disclosure is to convert an input signal to generate a plurality of quantized outputs based on a plurality of clock signals interleaved by a plurality of analog-to-digital converter circuit systems, each of the clock signals having a sampling frequency. Outputting a first digital signal by performing a downsampling operation based on the first control signal and the quantized output, the first digital signal being the analog-digital converter circuit system. And a frequency of the first digital signal is N/M times the sampling frequency, where N is a positive integer and the number of channels. is there.
In one embodiment, the frequency of the first control signal is N/M times the sampling frequency.

In one embodiment, the data output circuit system is coupled to the analog-to-digital converter circuit system and selects one of the quantized outputs based on a second control signal to output as a second digital signal. A multiplexer used to generate the first digital signal, the downsampling operation being based on the first control signal and the second digital signal to generate the first digital signal. And a downsampling circuit in which M is a prime number different from N.

In one embodiment, the frequency of the second control signal is N times the sampling frequency.

In one embodiment, the data output circuit system is coupled to the analog-to-digital converter circuit system and selects one of the quantized outputs based on the first control signal to provide a second digital signal. A multiplexer used to output, and a sequence circuit coupled to the multiplexer, used to combine the second digital signal and at least one redundant data to generate the first digital signal. ..

In one embodiment, the frequency of the second control signal is equal to the sampling frequency.

In one embodiment, the data output circuit system is coupled to the analog-to-digital converter circuit system and performs a data combining operation based on a second control signal and the quantized output to generate a second digital signal. A first data output sub-circuit used for generating the third digital signal by performing the downsampling operation based on the first control signal and the second digital signal, and the analog-digital conversion A quantized output based on a third control signal to output a fourth digital signal and perform the downsampling operation based on the fourth digital signal. A second data output sub-circuit used for generating a fifth digital signal, the first data output sub-circuit and the second data output sub-circuit, and the third digital signal And a control circuit used to selectively output one of the fifth digital signals as the first digital signal.

In one embodiment, the control circuit is coupled to the first data output sub-circuit to receive the third digital signal and the first data output sub-circuit is turned on when the first switch is turned on. Is coupled to the first switch for outputting the third digital signal as the first digital signal by the first switch and the second data output sub-circuit to receive the fifth digital signal. A second switch for outputting the fifth digital signal as the first digital signal by the second switch when the second switch is turned on.

To summarize the above, the analog-digital converter device and the signal-under-test generation method provided in the present disclosure perform the down-sampling operation on the quantized outputs of a plurality of channels to obtain the signal-under-test for low frequency. Can be generated. In this way, the hardware cost and difficulty of measuring the overall performance of the analog-to-digital converter device can be reduced.

The drawing description of the present disclosure is as follows.
FIG. 3 is a schematic diagram illustrating an analog-digital converter device according to an embodiment of the present disclosure. FIG. 1B is a schematic waveform diagram showing a plurality of clock signals in FIG. 1A according to an embodiment of the present disclosure. FIG. 1B is a circuit schematic diagram showing the data output circuit system in FIG. 1A according to an embodiment of the present disclosure. FIG. 1B is a circuit schematic diagram showing the data output circuit system in FIG. 1A according to an embodiment of the present disclosure. FIG. 3 is a circuit schematic diagram showing a data output circuit system and a control circuit according to an embodiment of the present disclosure. FIG. 6 is a flow diagram illustrating a method of generating a signal under test according to an embodiment of the present disclosure.

All terms as used herein have their ordinary meaning. The above vocabulary is defined in commonly used dictionaries, and the examples of use, including the vocabulary discussed herein, are merely exemplary and are not intended to limit the scope or meaning of the present disclosure. As such, the present disclosure is not limited to the various embodiments presented herein.

Further, as used in the specification, “coupling” or “connection” means that two or more elements are directly in contact with each other or are in electrical contact with each other, or indirectly are in contact with each other in contact with each other. Alternatively, two or more elements may operate or operate on each other.

The term "circuit system" as used herein refers to a single system composed of one or more circuits. The term "circuit" generally refers to an object in which one or more transistors and/or one or more active and passive elements are connected in a certain manner to process a signal.

As used in the specification, "about", "substantially" or "equivalent" generally refers to a numerical error or range within 20%, preferably within 10%, and more preferably 5%. Within. Unless stated otherwise, all numerical values mentioned are considered to be approximations, such as the error or range expressed in "about", "substantially" or "equivalent".

Please refer to FIG. 1A and FIG. 1B. FIG. 1A is a schematic diagram illustrating an analog-to-digital converter (ADC) device 100 according to an embodiment of the present disclosure. FIG. 1B is a schematic waveform diagram showing the plurality of clock signals CLK1 to CLKN in FIG. 1A according to an embodiment of the present disclosure. In one embodiment, ADC device 100 is operated as a time-interleaved ADC with multiple channels.

In one embodiment, ADC device 100 includes a plurality of analog-to-digital converter circuit systems AD1-ADN and a data output circuit system 130. Each of the analog-digital converter circuit systems AD1-ADN is operated as a single channel. That is, in this example, the ADC device 100 includes N channels and N is a positive integer greater than 1. The data output circuit system 130 performs a data combination operation and a down sample operation based on the quantized outputs Q1 to QN of a plurality of channels, or performs only a down sampling operation to generate the digital signal D0. Used for. In one embodiment, as shown in FIG. 3 below, the data output circuit system 130 can generate the digital signal D0 when the data combination operation is not performed.

As shown in FIG. 1A, the plurality of analog-to-digital converter circuit systems AD1 to ADN perform analog-to-digital conversion on the input signal VIN based on the corresponding ones of the plurality of clock signals CLK1 to CLKN, thereby performing a plurality of quantum conversions. It is used to generate the corresponding one of the converted outputs Q1 to QN. As shown in FIG. 1B, each cycle of the plurality of clock signals CLK1 to CLKN is set to TS and is equal to 1/fs. That is, the sampling frequency of the plurality of analog-digital converter circuit systems AD1 to ADN is fs.

Taking the first channel as an example, the analog-digital converter circuit system AD1 includes a sampling circuit 110 and an ADC circuit 120. The sampling circuit 110 samples the input signal VIN based on the corresponding clock signal CLK1 to generate the sampling signal S1. The ADC circuit 120 is coupled to the sampling circuit 110 and receives the sampling signal S1. The ADC circuit 120 performs analog-digital conversion based on the corresponding clock signal CLK1 to generate a quantized output Q1. The output of the ADC circuit 120 is coupled to the data output circuit system 130 and transmits the quantized output Q1 to the data output circuit system 130. The operation of the remaining channels is the same as that of the first channel and will not be described in detail here.

In one embodiment, there is a scheduled delay TD between two adjacent clock signals in the plurality of clock signals CLK1-CLKN. For example, as shown in FIG. 1B, there is a scheduled delay TD between the clock signal CLK1 and the clock signal CLK2. In this way, the first channel and the second channel perform sampling operation and analog-digital conversion at different times. By analogy with this, N channels may operate at multiple interleave timings.

The data output circuit system 130 is coupled to the plurality of ADC circuits 120 and receives the plurality of quantized outputs Q1 to QN. As described above, the data output circuit system 130 performs the data combination operation and the downsampling operation on the quantized outputs Q1 to QN by the plurality of channels to generate the digital signal D0. In one embodiment, the data output circuit system 130 performs a data combining operation (as shown in FIG. 2 below) on the plurality of quantized outputs Q1 to QN based on the control signal C1 so that the frequency of the control signal C1 is It is N times the sampling frequency fs. By the data combination operation, a plurality of quantized outputs Q1 to QN by N channels can be combined into a single digital signal (digital signal D1 in FIG. 2 below) having N times the sampling frequency fs. In one embodiment, the single digital signal from the data combination manipulation process is the valid digital data that ADC device 100 seeks to output.

For example, the number of channels N is 20, the resolution of each of the channels is 10 bits, and the sampling frequency fs is set to 500 megahertz (MHz). Under this condition, the data combination operation allows the ADC device 100 to output a digital signal having 10 bits, and its frequency is 1 billion hertz (GHz) (that is, 20×500 M).

Note that in one embodiment, the data output circuit system 130 performs a downsampling operation on the plurality of quantized outputs Q1 to QN based on the control signal C2 to generate the digital signal D0, and the frequency of the control signal C2 changes. It may be N/M times the sampling frequency fs (eg, as in FIG. 2 below) or equal to the sampling frequency fs (eg, as in FIG. 3 below). In this way, the frequency of the digital signal D0 (or the data transmission rate (data rate)) may be reduced to be equivalent to N/M times fs. In an embodiment, by measuring the digital signal D0, the performance of the entire plurality of ADC circuit systems AD1 to ADN (that is, the ADC device 100) can be determined.

In some embodiments (as shown in Figure 2 below), M may be set to N-1 or N+1. For example, if the number of channels N is 20, M may be set to 19 or 21. Under this condition, the down sampling operation allows the ADC device 100 to output a digital signal D0 having 10 bits, the frequency of which is (20/19)×500 MHz or (20/21)×500 MHz. The setting mode regarding M is only an example, and the present disclosure is not limited to this. All other prime numbers for which M can be set (for example, M is 2N+1 or 2N−1) are within the scope of the present disclosure. Setting M to a prime number prevents the data output circuit system 130 from outputting a constant and uniform quantized output, and the digital signal D0 is sufficient to reflect the performance of the ADC device 100. Can be secured.

In one related technology, in order to measure the performance of a time interleaved ADC, the ADC output in each channel is provided with a plurality of pins corresponding to the measurement by connecting to a measuring instrument, or output data to an external device. Separate memory is provided to store and store valid digital data as provided and measured. In these techniques, there are many different pin numbers for measurement (for example, if the ADC output of a channel is a 10-bit signal, then 10 pins need to be installed, so there are 10 channels). , 100 pins must be installed) or another memory with large storage space is required. In this way, unnecessary hardware costs are significantly increased. Further, when measuring valid digital data, it is necessary that the device be capable of handling high-speed (for example, N times the sampling frequency fs) digital data. Based on the above causes, the current related technology does not easily measure the performance of the time interleaved ADC.

In the present disclosure, the digital signal D0 resulting from the downsampling operation has a low frequency (ie, equivalent to N/M times the sampling frequency fs). In this way, the performance of the ADC device 100 can be supervised by measuring the digital signal D0. Compared to the above technique, the required number of pins (for example, 10 pins may be installed if the digital signal D0 has 10 bits) is reduced, and the measurement is performed without installing another memory. You can In this way, it is possible to save the related hardware cost and reduce the specification requirement required for the device. In a certain embodiment (the number of channels N=16, and the resolution of the ADC circuit system is 10 bits), the digital signal D1 or the digital signal D0 is analyzed by the above-mentioned installation form and fast Fourier transform, and the analyzed measurement results are similar. There are positive results.

See FIG. FIG. 2 is a circuit schematic diagram showing the data output circuit system in FIG. 1A according to an embodiment of the present disclosure. For ease of understanding, similar elements in FIG. 2 are designated with the same reference numbers with reference to FIG. 1A.

In one embodiment, as shown in FIG. 2, data output circuit system 130A includes multiplexer 132 and downsampling circuit 134. Multiplexer 132 is coupled to the outputs of ADC circuits 120 in FIG. 1A and receives the quantized outputs Q1-QN. The multiplexer 132 is used to perform the data combination operation based on the control signal C1 to generate the digital signal D1. For example, the multiplexer 132 selects one from the plurality of quantized outputs Q1 to QN based on the control signal C1 and outputs it as the digital signal D1. The data transmission rate (data rate) of the digital signal D1 is N times the sampling frequency fs.

Please continue to refer to FIG. The downsampling circuit 134 is coupled to the output of the multiplexer 132 and receives the digital signal D1. The down-sampling circuit 134 is used to perform a down-sampling operation on the digital signal D1 based on the control signal C2 to generate the digital signal D0. The frequency of the control signal C2 is N/M times the sampling frequency fs. is there. Thus, the data transmission rate of the digital signal D0 is equivalent to N/M times the sampling frequency fs. In this example, M may be any prime number greater or less than the number of channels N.

In this example, M may be set to a prime number different from N, such as, but not limited to, N-1 or N+1 above. When M is set to an even number with which N is divisible, the downsampling circuit 134 downsamples the digital signal D1 at a certain time point. As an example, when N is 16 and M is set to 4, the down-sampling circuit 134 is fixed to the fourth, eighth, twelfth, and sixteenth sampling points and the digital signal D1. Down sample. As described above, the data output circuit system 130A may not be able to effectively reflect the status of the overall operation of the ADC device 100. Therefore, by setting M to a prime number different from N, it is possible to prevent the above situation and ensure that the digital signal D0 by the data output circuit system 130A sufficiently reflects the overall performance of the ADC device 100.

See FIG. FIG. 3 is a circuit schematic diagram showing the data output circuit system in FIG. 1A according to an embodiment of the present disclosure. For ease of understanding, similar elements in FIG. 3 are designated with the same reference numbers with reference to FIGS. 1A and 2.

Compared to FIG. 2, in this example, the data output circuit system 130 can generate the digital signal D0 when no data combining operation is performed (ie, the multiplexer 132 is not included). As shown in FIG. 3, the data output circuit system 130B includes a multiplexer 136 and a sequence circuit 138. Multiplexer 136 is coupled to the outputs of ADC circuits 120 in FIG. 1A and receives the quantized outputs Q1-QN. The multiplexer 136 is used to perform the downsampling operation described above based on the control signal C2 to generate the digital signal D2. For example, the multiplexer 136 sequentially selects one of a plurality of quantized outputs Q1 to QN based on the control signal C2 and outputs it as a digital signal D2, and the frequency of the control signal C2 is equal to the sampling frequency fs.

Please continue to refer to FIG. The sequence circuit 138 is coupled to the output of the multiplexer 136 and receives the digital signal D2. The sequence circuit 138 is used to synchronize the multiple digital signals D2, add at least one redundant data, and equivalently execute the downsampling operation. For example, in this example, M is set to be larger than the number of channels N (for example, N+1) so that one redundant data is added when the multiple digital signals D2 are combined to generate the digital signal D0. Good. As an example, when N=16 and M=17, the sequence circuit 138 receives 15 digital signals D2, adds one redundant data (for example, bit 0), and outputs the 15 digital signals D2. The redundant data may be combined and output as a digital signal D0. In one embodiment, the sequencing circuit 138 can delay the digital signal D2 based on the operating schedule of the ADC circuit 120 in the N channels.

In some embodiments as shown in FIG. 3, M may be set to be the same as or different from N. In one embodiment, the at least one redundant data may have a preset scheduled data value. As described above, in the case of the subsequent measurement, by recognizing the predetermined data value, it is possible to remove the at least one redundant data from the digital signal D0 and ensure that the performance of the ADC device 100 is correctly determined. it can.

In one embodiment, sequence circuit 138 may be implemented with a data buffer. In one embodiment, the sequence circuit 138 may be implemented with a first in first out (FIFO) circuit. The implementation of the sequence circuit 138 is only an example, and any other various circuits capable of data synchronization are included in the scope of the present disclosure.

See FIG. FIG. 4 is a schematic circuit diagram showing the data output circuit systems 130A and 130B and the control circuit 400 according to an embodiment of the present disclosure. For ease of understanding, similar elements in FIG. 4 are designated with the same reference numbers with reference to FIGS.

In each embodiment, the ADC circuit system employs a single data output circuit system 130 (eg, the data output circuit system 130A of FIG. 2 or the data output circuit system 130B of FIG. 3) alone, or two data outputs. Circuit systems 130A and 130B may be employed simultaneously. For example, as shown in FIG. 4, in one embodiment, the ADC device 100 may include the two data output circuit systems 130A, 130B and the control circuit 400 described above. In this example, data output circuit system 130A, 130B is operated as two data output subcircuits of data output circuit system 130 in FIG. 1A.

The control circuit 400 includes two switches SW1 and SW2. Switch SW1 is coupled to the output of data output circuit system 130A. Switch SW2 is coupled to the output of data output circuit system 130B. When the switch SW1 is turned on, the digital signal D0-1 (that is, the digital signal D0 in FIG. 2) output by the data output circuit system 130A is output as the digital signal D0 by the switch SW1. Alternatively, when the switch SW2 is turned on, the digital signal D0-2 (that is, the digital signal D0 in FIG. 3) output by the data output circuit system 130B is output as the digital signal D0 by the switch SW2.

It should be explained that the frequency of the control signal C2 (for example, the control signal C2-1 in FIG. 4) for controlling the data output circuit system 130A is N times the sampling frequency fs and the data output is performed as described above. The frequency of the control signal C2 (for example, the control signal C2-2 in FIG. 4) for controlling the circuit system 130B is equal to the sampling frequency fs.

In this example, both the switch SW1 and the data output circuit system 130A are provided to be controlled by the operation signal EN1, and both the switch SW2 and the data output circuit system 130B are provided to be controlled by the operation signal EN2. .. That is, the switch SW1 may be turned on by the operation signal EN1. Further, the data output circuit system 130A may be activated by the operation signal EN1 to perform the related operation of FIG. Alternatively, the switch SW2 may be turned on by the actuation signal EN2 and the data output circuit system 130B may be activated by the actuation signal EN2 to perform the related operation of FIG.

The installation form related to the control circuit 400 described above is used only as an example, and any other control circuit capable of performing the same function is included in the scope of the present disclosure.

FIG. 5 is a flow diagram illustrating a method under test signal generation method 500 according to an embodiment of the present disclosure. For ease of understanding, the method 500 of generating a signal under test will be described with reference to the drawings.

In operation S501, the ADC device 100 having multiple channels generates a plurality of quantized outputs Q1 to QN based on the input signal VIN and a plurality of interleaved clock signals CLK1 to CLKN, and the clock signals CLK1 to CLKN are respectively generated. It has a sampling frequency fs.

For example, as shown in FIGS. 1A and 1B, the ADC device 100 is provided with N-channel ADC circuit systems AD1 to ADN and operated so as to be a time interleaved ADC. The N-channel ADC circuit system can convert the input signal VIN with a plurality of interleaved clock signals CLK1 to CLKN to generate a plurality of quantized outputs Q1 to QN.

In operation S502, the data output circuit system 130 performs a downsampling operation based on the plurality of quantized outputs Q1 to QN to generate the digital signal D0 under test, and the frequency of the digital signal D0 is (N/M )×fs.

For example, as shown in FIG. 2, the data output circuit system 130A performs a data combining operation based on the control signal C1 and the plurality of quantized outputs Q1 to QN to generate the digital signal D1, and the control signal C2. And a digital signal D0 can be generated by performing a downsampling operation based on the digital signal D1. Alternatively, as shown in FIG. 3, the data output circuit system 130B may directly perform the downsampling operation based on the control signal C2 and the plurality of quantized outputs Q1 to QN to generate the digital signal D0.

By the operation S502, it is possible to generate the digital signal D0 for the low frequency test. In this way, the hardware cost and difficulty of measurement of the ADC device 100 can be effectively reduced.

The steps of the signal-under-test generation method 500 are exemplary only, and are not limited to being performed in the order shown. The operations of the signal-under-test generation method 500 may be appropriately added, replaced, omitted, or performed in a different order as long as the operation modes and ranges of the respective embodiments of the present disclosure are not violated.

To summarize the above, the ADC analog-digital converter device and the signal-under-test generation method provided by the present disclosure perform the down-sampling operation on the outputs of the ADCs of a plurality of channels to generate a signal under-test for low frequency. Can be generated. In this way, the hardware cost and difficulty of measuring the overall performance of the ADC device can be reduced.

Although the present disclosure has been disclosed above by the embodiments, this is not intended to limit the present disclosure, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure is based on the content specified in the following claims.

Code explanation

100 analog-digital converter device 130, 130A, 130B data output circuit system 110 sampling circuit VIN input signal fs sampling frequency Q1 to QN quantized output N×fs times N times sampling frequency C1, C2 control signal TD scheduled delay 132, 136 multiplexer D0-1, D0-2, D0-D2 Digital signal EN1, EN2 Actuating signal SW1, SW2 Switch 500 Method C2-1, C2-2 Control signal AD1-ADN Analog-digital converter circuit system 120 Analog-converter circuit CLK1-CLKN Clock signals S1 to SN Sampling signal (N/M)×fs N/M times sampling frequency TS cycle 134 Down sampling circuit 138 Sequence circuit 400 Control circuit S501, S502 Operation

Claims (16)

A plurality of analogs each corresponding to a plurality of channels and used for converting an input signal based on a plurality of interleaved clock signals to generate a plurality of quantized outputs, each of the clock signals having a sampling frequency. A digital converter circuit system,
Coupled to said analog-to-digital converter circuit system, by selecting one from the plurality of quantized output based on selection frequency, down-sampling operation on said selected quantized output based on the first control signal And a data output circuit system used to output a first digital signal,
Including
The first digital signal is used to determine the performance of the analog-to-digital converter circuit system, the frequency of the first digital signal is N/M times the sampling frequency,
N/M times the sampling frequency is lower than the selection frequency,
N is Ri number der positive integer and said channel,
M is Ru different prime der and N,
Analog-to-digital converter device. The analog-digital converter device according to claim 1, wherein the frequency of the first control signal is N/M times the sampling frequency. The data output circuit system,
Coupled to said analog-to-digital converter circuit system, by selecting one from the plurality of quantized output based on the selected frequency, and a multiplexer used to output as a second digital signal,
A downsampling circuit coupled to the multiplexer and used to perform the downsampling operation based on the first control signal and the second digital signal to generate the first digital signal;
An analog-digital converter device according to claim 1 or 2, including: 4. The analog-digital converter device according to claim 3, wherein the selection frequency is N times the sampling frequency. The data output circuit system,
Coupled to the analog-to-digital converter circuit system and performing a data combining operation based on a second control signal and the quantized output to generate a second digital signal, the first control signal and the second control signal. A first data output sub-circuit used to generate the third digital signal by performing the downsampling operation based on the digital signal;
Is coupled to the analog-to-digital converter circuit system, selects one of the quantized outputs based on a third control signal and outputs the quantized output as a fourth digital signal, and outputs the down signal based on the fourth digital signal. A second data output subcircuit used to perform a sampling operation to generate a fifth digital signal;
It is coupled to the first data output sub-circuit and the second data output sub-circuit, and selectively outputs one of the third digital signal and the fifth digital signal as the first digital signal. A control circuit used for
An analog-to-digital converter device according to claim 1 including. The control circuit is
A first switch coupled to the first data output subcircuit for receiving the third digital signal;
A second switch coupled to the second data output subcircuit for receiving the fifth digital signal;
Only including,
When the first switch is turned on, the first data output sub-circuit outputs the third digital signal as the first digital signal by the first switch,
When the second switch is turned on, the second data output sub-circuit outputs the fifth digital signal as the first digital signal by the second switch,
An analog-to-digital converter device according to claim 5 . Converting an input signal based on a plurality of clock signals interleaved by a plurality of analog-to-digital converter circuit systems to generate a plurality of quantized outputs, each of the clock signals having a sampling frequency;
Select one of the plurality of quantized outputs based on a selected frequency, perform a downsampling operation on the selected quantized output based on a first control signal, and output a first digital signal. The process of
Including
The first digital signal is used to determine the performance of the analog-to-digital converter circuit system, the frequency of the first digital signal is N/M times the sampling frequency,
N/M times the sampling frequency is lower than the selection frequency,
N is Ri number der positive integer and said channel,
M is Ru different prime der and N,
Signal generation method under test. 8. The method of generating a signal under test according to claim 7 , wherein the frequency of the first control signal is N/M times the sampling frequency. The step of performing the downsampling operation,
Multiplexer selects one of the plurality of quantized output based on the selected frequency, and outputting a second digital signal,
A downsampling circuit performs the downsampling operation based on the first control signal and the second digital signal to generate the first digital signal;
The test signal generating method according to claim 7 or 8 including. The method for generating a signal under test according to claim 9 , wherein the selected frequency is N times the sampling frequency. The step of performing the downsampling operation,
A first data output sub-circuit performs a data combining operation based on a second control signal and the quantized output to generate a second digital signal, and outputs a second digital signal to the first control signal and the second digital signal. Performing the downsampling operation based on the step of generating a third digital signal;
A second data output sub-circuit selects one of the quantized outputs based on a third control signal and outputs the quantized output as a fourth digital signal, and performs the downsampling operation based on the fourth digital signal. Performing and generating a fifth digital signal,
Selectively outputting one of the third digital signal and the fifth digital signal as the first digital signal;
8. The method of generating a signal under test according to claim 7 , including: Selectively outputting one of the third digital signal and the fourth digital signal as the first digital signal,
When the first switch is turned on and the first switch is turned on, the first data output sub-circuit outputs the third digital signal as the first digital signal by the first switch. Process,
When the second switch is turned on and the second switch is turned on, the second data output sub-circuit outputs the fifth digital signal as the first digital signal by the second switch. Process,
The method of generating a signal under test according to claim 11 , further comprising: A plurality of analogs each corresponding to a plurality of channels and used for converting an input signal based on a plurality of interleaved clock signals to generate a plurality of quantized outputs, each of the clock signals having a sampling frequency. A digital converter circuit system,
A data output circuit system coupled to the analog-to-digital converter circuit system and used for performing a downsampling operation based on a first control signal and the quantized output to output a first digital signal;
Including
The first digital signal is used to determine the performance of the analog-to-digital converter circuit system, the frequency of the first digital signal is N/M times the sampling frequency, and N is a positive integer and Is the number of channels,
The data output circuit system,
A multiplexer coupled to the analog-to-digital converter circuit system for selecting one of the quantized outputs based on the first control signal for output as a second digital signal;
A sequence circuit coupled to the multiplexer and used to combine the second digital signal and at least one redundant data to generate the first digital signal;
An analog-to-digital converter device including. 14. The analog-digital converter device according to claim 13, wherein the frequency of the first control signal is equal to the sampling frequency. Converting an input signal based on a plurality of clock signals interleaved by a plurality of analog-to-digital converter circuit systems to generate a plurality of quantized outputs, each of the clock signals having a sampling frequency;
Performing a downsampling operation based on a first control signal and the quantized output to output a first digital signal;
Including
The first digital signal is used to determine the performance of the analog-to-digital converter circuit system, the frequency of the first digital signal is N/M times the sampling frequency, and N is a positive integer and Is the number of channels,
The step of performing the downsampling operation,
A multiplexer selecting one of the quantized outputs based on the first control signal and outputting it as a second digital signal;
Combining the second digital signal with at least one redundant data by a sequence circuit to generate the first digital signal;
A method for generating a signal under test, including: The method of generating a signal under test according to claim 15, wherein the frequency of the first control signal is equal to the sampling frequency.

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