JP4456220B2 - AD converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an AD conversion apparatus that facilitates testing of an AD converter that converts an input analog signal into a digital signal and outputs the digital signal.
[0002]
[Prior art]
Conventionally, a test for determining the quality of a manufactured AD converter has been performed using an LSI tester. In general, in a successive approximation type AD converter that operates at a frequency up to about several hundreds KHz and an ADSC for video rate compatible with NTSC that operates at a frequency up to about 20 MHz, the operation rate of the cells constituting these AD converters A test is being conducted.
[0003]
[Problems to be solved by the invention]
In recent years, AD converters operating at a high frequency of 50 MHz to 150 MHz are becoming widespread due to needs for digital television and the like. However, it is difficult for a conventional LSI tester to test an AD converter that operates at such a high frequency. Therefore, it is conceivable to test the AD converter at a conventional operation rate. However, this makes it difficult to guarantee whether the AD converter operates at a high frequency. In addition, it may be possible to introduce an expensive LSI tester capable of performing a test at a sufficiently high operation rate. However, using such an expensive LSI tester increases the test cost of the AD converter. A problem occurs. Further, when testing a so-called system-on-chip product in which a circuit including an AD converter is incorporated on one semiconductor chip, the ratio of the AD converter to the system-on-chip product is relatively low. Introducing an expensive LSI tester only for converter testing is a waste of resources (assets).
[0004]
SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide an AD conversion apparatus that can easily test an AD converter that operates at a high frequency while suppressing an increase in test cost.
[0005]
[Means for Solving the Problems]
Of the AD converters of the present invention that achieve the above object, the first AD converter is:
(1_1) AD converter for converting an input analog signal into a digital signal and outputting it
(1_2) A timing generator that receives an input clock signal from the outside and generates a timing signal for operating the AD converter based on the input clock signal
(1_3) A free-running clock generator for generating a free-running clock signal for confirming the operating frequency of a digital circuit, which is allowed to partially share the circuit with the timing generator.
It is provided with.
[0006]
One of the points to confirm the performance of the AD converter in high-speed operation is that the digital control system (control system digital circuit such as clock signal input circuit, timing generator, AD conversion control logic circuit, etc.) for the AD converter operation has a specified frequency. The point is whether or not to operate. The first AD converter of the present invention has been made paying attention to this point of view, and includes a free-running clock generator that generates a free-running clock signal for confirming the operating frequency of the control system digital circuit. By measuring the frequency of the free-running clock signal generated by the free-running clock generator externally, whether or not the delay by the control system digital circuit is within the specified allowable range, that is, the control system digital circuit is defined. It is possible to determine whether or not to operate at a different frequency. Therefore, it is not necessary to prepare an expensive LSI tester and input a clock signal having a high frequency, and it is possible to determine whether or not the AD converter operates at a specified high frequency. In addition, since the self-running clock generator is allowed to partially share the circuit with the timing generator, the size of the test circuit can be reduced.
[0007]
In addition, the second AD converter of the AD converters of the present invention that achieves the above object is
(2_1) AD converter for converting input analog signal to digital signal and outputting
(2_2) A timing generator that receives an input clock signal from the outside and generates a timing signal for operating the AD converter based on the input clock signal
(2_3) Upon receiving an input of a test clock control signal from the outside, a test clock signal corresponding to the test clock control signal is generated, and the generated test clock signal is used instead of the input clock signal. Test clock generator supplied to the timing generator
It is provided with.
[0008]
Another point for confirming the performance of the AD converter at high speed is whether or not the analog unit can follow and maintain its AC characteristics when the AD converter operates at a specified high frequency. Can be given. The second AD converter of the present invention has been made paying attention to this point of view, and receives a test clock control signal having a relatively low frequency from the outside, and receives a test clock generator. By generating a test clock signal having a high frequency and supplying it to the timing generator, the AD converter can be operated at high speed to test the AC characteristics of the analog unit. Therefore, it is not necessary to prepare an expensive LSI tester and input a clock signal having a high frequency, and the conventional LSI tester can operate the AD converter at a high frequency to test the AC characteristics.
[0009]
Here, in the second AD converter of the present invention, the test clock control signal is a clock signal, and the test clock generator multiplies the clock signal input as the test clock control signal. Preferably, the test clock signal is generated.
[0010]
In this way, a test clock signal having a relatively high frequency can be easily generated from a clock signal having a relatively low frequency prepared in a conventional LSI tester.
[0011]
In the second AD converter of the present invention, the test clock control signal is a voltage signal, and the test clock generator has a frequency corresponding to the voltage signal input as the test clock control signal. A test clock signal may be generated.
[0012]
As described above, when the test clock signal having a frequency corresponding to the voltage signal is generated, for example, only the voltage controlled oscillator (VCO) is required to generate the test clock signal, and the circuit configuration is simplified.
[0013]
Furthermore, the second AD converter of the present invention further comprises a data latch for latching the digital signal obtained by the AD converter,
The timing generator generates a latch timing clock signal for controlling the timing at which the digital signal in the data latch is latched;
By dividing the latch timing clock signal generated by the timing generator, a test latch timing clock signal supplied to the data latch is generated instead of the latch timing clock signal generated by the timing generator. It is also a preferred aspect that a peripheral device is provided.
[0014]
Thus, when the digital signal obtained by the AD converter is latched in the data latch by the test latch timing clock signal divided by the frequency divider, the digital signal is thinned and the output rate becomes low. The AD converter can be tested with an LSI tester having a relatively low operation rate.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0016]
FIG. 1 is a circuit diagram of an AD converter according to the first embodiment of the present invention.
[0017]
1 includes a test terminal 11 to which a test signal TEST1 is input, a test terminal 12 to which a test signal TEST2 is input, a clock terminal 13 to which a clock signal CK is input, and an analog signal AIN. Are input, a digital signal output terminal 15 from which a digital signal AOUT is output, and a clock signal output terminal 16 to be described later.
[0018]
Further, the AD conversion apparatus 1 is provided with an AD conversion block 50 composed of an analog part and a digital part for converting an analog signal AIN into a digital signal AOUT and outputting the digital signal AOUT.
[0019]
Furthermore, the AD converter 1 receives an external clock signal CK and generates delay signals 41, 42 for generating timing signals φ1, φ2, φ3 for operating the AD conversion block 50 based on the clock signal CK. , 43 (actually, n delay circuits are provided, but three delay circuits are illustratively shown here). These delay circuits 41, 42 and 43 correspond to the timing generator referred to in the present invention.
[0020]
The AD conversion apparatus 1 includes multiplexers 21 and 22 and a PLL (Phase Locked Loop) circuit 30. The PLL circuit 30 corresponds to a test clock generator according to the present invention. The PLL circuit 30 includes a PFD / CP (phase / frequency detection / charge pump) 31, a frequency divider 32, and a VCO (voltage controlled oscillator) 33. And an L / F (low-pass filter) 34.
[0021]
Further, the AD conversion apparatus 1 is provided with a delay circuit 61 and an inverter 62. The delay circuit 61 and the inverter 62 will be described later.
[0022]
First, the normal mode of the AD conversion apparatus 1 will be described. In the normal mode, the test signals TEST 1 and TEST 2 at the “L” level are input to the test terminals 11 and 12. Further, a clock signal CK having a frequency required for a normal conversion operation, for example, 80 MHz, is input to the clock terminal 13. Further, a desired analog signal AIN is input to the analog input terminal 14.
[0023]
Since the test signal TEST2 of “L” level is input to the control terminal 22a of the multiplexer 22, the clock signal CK input to the input terminal 22b is selected and output from the output terminal 22d in the multiplexer 22. . This clock signal CK is input to the input terminal 21 b of the multiplexer 21. Since the test signal TEST 1 of “L” level is input to the control terminal 21 a of the multiplexer 21, the clock signal CK is output from the output terminal 21 d of the multiplexer 21 in the same manner as the multiplexer 22. This clock signal CK is input to the delay circuit 41. In the delay circuit 41, the input clock signal CK is delayed to generate the timing signal φ 1 and output to the AD conversion block 50. Thereafter, the timing signals φ2 and φ3 are generated by the delay circuits 42 and 43 in the same manner. In this way, timing signals φ1, φ2, and φ3 having different phases are generated. These multiphase timing signals φ 1, φ 2 and φ 3 are input to the AD conversion block 50. The AD conversion block 50 performs AD conversion on the analog signal AIN input via the analog input terminal 14 by using the timing signals φ1, φ2, and φ3 by a level comparator (not shown) to generate a digital signal AOUT. And output to the digital output terminal 15. In this way, in the normal mode, the input analog signal AIN is AD-converted at a conversion rate with a specified frequency of 80 MHz and output as a digital signal AOUT.
[0024]
Next, the test mode of the AD conversion apparatus 1 will be described. The test mode includes a first test mode and a second test mode.
[0025]
First, the first test mode will be described. In the first test mode, a test is performed to determine whether or not the control system digital circuit including the delay circuits 41, 42, 43, and 61 of the AD converter 1 operates at a specified frequency (80 MHz). In the first test mode, the test signals 11 and 12 are inputted with the test signal TEST1 at the “H” level and the test signal TEST2 at the “L” level, respectively. The clock terminal 13 and the analog input terminal 14 are fixed to, for example, the “L” level.
[0026]
Since the test signal TEST1 of “H” level is input to the control terminal 21a of the multiplexer 21, the multiplexer 21 selects the feedback signal from the inverter 62 that is input to the input terminal 21c, and outputs from the output terminal 21d. Output. The output feedback signal is sequentially delayed by the delay circuits 41, 42, 43 and then input to the delay circuit 61. The delay circuit 61 is provided to compensate for a delay time of a gate (not shown) connected to the delay circuits 41, 42, and 43 and a settling time necessary for the conversion operation. The delay circuit 61 is input to the delay circuit 61. A delay signal delayed by a delay time such as the gate is generated with respect to the signal. This delay signal is input to the inverter 62. The inverter 62 inverts the logic of the delay signal and feeds it back to the input terminal 21 c of the multiplexer 21. In this way, a free-running clock generator including the multiplexer 21, the delay circuits 41, 42, 43, 61, and the inverter 62 is configured, and a free-running clock signal CKOUT having an oscillation frequency determined by the free-running clock generator is obtained. This free-running clock signal CKOUT is output to the clock signal output terminal 16. Here, the period of the free-running clock signal CKOUT output to the clock signal output terminal 16 is measured by an LSI tester to determine whether or not the control system digital circuit operates at a specified frequency of 80 MHz. For example, when the cycle of the measured free-running clock signal CKOUT corresponds to the cycle of a clock signal having a frequency of 70 MHz, it is determined as a defective product (NG) and the test is terminated. On the other hand, if the measured period of the free-running clock signal CKOUT corresponds to the period of the clock signal having a frequency of 90 MHz, there is a margin corresponding to the frequency of 10 MHz, and therefore it is determined as a good product (GO). As described above, in the first embodiment, in the first test mode, the period of the free-running clock signal generated by the free-running clock generator including the multiplexer 21, the delay circuits 41, 42, 43, 61, and the inverter 62 is calculated as the LSI. By measuring with a tester, it is determined whether or not the control system digital circuit operates at a specified frequency of 80 MHz. Therefore, an expensive LSI tester is prepared and an input clock signal having a high frequency is externally supplied. There is no need for input, and the increase in test costs can be suppressed. Further, the self-running clock generator has a configuration in which a delay circuit 61 and an inverter 62 are added to the delay circuits 41, 42, and 43 that generate timing signals φ1, φ2, and φ3 for operating the AD conversion block 50. The circuit scale for use is small.
[0027]
If it is determined as GO in the first test mode, the process proceeds to a second test mode described below.
[0028]
In the second test mode, a test is performed to determine whether or not the analog portion of the AD conversion block 50 satisfies the specified AC characteristics.
[0029]
In the second test mode, test signals TEST 1 and TEST 2 of “L” level are input to the test terminals 11 and 12, respectively. Also, a 20 MHz test clock control signal CK is input to the clock terminal 13, and an analog signal AIN having a predetermined magnitude is input to the analog input terminal 14.
[0030]
Since the test signal TEST2 of “H” level is input to the control terminal 22a of the multiplexer 22, the oscillation signal from the VCO 33 input to the input terminal 22c is selected in the multiplexer 22 and the test is performed from the output terminal 22d. Is output as a clock signal. This test clock signal is input to the input terminal 21 b of the multiplexer 21. Since the test signal TEST1 of the “L” level is input to the control terminal 21a of the multiplexer 21, the test clock signal input to the input terminal 21b is selected and output from the output terminal 21d in the multiplexer 21. The The test clock signal output from the output terminal 21d is input to the frequency divider 32. The frequency divider 32 divides the frequency of the input test clock signal by 1/4, for example, and outputs a frequency-divided signal having a frequency obtained by dividing the frequency by 1/4. This frequency-divided signal is input to the PFD / CP 31. The PFD / CP 31 also receives a test clock control signal CK having 20 MHz from the clock terminal 13. The PFD / CP 31 compares the frequency and phase of the frequency-divided signal and the test clock control signal CK, detects an error signal of the frequency and phase, and a DC level voltage control signal corresponding to the detected error signal. Outputs VCT. This voltage control signal VCT is input to the VCO 33. The VCO 33 outputs a test clock signal having a frequency corresponding to the input voltage control signal VCT. As described above, the PFD / CP31 reflects the frequency and phase error signals of the frequency-divided signal and the test clock control signal CK in the voltage control signal VCT input to the VCO 33, so that the frequency-divided signal and the test clock are supplied. Loop to match the frequency and phase with the control signal CK. As a result, a so-called phase-locked test clock signal having a frequency of 80 MHz multiplied by (four times) the clock signal input as the test clock control signal CK is output from the VCO 33 and passes through the multiplexers 22 and 21. And input to the delay circuits 41, 42, 43. Hereinafter, as described above, the timing signals φ1, φ2, and φ3 having different phases are generated by the delay circuits 41, 42, and 43, and the input analog signal AIN is converted by the level comparator (not shown) in the AD conversion block 50. The AD conversion is performed by comparing with the multiphase timing signals φ1, φ2, and φ3, and the digital signal AOUT is output from the digital output terminal 15. By measuring this digital signal AOUT with an LSI tester, it is determined whether or not the analog portion of the AD converter 1 satisfies the prescribed AC characteristics.
[0031]
In this example, the test clock control signal CK having 20 MHz is input to the PFD / CP 31 constituting the PLL circuit 30 to generate the test clock signal having 80 MHz. However, only the VCO 33 is provided. The test clock signal having 80 MHz may be generated by inputting the voltage control signal VCT from the outside to the VCO 33. This eliminates the need for the PFD / CP 31 and the frequency divider 32 and simplifies the test circuit.
[0032]
As described above, in the first embodiment, in the second test mode, the test clock signal CK having a frequency of 80 MHz is generated by the PLL circuit 30 or the voltage control signal VCT is input from the outside to the VCO 33 to obtain 80 MHz. Since the AC characteristic of the analog unit is tested by generating a test clock signal CK having the same, it is possible to test the AC characteristic by operating the AD conversion block 50 at a high frequency of 80 MHz with a conventional LSI tester. it can. Therefore, in combination with the first test mode, it is possible to facilitate the test in the high-speed operation state of the AD conversion block 50 that performs AD conversion at a high speed while suppressing an increase in test cost.
[0033]
FIG. 2 is a circuit diagram of an AD conversion apparatus according to the second embodiment of the present invention.
[0034]
The same components as those in the AD conversion apparatus 1 shown in FIG. 1 are denoted by the same reference numerals, and different points will be described.
[0035]
The AD converter 2 shown in FIG. 2 includes a PFD (phase / frequency detection) 31_1, a CP (charge pump) 31_2, an L / F (low-pass filter) 34, and a VCO 33.
[0036]
Further, the AD converter 2 includes a timing generator 44 that generates n timing signals φ1, φ2, φ3,..., Φn having different phases.
[0037]
Further, the AD converter 2 receives an analog signal AIN and timing signals φ1, φ2, φ3,..., Φn, and the input analog signal AIN is input to the multiphase timing signals φ1, φ2, φ3 by a level comparator (not shown). .., Φn are provided, and an AD conversion block 51 comprising an analog part and a digital part is provided which outputs a digital value by performing AD conversion by comparison.
[0038]
Further, the AD converter 2 latches the m-bit digital value obtained by the AD conversion block 51 and supplies the m-bit digital data D0, D1, D2,..., Dm to the digital output terminals 15_1, 15_2, 15_3. ,..., 15_m are provided.
[0039]
Further, the AD converter 2 generates a latch timing clock signal for controlling the timing at which the timing generator 44 latches the digital data in the data latch 114, and further, the latch timing clock generated by the timing generator 114. The frequency divider 32 generates a test latch timing clock signal supplied to the data latch 114 in place of the latch timing clock signal generated by the timing generator 114 by dividing the signal by, for example, ¼. It has been. A multiplexer 113 and an OR gate 111 are also provided.
[0040]
First, the normal mode of the AD converter 2 will be described. In the normal mode, the test signals TEST 1 and TEST 2 at the “L” level are input to the test terminals 11 and 12. Further, an 80 MHz clock signal CK is input to the clock terminal 13. Further, a desired analog signal AIN is input to the analog input terminal 14.
[0041]
Since the test signal TEST2 of “L” level is input to the control terminal 22a of the multiplexer 22, the clock signal CK input to the input terminal 22b is selected and output from the output terminal 22d in the multiplexer 22. . This clock signal CK is input to the input terminal 21 c of the multiplexer 21. Since the test signal TEST1 of “L” level is input to the control terminal 21a of the multiplexer 21, the clock signal CK is output from the output terminal 21d of the multiplexer 21. This clock signal CK is input to the timing generator 44. The timing generator 44 sequentially delays the input clock signal CK to generate n multiphase timing signals φ1, φ2, φ3,..., Φn and outputs them to the AD conversion block 51. The timing generator 44 distributes the input clock signal CK to the delay circuit 61, the frequency divider 32, and the multiplexer 113 and outputs the result. The AD conversion block 51 compares the analog signal AIN input via the analog input terminal 14 by using a multi-phase timing signal φ1, φ2, φ3,. And generate an m-bit digital value. These digital values are input to the data latch 114.
[0042]
Further, since both the test signal TEST1 and the test signal TEST2 of “L” level are input to the OR gate 111, a signal of “L” level is output from the OR gate 111. This 'L' level signal is input to the control terminal 113a of the multiplexer 113. Therefore, the multiplexer 113 selects the clock signal from the timing generator 44 that is input to the input terminal 113c and outputs it from the output terminal 113d. The data latch 114 latches the digital value with this clock signal and outputs m-bit digital data D0, D1, D2,..., Dm to the digital output terminals 15_1, 15_2, 15_3,. In this way, in the normal mode, the input analog signal AIN is AD-converted at a conversion rate with a frequency of 80 MHz, and m-bit digital data D0, D1, D2,..., Dm are obtained.
[0043]
Next, the first test mode of the AD conversion apparatus 2 will be described. In the first test mode, a test is performed to determine whether or not the timing generator 44 for operating the AD conversion block 51 operates at a specified frequency (80 MHz). In the first test mode, the test signals 11 and 12 are inputted with the test signal TEST1 at the “H” level and the test signal TEST2 at the “L” level, respectively. The clock terminal 13 and the analog input terminal 14 are fixed to, for example, the “L” level.
[0044]
Since the test signal TEST1 of “H” level is input to the control terminal 21a of the multiplexer 21, the multiplexer 21 selects the feedback signal from the inverter 62 that is input to the input terminal 21b, and outputs from the output terminal 21d. Output. The output feedback signal is input to the delay circuit 61 via the timing generator 44. The delay circuit 61 is provided to compensate for a delay time of a gate or the like (not shown) connected to the timing generator 44 and a settling time necessary for the conversion operation. The delay circuit 61 receives a signal from the timing generator 44. A delay signal delayed by the delay time of the gate or the like is generated. This delay signal is input to the inverter 62. The inverter 62 inverts the logic of the delay signal and outputs it to the input terminal 21 b of the multiplexer 21. In this manner, a free-running clock generator including the multiplexer 21, the timing generator 44, the delay circuit 61, and the inverter 62 is configured, and a free-running clock signal having an oscillation frequency determined by the free-running clock generator is obtained. This free-running clock signal is input to the frequency divider 32 via the timing generator 44. The frequency divider 32 divides the frequency of the input free-running clock signal by ¼ and outputs a latch timing clock signal having a frequency obtained by dividing the frequency by ¼. The latch timing clock signal is input to the input terminal 113b of the multiplexer 113. Here, since the test signal TEST1 of “H” level is input to the control terminal 113a of the multiplexer 113 via the OR gate 111, the multiplexer 1113 receives the latch timing clock signal input to the input terminal 113b. The signal is output to the clock signal output terminal 16 via the output terminal 113d. In this way, the latch timing clock signal CKOUT having a frequency of, for example, ¼ of the frequency of the free-running clock signal by the free-running clock generator is output to the clock signal output terminal 16. The period of the latch timing clock signal CKOUT is measured with an LSI tester. As described above, in the first test mode, in determining whether the timing generator 44 for operating the AD conversion block 51 operates at the specified frequency of 80 MHz, the latch timing clock signal CKOUT having a frequency of 20 MHz is used. Just measure the period.
[0045]
Next, the second test mode will be described. In the second test mode, a test is performed as to whether or not the analog portion of the AD conversion block 51 satisfies the specified AC characteristics.
[0046]
In the second test mode, test signals TEST 1 and TEST 2 of “L” level are input to the test terminals 11 and 12, respectively. Further, a test clock control signal CK having a frequency of 20 MHz is input to the clock terminal 13, and an analog signal AIN having a predetermined magnitude is input to the analog input terminal 14.
[0047]
Since the test signal TEST2 of “H” level is input to the control terminal 22a of the multiplexer 22, the oscillation signal from the VCO 33 input to the input terminal 22c is selected in the multiplexer 22 and the test is performed from the output terminal 22d. Is output as a clock signal. This test clock signal is input to the input terminal 21 c of the multiplexer 21. Since the test signal TEST1 of the “L” level is input to the control terminal 21a of the multiplexer 21, the test clock signal input to the input terminal 21c is selected and output from the output terminal 21d in the multiplexer 21. The The test clock signal output from the output terminal 21 d is input to the frequency divider 32 via the timing generator 44. The frequency divider 32 divides the frequency of the input test clock signal by, for example, ¼, and outputs a latch timing clock signal having a frequency obtained by dividing the frequency by ¼. The latch timing clock signal is input to the input terminal 113b of the multiplexer 113. Since the TEST signal TEST2 of “H” level is input to the control terminal 113a of the multiplexer 111 via the OR gate 111, the multiplexer 113 selects and outputs the latch timing clock signal input to the input terminal 113b. Output from the terminal 113d. This latch timing clock signal is input to the PFD 31_1. A test clock control signal CK having 20 MHz is input from the clock terminal 13 to the PFD 31_1. The PFD 31_1 compares the frequency and phase of the latch timing clock signal and the test clock control signal CK, and outputs an error signal of the frequency and phase. The output error signal is input to CP31_2. CP31_2 outputs a signal having a voltage level corresponding to the input error signal. This signal is input to the L / F 34. The L / F 34 converts the input signal into a DC level voltage control signal. This voltage control signal is input to the VCO 33. The VCO 33 outputs a test clock signal having a frequency corresponding to the input voltage control signal. In this way, a test clock signal having 80 MHz is output from the VCO 33 and input to the timing generator 44 via the multiplexers 22 and 21, and the multiphase timing signals φ1, φ2, φ3,. φn is generated. Further, the AD conversion block 51 compares the input analog signal AIN with a multi-phase timing signal φ1, φ2, φ3,. Is input to the data latch 114. The data latch 114 is a latch timing clock signal from the output terminal 113d of the multiplexer 113, latches the m-bit digital value output from the AD conversion block 51, and outputs m-bit digital data signals D0, D1, D2,. Dm is output from the data digital output terminals 15_1, 15_2, 15_3,. Here, these m-bit digital data signals D0, D1, D2,..., Dm are latched at an operation rate of, for example, 1/4 of an operation rate with a frequency of 80 MHz, so-called output rate is thinned to 1/4. This is a data signal. Therefore, the AD conversion block 51 can be tested with an LSI tester having a relatively low operation rate.
[0048]
As described above, in this embodiment, it is possible to perform the performance inspection of the AD conversion blocks 50 and 51 in the high-speed operation state with an inspection apparatus (LSI tester) having an operation rate lower than the cell performance. As a result, the ability of the cell performance can be quickly known and the mass production inspection cost can be reduced.
[0049]
【The invention's effect】
As described above, according to the present invention, it is possible to easily test an AD converter that operates at a high frequency while suppressing an increase in test cost.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an AD conversion apparatus according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram of an AD conversion apparatus according to a second embodiment of the present invention.
[Explanation of symbols]
1, 2 AD converter
11,12 Test terminal
13 Clock terminal
14 Analog signal input terminal
15 Digital signal output terminal
16 Clock signal output terminal
21, 22, 113 multiplexer
21a, 22a, 113a Control terminal
21b, 21c, 22b, 22c, 113b, 113c Input terminal
21d, 22d, 113d Output terminal
30 PLL (Phase Locked Loop) Circuit
31 PFD / CP (phase / frequency detection / charge pump)
31_1 PFD (phase / frequency detection)
31_2 CP (Charge Pump)
32 divider
33 VCO (Voltage Controlled Oscillator)
34 L / F (low-pass filter)
41, 42, 43, 61 delay circuit
44 Timing Generator
50, 51 AD conversion block
62 Inverter
111 or gate
114 Data latch
15_1, 15_2, 15_3, ..., 15_m Digital output terminal

Claims (2)

An AD converter that converts an input analog signal into a digital signal and outputs the digital signal;
A data latch that latches and outputs the digital signal obtained by the AD converter;
In the normal mode, a latch timing for receiving an input clock signal from the outside, generating a timing signal for the AD converter operation based on the input clock signal, and controlling a timing at which the data latch latches a digital signal A timing generator that generates a clock signal ;
A test clock generator for receiving a test clock control signal from the outside and generating a test clock signal corresponding to the test clock control signal;
With a frequency divider ,
In test mode,
Supplying a test clock signal to the timing generator instead of the input clock signal;
A test in which the timing generator supplies a timing signal generated based on the test clock signal to the AD converter, and the latch timing clock signal generated based on the test clock signal is frequency-divided by the frequency divider. By supplying the latch timing clock signal for use to the data latch instead of the latch timing clock signal, the data latch latches and outputs the data signal obtained by thinning out the digital value obtained by the AD converter. An AD converter characterized by that. The test clock signal is input to the timing generator in the test mode, a multiplexer that forms a free-running clock generator including the timing generator in the second test mode, and a free-running clock signal generated by the free-running clock generator The AD converter according to claim 1, further comprising: an output terminal that outputs a signal obtained by frequency-dividing the signal by the frequency divider.

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