JP6734099B2 - High frequency circuit board - Google Patents

Description

The present invention relates to a high frequency circuit board.

In a circuit board on which a high frequency circuit is mounted, a technique such as a microstrip line is used as a high frequency signal transmission line. In such a high-frequency circuit board, there are circuits such as a stub circuit and a bias tee circuit that require adjustment of their electrical length in order to obtain desired characteristics.

On the other hand, the stub circuit, the bias tee circuit, and the like require a certain mounting area in order to secure the above-mentioned electrical length, which may hinder the miniaturization of the circuit board. Therefore, conventionally, for example, as a dielectric substrate used for a circuit board, a member having a high dielectric constant is used to shorten the required electrical length. For example, the conventional high-frequency circuit board shown in FIG. 10 has conductor layers 11 and 12 and a dielectric layer 21, and the conductor layer 11 is formed with a line 111, a component land 112, and a stub 113. In such a high frequency circuit board, by using a member having a high dielectric constant for the dielectric layer 21, the required electrical length of the stub 113 can be shortened and the occupied area can be reduced.

However, when a dielectric material having a high dielectric constant is used, mismatching of characteristic impedance occurs in the component land 112 and the like, which may cause signal reflection.

Therefore, in the technique disclosed in Patent Document 1, the conductor of the intermediate layer of the multilayer substrate is hollowed out to adjust the impedance so that the characteristic impedance has a desired value, thereby preventing the occurrence of reflection.

JP, 2006-74014, A

By the way, in the technique disclosed in Patent Document 1, when a high dielectric constant dielectric material is used in order to shorten the electrical length, the high dielectric constant dielectric material also has a large transmission loss (tan δ). There is a problem that signal loss becomes large in a line or the like.

The present invention has been made in view of the above points, and an object of the present invention is to provide a high-frequency circuit board capable of preventing signal reflection and signal loss.

In order to solve the above problems, the present invention is a high-frequency circuit board configured by alternately stacking a plurality of dielectric layers and a plurality of conductor layers, the plurality of dielectric layers, at least a part of The layer has a dielectric constant different from that of the other layers, and at least one conductor layer has a circuit pattern, and the layer is disposed between the conductor layer on which the circuit pattern is formed and the lowermost layer or the uppermost conductor layer. Among the one or more conductor layers, at least the conductor layer adjacent to the conductor layer having the circuit pattern in the laminating direction corresponds so as to follow a predetermined circuit pattern of the circuit patterns, and is laminated. An opening is formed in a region including the entire predetermined circuit pattern in the direction .
According to such a configuration, it is possible to prevent signal reflection and prevent signal loss.

Further, the present invention is characterized in that the predetermined circuit pattern is a circuit pattern in which an electrical length or a characteristic impedance affects a circuit characteristic.
According to such a configuration, at least the conductor layer adjacent to the conductor layer in which the specific circuit is formed has the opening portion, so that the electrical length or the characteristic impedance of these can be adjusted to a desired value.

In the present invention, a dielectric material having a low dielectric constant is used for the dielectric layer close to the conductor layer having the predetermined circuit pattern, and a dielectric constant is used for the dielectric layer far from the conductor layer having the predetermined circuit pattern. Is characterized by using a high dielectric constant.
According to such a configuration, the effective permittivity can be increased, the electrical length can be shortened, and the characteristic impedance can be lowered as compared with the case where the opening is not provided.

Further, the present invention is characterized in that the predetermined circuit pattern is a stub circuit.
According to such a configuration, the electrical length of the stub circuit can be shortened by providing the opening.

Further, the invention is characterized in that the predetermined circuit pattern is a bias tee circuit.
According to such a configuration, the electrical length of the bias tee circuit can be shortened by providing the opening.

Also, in the present invention, the predetermined circuit pattern is formed on the uppermost conductor layer, the lowermost conductor layer is a ground layer, and the first dielectric layer adjacent to the uppermost conductor layer is formed. Is a dielectric having a low dielectric constant, and a dielectric layer located below the first dielectric layer is a dielectric having a higher dielectric constant than the first dielectric layer. An opening is formed in a region of the conductor layer arranged between the lowermost conductor layer and the uppermost conductor layer, the region corresponding to the predetermined circuit pattern.
According to such a configuration, by providing the opening in the conductor layer located below the predetermined circuit pattern, the electrical length of the predetermined circuit pattern can be shortened and the circuit scale can be reduced.

Further, according to the present invention, some of the circuit elements forming the predetermined circuit pattern are dispersedly arranged in conductor layers of different layers, and the circuit elements arranged in a dispersed manner are connected by through holes. It is characterized by
According to such a configuration, the circuit scale can be further reduced by disposing a part of the circuit elements in different conductor layers.

According to the present invention, it is possible to provide a high-frequency circuit board capable of preventing signal reflection and signal loss.

It is sectional drawing which shows the structural example of the high frequency circuit board which concerns on embodiment of this invention. It is a figure which shows the state which replaced the dielectric material layer shown in FIG. 1 with the dielectric material with the same dielectric constant. It is a figure which shows the structure for simulation of embodiment of this invention. This is a configuration example in which an opening is not provided in the lower layer of the stub circuit. It is a figure which shows the simulation result of FIG. This is a configuration example in the case where an opening is provided in the lower layer of the stub circuit. It is a figure which shows the simulation result of FIG. It is a figure which shows the other application target of this invention. It is a figure which shows the other application target of this invention. It is a figure which shows the structure of the conventional high frequency circuit board.

Next, an embodiment of the present invention will be described.

(A) Description of Embodiments of the Present Invention FIG. 1 is a cross-sectional view showing a configuration example of a high-frequency circuit board according to an embodiment of the present invention. In the example shown in FIG. 1, the high frequency circuit board 1 is configured by alternately laminating the conductor layers 11 to 14 and the dielectric layers 21 to 23.

Here, the conductor layers 11 to 14 are made of, for example, a member having a high electric conductivity such as copper. The dielectric layers 21, 22, and 23 are made of dielectric materials having relative permittivities of ε ₁ , ε ₂ , and ε ₃ , respectively. The relationship of ε ₁ <ε ₂ , ε ₃ is established between the relative permittivities ε ₁ , ε ₂ , ε ₃ . The relationship between the relative permittivity ε ₂ and ε ₃ can be, for example, ε ₂ =ε ₃ or ε ₂ <ε ₃ .

On the uppermost conductor layer 11, a line 111 whose characteristic impedance is set to 50Ω, a component land 112 for arranging chip components and the like, and a stub 113 as a distributed constant line are formed. The region of the conductor layer 12 that faces the line 111, the region of the conductor layer 13 that faces the component land 112, and the lower conductor layer 14 are ground layers. Further, an opening 120 is provided in a region of the conductor layer 12 corresponding to the component land 112 and the stub 113. Further, an opening 130 is provided in a region of the conductor layer 13 corresponding to the stub 113.

By the way, the electric length λ can be calculated by the following formula (1), where λ ₀ is the electric length in vacuum and ε _eff is the effective dielectric constant. That is, the larger the value of the effective dielectric constant ε _eff , the shorter the electrical length. Note that SQRT() is a function that calculates the square root in parentheses.

λ=λ ₀ /SQRT(ε _eff ) (1)

2 is a comparative example for explaining the effect of the present embodiment. In FIG. 2, as the dielectric layers 21 to 23, dielectrics having the same relative dielectric constant are used. Therefore, the effective permittivity ε _eff of each portion of the line 111, the component land 112, and the stub 113 is substantially the same except that the thickness of the dielectric layer is slightly affected, and the electrical lengths of the respective portions are also substantially equal. Therefore, as described above, it is not possible to individually design the electrical length according to the circuit pattern of each part. By comparison with the example of FIG. 2, in the present embodiment shown in FIG. 1, by using dielectric layers having different permittivities and arranging the openings under a predetermined circuit, the electrical length for each circuit pattern is increased. Since it is possible to change, it is possible to perform the optimum design according to the circuit pattern.

Next, a simulation result by the computer of the embodiment shown in FIG. 1 will be described. FIG. 3 shows a sectional view of a circuit pattern for simulation of the stub 113 shown in FIG. In this example, a stub 113 is formed on the conductor layer 11. Further, it is assumed that the air layer 20 exists above the conductor layer 11. Further, the conductor layers 11 to 14 are electrically connected to each other by the through holes 50. In addition, openings 120 and 130 are formed in regions corresponding to the stubs 113 of the intermediate conductor layers 12 and 13 sandwiched between the uppermost conductor layer 11 and the lowermost conductor layer 14. The dielectric layer 21 is made of Teflon (registered trademark) having a thickness of 0.508 mm, and the dielectric layers 22 and 23 are made of alumina having a thickness of 0.508 mm. The dielectric constant of the dielectric layer 21 is about 2, and tan δ is about 0.0002. The dielectric constants of the dielectric layers 22 and 23 are about 10, and tan δ is about 0.007.

FIG. 4 shows a more detailed configuration of the circuit used in the simulation. Note that FIG. 4 shows a configuration example in which the opening is not provided. FIG. 4A shows a plan view, and FIG. 4B shows a cross section of an arrow AA. In the example of FIG. 4A, the stub 113 extends from the line 111 toward the upper side of the figure. Further, the ground patterns 114 are arranged on both sides of the stub 113, and the ground patterns 114 are also arranged below the line 111. Further, in the example of FIG. 4, the left side of the figure is a port 1 to which a signal is input, and the right side is a port 2 to which a signal is output. Further, as shown in FIG. 4B, in this example, the conductor layers 12 and 13 below the stub 113 are not provided with openings.

FIG. 5 shows a simulation result of the circuit shown in FIG. As shown in FIG. 5, the circuit shown in FIG. 4 has band stop characteristics, and the gain at the frequency of 4.274 GHz, which is the stop band, is −39.306.

FIG. 6 shows a configuration example in which an opening is provided in the circuit shown in FIG. That is, as shown in FIG. 6B, openings 120 and 130 are provided in the conductor layers 12 and 13. FIG. 7 shows the simulation result of FIG. As shown in FIG. 7, the circuit shown in FIG. 6 has band stop characteristics, and the gain at the stop band frequency of 4.335 GHz is −35.438. Therefore, the circuit shown in FIG. Have In the example of FIG. 4, the vertical length of the stub 113 is about 12 mm, but in the example of FIG. 6 having substantially the same characteristics, the vertical length of the stub 113 is about 9.9 mm, about 20 mm. The length is shortened by about %. That is, in order to obtain substantially the same characteristics, the length of the stub is 12 mm in FIG. 4, whereas the length of the stub is as short as 9.9 mm in FIG. 6 to which the present invention is applied. From this, the effect of the present invention was clarified.

As described above, in the embodiment of the present invention, the dielectric layers having different dielectric constants and the conductor layers are alternately laminated, and the lower conductor layer is formed in accordance with the circuit pattern formed on the conductor layer. Since the opening is provided, the electrical length and the characteristic impedance can be adjusted for each circuit. Therefore, for example, in the stub circuit, by providing the opening, the electrical length can be shortened to reduce the circuit scale, and by not providing the opening in the line, the loss can be reduced.

(D) Description of Modified Embodiments It goes without saying that the above-described embodiments are merely examples, and the present invention is not limited to the above-described cases. For example, in the above embodiment, the stub 113 shown in FIG. 6 is described as an example, but the present invention can also be applied to the stub group used in the class F amplifier shown in FIG. 8, for example. That is, in FIG. 8, the length of each stub constituting the stub group is set to be a quarter wavelength of the harmonic. The impedance of each stub viewed from the point A in FIG. 8 is zero. By setting the length of the transmission line L1 to ¼ wavelength of the fundamental wave, the impedance of the matching circuit shown in FIG. 8 is 0 for even-order harmonic impedance and infinite for odd-order harmonic impedance. By arranging the matching circuit shown in FIG. 8 instead of the stub 113 shown in FIG. 1 and providing openings 120 and 130 in the lower conductor layers 12 and 13, the length of each stub can be shortened. it can. It should be noted that not all the stubs shown in FIG. 8 may be arranged in different conductor layers instead of being arranged in the same conductor layer and connected by through holes. According to such a method, the circuit scale can be further reduced by disposing the stubs in a distributed manner with respect to the vacant conductor layer. That is, instead of arranging all the circuit elements (each stub in FIG. 8) forming a predetermined circuit pattern (stub group in FIG. 8) in the same conductor layer, the circuit elements are dispersed and arranged in different conductor layers. The circuit scale can be further reduced.

The present invention can also be applied to the bias tee circuit shown in FIG. The example of FIG. 9 includes an amplifier 201, a bias tee circuit 202, and a capacitor 203. In this example, the impedance of the bias tee circuit 202 becomes infinite with respect to the AC signal output from the amplifier 201, and the impedance becomes 0 with respect to Vbias that is a DC voltage, so that the bias circuit side is not affected. In addition, a bias voltage can be applied to the amplifier 201. The bias tee circuit shown in FIG. 9 is arranged, for example, in place of the stub 113 shown in FIG. 1 and the openings 120 and 130 are provided in the lower conductor layers 12 and 13, thereby shortening the length of the bias tee circuit 202. can do.

Further, in the above embodiment, the three dielectric layers 21 to 23 and the four conductor layers 11 to 14 are provided, but the number of layers other than this may be used. For example, it may have two dielectric layers and three conductor layers, or may have four or more dielectric layers and five or more conductor layers.

Further, in the above embodiment, the circuit pattern is arranged on the uppermost conductor layer 11, but it may be arranged on the intermediate conductor layer. Of course, the same applies when the above-described four or more dielectric layers and five or more conductor layers are provided.

Further, in the above embodiments, the dielectric layers 21 to 23 have the same dielectric constant as the dielectric layers 22 and 23, but the dielectric layer 23 has a larger dielectric constant than the dielectric layer 22. You may have.

Further, in the above embodiment, the openings 120 and 130 are provided in the conductor layers 12 and 13 arranged below the stub 113. However, for example, the openings 120 may be provided only in the conductor layer 12. Good.

Further, in the above embodiments, only the electrical length has been described, but the characteristic impedance can also be changed by changing the effective dielectric constant. Therefore, for example, the characteristic impedance may be set to a desired value by providing or not providing the opening.

Further, the electrical length and the characteristic impedance may be adjusted by adjusting the areas of the openings 120 and 130. That is, by adjusting the area of at least one of the openings 120 and 130 formed in the conductor layers 12 and 13 arranged below the stub 113, the electrical length and the characteristic impedance are adjusted to desired values. You may

1 High Frequency Circuit Board 11-14 Conductor Layers 21-23 Dielectric Layer 50 Through Hole 111 Line 112 Component Land 113 Stub 114 Ground Pattern 120, 130 Opening 201 Amplifier 202 Bias Tee Circuit 203 Capacitor

Claims (7)

In a high frequency circuit board configured by alternately laminating a plurality of dielectric layers and a plurality of conductor layers,
At least a part of the plurality of dielectric layers has a different dielectric constant from other layers, and at least one conductor layer has a circuit pattern,
Of the one or more conductor layers arranged between the conductor layer on which the circuit pattern is formed and the lowermost or uppermost conductor layer, at least adjacent to the conductor layer having the circuit pattern in the stacking direction. The conductor layer to correspond to along a predetermined circuit pattern of the circuit pattern, and has an opening in a region including the entire predetermined circuit pattern in the stacking direction ,
A high frequency circuit board characterized by the above. The high-frequency circuit board according to claim 1, wherein the predetermined circuit pattern is a circuit pattern in which an electrical length or a characteristic impedance affects a circuit characteristic. A dielectric having a low dielectric constant is used for the dielectric layer close to the conductor layer having the predetermined circuit pattern, and a dielectric having a high dielectric constant is used for the dielectric layer far from the conductor layer having the predetermined circuit pattern. The high-frequency circuit board according to claim 2, wherein the high-frequency circuit board is provided. The high-frequency circuit board according to claim 2 or 3, wherein the predetermined circuit pattern is a stub circuit. The high frequency circuit board according to claim 2 or 3, wherein the predetermined circuit pattern is a bias tee circuit. The predetermined circuit pattern is formed on the uppermost conductor layer, the lowermost conductor layer is a ground layer, and the first dielectric layer adjacent to the uppermost conductor layer has a low dielectric constant. A body having a higher dielectric constant than that of the first dielectric layer is used as the dielectric layer located below the first dielectric layer, and a dielectric layer having a dielectric constant higher than that of the first dielectric layer is used. 6. An opening is formed in a region corresponding to the predetermined circuit pattern formed on the uppermost conductor layer of the conductor layer disposed between the openings. The high frequency circuit board according to item 1. A part of the circuit elements forming the predetermined circuit pattern are dispersedly arranged in conductor layers of different layers, and the circuit elements arranged in a dispersed manner are connected by through holes. The high frequency circuit board according to any one of items 1 to 5.

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