JP6723613B2 - Image processing system, game machine - Google Patents

Description

The present invention relates to an image processing system for displaying an image drawn using data on a plurality of display means, and a gaming machine using such an image processing system.

With the development of image display technology, an image processing system that forms an image to be displayed on this image display device is used in various fields and various devices together with an image display device such as a display. Conventionally, many image processing systems have been proposed which store compression-encoded data of a moving image obtained by a compression algorithm such as MPEG, decode it, and display it on an image display device such as a liquid crystal display. In recent years, for example, in a gaming machine such as a game machine or a pachinko machine, a plurality of displays (display means) are used for one device, and a display effect is enhanced by displaying a moving image or a still image on each display. Things are also increasing.

Further, in recent years, as the resolution of images has increased, the volume of image information has increased, and there is an increasing need to process a large amount of compression-coded data during image processing and image formation. As means for responding to such a need, conventionally, an inexpensive and large-capacity memory such as a NAND flash memory is used outside an integrated circuit for image processing to perform image processing, and a formed image is displayed on a display device. There is known a technique for displaying an image on the screen (for example, see Patent Document 1). Further, conventionally, in an image processor having an external memory and an on-chip memory, whether the judging means should write the series of data read from the predetermined address range of the external storage device by the data processing means into the internal storage means. If it is determined whether or not to write, the data determined to be written is written in the internal storage means, and when the data processing means reads the data in the same address range of the external storage device again, the data is read from the internal storage means instead. An invention is known in which image processing is performed in (see, for example, Patent Document 2).

JP, 2011-147815, A JP 2005-18428 A

Here, in order to process a large amount of compression-coded data, it is necessary to increase the capacity of the memory and speed up the reading and writing of the memory. On the other hand, however, if the memory capacity and speed are increased, the manufacturing cost of the image processing system will increase. This problem becomes more remarkable in an environment in which a plurality of displays are provided in one device and more image information is processed.

However, in Patent Document 1 described above, the number of external memories and the number of wirings connected to the external memories must be increased as the number of parallel processes in image processing or the number of parallel processes increases, so that the number of displays increases. If the parallel processing or the amount of data to be processed in parallel increases, the manufacturing cost of the image processing system increases, and there is a problem that a large amount of data or high speed processing is practically limited.

Further, in the above-mentioned Patent Document 2, although specific data can be stored in the internal storage means on the basis of the address from which the data is read out, the processing procedure itself in the image processing is based on the use of a memory similar to the conventional one. Therefore, there is a problem in that a large amount of data used in a plurality of displays or high-speed processing cannot be performed.

The present invention has been made in view of the above problems, and when simultaneously displaying images on a plurality of screens, image formation and image display can be performed at high speed, and an increase in manufacturing cost can be suppressed. , And to provide a game machine using such an image processing system.

In order to solve such a problem, the invention according to claim 1 is an image processing system for displaying an image on a plurality of display means, and an image forming means for forming an image to be displayed on the display means, A first storage unit used as a drawing region for drawing an image displayed on at least one of the plurality of display units by the image forming unit to generate image data; and the image forming unit. A plurality of second storage means for storing the image data generated in the first storage means, which are formed in a quantity corresponding to the quantity of the display means, and the image data from the second storage means. A plurality of image display circuits that are provided corresponding to the respective display means and that are acquired and displayed on the respective display means; and between the first storage means and the second storage means. And a transmission/reception unit for transmitting/receiving image data and transmitting/receiving the image data between the second storage unit and the image display circuit, the first storage unit and the plurality of image displays. The circuits are respectively provided in the main body of the image processing apparatus for generating and displaying the image data, and the main body of the image processing apparatus is connected to the external communication means constituting the transmitting/receiving means, and the external communication means. Is connected to the second storage means, the first storage means has a higher access speed to the recorded data than the second storage means, the second storage means, The data storage capacity is configured to be larger than that of the first storage means, and the image forming means stores the image data generated in the first storage means from the image processing apparatus main body portion to the second storage means. The image data stored in the second storage means to the image processing apparatus main body, and the moved image data is displayed in the image display. It is characterized in that it is supplied to a circuit and an image based on the image data is displayed on the display means.

According to a second aspect of the present invention, in addition to the configuration according to the first aspect, one frame in which the drawing area of the first storage unit is displayed in a display unit having a maximum total number of pixels The data amount of one frame displayed on all the display means is less than the total amount of data of one frame displayed on all the display means, and the second storage means stores the data amount of one frame displayed on all the display means. Is formed to have a capacity not less than the total of the above.

According to a third aspect of the present invention, in addition to the configuration according to the first or second aspect, the second storage means has at least twice the total amount of data of one frame displayed by all the display means. In addition to being formed in a capacity, it is configured to temporarily store the generated image by storing the generated image and transmit the stored image to the image display circuit by a configuration of two or more buffers. It is characterized.

According to a fourth aspect of the present invention, in addition to the configuration according to any one of the first to third aspects, the first bandwidth of data transmission between the image forming unit and the first storage unit is The second bandwidth for data transmission between the image display circuit and the second storage means is configured to have the relationship of the following expression (1).
Number of layers+1.5≦first bandwidth/second bandwidth≦number of layers×2+2.5 (1)
According to a fifth aspect of the present invention, in addition to the configuration according to any one of the first to fourth aspects, the first storage unit and the second storage unit are each formed of a RAM. Is characterized by.

The invention according to claim 6 is a game machine, comprising a plurality of display means, and using the image processing system according to any one of claims 1 to 5.

According to the first aspect of the present invention, the first storage means includes a drawing area for the drawing means to draw an image displayed on at least one of the plurality of display means to generate image data. The second storage means is configured such that the drawing means stores the image data generated in the first storage means. Temporary storage of the generated image data can be simultaneously performed in the first storage means and the second storage means in parallel. Further, a transmission/reception means for transmitting/receiving image data between the first storage means and the second storage means and transmitting/receiving image data between the second storage means and the image display circuit are provided. The image processing apparatus main body is connected to an external communication unit that constitutes a transmission/reception unit, a second storage unit is connected to the external communication unit, and the first storage unit is the second storage unit. Access speed to the recorded data is higher than that of the first storage means, and the second storage means is configured to have a larger data storage capacity than the first storage means. The image data of the image to be displayed by the display means is generated at high speed and sent to the second storage means, and the image data to be displayed on each display means is stored and temporarily stored in the second storage means. can do. Moreover, it is possible to prevent the capacity of the first storage means from becoming excessive by limiting the processing performed in the first storage means to only the minimum processing that requires high processing speed in the generation of image data. Further, by temporarily storing the image data to be displayed on the display means by the second storage means having a larger capacity than the first storage means, a still image or a moving image that does not cause visual discomfort can be displayed on each display means. Can be displayed. As a result, it is possible to provide an image processing system capable of performing image formation and image display at high speed and suppressing an increase in manufacturing cost when simultaneously displaying images on a plurality of screens.

According to the second aspect of the present invention, the drawing area of the first storage means is displayed on all the display means with a data amount of one frame or more displayed on the display means having the maximum total number of pixels. Since it is formed with a capacity equal to or less than the total amount of data of one frame, the first storage means can generate image data to be displayed on all display means at high speed and send it to the second storage means. Can be configured as required capacity. Further, since the second storage means is formed to have a capacity equal to or larger than the total amount of data of one frame displayed by all the display means, the second storage means is displayed on each display means. The image data of can be configured as a capacity required for temporarily storing each display unit. As a result, it is possible to provide an image processing system capable of performing image formation and image display at high speed and suppressing an increase in manufacturing cost when simultaneously displaying images on a plurality of screens.

According to the invention described in claim 3, in the second storage means, the temporary storage of the image by the structure of two or more buffers and the transmission of the formed image to the image display circuit are continuously and at high speed. It will be possible to do. As a result, it is possible to provide an image processing system capable of performing image formation and image display at high speed and suppressing an increase in manufacturing cost when simultaneously displaying images on a plurality of screens.

According to the invention described in claim 4, the value obtained as a result of performing the predetermined calculation with the first bandwidth and the second bandwidth is defined by the relationship with the predetermined value based on the number of layers. By doing so, when the configuration of the image data using the first storage means and the temporary storage of the image data using the second storage means and the transmission to the image display circuit are performed, the first storage means The data transmission from the second storage means to the second storage means and the data transmission from the second storage means to the image display circuit can be performed continuously and concurrently. As a result, it is possible to provide an image processing system capable of performing image formation and image display at high speed and suppressing an increase in manufacturing cost when simultaneously displaying images on a plurality of screens.

According to the invention described in claim 5, a plurality of screens are provided by using RAMs capable of reading and writing data and randomly accessing recorded data respectively for the first storage means and the second storage means. It is possible to configure an image processing system capable of performing image formation and image display at high speed when simultaneously displaying images on the screen, and suppressing a rise in manufacturing cost.

According to the invention described in claim 6, when the images are simultaneously displayed on a plurality of screens by using the image processing system of the present invention, the image formation and the image display can be performed at high speed, and the manufacturing cost can be reduced. It is possible to provide a gaming machine capable of suppressing soaring.

It is a figure which shows the whole structure of the image processing system and game machine which concern on embodiment of this invention. It is a figure which shows typically the processing content in an internal memory and external memory of an image processing system same as the above. FIG. 3 is a diagram showing, for each layer of image data, a relationship between read/write speeds of an external memory and an internal memory for appropriately performing processing in the image processing system. It is a flow chart which shows a processing procedure of an image processing system same as the above. It is a figure which shows the processing procedure of an image processing system same as the above typically.

1 to 5 show an embodiment of the present invention.

[Basic configuration]
FIG. 1 is a block diagram showing an overall configuration of an image processing system and a gaming machine according to this embodiment.

The image processing system 1A shown in FIG. 1 is incorporated in a gaming machine 100 such as a pachinko machine or a pachi-slot machine, and forms an image displayed on a plurality of display units 6 ₀ , 6 ₁ ,... 6 _n of the gaming machine 100. Used for. The image processing system 1A is arranged in the housing of the gaming machine 100.

An image processing system 1A of this embodiment shown in FIG. 1 includes an image processing device 1, a first auxiliary storage device 2, a second auxiliary storage device 3, and an external device as a "second storage means". The memory 4 and a plurality of display units 6 ₀ , 6 ₁ ,... 6 _n are provided. The first auxiliary storage device 2, the second auxiliary storage device 3, and the external memory 4 are bus-connected to an external data bus 5 as "transmission/reception means", and image processing is performed via the external data bus 5. It is connected to the device 1.

The image processing apparatus 1 of the image processing system 1A is, for example, a GPU (Graphics Processing Unit), and is a unit including various configurations for performing image processing and image drawing in a computer device or a computer unit. In this embodiment, the image processing apparatus 1 based on various programs and data to form a plurality of images (still image, any video including), displays each image forming section 6 _0, 6 ₁ ,... 6 _n are displayed.

The image processing apparatus 1 includes a control unit 7, a drawing unit 8, a transfer unit 9, an internal memory 10 as a “first storage unit”, a display circuit unit 11, and a communication interface (I/F) unit 12, and these The configuration is bus-connected to an internal data bus 13 as "transmission/reception means". The display circuit unit 11 is provided with the same number of image display circuits 14 ₀ , 14 ₁ ,... 14 _{n as} the display units 6 ₀ , 6 ₁ ,... 6 _n .

The control unit 7 is, for example, a CPU (Central Processing Unit), and integrally controls transmission and reception of signals and data of the entire image processing apparatus 1, and signal processing and data processing. Specifically, for example, a program of control information is read from the first auxiliary storage device 2, each component such as the drawing unit 8 and the transfer unit 9 of the image processing system 1A is controlled based on this program, and the game is played. The command generation for forming the image data requested by the upper control unit of the machine 100 in the image processing system 1A is performed.

The drawing unit 8 performs various processes necessary for image processing and image drawing. In this embodiment, the drawing unit 8 is supplied from the control unit 7 (based on a display list (not shown) for the control unit 7 to form an image requested by the upper control unit of the gaming machine 100). Te, by performing the graphic drawing, etc., each layer constituting each of the display section 6 _0, 6 _1, one frame of the predetermined unit (e.g., video constituting the image displayed on · · · 6 _n (hierarchy) ), the drawing data (hereinafter simply referred to as “layer data”, which is the same in the present specification) forming the image data for each image, and the display units 6 ₀ , 6 ₁ , The process of generating image data (hereinafter simply referred to as “image data”; the same in this specification) as an image displayed on 6 _n is performed.

Specifically, for example, the drawing unit 8 uses the internal memory 10 as a work area, and the image content data read from the second auxiliary storage device 3 and necessary for image formation (for example, compressed by a compression CODEC such as MPEG). Data) is used to perform a predetermined drawing process, and individual layer data and image data are generated as a result of the drawing process (see FIG. 2; details will be described later).

Under the control of the control unit 7, the transfer unit 9 transfers the image data recorded in the frame buffer 110 of the internal memory 10 to the external memory 4 and temporarily stores the image data. Specifically, for example, the transfer unit 9 reads out and takes in the image data stored in the frame buffer 110 of the internal memory 10 under the control of the control unit 7, and stores the taken-in image data in any one of the external memories 4. stored is written in the area (for example, ₀ the first region 161 of the storage areas 16 _0). As a result, the image data is temporarily stored in the external memory 4 (details will be described later).

The internal memory 10 is a storage unit such as an eDRAM (embedded DRAM) or an SRAM (Static Random Access Memory) capable of high-speed access to recorded data. The internal memory 10 is used as a work area for drawing processing in the drawing unit 8 (see FIG. 2; details will be described later), and stores a frame buffer 110 as a “drawing area” for storing image data and layer data. It has a layer data storage unit 120.

Capacity of the frame buffer 110 in the internal memory 10, and the capacity of the external memory 4, a plurality of display portions 6 _0, 6 _1, is set based on the data amount of an image to be displayed at a time · · · 6 _n ( See FIG. 3. Details will be described later.).

Display circuit unit 11, and an image display circuit _{14 0, 14 1, ··· 14} n acquires the image data stored in the external memory 4, a display section _{6 0,} 6 1, the · · · _{6 n} Various types of processing are performed for converting into a displayable data format and transmitting various images to the display units 6 ₀ , 6 ₁ ,... 6 _n for display. Specifically, the display circuit unit 11 reads the image data recorded in the external memory 4 and sends it to the image display circuits 14 ₀ , 14 ₁ ,... 14 _n . The image display circuits 14 ₀ , 14 ₁ ,... 14 _n convert the acquired image data into data that can be displayed on the display units 6 ₀ , 6 ₁ ,... 6 _n , and the data transmission unit 15 _0. , ₁₅ 1, ... 15 display unit ₆ through the _{n 0,} 6 1, and sent to ... _{6 n,} the display section _{6 0,} 6 1, is an image displayed on ... _{6 n.}

The communication interface unit 12 performs various processes necessary for transmitting and receiving data inside and outside the image processing apparatus 1 (for example, conversion of data itself, conversion of address information for transmission and reception).

The internal data bus 13 constitutes a transmission/reception path for data and signals between the respective components inside the image processing apparatus 1. It is desirable that the internal data bus 13 be configured so that it can simultaneously transmit and receive a plurality of data and signals in parallel.

The first auxiliary storage device 2 is, for example, various ROMs, and is connected to the image processing device 1 by an external data bus 5 and an internal data bus 13. The first auxiliary storage device 2 stores a program for controlling each component of the image processing system 1A such as the drawing unit 8 and the transfer unit 9 and the like.

The second auxiliary storage device 3 is also various storage devices, for example, and is connected to the image processing device 1 by the external data bus 5 and the internal data bus 13. In the second auxiliary storage device 3, various content data used for drawing an image on the display units 6 ₀ , 6 ₁ ,... 6 _n and forming an image are recorded. Specifically, the second auxiliary storage device 3 is an SSD (Solid State Device), and compressed data for generating image data by the processing of the drawing unit 8 compressed by a compression CODEC such as MPEG is recorded. ing.

The external memory 4 is various types of RAM, and the image data that has undergone drawing processing in the frame buffer 110 of the internal memory 10 is transferred and recorded. The external memory 4 has a slower access speed to the recorded data than the internal memory 10, but it is possible to use SDRAM (Synchronous DRAM) or GDDR (Graphics DDR) which can be formed with a larger storage capacity than the internal memory 10.

As described above, the external memory 4 stores image data for each frame displayed on the display units 6 ₀ , 6 ₁ ,... 6 _n . Specifically, the external memory 4 has a plurality of storage areas 16 ₀ , 16 ₁ ,... 16 _n , for example, the same number as the number of the display sections 6 ₀ , 6 ₁ ,... 6 _n (that is, n+1). Has been formed. Further, each storage area is divided into two to form a first area 161 ₀ , 161 ₁ ,... 161 _n and a second area 162 ₀ , 162 ₁ ,... 162 _n , and double buffering ( in the two storage areas, it is temporarily stored in the image data generated in the internal memory 10 in one storage area for example the first region 161 ₀ is stored, is stored from the other storage areas for example second regions 162 ₀ The process of alternately repeating the state in which the transfer of the image data is performed) is performed. In this embodiment, the storage area is the double buffering that uses the first area and the second area. However, the present invention is not limited to this, and a multi-buffer configuration in which two or more areas are configured. If it is good.

The storage capacity of the external memory 4 is set based on the data amount of the image displayed at one time on the plurality of display units 6 ₀ , 6 ₁ ,... 6 _n (see FIG. 3; details will be described later). ..

The external data bus 5 connects the respective components outside the image processing apparatus 1 in a state capable of mutually transmitting and receiving data and signals to form a data and signal transmission/reception path. It is desirable to configure so that a plurality of data and signals can be simultaneously transmitted/received in parallel.

The bus width of the internal data bus can be set to several thousand bits, whereas the bus width used as a connection interface for external devices such as PCI is 64 bits, and when driven at the same frequency, It is common that the transmission speed is about several hundredths to several tens of minutes. Internal data bus 13 and the bandwidth of the external data bus 5 (communication speed), and capacity of the frame buffer 110 of the internal memory 10, the capacity of the external memory 4, i.e., a plurality of display portions _{6 0,} 6 1, ... It is set based on the amount of image data to be displayed at once in 6 _n (details will be described later).

[Processing in internal memory and transfer to external memory by drawing unit]
FIG. 2 schematically shows the processing in the internal memory 10 by the drawing unit 8 and the transfer processing to the external memory 4 in the image processing system 1A of this embodiment.

As shown in FIG. 2, in this embodiment, the drawing unit 8, layer data storage section 120 of the internal memory 10, a frame buffer 110 by using a work area, each of the display section _{6 0, 6} 1, ... Generate image data for each frame to be displayed at 6 _n .

Specifically, the drawing unit 8 uses the image content data (for example, data compressed by a compression CODEC such as MPEG) read from the second auxiliary storage device 3 (see FIG. 1) and necessary for image formation. Perform predetermined drawing processing.

For example, as shown in FIG. 2, in the case of an image in which a background, a person, and a smoke effect are present, first, the data regarding the background layer is read from the second auxiliary storage device 3, decoded by the drawing unit 8, and the result is obtained. Certain background layer data is stored in the layer data storage unit 120 of the internal memory 10. Thereafter, the drawing unit 8 stores the background layer data stored in the layer data storage unit 120 of the internal memory 10 and the image data stored in the frame buffer 110 (whether the data in the frame buffer is empty when the background layer is created, Or (a single color) is read, the image of the background layer is superimposed on the image data in the frame buffer 110, and the image data (A) as the drawing result is stored in the frame buffer 110 of the internal memory 10.

Next, the data regarding the symbol layer is read from the second auxiliary storage device 3, decoded by the drawing unit 8, and the resulting symbol layer data is stored in the layer data storage unit 120 of the internal memory 10. After that, the symbol layer data stored in the layer data storage unit 120 and the image data (A) stored in the frame buffer 110 are read, and the image data (A) and the symbol layer data are drawn and drawn. The resulting image (B) is stored in the frame buffer 110 of the internal memory 10.

Further, the data regarding the effect layer is read from the second auxiliary storage device 3, decoded by the drawing unit 8, and the resulting effect layer data is stored in the layer data storage unit 120 of the internal memory 10. After that, the effect layer data stored in the layer data storage unit 120 and the image data (B) stored in the frame buffer 110 are read, and the image data (B) and the effect layer data are superimposed and drawn, The resulting image (C) is stored in the frame buffer 110 of the internal memory 10.

When the image of all the layers are combined with the image data of the frame buffer 110, image data is first region e.g. a first storage area for example storage region 16 ₀ of the external memory 4 via the communication interface unit 12 from the frame buffer 110 regions 161 _0, or the second region for example second regions 162 _0, is transferred to either one of the (e.g. ₀ first region 161) and stored (see FIG. 2). At that time, the image data drawn in the previous frame is stored in the other area (for example, the second area 162 ₀ ) of the external memory 4 (see FIG. 2). The display circuit unit 11 reads the image data from the other side of the area, and displays the corresponding specific display example, the display unit 6 _0.

In FIG. 2, but describes only the processing of the first region 161 ₀ of the one storage area 16 ₀ of the external memory 4 and the second region 162 _0, other storage area ₁₆ 1, ... The same processing is performed in the 16 _n first areas 161 ₁ ,... 161 _n and the second areas 162 ₁ ,... 162 _n . Then, as a result of the processing, the image data is displayed on the corresponding display units 6 ₁ ,... 6 _n .

Generates individual image data performs a drawing process in a high-speed internal memory 10 of the reading, the display section _{6 0,} 6 1, the number of storage areas ₁₆ corresponding to the · · · _{6 n 0,} 16 1, · · · 16 By storing the image data for each frame in the external memory 4 having _n , the individual image data is generated at high speed, and the image data is used to display the individual display units 6 ₀ , 6 ₁ ,... 6 _n can be displayed. That is, generation of individual image data by drawing processing and generation of image data for each frame using the image data are performed as continuous processing to speed up the processing of generating image data, Smooth video playback can be realized.

[Assumptions for setting memory capacity and transfer speed]
For example, the gaming machine 100 is provided with five display units 6 ₀ , 6 ₁ ,... 6 ₄ and the respective display units 6 ₀ , 6 ₁ ,... 6 ₄ are shown in the following <Table 1>. Consider the case of specs.

この場合、従来技術においては、全ての表示部６_０，６_１，・・・６_４における処理を高速化するためには、内部メモリ１０のフレームバッファ１１０の容量は、表示部６_０，６_１，・・・６_４の必要メモリ容量の合計以上の大きさ、例えば５５０Ｍｂが必要とされる。すなわち、描画部が描画する全ての画像データをフレームバッファ１１０に記憶しておき、それを表示回路で表示するためである。 <Table 1>

In this case, in the conventional technique, in order to speed up the processing in all the display units 6 ₀ , 6 ₁ ,... 6 ₄ , the capacity of the frame buffer 110 of the internal memory 10 is set to the display units 6 ₀ , 6 6. _1, greater than or equal to the sum of the size of the required memory capacity.. _{6 4,} for example, 550Mb are required. That is, this is for storing all the image data drawn by the drawing unit in the frame buffer 110 and displaying it on the display circuit.

However, as described above, the internal memory 10 is expensive, and an increase in the memory capacity of the internal memory 10 leads to a cost increase.

On the other hand, considering that the images are displayed on the plurality of display units 6 ₀ , 6 ₁ ,... 6 ₄ , the external memory 4 having a low access speed is used to draw the image with the minimum internal memory. However, it is desirable that the external memory capacity is secured and the drawing processing is performed with the internal memory capacity on the premise of displaying on a plurality of display units 6 ₀ , 6 ₁ ,... 6 ₄ . Previously, no consideration was given to the point.

Therefore, in the present embodiment, as described above, when the image data is generated using the internal memory 10 having a data reading speed higher than that of the external memory 4 and the external memory 4 having a larger capacity than the internal memory 10, a plurality of display portions 6 _0, 6 _1, found relationship from ... 6 ₄ resolutions and internal memory capacity and transfer rate and external memory transfer rate relationships and internal memory and external memory, the internal minimum (EN) An image processing device that supports a plurality of display units and has a reduced memory cost by using a memory capacity.

Hereinafter, it displays a smooth moving motion each display section 6 _0, 6 _1, in ... 6 ₄ without excessive memory capacity, the memory capacity of the internal memory 10 and external memory 4, the internal data bus 13 An example of the setting mode of the bandwidth of the external data bus 5 (of which the bandwidth is smaller) and the access speed to the data recorded in the internal memory 10 will be described.

[Set internal memory capacity]
In the image processing system 1A of this embodiment, the memory capacity of the internal memory 10, specifically, the capacity of the frame buffer 110 which is formed in the internal memory 10 when performing the process, all of the display section 6 _0, 6 ₁ ,... 6 ₄ is larger than the capacity for storing one frame of image data displayed at the maximum resolution, and in all display units 6 ₀ , 6 ₁ ,... 6 ₄ . It is set smaller than the capacity for storing the image of the maximum resolution for one frame.

For example, when the display units 6 ₀ , 6 ₁ ,... 6 _{4 of} the image processing system 1A have the specifications described in <Table 1> above, the capacity of the frame buffer 110 is represented by the following formula (1). To set.

About 283Mb (display section _{6 0} (i.e., all the display section _{6 0,} 6 1, substantially the same memory capacity capable of storing image data of one frame of full resolution ones) in ... _{6 4)} <Internal capacity of the frame buffer 110 of the memory 10 <about 548Mb (all display portion _{6 0,} 6 1, substantially the same in the memory capacity to store all the image data of one frame of ... _{6 4)} (1)

[Set external memory capacity]
In the image processing system 1A of this embodiment, as described above, each of the display section ₆ 0 in the external memory _4, 6 1, ... _{6 4} same number of storage areas ₁₆ and _0, 16 1, ... 16 _n is provided, and the drawing unit 8 performs processing by double buffering in each storage area. That is, divides each of the storage areas into two, divided one region (e.g., 0 first region 161 of the storage areas 16 ₀₎ and stores the image data generated in the internal memory 10 temporarily storing region, the other region (e.g., 0 second region 162 of the storage areas 16 ₀₎ is used as an area for sending the stored image data to the display circuit unit 11.

In order to realize such processing, in this embodiment, each of the storage areas 16 ₀ , 16 ₁ ,... 16 _n of the external memory 4 has all the display sections 6 ₀ , 6 ₁ ,. the largest resolution of the _four sets so that the memory capacity of more than 2 times the memory capacity capable of storing image data of one frame of the (display section 6 ₀ in Table _1).

For example, when the display units 6 ₀ , 6 ₁ ,... 6 _{4 of} the image processing system 1A have the specifications described in <Table 1> above, the capacity of the external memory 4 is expressed by the following formula (2). To set.

External memory 4 capacity ≧1096 Mb (about 548 Mb×2) (2)

[Relationship in transfer speed between external memory and internal memory]
For example, five of the display section _{6 0,} 6 1, ... _{6 4} specifications are as shown in <Table 1> (4K2K: 1 single, Full HD: 4 units), each of the display section ₆ 0, When the image (moving image) displayed by 6 ₁ ,... 6 ₄ is 30 fps, the amount of data to be transmitted to all the display units 6 ₀ , 6 ₁ ,... 6 ₄ is the following value (3 ) It becomes like following formula (5) based on (4).

Display unit 6 ₀ , 6 ₁ ,... 6 ₄ Full screen capacity: 548 Mb... (3)
Number of display frames per second: 30 fps (4)
Data amount to be transmitted to the display units 6 ₀ , 6 ₁ ,... 6 ₄ in 1 second=(3)×(4)=548(Mb)×30(fps)=16.461 Gb...(5)

This transfer speed is the speed necessary for the image display circuits 14 ₀ , 14 ₁ ,... 14 _n to read data from the external memory 4, and the drawing data from the frame buffer 110 of the internal memory 10 by the transfer unit 9 Since the writing is also performed at the same time, the transfer rate of the external memory 4 is at least the value shown in the following expression (6), which is twice the 16.461 Gbps of the above (5).

Transfer rate of external memory 4 ≧32.922 Gbps (6)

The value of this transfer rate changes depending on the specifications of the display units 6 ₀ , 6 ₁ ,... 6 ₄ . For example, five of the display section _{6 0,} 6 1, if all of the ... _{6 4} also having a resolution of 4K2K display section _{6 0,} the capacity of the external memory 4 becomes as shown in the following equation (7), The operating frequency of the external memory 4 is as shown in the following equation (8).

External memory 4 capacity = 283.1 (Mb) x 5 (units) x 2 (times) = about 2.8 Gb (7)
Transfer rate of external memory 4 = 1415.5 (Mbit) x 30 (fps) x 2 (times) = 84.930 Gbps (8)

When the above equations (3) to (8) are combined, the transfer speed of the external memory 4 is as shown in the following equation (9).

Transfer rate of external memory 4≧total required memory capacity corresponding to resolution of display units 6 ₀ , 6 ₁ ,... 6 ₄ x number of display frames per second x 2 (9)

[Transfer speed of internal memory 10]
In the internal memory 10, writing/reading of the decoding result of the compression coded data in the drawing unit 8, writing/reading of the drawing data in the drawing unit 8, reading to the transfer unit 9 and the like are performed simultaneously. Therefore, those processes need to be performed without delay.

Here, the speed required for writing and reading in the internal memory 10 will be examined with reference to the layer of image data.

<When the number of image layers is 1>
In this example, the following processing is performed.
[Procedure A]
(Procedure 01) The drawing unit 8 decodes the encoded data stored in the second auxiliary storage device 3, and the layer data that is the decoding result is written in the layer data storage unit 120 of the internal memory 10 (Procedure 02) The drawing unit 8 reads the layer data stored in the layer data storage unit 120 of the memory 10 (procedure 03), the drawing unit 8 reads the image data stored in the frame buffer 110 (procedure 04), and the layer data and the image data. And the combined image data is written to the frame buffer 110 (procedure 05). The image data stored in the frame buffer 110 is read, transferred to the external memory 4 via the transfer unit 9, and written to the external memory 4. Assuming that the total processing speed of the two processes of reading and reading is “1”, in order to perform the process of [Procedure A], the access to the internal memory 10 is totaled as described in the above procedure 01 to procedure 05. Since it occurs 5 times, the writing and reading speeds are required to be 2.5 times (=5 accesses/2 accesses) of the external memory 4 (see arrow 200 in FIG. 3).

<When the number of image layers is 2>
In this case, since the encoded data is decoded for each layer, the writing of the decoding result and the reading of the decoding result are performed twice, and the image data of one frame for which drawing has been completed is transferred via the transfer unit 9. The reading for storing in the external memory 4 is also once. On the other hand, the combination of the layer data stored in the layer data storage unit 120 of the internal memory 10 and the image data in the frame buffer may be performed for each layer in some cases, or may not be performed for each layer and It may be stored in the data storage unit 120, and may be combined with the image data in the frame buffer 110 after all layer data is stored.

Therefore, the procedure when the drawing unit 8 combines all layers at once will be described as [Procedure B], and the procedure when performing composition for each layer will be described as [Procedure C].
[Procedure B]
(Procedure 11) The drawing unit 8 decodes the encoded data stored in the second auxiliary storage device 3, and writes the first layer data, which is the decoding result, to the layer data storage unit 120 of the internal memory 10 (Procedure 12). ) The drawing unit 8 decodes the encoded data stored in the second auxiliary storage device 3, and the second layer data that is the decoding result is written to the layer data storage unit 120 of the internal memory 10 (in this case, The layer data storage unit 120 needs a capacity for storing the first layer data and the second layer data.)
(Procedure 13) The drawing unit 8 reads the image data stored in the frame buffer 110 (Procedure 14) Reads the first layer data stored in the layer data storage unit 120 of the internal memory 10 (Procedure 15) Internal memory 10 The second layer data stored in the layer data storage unit 120 is read (step 16), the image data read in steps 23 to 24, the first and second layer data are combined, and the combined image data is added to the frame buffer 110. Write (procedure 17) The image data stored in the frame buffer 110 is read and transferred to the external memory 4 via the transfer unit 9. Then, in this case, the total of the two processes of writing to and reading from the external memory 4 is performed. If the processing speed is set to "1", in order to perform the processing of [Procedure B], since the access to the internal memory 10 occurs 7 times in total as described in Procedure 11 to Procedure 17, the write and read operations are performed. The speed is required to be 3.5 times (=7 accesses/2 accesses) that of the external memory 4 (see arrow 300 in FIG. 3).
[Procedure C]
(Procedure 21) The drawing unit 8 decodes the encoded data stored in the second auxiliary storage device 3 and writes the first layer data, which is the decoding result, to the layer data storage unit 120 of the internal memory 10 (Procedure 22). ) The drawing unit 8 reads the first layer data stored in the layer data storage unit 120 of the internal memory 10 (procedure 23), and the drawing unit 8 reads the image data stored in the frame buffer 110 (procedure 24) The layer data and the image data are combined, the combined first image data is written in the frame buffer 110 (procedure 25), the encoded data stored in the second auxiliary storage device 3 is decoded by the drawing unit 8, and the decoding is performed. Write the resulting second layer data to the layer data storage unit 120 of the internal memory 10 (the first layer data can be overwritten)
(Procedure 26) The drawing unit 8 reads the second layer data stored in the layer data storage unit 120 of the internal memory 10 (Step 27) The drawing unit 8 reads the first image data stored in the frame buffer 110 ( Step 28) The first layer data and the first image data are combined, the combined second image data is written in the frame buffer 110 (step 29), the second image data stored in the frame buffer 110 is read out, and the transfer unit If the total processing speed of the two processes of writing and reading of the external memory 4 is set to “1”, the data is transferred to the internal memory 10 in order to perform the process of [Procedure C]. Since the above access occurs 9 times in total as described in steps 21 to 29, the write and read speeds are required to be 4.5 times (=9 accesses/2 accesses) that of the external memory 4 (FIG. 3). Arrow 400).

FIG. 3 shows, for each layer of image data, the relationship between the read/write speeds of the external memory 4 and the internal memory 10 for properly performing the processing, which is calculated based on the calculations of the above procedure A to procedure C. It is a figure. When these are put together, the ratio of the writing/reading speed (first bandwidth) of the internal memory 10 to the writing/reading speed (second bandwidth) of the external memory 4 is given by the following equation (10). It is calculated.

Number of layers+1.5≦speed ratio (first bandwidth/second bandwidth)≦number of layers×2+2.5 (10)

In addition, when the layers are combined as described above, the capacity of the layer data storage unit is ensured so that the layer data of the image with the maximum resolution can be stored and a plurality of layer data is handled. Also, layer data may be sequentially overwritten. However, when synthesizing layers at one time, it is necessary to store each layer data in the layer data storage unit until the synthesizing process is performed. It is necessary to have the capacity to store all the layer data.

In addition, the number of layers in the above-described embodiment refers to a layer having a data amount of the same size as the capacity of the frame buffer in the frame in which the number of drawing pixels is maximum among the contents displayed by the image processing system on the plurality of display devices. It is based on the number of drawings. Therefore, when one layer is divided into a plurality of small layers, the above formula (10) is not satisfied, but in such a case, a plurality of divided small layers having the same size as the capacity of the frame buffer are The above condition is satisfied by considering it as a layer.

[Processing procedure]
FIG. 4 is a flowchart showing a processing procedure of the image processing system 1A of this embodiment. FIG. 5 schematically shows the same procedure on a functional block diagram. The processing procedure of the image processing system 1A of this embodiment will be described below with reference to FIG. For the sake of simplicity, the image data is created in the order of the display units 6 ₀ , 6 ₁ ,... 6 ₄ and is displayed on the respective display units 6 ₀ , 6 ₁ ,... 6 ₄ . The case where the image to be displayed is one layer will be described below.

First, the control unit 7 reads a program for controlling the image processing system 1A from the first auxiliary storage device 2. Based on this program, the control unit 7 causes the drawing unit 8 and the transfer unit 9 to generate image data described below and display units 6 ₀ , 6 ₁ ,... 6 based on the generated image data. Control for displaying an image on the image display device ₄ is performed (step S1).

When the image data is requested from the upper control unit of the gaming machine 100, the control unit 7 outputs a display list for drawing the image data to the drawing unit 8, and the drawing unit 8 stores in the internal memory 10. to ensure the capacity required for the image data processing to be output to the display section 6 ₀ as the frame buffer 110 (step S1). For example, if an image of 4K2K displayed on the display unit _{6 0,} to ensure more capacitance 283.1Mb as a frame buffer 110.

Next, the drawing unit 8 reads the encoded image content data from the second auxiliary storage device 3, decodes the data, and stores it as layer data in the layer data storage unit 120 of the internal memory 10, and further stores the layer data. The layer data of the unit 120 and the image data of the frame buffer 110 are read, combined, and the image data is written to the frame buffer 110 (step S2).
Then, the transfer unit 9, and transfers the image data stored in the frame buffer 110 of one frame of the internal memory 10 storage areas of the external memory 4, for example, the first region 161 0 storage area 16 _0, to (step S3).

Next, the drawing unit 8 releases the area of the internal memory 10 used as the frame buffer 110 (step S4).

The rendering unit 8 ensures the capacity necessary for image data processing to be output to the display unit ₆₁ as a frame buffer 110, the number of images to generate the step S4 from the same step S1, i.e., the display unit Steps S1 to S4 are repeated as many times as “No” (“No” in Step S5) to generate image data for forming images displayed on the display units 6 ₁ ,..., 6 ₄ .

At this time, in the process corresponding to step S1, in the case shown in <Table 1> above, the drawing unit 8 displays the image data forming the Full HD image displayed on the display units 6 ₁ ,... 6 _4. In order to generate, the capacity of about 70 Mb is secured as the frame buffer 110 in the internal memory 10 and the drawing data is generated. Then, the processing corresponding to steps S2 to S4 is also repeated.

By repeating 4 more times the processing in step S1 to S4, all the display section ₆ 0, one of the storage areas of the drawing data displayed in ... _{6 4} external memory 4, for example, the first region ₁₆₁ 0, 161 _1, is stored in the ... 161 _4, a state in which image data is generated, all the display section ₆ 0,... _{6 4} of the image data generation is completed (step S5 "Yes").

Step S5 is “Yes”, and after the image data to be displayed on all the display units 6 ₀ ,..., 6 ₄ are stored in the external memory 4, the display units 6 ₀ , 6 ₁ ,. _At the display timing of ₄ , the image display circuits 14 ₀ , 14 ₁ , 14 ₄ read the image data from the external memory 4, and the image display circuits 14 ₀ , 14 ₁ ,... 14 ₄ use the acquired image data in the data transmission unit. 15 _{0, 15} 1, ... 15 ₄ display section ₆ 0 through ₆ 1, and sent to ... _{6 4,} the display unit _{6 0,} 6 1, is an image displayed on ... _{6 4} (step S6). When the display units 6 ₀ , 6 ₁ ,... 6 ₄ display one frame at 30 fps, each image display circuit reads out necessary image data from the external memory 4 every 33.3 msec.

As described above, the capacity of the internal memory 10, the capacity of the external memory 4, the transfer speed of the internal data bus 13 and the external data bus 5, the control of the drawing unit 8, the display circuit unit 11 and the image display circuits 14 ₀ , 14 ₁ , · · · 14 _n control, etc. by performing the, while suppressing the capacity of the frame buffer 110 for expensive internal memory 10 in one screen of any one of the display unit for example, the display section 6 _0, a plurality of display portions 6 ₀ , 6 ₁ ,... 6 _n , it is possible to perform drawing and display processing of a plurality of screens at high speed.

Above, in this embodiment, the internal memory 10, the drawing unit 8, a plurality of display portions 6 _0, 6 _1, by drawing the image displayed in at least one of · · · 6 _n image It is configured to be used as a drawing area for generating data, and the external memory 4 is configured to be used as a storage area for image data of images displayed on the display units 6 ₀ , 6 ₁ ,... 6 _n . As a result, a plurality of image data required for display are generated by utilizing the high-speed access speed of the internal memory 10, the generated plurality of image data are stored in the external memory 4, and a plurality of display data are displayed from the external memory 4. Since the image data is supplied to the units 6 ₀ , 6 ₁ ,... 6 _n , it is possible to prevent the internal memory 10 from having an excessively large capacity.

In In this embodiment, the frame buffer 110 in the internal memory 10, the display section 6 _0, 6 _1, the total number of pixels among the · · · 6 _n or more data volume per frame displayed largest of by being formed in total less of the capacity of data amount for one frame to be displayed on all the display unit (for example, the display section 6 _0), the internal memory 10, all the display section 6 _0, 6 _1, ... It can be configured as a capacity necessary to generate image data to be displayed at 6 _n at high speed and send it to the external memory 4. Further, since the external memory 4 is formed to have a capacity equal to or larger than the total amount of data of one frame displayed by all the display units 6 ₀ , 6 ₁ ,... 6 _n , the external memory 4 is of the display unit _{6 0,} 6 1, the image data to be displayed on · · · _{6 n,} the display section _{6 0,} 6 1, as the capacity required to form concurrently every · · · _{6 n} Can be configured. As a result, it is possible to provide the image processing system 1A which can perform the image formation and the image display at high speed when simultaneously displaying the images on the plurality of screens and can suppress the increase in the manufacturing cost.

In this embodiment, in the external memory 4, it becomes possible to temporarily store the image data by double buffering and to transmit the temporarily stored image data, thereby forming an image and storing the image. It becomes possible to perform transmission continuously and at high speed. As a result, it is possible to provide the image processing system 1A which can perform the image formation and the image display at high speed when simultaneously displaying the images on the plurality of screens and can suppress the increase in the manufacturing cost.

In this embodiment, the internal data bus 13, and / or, the bandwidth of the external data bus 5, the generation of the image data and the display section 6 _0, 6 _1, the display of an image in · · · 6 _n consecutive With this configuration, when the drawing data is configured using the internal memory 10 and the image data is generated using the external memory 4, the data transmission from the internal memory 10 to the external memory 4 and the external memory 4 are performed. It is possible to continuously transmit data from the display circuit unit 11 to 14 ₀ , 14 ₁ ,... 14 _n continuously and concurrently. As a result, it is possible to provide the image processing system 1A which can perform the image formation and the image display at high speed when simultaneously displaying the images on the plurality of screens and can suppress the increase in the manufacturing cost.

In this embodiment, RAMs capable of reading and writing data and randomly accessing recorded data are used for the internal memory 10 and the external memory 4, respectively, to display images on a plurality of screens simultaneously. Thus, it is possible to configure the image processing system 1A that can perform image formation and image display at high speed and can suppress a rise in manufacturing cost.

In this embodiment, when the images are simultaneously displayed on a plurality of screens using the image processing system 1A of the present invention, the image formation and the image display can be performed at high speed, and the increase of the manufacturing cost can be suppressed. It is possible to provide the gaming machine 100 capable of doing so.

In this embodiment, the image processing system 1A of the present invention is used for the gaming machine 100, but it is also applicable to the image processing system 1A used for other than the gaming machine 100.

Further, in this embodiment, the "drawing area" of the internal memory 10 is the frame buffer 110, but the present invention is not limited to this, and an area in which the frame buffer 110 in the internal memory 10 and other configurations are integrated is ". It may be a "drawing area". Specifically, for example, an area in which the frame buffer 110 and the layer data storage unit 120 are integrated may be set as the “drawing area”. Alternatively, an area other than the frame buffer 110 in the internal memory 10, for example, the layer data storage unit 120 or an area (not shown) other than the layer data storage unit 120 may be used as the “drawing area”.

It goes without saying that the above embodiment is an example of the present invention and does not mean that the present invention is limited to the above embodiment.

1A... Image processing system 4... External memory 5... External data bus (transmission/reception means)
6 ₀ , 6 ₁ ,..., 6 ₄ , 6 _n ... Display unit (display means)
8: Drawing unit (image forming means)
10... Internal memory (first storage means)
13... Internal data bus (transmission/reception means)
14 ₀ , 14 ₁ ,... 14 _n ... Image display circuit 100... Gaming machine 110... Frame buffer (drawing area)

Claims (6)

An image processing system for displaying an image on a plurality of display means,
Image forming means for forming an image to be displayed on the display means,
A first storage unit used as a drawing area for drawing an image displayed on at least one of the plurality of display units by the image forming unit to generate image data;
A plurality of second storage means for storing the image data generated in the first storage means, which are formed by the image forming means in a quantity corresponding to the quantity of the display means;
A plurality of image display circuits provided corresponding to the respective display means for obtaining the image data from the second storage means and displaying the image data on the respective display means;
To transmit and receive the image data between the first storage means and the second storage means, and to transmit and receive the image data between the second storage means and the image display circuit. And a transmitting and receiving means of
The first storage unit and the plurality of image display circuits are respectively provided in an image processing apparatus main body section for generating and displaying the image data,
The image processing apparatus main body is connected to an external communication unit that constitutes the transmission/reception unit, and the external communication unit is connected to the second storage unit.
The first storage means has a faster access speed to the recorded data than the second storage means,
The second storage means is configured to have a storage capacity of the data larger than that of the first storage means,
The image forming unit moves the image data generated in the first storage unit from the image processing apparatus main body unit to the second storage unit and stores the image data in the second storage unit, and The image data stored in the second storage means is moved to the image processing apparatus main body, the moved image data is supplied to the image display circuit, and an image based on the image data is displayed on the display means. An image processing system characterized by: The drawing area of the first storage means is equal to or larger than the data amount of one frame displayed on the one of the display devices having the largest total number of pixels, and the data amount of one frame displayed on all the display devices. Is formed with a capacity less than or equal to
The image processing system according to claim 1, wherein the second storage unit is formed to have a capacity equal to or larger than a total amount of data of one frame displayed by all the display units. The second storage means is formed to have a capacity of at least twice the total amount of data of one frame displayed by all the display means, and
The two or more multi-buffer configuration is configured to perform temporary storage by storing the generated image and transmission of the stored image to the image display circuit. Or the image processing system according to 2. The first bandwidth of data transmission between the image forming means and the first storage means is relative to the second bandwidth of data transmission between the image display circuit and the second storage means. The image processing system according to any one of claims 1 to 3, wherein the image processing system is configured to have a relationship of the following expression (1).
Number of layers+1.5≦first bandwidth/second bandwidth≦number of layers×2+2.5 (1) The image processing system according to claim 1, wherein the first storage unit and the second storage unit are each formed of a RAM. A gaming machine comprising a plurality of display means and using the image processing system according to any one of claims 1 to 5.

Images