JP6722371B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.

Patent Document 1 discloses a semiconductor device including a substrate, an electrode formed on the substrate, a sealing film that covers the upper surface and side surfaces of the substrate, and a resin film that is a support film that covers the lower surface of the substrate. ing. The sealing film covers the electrodes on the substrate.

JP, 2011-181858, A

An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device, which can realize miniaturization.

A semiconductor device according to one aspect of the present invention for achieving the above object is a semiconductor chip, a first electrode formed on the semiconductor chip, a second electrode formed on the first electrode, and And an insulating film that covers the outer surface of the semiconductor chip. The insulating film covers the first electrode and the second electrode on the semiconductor chip so as to expose the surface of the second electrode. According to this structure, the insulating film also serves as a part of the semiconductor package, so that the size of the semiconductor device can be reduced.

In the semiconductor device, it is preferable that the second electrode is formed on the first electrode in an area smaller than that of the first electrode in a plan view seen from a direction normal to a surface of the semiconductor chip. Further, it is preferable that the insulating film covers an upper portion of the first electrode and a side portion of the second electrode.
The electrodes formed on the semiconductor chip may be mounted on a mounting board via solder, for example. During this mounting, the semiconductor device is heated to melt the solder. As a result, the electrodes are heated to cause thermal expansion, and as a result, the stress may peel off the surface of the semiconductor chip. If the electrodes are peeled off from the surface of the semiconductor chip, they will fall off from the insulating film and cause a connection failure or the like.

Therefore, in the present invention, the area of the second electrode in plan view is formed smaller than that of the first electrode, and the upper portion of the first electrode and the side portion of the second electrode are covered with the insulating film. .. Thereby, the anchor effect of the first electrode and the second electrode with respect to the insulating film can be enhanced, so that the first electrode and the second electrode can be prevented from peeling off from the semiconductor chip and falling off from the insulating film. As a result, it is possible to provide a semiconductor device that can be downsized while suppressing poor connection.

In the semiconductor device, the insulating film covers a first insulating film that covers the first electrode and the second electrode inside the semiconductor chip, and covers an outer surface of the semiconductor chip outside the semiconductor chip. The second insulating film may be included. In this structure, the second insulating film may cover the first insulating film.
The first insulating film may include at least one of an epoxy resin and a polyimide resin. Further, the second insulating film may contain at least one of an epoxy resin and a polyimide resin. The second insulating film may include an insulating material different from that of the first insulating film.

It is preferable that the semiconductor device further includes a conductive bonding material interposed between the first electrode and the second electrode. With this configuration, the connection strength between the first electrode and the second electrode can be increased. In the semiconductor device, the first electrode may include one or more metal species selected from the group including copper, gold and nickel. In the semiconductor device, the second electrode may contain one or more metal species selected from the group containing copper, gold and nickel.

In the semiconductor device, the second electrode may be formed as an external terminal that is externally connected inside the semiconductor chip in a plan view when viewed from a normal direction of a surface of the semiconductor chip. With this configuration, it is possible to provide a Fan-in type semiconductor device in which external terminals are formed in a region surrounded by the side surface of the semiconductor chip in a plan view.
The semiconductor device further includes a rewiring electrically connected to the second electrode and extending from the second electrode onto the insulating film in a plan view seen from a normal direction of a surface of the semiconductor chip. You can leave. The semiconductor device may further include an external terminal electrically connected to the rewiring and at least partially externally connected outside the semiconductor chip in the plan view. With this configuration, it is possible to provide a Fan-out type semiconductor device in which at least a part of the external terminal is formed outside the region surrounded by the side surface of the semiconductor chip in plan view.

A method of manufacturing a semiconductor device according to the present invention for achieving the above-mentioned object, comprising: a semiconductor chip including an electrode formed on a surface thereof; and a supporting member including a conductor formed on the surface, wherein the electrode and the conductive material are provided. By joining the bodies, a chip fixing step of fixing the semiconductor chip on the support member, and by forming an insulating film that covers the semiconductor chip in a state in which the semiconductor chip is fixed to the support member, A sealing structure forming step of forming a sealing structure in which the semiconductor chip is sealed by the insulating film; and removing the support member from the sealing structure to remove the conductor formed on the support member. And a transfer step of transferring to the sealing structure.

According to this method, the electrodes of the semiconductor chip and the conductors of the supporting member are bonded with the surface of the semiconductor chip facing the surface of the supporting member. The conductor of the support member is electrically connected to the semiconductor chip via the electrode. In this state, the semiconductor chip is covered with the insulating film to form a sealing structure in which the semiconductor chip is sealed with the insulating film. After that, the conductor is transferred to the sealing structure by removing the supporting member. The conductor transferred to the sealing structure is exposed from the sealing structure. As a result, an electrode layer including the electrode as the first electrode and the conductor as the second electrode is formed on the surface of the semiconductor chip. The electrode layer exposed from the sealing structure can be used as a connection electrode that can be electrically connected to the outside of the sealing structure.

According to this method, the electrode layer exposed from the sealing structure can be formed by removing the supporting member after the semiconductor chip is covered with the insulating film to form the sealing structure, and thus the insulating film is used to form the electrode layer. It is not entirely covered. Accordingly, the step of grinding the insulating film to expose the electrode layer can be omitted, so that the manufacturing process can be simplified. Furthermore, since the insulating film that covers the semiconductor chip also serves as a semiconductor package, the size of the semiconductor device can be reduced.

In the manufacturing method, the conductor in the support member is formed in an area smaller than the area of the electrode in a plan view seen from the normal direction of the surface of the semiconductor chip, and the sealing structure forming step. In the above, it is preferable that the insulating film is formed between the semiconductor chip and the supporting member so as to cover an upper portion of the electrode and a side portion of the conductor.

According to this method, the anchor effect of the electrode layer (electrode and conductor) to the insulating film can be enhanced in the step of forming the sealing structure, so that the electrode layer is peeled off from the semiconductor chip or slipped off from the insulating film. Can be suppressed. As a result, it is possible to manufacture a semiconductor device capable of suppressing the occurrence of connection failure while realizing miniaturization.
In the manufacturing method, the semiconductor chip may include a first insulating film that covers a surface of the semiconductor chip. In this case, in the chip fixing step, the chip fixing step melts the first insulating film and seals the electrode and the conductor with the first insulating film between the semiconductor chip and the supporting member. It is preferable that the step of stopping and the step of electrically connecting the electrode and the conductor are performed together. The sealing structure forming step preferably includes a step of forming the sealing structure by covering the semiconductor chip with a second insulating film as the insulating film.

When a semiconductor chip is covered with an insulating film to form a sealing structure, it is necessary to pour the insulating film into the gap between the semiconductor chip and the support member. However, it is expected that the gap between the semiconductor chip and the supporting member will be miniaturized to such an extent that it becomes difficult to pour the insulating film along with the miniaturization of the semiconductor device. If the insulating film is not sufficiently distributed in the gap between the semiconductor chip and the supporting member, not only will the sealing with the insulating film be insufficient in the subsequent manufacturing process, but also the electrodes and conductors will be misaligned. It may occur.

Therefore, in this method, after fixing the semiconductor chip including the first insulating film covering the surface to the supporting member, the first insulating film is melted, so that the electrode and the conductor are provided between the semiconductor chip and the supporting member. Are sealed by the first insulating film. This eliminates the need to pour an insulating film between the semiconductor chip and the supporting member, so that the electrode and the conductor can be made good by the first insulating film without being restricted by the gap between the semiconductor chip and the supporting member. Can be sealed.

Further, the first insulating film and the second insulating film can be used as a semiconductor package. As a result, it is possible to manufacture a semiconductor device that can be miniaturized while satisfactorily eliminating the risk of misalignment of electrodes and conductors in the manufacturing process. Further, since the manufactured semiconductor device can have the electrode (first electrode) and the conductor (second electrode) whose positional displacement is suppressed, it is possible to suppress the occurrence of connection failure and the like.

In the manufacturing method, the chip fixing step may include a step of joining the electrode and the conductor with a conductive joining material.
In the manufacturing method, the chip fixing step includes a step of fixing the plurality of semiconductor chips to the support member, and the sealing structure forming step collectively covers the plurality of semiconductor chips with the insulating film. It may include a step. In this case, the manufacturing method may further include an individualizing step of cutting individual pieces of the plurality of semiconductor devices by selectively cutting the sealing structure after the transferring step. According to this method, the process of forming the sealing structure can be made common to a plurality of semiconductor chips, so that the manufacturing efficiency can be improved.

In the manufacturing method, the transferring step also serves as a step of forming the conductor as an external terminal to be externally connected inside the semiconductor chip in a plan view seen from a direction normal to a surface of the semiconductor chip. Good. According to this method, it is possible to manufacture a Fan-in type semiconductor device in which external terminals are formed in a region surrounded by the side surface of the semiconductor chip in plan view.

In the manufacturing method, after the transferring step, a rewiring forming step of forming a rewiring drawn out from the conductor onto the sealing structure in a plan view seen from a direction normal to a surface of the semiconductor chip is further included. May be included.
The manufacturing method further includes a step of, after the rewiring formation step, forming an external terminal electrically connected to the rewiring and at least a part of which is externally connected outside the semiconductor chip in the plan view. May be included. According to this method, it is possible to manufacture a Fan-out type semiconductor device in which at least a part of the external terminal is formed outside the region surrounded by the side surface of the semiconductor chip in plan view.

In the manufacturing method, the support member may be a plate-shaped member capable of forming the conductor and being separable from the sealing structure. In this case, the step of removing the support member from the sealing structure may include a step of peeling the plate-shaped member from the sealing structure. According to this method, the conductor can be easily transferred to the sealing structure by peeling the plate-shaped member from the sealing structure. The plate-shaped member is preferably a metal plate containing stainless steel or copper. If the plate-shaped member is a metal plate containing stainless steel or copper, it can be favorably peeled from the sealing structure. As a result, the conductor can be satisfactorily transferred to the sealing structure without complicating the manufacturing process.

In the manufacturing method, the support member may be a plate-shaped member capable of forming the conductor and capable of being etched. In this case, the step of removing the support member from the sealing structure may include a step of removing the plate-shaped member by etching. According to this method, the conductor can be easily transferred to the sealing structure by removing the plate member by etching. The plate-shaped member is preferably a semiconductor plate. If the plate-shaped member is a semiconductor plate, the semiconductor plate can be satisfactorily removed by etching. As a result, the conductor can be satisfactorily transferred to the sealing structure without complicating the manufacturing process.

A semiconductor device according to another aspect of the present invention includes a semiconductor chip, an electrode having a convex cross-section formed on the semiconductor chip, and an insulating film covering an outer surface of the semiconductor chip. The electrode having a convex cross-section has a relatively wide portion and a narrow portion that is narrower than the wide portion and protrudes upward from the wide portion. The insulating film covers the electrode on the semiconductor chip so as to surround the narrow portion on the wide portion. According to this structure, the anchor effect of the electrode with respect to the insulating film can be enhanced, so that the electrode can be prevented from peeling off from the semiconductor chip and falling off from the insulating film. As a result, it is possible to provide a semiconductor device that can be downsized while suppressing poor connection.

FIG. 1A is a perspective sectional view of a semiconductor device according to a first embodiment of the present invention. 1B is a partially enlarged cross-sectional view of the semiconductor device shown in FIG. 1A. FIG. 2A is a perspective sectional view showing a method of manufacturing the semiconductor device shown in FIG. 1A. FIG. 2B is a perspective view showing the next step of FIG. 2A. FIG. 2C is a perspective view showing the next step of FIG. 2B. FIG. 2D is a sectional view showing a step subsequent to FIG. 2C. FIG. 2E is a sectional view showing a step subsequent to FIG. 2D. 2F is a sectional view showing a step subsequent to FIG. 2E. FIG. 2G is a sectional view showing a step subsequent to FIG. 2F. FIG. 3 is a perspective sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 4A is a perspective sectional view showing a method of manufacturing the semiconductor device shown in FIG. FIG. 4B is a perspective view showing the next step of FIG. 4A. FIG. 4C is a perspective view showing a step subsequent to FIG. 4B. FIG. 4D is a sectional view showing a step subsequent to FIG. 4C. FIG. 4E is a sectional view showing a step subsequent to FIG. 4D. FIG. 4F is a sectional view showing a step subsequent to FIG. 4E. FIG. 4G is a sectional view showing a step subsequent to FIG. 4F. FIG. 4H is a sectional view showing a step subsequent to FIG. 4G. FIG. 5 is a perspective sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 6 is a sectional view of a semiconductor device according to the fourth embodiment of the present invention. FIG. 7 is a sectional view of a semiconductor device according to a modification. FIG. 8 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First Embodiment>
FIG. 1A is a perspective sectional view of a semiconductor device 1 according to the first embodiment of the present invention. 1B is a partially enlarged cross-sectional view of the semiconductor device 1 shown in FIG. 1A. In FIG. 1A, the excised part of the semiconductor device 1 is shown separately.

The semiconductor device 1 includes a semiconductor chip 2. The semiconductor chip 2 has, for example, a substantially rectangular parallelepiped shape, and includes two main surfaces 2A and 2B and a side surface 2C that connects the two main surfaces 2A and 2B. In the following, of the two main surfaces 2A and 2B, the main surface 2A on which the semiconductor element is formed is referred to as "element formation surface 2A", and the opposite main surface 2B is referred to as "back surface 2B". The element forming surface 2A, the back surface 2B and the side surface 2C of the semiconductor chip 2 form the outer surface of the semiconductor chip 2. The thickness of the semiconductor chip 2 may be, for example, 30 μm or more and 725 μm or less.

The semiconductor element can include, for example, various semiconductor elements formed using a semiconductor. The semiconductor element may include, for example, a transistor, a diode, or the like. Further, the semiconductor element may form part of a voltage control element such as LDO (Low Drop Out) or a part of amplification element such as an OP amplifier. Further, the semiconductor element is one of integrated circuits such as SSI (Small Scale Integration), LSI (Large Scale Integration), MSI (Medium Scale Integration), VLSI (Very Large Scale Integration) or ULSI (Ultra-Very Large Scale Integration). You may form the part.

On the element formation surface 2A of the semiconductor chip 2, a plurality of (four in the present embodiment) electrode layers 3 electrically connected to the semiconductor element are formed. More specifically, as shown in FIG. 1B, the wiring layer 10 is formed on the element forming surface 2A of the semiconductor chip 2. The wiring layer 10 includes a connection pad 11, a passivation film 12, and a wiring film 13. The connection pad 11 is formed on the element formation surface 2A of the semiconductor chip 2 so as to be electrically connected to the semiconductor element.

The passivation film 12 is formed on the element formation surface 2A of the semiconductor chip 2 so as to selectively expose the connection pads 11. The passivation film 12 may be a laminated film in which a plurality of insulating films are laminated. This laminated film may include one or more insulating films selected from the group including a silicon oxide film, a silicon nitride film, and a resin film. The wiring film 13 is formed on the passivation film 12 so as to be electrically connected to the connection pad 11.

The electrode layer 3 is formed on the wiring film 13. The electrode layer 3 is electrically connected to the semiconductor element via the connection pad 11 and the wiring film 13. For example, when the wiring layer 10 includes a multilayer wiring structure, the electrode layer 3 may be electrically connected to the uppermost layer wiring exposed from the outermost surface of the multilayer wiring structure. In this case, the multilayer wiring structure has a via electrode that electrically connects a plurality of insulating films and a plurality of wiring layers alternately stacked on the element formation surface 2A and wiring layers arranged above and below with the insulating film interposed therebetween. May be included.

The electrode layer 3 is formed in a plate shape, a block shape, or a column shape. In this embodiment, an example in which the electrode layer 3 is formed in a prismatic shape is shown. The electrode layer 3 includes a first electrode 4 formed on the element formation surface 2A of the semiconductor chip 2, a second electrode 5 formed on the first electrode 4, a first electrode 4 and a second electrode 5. It has a laminated structure including a conductive bonding material 6 interposed therebetween.
The first electrode 4 is formed, for example, in a substantially rectangular shape in a plan view (hereinafter, simply referred to as “plan view”) viewed from a direction normal to the element formation surface 2A of the semiconductor chip 2. The first electrode 4 comprises one or more metal species selected from the group comprising copper, gold and nickel. In this embodiment, the first electrode 4 made of a nickel film is formed. The width W ₁ of the first electrode 4 may be, for example, 20 μm or more and 500 μm or less. The thickness T ₁ of the first electrode 4 may be, for example, 3 μm or more and 100 μm or less. The first electrode 4 may be a laminated film including a nickel film and a gold film formed in this order from the element formation surface 2A side of the semiconductor chip 2.

The second electrode 5 is formed in an area smaller than that of the first electrode 4 so as to expose at least a part of the peripheral edge of the first electrode 4 in a plan view. In the present embodiment, the second electrode 5 is formed in a substantially rectangular shape in plan view on the central portion of the first electrode 4. The second electrode 5 forms a step 7 with the first electrode 4. As a result, the electrode layer 3 is formed in a convex shape in cross section having a relatively wide portion and a narrow portion that is narrower than the wide portion and protrudes upward (on the side opposite to the element forming surface 2A). ing.

The second electrode 5 includes one or more metal species selected from the group including copper, gold and nickel. In the present embodiment, the second electrode 5 is a laminated film including a nickel film and a gold film formed in this order from the element formation surface 2A side of the semiconductor chip 2. The width W ₂ of the second electrode 5 may be, for example, 20 μm or more and 500 μm or less. The thickness T ₂ of the second electrode 5 may be, for example, 3 μm or more and 100 μm or less.

The conductive bonding material 6 may be solder, metal paste, or the like. The solder may include one or more metal species selected from the group including tin, lead, phosphorus, silver, copper, nickel, germanium, bismuth, indium, zinc, aluminum, antimony and cobalt. The solder may be, for example, an alloy containing tin and lead, an alloy containing tin and phosphorus, or an alloy containing tin and antimony. The metal paste may include one or more metal species selected from the group including silver, gold, copper, palladium, nickel, platinum and tungsten.

A sealing resin 8 as an example of the insulating film of the present invention is formed so as to cover the outer surface of the semiconductor chip 2. The sealing resin 8 may be an epoxy resin, for example. The sealing resin 8 is formed so as to cover the entire area of each of the element formation surface 2A, the back surface 2B, and the side surface 2C of the semiconductor chip 2. The sealing resin 8 is formed into a substantially rectangular parallelepiped shape and also serves as a semiconductor package. The sealing resin 8 includes one main surface 8A located on the element formation surface 2A side of the semiconductor chip 2, the other main surface 8B located on the back surface 2B side of the semiconductor chip 2, and these main surfaces 8A and 8B. It has a connecting side surface 8C. The sealing resin 8 covers the first electrode 4 and the second electrode 5 so as to expose the outermost surface of the second electrode 5 on the element formation surface 2A of the semiconductor chip 2.

More specifically, the sealing resin 8 covers the side portion and the upper portion of the first electrode 4 so as to wrap around the region on the step portion 7 of the first electrode 4 and the second electrode 5, and The side portion of the second electrode 5 is covered so that the outermost surface of the electrode 5 is exposed. That is, the sealing resin 8 overlaps the first electrode 4 and surrounds the second electrode 5. In other words, the sealing resin 8 surrounds the narrow portion protruding upward from the wide portion on the wide portion in the electrode layer 3 having a convex cross-section.

The outermost surface of the second electrode 5 exposed from one main surface 8A of the sealing resin 8 is formed flat with respect to the main surface 8A of the sealing resin 8 and is formed as an external terminal 9 to be externally connected. ing. The external terminal 9 is formed in a region surrounded by the side surface 2C of the semiconductor chip 2 in plan view. That is, the semiconductor device 1 is a Fan-in type semiconductor device.
2A to 2C are perspective views showing an example of a method of manufacturing the semiconductor device 1 shown in FIG. 1A. 2D to 2G are sectional views showing steps after FIG. 2C.

Prior to manufacturing the semiconductor device 1, the semiconductor chip 2 is formed. In forming the semiconductor chip 2, as shown in FIG. 2A, first, one semiconductor wafer 20 is prepared. On the surface of the semiconductor wafer 20, chip regions 21 corresponding to the plurality of semiconductor chips 2 are set in a matrix at intervals along the row direction and the column direction orthogonal to the row direction. A dicing line 22 is drawn between the adjacent chip regions 21. A predetermined semiconductor element and a wiring layer 10 (see FIG. 1B) are formed in each chip region 21.

Next, the electrode 23 that will become the first electrode 4 in a later step is formed on the surface of the semiconductor wafer 20. More specifically, a nickel film is formed so as to cover the surface of the semiconductor wafer 20 by, for example, a sputtering method. Next, the nickel film is patterned into a predetermined shape (generally rectangular in a plan view in this embodiment) by etching through a mask, for example. As a result, a plurality of (four in the present embodiment) electrodes 23 are formed in the chip region 21.

Next, as shown in FIG. 2B, the semiconductor wafer 20 is cut along the dicing line 22. Thereby, the individual pieces of the plurality of semiconductor chips 2 are cut out from the semiconductor wafer 20. The individualized semiconductor chip 2 includes a plurality of electrodes 23 formed on the element formation surface 2A.
While the semiconductor chip 2 is formed, a supporting member 24 is prepared as shown in FIG. 2C. The support member 24 may be, for example, a circular plate having a substantially circular shape in plan view, or a flat plate having a substantially rectangular shape in plan view. The support member 24 is preferably a plate-shaped member that can be removed (peeled and/or etched) from the sealing resin 8. The plate-shaped member that can be separated from the sealing resin 8 may be a metal plate containing stainless steel or copper. On the other hand, the plate-shaped member that can be removed from the sealing resin 8 by etching may be a semiconductor plate such as a silicon wafer.

On the surface of the support member 24, a plurality of chip placement regions 25 in which a plurality of semiconductor chips 2 are placed one by one in a later step are set (see the dashed line in FIG. 2C). The plurality of chip placement regions 25 are arranged in a matrix along the row direction and the column direction orthogonal to the row direction. In the present embodiment, each chip placement region 25 is set to have a larger area than the element formation surface 2A of the semiconductor chip 2 in a plan view when viewed from the normal direction of the surface of the support member 24.

A plurality of (four in the present embodiment) conductors 26 that will become the second electrodes 5 in a later step are formed in each chip placement region 25. The conductor 26 is formed in a position corresponding to the electrode 23 of the semiconductor chip 2 and in an area smaller than the area of the electrode 23 in a plan view seen from the normal direction of the surface of the support member 24. The conductor 26 is formed, for example, by forming a copper film, a gold film, or a nickel film on the support member 24 by a sputtering method, and then patterning by etching through a mask.

The conductor 26 may be a laminated film including a gold film and a nickel film formed in this order from the front surface side of the support member 24. The conductor 26 may be a laminated film including a nickel film and a gold film formed in this order from the front surface side of the support member 24. In this case, the gold film may be formed on the nickel film by, for example, electroless plating or electrolytic plating. Next, the conductive bonding material 6 is formed on the conductor 26. In the present embodiment, the conductive bonding material 6 is solder and is formed by, for example, electroless plating or electrolytic plating.

Next, as shown in FIGS. 2C and 2D, the plurality of semiconductor chips 2 are arranged in the chip arrangement regions 25 of the support member 24, respectively. More specifically, in the plurality of semiconductor chips 2, the electrode 23 of the semiconductor chip 2 and the conductor 26 of the support member 24 are conductively bonded in a state where the element forming surface 2A faces the surface of the support member 24. They are joined by the material 6 and fixed on the support member 24. That is, the semiconductor chip 2 is flip-chip bonded to the support member 24. The conductor 26 of the support member 24 is electrically connected to the semiconductor chip 2 via the conductive bonding material 6 and the electrode 23. Each semiconductor chip 2 is fixed on the support member 24 with a predetermined gap from the surface of the support member 24.

Next, as shown in FIG. 2E, with the plurality of semiconductor chips 2 fixed to the support member 24, the plurality of semiconductor chips 2 are collectively covered with the sealing resin 8 containing an epoxy resin. The sealing resin 8 fills the gap between the support member 24 and each semiconductor chip 2, and seals each semiconductor chip 2 so as to cover the side surface 2C and the back surface 2B of each semiconductor chip 2. That is, the electrode 23, the conductor 26, and the conductive bonding material 6 are sealed together with the semiconductor chip 2 by the sealing resin 8. Then, heat is applied to the sealing resin 8 to cure the sealing resin 8. As a result, the sealing structure 27 in which the plurality of semiconductor chips 2 are collectively sealed with the sealing resin 8 is formed.

Next, as shown in FIG. 2F, the support member 24 is removed from the sealing structure 27. When the support member 24 is a metal plate containing stainless steel or copper, the metal plate is peeled off from the sealing structure 27. On the other hand, when the support member 24 is a semiconductor plate, the semiconductor plate is removed by etching. By removing the support member 24 from the sealing structure 27, the conductor 26 formed on the support member 24 is transferred to the sealing structure 27. The connection portion of the conductor 26 transferred to the sealing structure 27 to the support member 24 is exposed from the sealing structure 27. Further, this connecting portion has a flat surface that is flat with respect to the main surface 27A of the sealing structure 27. As a result, the electrode 23 becomes the first electrode 4, the conductor 26 becomes the second electrode 5, and the electrode layer 3 including the first electrode 4, the second electrode 5, and the conductive bonding material 6 is formed.

Next, as shown in FIG. 2G, for example, a dicing blade 28 cuts the sealing structure 27 along dicing lines 29 set between the plurality of semiconductor chips 2. The dicing line 29 may be set based on, for example, the boundaries of the chip placement regions 25 set on the support member 24. As a result, the individual pieces of the semiconductor devices 1 are cut out from the sealing structure 27.

As described above, in the present embodiment, the electrode layer 3 including the second electrode 5 formed on the first electrode 4 is formed in an area smaller than that of the first electrode 4 in plan view. Then, the sealing resin 8 covers the upper portion of the first electrode 4 and the side portions of the second electrode 5. More specifically, the sealing resin 8 surrounds the second electrode 5 and the conductive bonding material 6 on the first electrode 4, and the upper portion and the side portion of the first electrode 4 and the side portion of the second electrode 5. Is covered. Thereby, the anchor effect of the electrode layer 3 with respect to the sealing resin 8 can be enhanced, so that the electrode layer 3 can be prevented from peeling off from the semiconductor chip 2 or falling off from the sealing resin 8. As a result, it is possible to provide the semiconductor device 1 that can realize downsizing while suppressing connection failure.

Further, in the manufacturing method of the present embodiment, the electrode layer 3 exposed from the sealing structure 27 can be formed by removing the support member 24 after forming the sealing structure 27. The entire 3 is not covered. As a result, the step of grinding the sealing resin 8 to expose the electrode layer 3 can be omitted, so that the manufacturing process can be simplified.
<Second Embodiment>
FIG. 3 is a perspective sectional view of a semiconductor device 31 according to the second embodiment of the present invention. In FIG. 3, the cut away portion of the semiconductor device 31 is shown separately. The semiconductor device 31 is different from the semiconductor device 1 described above in that an electrode layer 32 is formed instead of the electrode layer 3 and a sealing resin 33 is formed instead of the sealing resin 8. .. The other configurations of the semiconductor device 31 are substantially the same as those of the semiconductor device 1 described above. In FIG. 3, parts corresponding to the parts shown in FIG. 1A and the like are given the same reference numerals, and description thereof will be omitted.

As shown in FIG. 3, the electrode layer 32 includes a first electrode 4 and a second electrode 5 that are formed to have substantially the same area and shape in a plan view. The sealing resin 33 is formed so as to cover the entire area of the element forming surface 2A, the back surface 2B, and the side surface 2C of the semiconductor chip 2. The sealing resin 33 is formed in a substantially rectangular parallelepiped shape and also serves as a semiconductor package. The sealing resin 33 includes one main surface 33A located on the element forming surface 2A side of the semiconductor chip 2, the other main surface 33B located on the back surface 2B side of the semiconductor chip 2, and these main surfaces 33A, 33B. It has a side surface 33C to be connected.

More specifically, the sealing resin 33 is a first insulating film of the present invention which covers the first electrode 4 and the second electrode 5 so as to expose the outermost surface of the second electrode 5 inside the semiconductor chip 2. It includes a first sealing resin 34 as an example. The encapsulating resin 33 further includes a second encapsulating resin 35 as an example of the second insulating film of the present invention which covers the outer surface (the back surface 2B and the side surface 2C) of the semiconductor chip 2 outside the semiconductor chip 2.

The first sealing resin 34 includes at least one of epoxy resin and polyimide resin. In this embodiment, the first sealing resin 34 includes an epoxy resin. As the material of the first sealing resin 34, in addition to the above materials, a polymeric insulating material, an organic insulating material, and the like are also suitable. The first sealing resin 34 is formed on the element forming surface 2A of the semiconductor chip 2 and has a flat surface 34A forming a part of the main surface 33A on one side of the sealing resin 33. The first sealing resin 34 also has a side portion 34B that rises along the side surface 2C of the semiconductor chip 2 in a direction away from the element formation surface 2A of the semiconductor chip 2.

The side portion 34B of the first sealing resin 34 is formed along the side surface 2C of the semiconductor chip 2 in a plan view. As a result, the surface 34A of the first sealing resin 34 is formed in a substantially rectangular shape in plan view that substantially matches the element forming surface 2A of the semiconductor chip 2. The outermost surface of the second electrode 5 is formed flat with respect to the surface 34A of the first sealing resin 34, and is formed as an external terminal 9 to be externally connected. The external terminal 9 is formed in a side surface 2C of the semiconductor chip 2 in a plan view, more specifically, in a region surrounded by the side portion 34B of the first sealing resin 34. That is, the semiconductor device 31 is a Fan-in type semiconductor device.

The second sealing resin 35 includes at least one of epoxy resin and polyimide resin. In the present embodiment, the second sealing resin 35 contains a polyimide resin. As the material of the second sealing resin 35, in addition to the above materials, a polymeric insulating material, an organic insulating material, and the like are also suitable. The second sealing resin 35 covers the back surface 2B, the side surface 2C of the semiconductor chip 2 and the side portion 34B of the first sealing resin 34. That is, the second sealing resin 35 surrounds the first sealing resin 34 in a substantially square ring shape in plan view. The second sealing resin 35 has a front surface 35A that forms a part of the main surface 33A on one side of the sealing resin 33, and forms a back surface 33B and a side surface 33C of the sealing resin 33. The surface 35A of the second sealing resin 35 is formed flat with respect to the surface 34A of the first sealing resin 34.

4A to 4C are perspective views showing an example of a method for manufacturing the semiconductor device 31 shown in FIG. 4D to 4H are cross-sectional views showing steps after FIG. 4C.
Prior to manufacturing the semiconductor device 31, the semiconductor chip 2 is formed. In forming the semiconductor chip 2, as shown in FIG. 4A, a semiconductor wafer 20 is prepared as in the above-described first embodiment, and a plurality of semiconductor wafers (four in this embodiment are used as the first electrodes 4 in subsequent steps) are prepared. ) Electrode 23 is formed. Next, the underfill material 40 is applied so as to cover the entire area of the semiconductor wafer 20.

The underfill material 40 contains at least one of an epoxy resin and a polyimide resin. The underfill material 40 may be, for example, NCP (Non Conductive Paste) or NCF (Nom Conductive Film). In this embodiment, the underfill material 40 is NCF containing an epoxy resin. When the underfill material 40 is made of NCF, the outermost surface of the electrode 23 formed in the chip region 21 may be covered with NCF.

Next, as shown in FIG. 4B, the semiconductor wafer 20 is cut along the dicing line 22. Thereby, the individual pieces of the plurality of semiconductor chips 2 are cut out from the semiconductor wafer 20. The underfill material 40 is formed as the first sealing resin 34 that covers the element forming surface 2A of the semiconductor chip 2. That is, the individual semiconductor chip 2 includes the plurality of electrodes 23 formed on the element forming surface 2A and the first sealing resin 34 that covers the element forming surface 2A. The first sealing resin 34 may cover the outermost surfaces of the plurality of electrodes 23.

While the semiconductor chip 2 is formed, as shown in FIG. 4C, as in the first embodiment described above, a support member 24 is prepared and a plurality of second electrodes 5 are formed in the subsequent step (this embodiment). Then, four conductors 26 are formed. In the present embodiment, the conductor 26 is formed at a position corresponding to the electrode 23 of the semiconductor chip 2 and in the same area and shape as the electrode 23 in a plan view seen from the direction normal to the surface of the support member 24. It Next, the conductive bonding material 6 is formed on the conductor 26. In the present embodiment, the conductive bonding material 6 is solder, and is formed on the conductor 26 by, for example, electroless plating or electrolytic plating.

Next, as shown in FIGS. 4C and 4D, the plurality of semiconductor chips 2 are arranged in the chip arrangement regions 25 of the supporting member 24, respectively. More specifically, in the plurality of semiconductor chips 2, the electrodes 23 on the semiconductor chips 2 are overlapped with the conductors 26 on the support member 24 with the element formation surface 2A facing the surface of the support member 24. And is disposed on the support member 24. Each semiconductor chip 2 is arranged on the support member 24 with a predetermined gap from the surface of the support member 24.

Next, as shown in FIG. 4E, heat is applied to the semiconductor chip 2 to melt the first sealing resin 34 and the conductive bonding material 6. The first sealing resin 34 melts from the element forming surface 2A side of the semiconductor chip 2 toward the support member 24 while being in contact with the electrode 23, the conductor 26, and the conductive bonding material 6. The first sealing resin 34 seals the electrode 23, the conductor 26, and the conductive bonding material 6 by melting between the semiconductor chip 2 and the support member 24. By melting the conductive bonding material 6, the electrode 23 and the conductor 26 are electrically connected between the semiconductor chip 2 and the support member 24. Then, heat is applied to the semiconductor chip 2 to cure the first sealing resin 34. In this way, the semiconductor chip 2 is flip-chip bonded to the support member 24.

Next, as shown in FIG. 4F, with the plurality of semiconductor chips 2 fixed to the support member 24, the plurality of semiconductor chips 2 are collectively covered with the second sealing resin 35 containing a polyimide resin. The second sealing resin 35 seals each semiconductor chip 2 so as to cover the side portion 34B of each first sealing resin 34 and the side surface 2C and back surface 2B of each semiconductor chip 2. After that, heat is applied to each semiconductor chip 2 to cure the second sealing resin 35. As a result, the sealing structure 41 in which the plurality of semiconductor chips 2 are collectively sealed with the first sealing resin 34 and the second sealing resin 35 is formed.

Next, as shown in FIG. 4G, the support member 24 is removed from the sealing structure 41 in the same manner as in FIG. 2F described above. As a result, the conductor 26 on the support member 24 is transferred to the sealing structure 41. The connection portion of the conductor 26 transferred to the sealing structure 41 to the support member 24 is exposed from the sealing structure 41. In addition, this connecting portion has a flat surface that is flat with respect to the main surface 41A of the sealing structure 41. As a result, the electrode 23 becomes the first electrode 4, the conductor 26 becomes the second electrode 5, and the electrode layer 32 including the first electrode 4, the second electrode 5, and the conductive bonding material 6 is formed.

Next, as shown in FIG. 4H, the sealing structure 41 is cut along a dicing line 29 set between the plurality of semiconductor chips 2 by a dicing blade 28, for example. Thereby, the individual pieces of the semiconductor devices 31 are cut out from the sealing structure 41.
For example, referring to FIG. 4D, it is assumed that the gap between the semiconductor chip 2 and the support member 24 is miniaturized to the extent that it becomes difficult to pour the sealing resin as the semiconductor device is miniaturized. To be done. When the sealing resin is not sufficiently distributed in the gap between the semiconductor chip 2 and the supporting member 24, not only the sealing with the sealing resin becomes insufficient in the subsequent manufacturing process, but also the electrode 23 and the conductive material The body 26 may be displaced.

In the manufacturing method of the present embodiment, the semiconductor chip 2 including the first sealing resin 34 that covers the element forming surface 2A is placed on the support member 24, and then the first sealing resin 34 is melted. That is, the electrode 23 and the conductor 26 can be sealed with the first sealing resin 34 between the semiconductor chip 2 and the support member 24. As a result, it is not necessary to pour the sealing resin into the gap between the semiconductor chip 2 and the support member 24, so that the electrode 23 and the conductor are not restricted by the gap between the semiconductor chip 2 and the support member 24. 26 can be excellently sealed by the first sealing resin 34. Further, the first sealing resin 34 and the second sealing resin 35 can be used as a semiconductor package.

As a result, it is possible to manufacture the semiconductor device 31 which can realize miniaturization while satisfactorily eliminating the possibility that the electrodes 23 and the conductors 26 are displaced in the subsequent manufacturing process. Further, since the manufactured semiconductor device 31 can have the electrode layer 32 including the electrode 23 and the conductor 26 whose positional deviation is suppressed as the first electrode 4 and the second electrode 5, the poor connection and the like can be favorably performed. Can be suppressed.
<Third Embodiment>
FIG. 5 is a perspective sectional view of a semiconductor device 51 according to the third embodiment of the present invention. In FIG. 5, the excised portion of the semiconductor device 51 is shown separately. The semiconductor device 51 is different from the semiconductor device 31 described above in that the electrode layer 3 is formed instead of the electrode layer 32 according to the first embodiment. The other configuration of the semiconductor device 51 is substantially the same as that of the semiconductor device 31 described above. 5, parts corresponding to the parts shown in FIG. 1A, FIG. 3 and the like described above are designated by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 5, the first sealing resin 34 is formed so as to cover the electrode layer 3. More specifically, the first sealing resin 34 covers the side portion and the upper portion of the first electrode 4 so as to wrap around the region on the step portion 7 of the first electrode 4 and the second electrode 5, and The side portion of the second electrode 5 is covered so that the outermost surface of the second electrode 5 is exposed. That is, the first sealing resin 34 overlaps the first electrode 4 and surrounds the second electrode 5. In other words, the first sealing resin 34 surrounds the narrow portion protruding from the wide portion on the wide portion in the electrode layer 3 having a convex cross-section. With such a configuration, the same effects as the effects described in the first embodiment and the second embodiment described above can be obtained.
<Fourth Embodiment>
FIG. 6 is a sectional view of a semiconductor device 52 according to the fourth embodiment of the present invention. The semiconductor device 52 differs from the semiconductor device 51 described above in that it includes a redistribution structure 53. The other configuration of the semiconductor device 52 is substantially the same as that of the semiconductor device 51 described above. 6, parts corresponding to the parts shown in FIG. 5 and the like described above are designated by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 6, the rewiring structure 53 is formed on the main surface 33A on one side of the sealing resin 33. The rewiring structure 53 is electrically connected to the electrode layer 3 and is laid out from the electrode layer 3 onto the sealing resin 33, the insulating film 55 covering the rewiring 54, and the rewiring 54. A plurality of (four in the present embodiment) external terminals 56 electrically connected to the external terminals.

The redistribution line 54 may include copper, for example. The rewiring 54 is drawn from the second electrode 5 onto the main surface 33A on one side of the sealing resin 33, and is formed so as to cross the side surface 2C of the semiconductor chip 2 in a plan view. In the present embodiment, the rewiring 54 has one end 54A electrically connected to the electrode layer 3 on the first sealing resin 34 and the other end 54B drawn on the second sealing resin 35. Have

The insulating film 55 is formed on the main surface 33A on one side of the sealing resin 33 so as to cover the rewiring 54. The insulating film 55 may be an insulating film such as a silicon oxide film or a silicon nitride film, or a resin film such as polyimide. The side surface of the insulating film 55 is formed flat with respect to the side surface 33C of the sealing resin 33. External terminals 56 are embedded in the insulating film 55. More specifically, the insulating film 55 has a pad opening 58 for exposing a part of the other end portion 54B of the rewiring 54 as an electrode pad 57. External terminals 56 are embedded in the pad openings 58.

The external terminal 56 is electrically connected to the semiconductor chip 2 via the rewiring 54 and the electrode layer 3. The external terminals 56 include, for example, one or more metal species selected from the group including a copper film, a gold film, and a nickel film. The external terminal 56 may be a laminated film including a nickel film and a gold film formed in this order from the rewiring 54 side. At least a part of the external terminal 56 is located on the second sealing resin 35 in a plan view, that is, in an area outside the area surrounded by the side surface 2C of the semiconductor chip 2. That is, the semiconductor device 51 is a Fan-out type semiconductor device. Of course, the entire external terminal 56 may be located in a region outside the region surrounded by the side surface 2C of the semiconductor chip 2. The external terminal 56 may have a flat surface with respect to the surface of the insulating film 55.

In order to manufacture such a semiconductor device 51, after the peeling step of the supporting member 24 of FIG. 4G and prior to the cutting step of the sealing structure 41 of FIG. 4H, the main surface of the sealing structure 41 is formed by, for example, a sputtering method. A copper film is formed on 41A. Next, the copper film is patterned by, for example, etching through a mask to form the rewiring 54. Next, the insulating film 55 is formed by laminating a silicon nitride film on the main surface 41A of the sealing structure 41 by, for example, the CVD method.

Next, a pad opening 58 for exposing a part of the rewiring 54 as an electrode pad 57 is formed in the insulating film 55 by etching through a mask, for example. Next, a nickel film and a gold film are sequentially formed in the pad opening 58 by, for example, electroless plating or electrolytic plating. As a result, the external terminal 56 is formed. After that, the sealing structure 41 is cut and individual pieces of the plurality of semiconductor devices 52 are cut out.

Even with such a configuration, the same effects as the effects described in the first embodiment and the second embodiment can be obtained. Of course, such a rewiring structure 53 can be applied to the semiconductor device 1 according to the first embodiment described above.
Although the embodiments of the present invention have been described above, the present invention can be implemented in other forms.

For example, in each of the above-described embodiments, an example in which the first electrode 4 and the second electrode 5 are formed in a rectangular shape in plan view has been described. However, the first electrode 4 and the second electrode 5 may have a circular shape in plan view or an elliptical shape in plan view. That is, the electrode layer 3 may be formed in a columnar shape. The first electrode 4 and the second electrode 5 may be formed in a polygonal shape in plan view such as a triangular shape in plan view or a hexagonal shape in plan view. That is, the electrode layer 3 may be formed in a polygonal column shape. Further, while the first electrode 4 is formed in a circular shape in plan view, the second electrode 5 may be formed in a polygonal shape in plan view, or the second electrode 5 is formed in a circular shape in plan view. The first electrode 4 may be formed in a polygonal shape in plan view.

Further, in each of the above-described embodiments, the example in which the four external terminals 9 and 56 are formed has been described. However, two external terminals 9 and 56 may be formed, or four or more external terminals 9 and 56 may be formed. Further, solder balls may be externally connected to the external terminals 9 and 56.
In each of the above-described embodiments, the example of the semiconductor device 1, 31, 51, 52 in which one semiconductor chip 2 is sealed in the sealing resin 8, 33 has been described. However, a semiconductor device in which a plurality (two or more) of semiconductor chips 2 are encapsulated in the encapsulating resins 8 and 33 may be adopted.

Further, in each of the above-described embodiments, the process of forming the conductive bonding material 6 on the conductor 26 of the support member 24 has been described (see FIGS. 2C and 4C ). However, the conductive bonding material 6 may be formed on the electrode 23 of the semiconductor chip 2 or both of the conductor 26 of the support member 24 and the electrode 23 of the semiconductor chip 2.
Further, the first sealing resin 34 according to the above-described second to fourth embodiments can also take a form as shown in FIG. 7. FIG. 7 is a cross-sectional view of the semiconductor device 61 according to the modification. 6, parts corresponding to the parts shown in FIG. 3 and the like described above are designated by the same reference numerals, and description thereof will be omitted. As shown in FIG. 7, the first sealing resin 34 of the semiconductor device 61 is formed in a divergent shape as it goes away from the element forming surface 2A of the semiconductor chip 2 in a sectional view. That is, the first sealing resin 34 is formed in a taper shape in a sectional view.

The side portion 34B of the first sealing resin 34 may be located in a region partially surrounded by the side surface 2C of the semiconductor chip 2 in plan view. Then, the second sealing resin 35 may enter the portion where the element forming surface 2A of the semiconductor chip 2 is exposed from the first sealing resin 34. As shown in FIG. 8, such a divergent first sealing resin 34 melts divergently toward the support member 24 during the melting process of the first sealing resin 34. It is formed by

Besides, various design changes can be made within the scope of the matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor chip 2A Semiconductor chip element formation surface 2B Semiconductor chip back surface 2C Semiconductor chip side surface 4 First electrode 5 Second electrode 6 Conductive bonding material 8 Sealing resin 9 External terminal 23 Electrode (first electrode)
24 Support Member 26 Conductor (Second Electrode)
27 sealing structure 31 semiconductor device 33 sealing resin 34 first sealing resin (first insulating film)
34B Side portion of first sealing resin 35 Second sealing resin (second insulating film)
41 sealing structure 51 semiconductor device 52 semiconductor device 54 rewiring 56 external terminal 61 semiconductor device

Claims (23)

A semiconductor chip having a first main surface on one side, a second main surface on the other side, and a side surface connecting the first main surface and the second main surface;
A first electrode formed on the first main surface of the semiconductor chip;
A second electrode formed on the first electrode, having an area smaller than the area of the first electrode in plan view, and formed in a region surrounded by a peripheral edge of the first electrode;
A conductive bonding material interposed between the first electrode and the second electrode,
The first main surface, the second main surface and the side surface of the semiconductor chip are covered, and the first electrode is exposed so as to expose the surface of the second electrode on the first main surface of the semiconductor chip. A semiconductor device, comprising: an electrode, the second electrode, and a sealing resin that covers the conductive bonding material and has a surface that is flush with the surface of the second electrode . The semiconductor device according to claim 1, wherein the sealing resin also serves as a semiconductor package. The semiconductor device according to claim 1, wherein the sealing resin covers an upper portion of the first electrode and a side portion of the second electrode via the conductive bonding material. The sealing resin is a first sealing resin that covers the first electrode and the second electrode on the first main surface of the semiconductor chip, and the second main surface and the side surface of the semiconductor chip. The semiconductor device according to any one of claims 1 to 3, further comprising a second encapsulating resin that covers the. The semiconductor device according to claim 4, wherein the second sealing resin covers the first sealing resin. The first sealing resin contains at least one of an epoxy resin and a polyimide resin,
The semiconductor device according to claim 4, wherein the second sealing resin contains at least one of an epoxy resin and a polyimide resin. The semiconductor device according to claim 4, wherein the second sealing resin contains a resin material different from that of the first sealing resin. It said first electrode is made of a nickel film, a semiconductor device according to any one of claims 1 to 7. The second electrode is composed of a laminated film including a nickel film and a gold film laminated in this order from the first electrode side ,
The semiconductor device according to claim 8 , wherein the conductive bonding material is interposed between the nickel film of the first electrode and the nickel film of the second electrode . The semiconductor device according to claim 1, wherein the second electrode is formed as an external terminal that is externally connected inside the semiconductor chip in a plan view. The semiconductor device according to claim 1, further comprising a rewiring that is electrically connected to the second electrode and is drawn from the second electrode onto the sealing resin in a plan view. .. The semiconductor device according to claim 11, further comprising an external terminal electrically connected to the rewiring and externally connected at least partially outside the semiconductor chip in a plan view. It has a first main surface on one side, a second main surface on the other side, and a side surface connecting the first main surface and the second main surface, and a first electrode is formed on the first main surface. And a step of preparing the semiconductor chip
Has a flat surface, steps over the surface, have a smaller area than the area of the first electrode, and providing a support member connecting surface with respect to the surface is formed flat second electrode When,
By bonding the first electrode to the second electrode via a conductive bonding material so that the second electrode is located in a region surrounded by the periphery of the first electrode, the surface of the support member is formed. A chip fixing step of fixing the semiconductor chip on the
The first electrode, the second main surface of the semiconductor chip, the second main surface and the side surface are covered, and the first electrode, the first main surface of the semiconductor chip and the surface of the supporting member are provided between the first electrode and the second electrode. By forming a sealing resin that covers the two electrodes and the conductive bonding material, the semiconductor chip, the first electrode, the second electrode, and the conductive bonding material are sealed with the sealing resin. A sealing structure forming step of forming a stop structure,
By removing the supporting member from the sealing structure, the second electrode formed on the supporting member is transferred to the sealing structure, and at the same time, the surface is flush with the surface of the second electrode. A transfer step of taking out the sealing structure ,
A method of manufacturing a semiconductor device, which comprises a step of cutting individual pieces of a semiconductor device by selectively cutting the sealing structure. In the encapsulation structure forming step, the encapsulation resin covers an upper portion of the first electrode between the semiconductor chip and the support member via the conductive bonding material and a side portion of the second electrode. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the method is formed so as to cover. The semiconductor chip includes a first sealing resin that covers the first main surface,
In the chip fixing step, the first sealing resin is melted to seal the first electrode and the second electrode between the first main surface of the semiconductor chip and the surface of the support member in the first sealing. Sealing with a stop resin, and electrically connecting the first electrode and the second electrode,
14. The encapsulation structure forming step includes a step of forming the encapsulation structure by covering the second main surface and the side surface of the semiconductor chip with a second encapsulation resin as the encapsulation resin. Alternatively, the method of manufacturing a semiconductor device according to Item 14. The chip fixing step includes a step of fixing a plurality of the semiconductor chips to the support member,
The method for manufacturing a semiconductor device according to claim 13, wherein the sealing structure forming step includes a step of collectively covering the plurality of semiconductor chips with the sealing resin. 17. The semiconductor device according to claim 13, wherein the transfer step also serves as a step of forming the second electrode as an external terminal to be externally connected inside the semiconductor chip in a plan view. Production method. After the transferring step, prior to the individualizing step, a rewiring forming step of forming a rewiring drawn out from the second electrode onto the sealing structure in a plan view is further included. The method for manufacturing a semiconductor device according to any one of 1. 19. The method according to claim 18, further comprising: after the rewiring forming step, forming an external terminal electrically connected to the rewiring and externally connected at least partially outside the semiconductor chip in a plan view. Of manufacturing a semiconductor device of. The supporting member is a plate-shaped member that can form the second electrode and that can be peeled from the sealing structure.
The method of manufacturing a semiconductor device according to claim 13, wherein the step of removing the supporting member includes a step of peeling the plate-shaped member from the sealing structure. The method for manufacturing a semiconductor device according to claim 20, wherein the plate-shaped member is made of a metal plate containing stainless steel or copper. The support member is a plate-shaped member capable of forming the second electrode and capable of being etched,
The method of manufacturing a semiconductor device according to claim 13, wherein the step of removing the supporting member includes a step of removing the plate-shaped member by etching. 23. The method of manufacturing a semiconductor device according to claim 22, wherein the plate member is a semiconductor plate.

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