JP6720062B2 - Evaluation method - Google Patents

Description

The present invention relates to a method for evaluating a heterojunction composed of different kinds of nitride semiconductors.

A device using a heterojunction composed of different kinds of nitride semiconductors is drawing attention. The nitride semiconductor is a general term for GaN, AlN, and InN, and a ternary mixed crystal semiconductor and a quaternary mixed crystal semiconductor thereof. These nitride semiconductors are characterized by having (1) a large bandgap and (2) a large dielectric breakdown electric field as compared with silicon, and are materials constituting a high-power element capable of operating at high temperatures. This is because it is considered as promising.

An example of a heterojunction of a nitride semiconductor is an AlGaN/GaN heterojunction obtained by forming an AlGaN layer on a GaN layer. A high electron mobility transistor (HEMT) is an example of a device using a heterojunction of a nitride compound. In the following, a heterojunction of AlGaN/GaN will be described as an example. Unless otherwise specified, the heterojunction refers to an AlGaN/GaN heterojunction.

The characteristics of the device using the AlGaN/GaN heterojunction strongly depend on the density of the localized level (interface level) generated at the junction interface of the heterojunction. Therefore, it is important to evaluate the interface state density of the heterojunction, that is, the interface state density D _it , prior to device fabrication. As a method of evaluating _Dit of a heterojunction, the conductance method described in Non-Patent Documents 1 to 3 and the High-Low method described in Non-Patent Documents 1 to 5 are known.

Conductance method, while changing the applied voltage to measure the frequency dependency of the conductance of the heterojunction, by comparing the conductance curve at high and low frequency, deriving a D _it heterozygous. In the conductance method, it is possible to obtain the electron capture/emission time constant and the capture cross section σ. The position of the level can be obtained by assuming the thermal velocity V _th of the carrier at the measurement temperature and the electron density N _c of the conductor.

High-Low method is by comparing the voltage dependence of the capacitance at high frequency and 1kHz or lower frequency than the _1kHz, to derive a _{D it.} In the High-Low method, in order to derive D _it , the oxide film capacitance C _ox and the impurity concentration of the substrate are assumed. Further, it is premised that the high frequency limit is obtained in the voltage dependence of the capacitors to be compared. When the frequency of the AC signal is increased in order to compare the voltage dependence of the capacitance of the heterojunction, the electrons trapped in the interface state become unable to respond to the AC signal as the frequency of the AC signal increases. When the frequency of the AC signal becomes high enough that electrons trapped in the interface state cannot respond, only the electrons that are majority carriers can respond to the AC signal. In this case, the curve showing the voltage dependence of the capacitance of the heterojunction approximately matches the ideal curve. In this way, when the frequency is sufficiently high, the fact that the curve showing the voltage dependence of the capacitance of the heterojunction and the ideal curve approximately match is referred to as "high frequency limit has been obtained".

Note that the High-Low method may underestimate _Dit if the high-frequency and low-frequency capacitance measurements are not sufficient. That is, the interface characteristics of the heterojunction tend to be evaluated favorably. _Therefore, if you want more precise evaluation of _{D it} is preferably to use a conductance method from High-Low method.

E. H. Nicollian and J. R. Brews, MOS Physics and Technology (Wiley, New York, 1982). D. K. Schroder, Semiconductor material and Device Characterization (Wiley, New Jersey, 2006). R. Engel-Herbert et al., Journal of Applied Physics 108, 124101 (2010). M. Xu et al., Journal of Applied Physics 113, 013711 (2013). C. Y. Chang et al., Applied Physics Letter 102, 093506 (2013). J. J. Freedsman et al., Applied Physics Letter 99, 033504 (2011). J. J. Freedsman et al., Applied Physics Letter 101, 013506 (2012).

Operable structure as HEMT and even when using a substrate (e.g. a silicon substrate) heterojunction AlGaN / GaN are formed using any of the High-Low method and conductance method for evaluating the _{D it,} That is, a heterojunction is processed into a mesa shape, and a FET structure in which a gate electrode, a source electrode, and a drain electrode are formed on the upper surface of the mesa shape is manufactured (for example, see Non-Patent Documents 6 and 7).

However, in order to evaluate the _Dit of the heterojunction using the FET structure, _it is naturally necessary to carry out a manufacturing process for manufacturing the FET structure, which is troublesome. For example, as is the case for the purpose of quality evaluation of substrate heterojunction AlGaN / GaN is formed, without regard to the structure of the heterojunction to be used for evaluation, there is a desire to assess D _it as much as possible simplified ..

The present invention has been made in view of the above problems, and an object thereof is to provide an evaluation method capable of easily evaluating the interface characteristics of a heterojunction composed of different kinds of nitride semiconductors. is there.

In order to solve the above problems, an evaluation method according to one aspect of the present invention is a method for evaluating a heterojunction composed of different kinds of nitride semiconductors, wherein the surface of the heterojunction has a first annular shape. An electrode and a second electrode disposed inside the inner edge of the first electrode and separated from the first electrode are formed, and a plurality of electrodes are provided between the first electrode and the second electrode. The frequency dependence of the conductance between the first electrode and the second electrode is measured in each of the states in which the bias voltage is applied, and based on the frequency dependence of the conductance corresponding to each of the plurality of bias voltages. And an interface state density deriving step of deriving the interface state density of the heterojunction.

According to the above configuration, the annular first electrode and the second electrode arranged inside the inner edge of the first electrode and separated from the first electrode form a heterojunction formed on the surface thereof. It can be used to evaluate the interface state density of a heterojunction. That is, the production of the FET structure becomes unnecessary. Therefore, by using this evaluation method, the interface characteristics of the heterojunction composed of different kinds of nitride semiconductors can be easily evaluated.

In the evaluation method according to one aspect of the present invention, each of the curves forming the inner edge of the first electrode and the outer edge of the second electrode is circular, and the second electrode has the outer edge as the inner edge. It is preferable that they are arranged concentrically.

According to the above configuration, when an electric field is applied to the second electrode, the shape of the electric field formed between the second electrode and the first electrode is isotropic. Therefore, it becomes easy to calculate the capacitance generated between the second electrode and the first electrode. As a result, the interface state density can be derived more easily.

In the evaluation method according to one aspect of the present invention, the contact between the first electrode and the surface of the heterojunction may be ohmic contact.

According to the above configuration, it is possible to prevent a capacitance from being generated between the first electrode and the surface. Therefore, accuracy in deriving the interface state density in the interface state density deriving step can be improved.

The evaluation method according to one aspect of the present invention can be suitably used for a heterojunction composed of a GaN layer and an AlGaN layer formed on the surface of the GaN layer.

An evaluation method according to one aspect of the present invention is a specific range determination step that determines a specific range in the interface state density of a heterojunction composed of different kinds of nitride semiconductors, and the above-mentioned derived in the interface state density derivation step. A comparison step of comparing the interface state density with the specific range, and depending on the result of the comparison step, (1) determines that the heterojunction is acceptable when the interface state density is within the specific range, (2) It is preferable that the method further includes a determination step of determining the heterojunction as a failure when the interface state density is not within the specific range.

According to the above configuration, it is possible to determine whether the interface state density of the heterojunction is acceptable or not.

The present invention can provide an evaluation method capable of easily evaluating the interface characteristics of a heterojunction composed of different kinds of nitride semiconductors.

It is a flow chart which shows the evaluation method concerning a 1st embodiment of the present invention. (A) is a cross-sectional view of the heterojunction before performing the etching step included in the flowchart shown in FIG. 1. (B) is a cross-sectional view of the heterojunction after the etching process is performed. FIG. 3C is a cross-sectional view of the heterojunction after the electrode forming step included in the flowchart shown in FIG. 1 is performed. FIG. 3A is a cross-sectional view of a heterostructure for performing the interface state density derivation step included in the flowchart shown in FIG. 1. (B) is a plan view of the heterostructure shown in (a). FIG. 3 is a circuit diagram of a measurement system that performs an interface state density deriving step included in the flowchart shown in FIG. (A) is a circuit diagram which shows the equivalent circuit of the heterostructure shown in FIG. (B) is a circuit diagram showing a simplified circuit of the equivalent circuit of (a). (C) is a circuit diagram showing a measurement circuit for measurement in the interface state density deriving step included in the flowchart shown in FIG. 1. FIG. 4 is an energy band diagram of the heterostructure shown in FIG. 3. (A) is a graph which shows the conductance curve of the heterojunction which is the 1st Example of this invention, (b) is a graph which shows the bias voltage dependence of the interface state density of the same heterojunction. (C) is a graph showing a conductance curve of a heterojunction that is the second embodiment of the present invention, and (d) is a graph showing the bias voltage dependence of the interface state density of the heterojunction. (E) is a graph showing a conductance curve of the heterojunction according to the third embodiment of the present invention, and (f) is a graph showing the bias voltage dependence of the interface state density of the heterojunction. It is a flowchart which shows the evaluation method which concerns on the 2nd Embodiment of this invention. (A) is a graph which shows the conductance curve of the heterojunction which is the 4th Example of this invention, (b) is a graph which shows the bias voltage dependence of the interface state density of the same heterojunction. (C) is a graph showing a conductance curve of a heterojunction according to a fifth embodiment of the present invention, and (d) is a graph showing a bias voltage dependence of an interface state density of the heterojunction. (E) is a graph showing a conductance curve of the heterojunction according to the sixth embodiment of the present invention, and (f) is a graph showing the bias voltage dependence of the interface state density of the heterojunction. It is a flowchart which shows the evaluation method which concerns on the 3rd Embodiment of this invention. FIG. 11A is a cross-sectional view of the heterojunction before the first electrode forming step included in the flowchart shown in FIG. 10 is performed. FIG. 11B is a cross-sectional view of the heterojunction before performing the heating step included in the flowchart shown in FIG. 10. (C) is a cross-sectional view of the heterojunction after the heating step is performed. FIG. 11D is a cross-sectional view of the heterojunction after the second electrode forming step included in the flowchart shown in FIG. 10 is performed. It is a flowchart which shows the evaluation method which concerns on the 4th Embodiment of this invention. (A) is sectional drawing of the heterostructure which is a comparative example of this invention. (B) is a plan view of the same heterostructure. (A) And (b) is a graph which shows the conductance curve of the heterostructure which is the comparative example shown in FIG.

[First Embodiment]
An evaluation method according to the first embodiment of the present invention will be described with reference to FIGS. This evaluation method is an evaluation method of a heterojunction composed of different kinds of nitride semiconductors. More specifically, _it is an evaluation method for evaluating the density of localized levels (interface levels) generated at the junction interface of the heterojunction, that is, the interface level density D _it .

FIG. 1 is a flowchart showing this evaluation method.

FIG. 2A is a cross-sectional view of the heterojunction before performing the etching step S12. FIG. 2B is a cross-sectional view of the heterojunction after performing the etching step S12. FIG. 2C is a cross-sectional view of the heterojunction after performing the electrode forming step S14. The cross-sectional views of FIGS. 2A to 2C are cross-sectional views taken along the line AA shown in FIG.

FIG. 3A is a cross-sectional view of the heterostructure 10 for performing the interface state density deriving step S16 included in the present evaluation method. This sectional view is a sectional view taken along a line AA shown in FIG. FIG. 3B is a plan view of the hetero structure 10.

FIG. 4 is a circuit diagram of a measurement system that implements the interface state density derivation step S16.

Each of FIG. 5 (a) ~ (c) is a circuit diagram showing a circuit used to derive D _it in the interface state density deriving step S16. FIG. 5A is a circuit diagram showing an equivalent circuit of the heterostructure 10. FIG. 5B is a circuit diagram showing a simplified circuit of the equivalent circuit of FIG. FIG. 5C is a circuit diagram showing a measurement circuit measured by the LCR meter 30 described later.

FIG. 6 is an energy band diagram of the heterostructure 10.

As shown in FIG. 1, the present evaluation method includes an etching step S12, an electrode forming step S14, and an interface state density deriving step S16.

In the present embodiment, the present evaluation method will be described using GaN and AlGaN as different kinds of nitride semiconductors. As shown in FIG. 2A, the heterojunction 13 used in the description of the present evaluation method is an AlGaN/GaN heterojunction obtained by forming the AlGaN layer 132 on the GaN layer 131. A 2DEG (two-dimensional electron gas) 131a is formed near the bonding interface in the GaN layer 131.

The heterojunction 13 is formed on the silicon substrate 11 via the buffer layer 12 (see FIG. 3A). The silicon substrate 11 has a (111) orientation.

(Etching step S12)
In the etching step S12, in order to separate a region used for evaluating the interface state density (a region where a first electrode 15 and a second electrode 16 described later are formed) from the other region on the surface 13a of the heterojunction 13. This is a process to be carried out. Specifically, the AlGaN layer 132 located at the outer edge of the region used for evaluating the interface state density and a part of the GaN layer 131 are etched (see FIG. 2B).

As a technique for etching the outer edge of the region used for evaluating the interface state density, a method for producing an existing HEMT may be adopted. For example, reactive ion etching (RIE) can be used to etch the AlGaN layer 132 and a portion of the GaN layer 131.

(Electrode forming step S14)
The electrode forming step S14 is a step of forming the first electrode 15 and the second electrode 16 on the surface 13a of the heterojunction 13 (see (c) of FIG. 2). As shown in FIG. 3B, the first electrode 15 is an annular electrode having an outer edge that is rectangular and an inner edge 151 that is circular. The second electrode 16 is an electrode that is arranged inside the inner edge 151 and is separated from the first electrode 15.

As a method of forming the first electrode 15 and the second electrode 16, a method for manufacturing an existing high electron mobility transistor (HEMT) may be adopted. As a material forming the first electrode 15 and the second electrode 16, for example, a metal multilayer film such as Au/Ni or Al/Au/Ni, or a metal single layer film such as Ni can be adopted. As a technique for forming a mask that determines the electrode patterns of the first electrode 15 and the second electrode 16, for example, photolithography technique can be adopted.

As described above, by performing the etching step S12 and the electrode forming step S14, it is possible to obtain the heterostructure 10 in which the first electrode 15 and the second electrode 16 are formed on the surface 13a of the heterojunction 13. Unlike the heterostructure 50 of the comparative example, which will be described later with reference to FIG. 13, the heterostructure 10 does not need to have a FET structure. Therefore, by using this evaluation method, the interface characteristics of the heterojunction composed of different kinds of nitride semiconductors can be easily evaluated.

Further, in the heterostructure 10, the first electrode 15 is formed so as to surround the second electrode 16 (see (b) of FIG. 3 ). Therefore, when a voltage is applied between the first electrode 15 and the second electrode 16, the current flowing between the first electrode 15 and the second electrode 16 is confined inside the inner edge 151. That is, the heterostructure 10 can prevent the current from leaking to the outside of the first electrode 15. Therefore, in this evaluation method, the etching step S12 can be omitted. By omitting the etching step S12, the heterostructure 10 can be manufactured more easily. Therefore, it becomes easier to evaluate the interface characteristics of the heterostructure 10.

Further, (1) each of the curved lines forming the inner edge 151 of the first electrode 15 and the outer edge 161 of the second electrode 16 is circular, and (2) the outer edge 161 of the second electrode 16 has the outer edge 161 of the first electrode 15. It is preferably arranged so as to be concentric with the inner edge 151 (see FIG. 3B).

According to this structure, when an electric field is applied between the first electrode and the second electrode, an isotropic electric field is formed between the first electrode and the second electrode. Therefore, it becomes easy to calculate the capacitance generated between the first electrode and the second electrode. As a result, the present evaluation method can more easily derive the D _{it of the} heterojunction 13.

The evaluation method may further include a passivation film forming step after the electrode forming step S14. The passivation film forming step is a step of forming a passivation film on the surface of the heterostructure 10. The passivation film is, for example, a SiN film and has a function of rendering the surface of the heterostructure 10 non-conducting. The passivation film can be formed by using an existing technique such as a CVD method.

(Interface state density derivation step S16)
In the interface state density derivation step S16, the conductance G _m between the first electrode 15 and the second electrode 16 in each of the states in which a plurality of bias voltages are applied between the first electrode 15 and the second electrode 16. the frequency-dependent measure is a step of deriving a D _it heterojunction 13 on the basis of the frequency dependence of G _m corresponding to each of the plurality of bias voltages. An existing measuring method can be adopted as the measuring method of the conductance. In the present embodiment, as shown in FIG. 4, a measurement method using an LCR meter 30 will be described as an example. As the LCR meter 30, for example, an E4980A precision LCR meter manufactured by Agilent can be used.

(1. Measurement of G _m and C _m )
In order to connect to the LCR meter 30, the terminal 152 is wired to the first electrode 15 and the terminal 162 is wired to the second electrode 16. The terminal 152 is collectively connected to the negative terminal of the LCR meter 30. The terminal 162 is connected to the positive terminal of the LCR meter 30. The connection mode between the LCR meter and the first electrode 15 and the second electrode 16 of the heterostructure 10 may be appropriately changed according to the specifications of the LCR meter used.

The LCR meter 30 includes an AC current source 31, a DC voltage source 32, an ammeter 33, and a voltmeter 34. The alternating current source 31 generates an alternating current signal flowing between the first electrode 15 and the second electrode 16 and supplies the alternating current signal to the heterostructure 10. The DC voltage source 32 is a variable voltage source and controls the bias voltage applied between the first electrode 15 and the second electrode 16. The ammeter 33 detects the current flowing between the first electrode 15 and the second electrode 16. The voltmeter 34 detects the voltage generated between the first electrode 15 and the second electrode 16.

By using the LCR meter 30 configured as described above, in the state where a predetermined bias voltage is applied between the first electrode 15 and the second electrode 16, the voltage between the first electrode 15 and the second electrode 16 is increased. The conductance G _m and the capacitance C _m are measured.

LCR meter 30, in a state of applying the first bias voltage, by changing the frequency of the AC signal alternating current source 31 to produce, measuring the frequency dependence of G _m and C _m.

After measuring the frequency dependence of G _m and C _m of the heterostructure 10 for the first bias voltage, the DC voltage source 32 changes the bias voltage to the second bias voltage. LCR meter 30, in a state of applying the second bias voltage, to measure the frequency dependence of _{G m} and _{C m.}

As described above, in the interface state density derivation step S16, the value of the bias voltage is sequentially changed from the first voltage to the nth voltage (n is an integer), and G _m and G corresponding to each voltage are changed. The frequency dependence of C _m is measured.

(2. Derivation of D _it )
The interface state density deriving step S16 derives D _it based on the measured G _m and C _m . Method for deriving the D _it is known as the conductance method as described in Non-Patent Documents 1 to 3. The conductance method uses the equivalent circuit, the simplification circuit, and the measurement circuit of the heterostructure 10 shown in each of FIGS.

In FIG. 5A, C _ox is the capacitance of the AlGaN layer 132, C _s is the depletion layer capacitance of the GaN layer 131, R _it is the interface resistance of the heterojunction 13, and C _it is the heterojunction 13. Is the interfacial capacity of. In FIG. 5B, C _p and G _p are parallel capacitance and parallel conductance when C _s , R _it, and C _it are simplified.

The combined admittance Y _m in the measurement circuit is given by equation (1).

等価回路（図５の（ａ））及び単純化回路（図５の（ｂ））より、式（２）〜式（３）が得られる。

Expressions (2) to (3) are obtained from the equivalent circuit ((a) of FIG. 5) and the simplified circuit ((b) of FIG. 5).

なお、各パラメータは、以下のように対応している。

In addition, each parameter corresponds as follows.

また、単純化回路（図５の（ｂ））及び測定回路（図５の（ｃ））おり、式（４）が得られる。なお、ｑは電子の電荷量であり、ωは交流信号の角周波数であり、ｆは交流信号の周波数であり、τ_ｉｔは界面準位の遅延時間である。

Further, since there is a simplified circuit ((b) in FIG. 5) and a measurement circuit ((c) in FIG. 5), the equation (4) is obtained. Note that q is the charge amount of electrons, ω is the angular frequency of the AC signal, f is the frequency of the AC signal, and τ _it is the delay time of the interface state.

界面準位密度導出工程Ｓ１６は、上述した（１．Ｇ_ｍ，Ｃ_ｍの測定）で測定した、コンダクタンスの周波数依存性から、式（４）のＧ_ｐ／ωを求める。そのうえで、得られた式（４）のＧ_ｐ／ωを式（３）でフィッティングすることによって、式（３）中のＤ_ｉｔ及びτ_ｉｔを導出することができる。なお、界面準位密度導出工程Ｓ１６は、複数のバイアス電圧の各々に対応するコンダクタンスの周波数依存性を測定しているため、複数のバイアス電圧の各々に対応するＤ_ｉｔ及びτ_ｉｔを導出することができる。

In the interface state density derivation step S16, G _p /ω of the equation (4) is obtained from the frequency dependence of the conductance measured in the above (1. G _m , C _m measurement). Then, by fitting the obtained G _p /ω in the equation (4) with the equation (3), D _it and τ _it in the equation (3) can be derived. Incidentally, the interface state density deriving step S16, because it measures the frequency dependency of the conductance corresponding to each of the plurality of bias voltages, deriving a D _it and tau corresponds to each of the plurality of bias voltages You can

As described above, the interface state density deriving step S16, to a D _it heterojunction 13, it is possible to derive a D _it corresponding to each of the plurality of bias voltages.

(Band structure of heterojunction 13)
As shown in FIG. 6, a forbidden band occurs between the energy level E _V of the valence band and the energy level E _C of the conduction band of the GaN layer 131. At the junction interface of the heterojunction 13, a plurality of interface states (5 interface states are schematically shown in FIG. 6) are generated. This is because discontinuity DE _{it of the} crystal structure occurs at the junction interface due to the difference in the lattice constant of the GaN layer 131 and the lattice constant of the AlGaN layer 132 (see (a) of FIG. 3 ).

In the heterostructure 10, the electrons trapped in the interface state of the heterojunction 13 absorb the energy of the AC signal flowing between the first electrode 15 and the second electrode 16, and thus the conduction band of the GaN layer 131. Excited to E _C. In the interface state density deriving step S16 described above, while varying the bias voltage applied between the first electrode 15 and the second electrode 16, to derive the D _it corresponding to a plurality of bias voltages. Changing the bias voltage corresponds to changing the Fermi level E _F at the heterojunction 13. Also, changing the bias voltage corresponds to changing the difference E _C -E _T the electron energy level E _T which has been captured and E _C.

Therefore, by deriving the D _it corresponding to a plurality of bias voltages, it is possible to evaluate the energy distribution of D _it. Specifically, the larger the bias voltage, it is possible to evaluate the D _it deep interface state.

(First to third embodiments)
For _{D it} of the first to heterostructure 10A~10C according to a third embodiment of the present invention will be described with reference to FIG. 7A is a graph showing the frequency dependence of G _p /ω of the heterostructure 10A, and FIG. 7B is a graph showing the bias voltage dependence of D _it of the heterostructure 10A. Hereinafter, the frequency dependence of G _p /ω is referred to as a conductance curve. 7C is a graph showing the conductance curve of the heterostructure 10B, and FIG. 7D is a graph showing the bias voltage dependence of D _it of the heterostructure 10B. FIG. 7E is a graph showing the conductance curve of the heterostructure 10C, and FIG. 7F is a graph showing the bias voltage dependence of D _it of the heterostructure 10C.

The heterostructures 10A to 10C have a common configuration except that the AlGaN layer 132 has a different thickness. The configurations of the heterostructures 10A to 10C are as follows.

As the silicon substrate 11, a silicon wafer having a plane orientation of (111) was adopted.

As the buffer layer 12, a multilayer structure of AlN/AlGaN is adopted. The thickness of the buffer layer 12 is 3500 nm.

The GaN layer 131 was formed using the MOCVD method. The GaN layer 131 has a thickness of 750 nm.

The AlGaN layer 132 was formed using the MOCVD method. The thickness of the AlGaN layer 132 is 20 nm in the heterostructure 10A, 35 nm in the heterostructure 10B, and 60 nm in the heterostructure 10C.

The first electrode 15 and the second electrode 16 are made of Al/Au/Ni. The thickness of each of the first electrode 15 and the second electrode 16 is 180/30/20 nm for each of Al/Au/Ni.

Regarding the heterostructure 10A, a conductance curve corresponding to each bias voltage was obtained while changing the bias voltage in the range of -2.05 V or more and -1.85 V or less. In FIG. 7A, the conductance curves obtained when the bias voltages are -2.05V, -2.00V, -1.95V, -1.90V, and -1.85V are shown.

Regarding the heterostructure 10B, a conductance curve corresponding to each bias voltage was obtained while changing the bias voltage in the range of −3.85 V to −3.55 V. In FIG. 7C, the conductance curves obtained when the bias voltages are -3.85V, -3.70V, -3.65V, -3.60V, and -3.55V are shown.

Regarding the heterostructure 10C, the conductance curve corresponding to each bias voltage was obtained while changing the bias voltage in the range of −6.45 V or more and −6.25 V or less. FIG. 7E shows the conductance curves obtained when the bias voltage is −6.45V, −6.40V, −6.35V, −6.30V, −6.25V.

Dits of the heterostructures 10A, 10B and 10C derived from the conductance curves corresponding to the respective bias voltages are shown in (b), (d) and (f) of FIG. 7, respectively.

From the results of (b), (d), and (f) of FIG. 7, the present evaluation method is used even when the heterostructures 10A to 10C having the electrode structure which can be manufactured more easily than the FET structure are used. It was found to be capable of evaluating the D _it by.

[Second Embodiment]
An evaluation method according to the second embodiment of the present invention will be described with reference to FIG. FIG. 8 is a flowchart showing this evaluation method. The evaluation method according to the present embodiment is an evaluation method for a heterojunction composed of different kinds of nitride semiconductors, like the evaluation method according to the first embodiment.

The evaluation method according to the present embodiment differs from the evaluation method according to the first embodiment in the step of forming an electrode on the surface of the heterojunction. In the present embodiment, the process of forming this electrode will be mainly described.

As shown in FIG. 8, the present evaluation method includes an etching step S21, a first electrode forming step S22, a heating step S23, a second electrode forming step S24, and an interface state density deriving step S26. I'm out.

In this embodiment, as in the first embodiment, GaN and AlGaN are used as different kinds of nitride semiconductors. That is, also in this embodiment, the AlGaN/GaN heterojunction obtained by forming the AlGaN layer on the GaN layer is used.

(Etching step S21)
The etching step S21 corresponds to the etching step S12 shown in FIG. Therefore, a detailed description thereof will be omitted here.

(First electrode forming step S22)
The first electrode forming step S22 is a step of forming an annular first electrode on a part of the surface of the heterojunction. The shape of the first electrode of the present embodiment is the same as the shape of the first electrode 15 shown in FIG.

As a method for forming the first electrode, a method for manufacturing an existing high electron mobility transistor (HEMT) may be adopted. As a material forming the first electrode, for example, a metal multilayer film such as Au/Ti/Al/Ti or Au/Mo/Al/Ti can be used. Moreover, as a technique for forming a mask that determines the electrode pattern of the first electrode, for example, a photolithography technique can be adopted.

(Heating step S23)
The heating step S23 is a step performed after the first electrode forming step S22. The heating step S23 is a heating step of heating (annealing) the heterojunction on which the first electrode is formed to bring the first electrode and the surface of the heterojunction into ohmic contact. By heating the heterojunction on which the first electrode is formed, the contact at the interface between the first electrode and the heterojunction becomes ohmic contact.

As a method for heating the heterojunction, a method for producing a source electrode and a drain electrode (an electrode in ohmic contact with the heterojunction) of the existing HEMT may be adopted. To heat the heterojunction, for example, a short-time heat treatment device (RTA: Rapid Thermal Anneal) can be used.

(Second electrode forming step S24)
The second electrode forming step S24 is a step of forming the second electrode on a part of the surface of the heterojunction. The shape of the second electrode of the present embodiment is the same as the shape of the second electrode 16 shown in FIG. By performing the second electrode forming step S24, a heterostructure in which the first electrode and the second electrode are formed on a part of the surface of the heterojunction is obtained.

The second electrode of the present embodiment can be formed using the same method as the first electrode 15 and the second electrode 16 of the first embodiment.

(Interface state density derivation step S26)
The interface state density deriving step S26 corresponds to the interface state density deriving step S16 shown in FIG. Therefore, a detailed description thereof will be omitted here.

According to this evaluation method, the contact between the first electrode and the surface of the heterojunction is ohmic contact. As a result, it is possible to prevent a capacitance from being generated between the first electrode and the surface of the heterojunction, so that the accuracy in deriving the interface state density D _it in the interface state density deriving step S26 described later can be improved. Can be increased.

In this evaluation method as well, the etching step S21 can be omitted, as in the evaluation method according to the first embodiment. By omitting the etching step S21, the heterostructure can be formed more easily. Therefore, it becomes easier to evaluate the interface characteristics of the heterojunction.

(Fourth to Sixth Embodiments)
For _{D it} of the fourth to sixth heterostructure 20A~20C an embodiment of the present invention will be described with reference to FIG. The heterostructures 20A to 20C are heterostructures in which the first electrode and the second electrode are formed by performing the etching step S21 to the second electrode forming step S24 shown in FIG. 8, respectively.

9A is a graph showing the frequency dependence of G _p /ω of the heterostructure 20A, and FIG. 9B is a graph showing the bias voltage dependence of D _it of the heterostructure 20A. Hereinafter, the frequency dependence of G _p /ω is referred to as a conductance curve. 9C is a graph showing the conductance curve of the heterostructure 20B, and FIG. 9D is a graph showing the bias voltage dependence of D _it of the heterostructure 20B. 9E is a graph showing the conductance curve of the heterostructure 20C, and FIG. 9F is a graph showing the bias voltage dependence of D _it of the heterostructure 20C.

The heterostructures 20A to 20C are configured similarly to the heterostructures 10A to 10C, respectively, except that the method of forming electrodes is different.

The first electrode is composed of Au/Ti/Al/Ti. The thickness of the first electrode is 30/25/90/25 nm for each of Au/Ti/Al/Ti.

In the heating step S23, the heating temperature was 850° C. and the heating time was 30 seconds.

The second electrode is made of Al/Au/Ni. The thickness of the second electrode is 180/30/20 nm for each of Al/Au/Ni.

Regarding the heterostructure 20A, a conductance curve corresponding to each bias voltage was obtained while changing the bias voltage in the range of −1.55 V to −1.35 V. In FIG. 9A, the conductance curves obtained when the bias voltages are −1.55V, −1.50V, −1.45V, −1.40V, −1.35V are shown.

Regarding the heterostructure 20B, a conductance curve corresponding to each bias voltage was obtained while changing the bias voltage in the range of −3.80 V to −3.60 V. In FIG. 9C, the conductance curves obtained when the bias voltages are −3.80 V, −3.75 V, −3.70 V, −3.65 V, −3.60 V among them are shown.

Regarding the heterostructure 20C, a conductance curve corresponding to each bias voltage was obtained while changing the bias voltage in the range of −6.65 V or more and −6.45 V or less. FIG. 9(e) shows the conductance curves obtained when the bias voltage is −6.65V, −6.60V, −6.55V, −6.50V, −6.45V.

Dit of the heterostructures 20A, 20B and 20C derived from the conductance curves corresponding to the respective bias voltages are shown in (b), (d) and (f) of FIG. 9, respectively.

From the results of (b), (d), and (f) of FIG. 9, the present evaluation method is used even when the heterostructures 20A to 20C having the electrode structure which can be manufactured more easily than the FET structure are used. It was found to be capable of evaluating the D _it by.

[Third Embodiment]
An evaluation method according to the third embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a flowchart showing the evaluation method according to this embodiment. 11A is a cross-sectional view of the heterojunction 33 before performing the first electrode forming step S32 included in the flowchart shown in FIG. 10 (after performing the etching step S31). 11B is a cross-sectional view of the heterojunction 33 before the heating step S33 included in the flowchart shown in FIG. 10 is performed. FIG. 11C is a cross-sectional view of the heterojunction 33 after performing the heating step S33. 11D is a cross-sectional view of the heterojunction 33 (heterostructure 30) after the second electrode formation step included in the flowchart shown in FIG. 10 is performed.

This evaluation method is, like the evaluation method shown in FIG. 1, a method for evaluating a heterojunction composed of different kinds of nitride semiconductors. More specifically, _it is an evaluation method for evaluating the density of localized levels (interface levels) generated at the junction interface of the heterojunction, that is, the interface level density D _it .

As shown in FIG. 10, the present evaluation method includes an etching step S31, a first electrode forming step S32, a heating step S33, a second electrode forming step S34, and an interface state density deriving step S36. I'm out. The first electrode forming step S32 to the interface state density deriving step S36 correspond to the first electrode forming step S22 to the interface state density deriving step S26 shown in FIG. 8, respectively. That is, this evaluation method is obtained by replacing the etching step S21 with the etching step S31 in the evaluation method shown in FIG.

Also in the present embodiment, the present evaluation method will be described using GaN and AlGaN as different kinds of nitride semiconductors. The heterojunction 33 before performing the present evaluation method has the same structure as the heterojunction 13 shown in FIG. That is, the heterojunction 33 is an AlGaN/GaN heterojunction obtained by forming the AlGaN layer 332 on the GaN layer 131.

(Etching step S31)
The etching step S31 is performed before the first electrode forming step S32. The etching step S31 is a step of forming an annular recess 332a in a part of the surface 33a of the heterojunction 33.

As a method of forming the recess 332a, a method for manufacturing an existing HEMT may be adopted. For example, the surface 33a of the heterojunction 33 can be etched using reactive ion etching (RIE).

The thickness of the AlGaN layer 332 in the region where the recess 332a is formed may be any thickness that can achieve ohmic contact between the first electrode 35 and the heterojunction 33 after the heating step S33 described below is performed.

(First electrode forming step S32)
Similar to the first electrode forming step S22, the first electrode forming step S32 is a step of forming the annular first electrode 35 on a part of the surface 33a of the heterojunction 33 (see FIG. 11B). ). However, in the first electrode forming step S32, the first electrode 35 is formed inside the recess 332a (a region sandwiched between the inner edge and the outer edge of the recess 332a). Similar to the first electrode 15 (see FIG. 3B), the first electrode 35 is an annular electrode having an inner edge 351 and an outer edge.

In the heterojunction 33 shown in FIG. 11B, the contact at the interface between the first electrode 35 and the heterojunction 33 is Schottky contact.

As a method for forming the first electrode 35, a method for producing a source electrode and a drain electrode (an electrode that makes ohmic contact with a heterojunction) of an existing HEMT may be adopted. As a material forming the first electrode 35, for example, a metal multilayer film such as Au/Ti/Al/Ti or Au/Mo/Al/Ti can be used. As a technique for forming a mask that determines the electrode pattern of the first electrode 35, for example, photolithography technique can be adopted.

(Heating step S33)
The heating step S33 corresponds to the heating step S23 shown in FIG. In the heterojunction 33 that has undergone the heating step S33 (see FIG. 11C), the contact at the interface between the first electrode 35 and the heterojunction 33 is ohmic contact.

(Second electrode forming step S34)
By performing the second electrode forming step S34 after the heating step S33, the heterostructure 30 in which the first electrode 35 and the second electrode 16 are formed on the surface 33a of the heterojunction 33 can be obtained (see FIG. 11). (See (d)).

As described above, in the heterostructure 30, the first electrode 35 and the heterojunction 33 are in ohmic contact. By evaluating the interface characteristics of the heterojunction 33 using the heterostructure 30, it is possible to prevent a capacitance from being generated between the first electrode 35 and the surface 33a.

[Fourth Embodiment]
An evaluation method according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 12 is a flowchart showing this evaluation method.

As shown in FIG. 12, the present evaluation method further includes a specific range determination step S41, a comparison step S42, and a determination step S43, as compared with the evaluation method shown in FIG.

The specific range determination step S41 is a step performed before the etching step S12 to the interface state density derivation step S16, and defines a specific range in the interface state density of the heterojunction composed of different kinds of nitride semiconductors. It is a process. The lower limit value and the upper limit value of this specific range are in a preferable range as the interface state density D _it of the heterojunction composed of different kinds of nitride semiconductors (for example, the range allowed when shipping the heterojunction as a product). It can be determined based on.

The comparison step S42 is a step of comparing the interface state density D _it derived in the interface state density deriving step S16 with the specific range. The determination step S43 determines that the heterojunction is acceptable when (1) the interface state density D _it is within the specific range according to the result of the comparison step S42, and (2) the interface state density D _it. Is a step of judging the above-mentioned heterojunction as a failure when it is not within the specific range.

The present evaluation method can determine the success or failure of the heterojunction based on whether or not the interface state density D _it of the heterojunction is included in a specific range that is a preferable range. In addition, a program for executing the interface state density derivation step S16, the specific range determination step S41, the comparison step S42, and the determination step S43 included in the present evaluation method is created, and the program is executed by the control unit (CPU: Central Processing) of the computer. Unit), the evaluation apparatus according to the embodiment of the present invention derives the interface state density D _it of the heterojunction composed of different kinds of nitride semiconductors, and derives the derived interface state density D _it. The pass/fail can be automatically determined based on the. In this evaluation device, (1) the specific range determination step S41 may be configured to be performed each time the heterojunction is evaluated, or (2) the specific range determination step S41 performed in advance. The specific range may be stored in a storage medium, and the specific range stored in the storage medium may be referred to when the heterojunction is evaluated.

[Comparative example]
A heterostructure 50 that is a comparative example of the present invention will be described with reference to FIGS. 13 and 14. FIG. 13A is a cross-sectional view of the hetero structure 50. FIG. 13B is a plan view of the hetero structure 50. The sectional view shown in FIG. 13A is a sectional view taken along the line BB shown in FIG. 14A and 14B are graphs showing the conductance curves of the heterostructure 50.

The heterostructure 50 is manufactured by using the heterojunction shown in FIG. 2A similarly to the heterostructure 10. The heterostructure 50 differs from the heterostructure 10 in that it employs a FET structure that can operate as a HEMT.

In the heterostructure 50, the heterojunction 53 formed by the GaN layer 531 and the AlGaN layer 532 is etched into a mesa shape. The heterostructure 50 includes a gate electrode 57 arranged in the center of the mesa, a source electrode 55 arranged below the gate electrode 57 with a space, and a drain electrode arranged above the gate electrode 57 with a space. And 56. The source electrode 55 and the drain electrode 56 are in ohmic contact with the heterojunction 53.

In the heterostructure 50, each of the source electrode 55 and the drain electrode is composed of Au/Al/Mo/Al/Ti. The thickness of the source electrode 55 and the drain electrode is -50/-1/35/60/15 nm for each of Au/Al/Mo/Al/Ti. The gate electrode 57 is composed of a Ni layer having a thickness of 50 nm.

To derive _{D it} heterojunction 53, (1) the source electrode 55 and drain electrode 56 are connected together to the negative terminal of the LCR meter 30, (2) the gate electrode 57, a positive LCR meter 30 It is connected to the side terminal. As meter for deriving D _it, using the same as the measurement meter shown in FIG.

In addition, in this comparative example, a heterostructure 50 having a configuration of L/W=50/100 μm and a heterostructure 50 having a configuration of L/W=100/100 μm were manufactured. The conductance curve of the heterostructure 50 adopting the L/W=50/100 μm structure is shown in FIG. 14A, and the conductance curve of the heterostructure 50 adopting the L/W=100/100 μm structure is shown in FIG. It shows in (b). The conductance curves shown in (a) and (b) of FIG. 14 are obtained when the bias voltage is −3.85V, −3.90V, −3.95V, −4.00V, −4.05V. Is the conducted conductance curve.

Is it the purpose of manufacturing the HEMT, when evaluating D _it as part of the characterization of the HEMT produced may be used a method of fabricating an FET structure as described above.

However, when there are a large number of substrates on which an AlGaN/GaN heterojunction is formed and only the interface characteristics of the heterojunction are desired to be evaluated, that is, when the HEMT is not intended to be manufactured. It takes time to manufacture the above-mentioned FET structure.

The heterostructure 10 has an advantage that it can be manufactured more easily than the heterostructure 50 that is an FET structure.

The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Is also included in the technical scope of the present invention.

10, 10A, 10B, 10C, 20A, 20B, 20C, 30, 50 Heterostructure 11 Silicon substrate 12 Buffer layer 13, 33, 53 Heterojunction 13a, 33a Surface 131, 531 GaN layer 131a, 531a 2DEG (two-dimensional electron gas) )
132,331,532 AlGaN layer 15,35 electrode (first electrode)
151,351 inner edge 152,162,551,561,571 terminal 16 electrode (second electrode)
161 Outer edge 332a Recess 30 LCR meter 31 AC current source 32 DC voltage source 33 Ammeter 34 Voltmeter 55 Source electrode 56 Drain electrode 57 Gate electrode

Claims (5)

A method for evaluating a heterojunction composed of different kinds of nitride semiconductors,
On the surface of the heterojunction, a ring-shaped first electrode, and a second electrode disposed inside the inner edge of the first electrode and separated from the first electrode are formed,
In each of the states in which a plurality of bias voltages are applied between the first electrode and the second electrode, the frequency dependence of the conductance between the first electrode and the second electrode is measured to obtain a plurality of biases. An interface state density deriving step of deriving an interface state density of the heterojunction based on the frequency dependence of the conductance corresponding to each voltage.
An evaluation method characterized by the above. Each of the curves forming the inner edge of the first electrode and the outer edge of the second electrode is circular,
The second electrode is arranged such that the outer edge is concentric with the inner edge.
The evaluation method according to claim 1, wherein: The contact between the first electrode and the surface of the heterojunction is ohmic contact.
The evaluation method according to claim 1 or 2, characterized in that. The heterojunction is composed of a GaN layer and an AlGaN layer formed on the surface of the GaN layer,
The evaluation method according to any one of claims 1 to 3, characterized in that. A specific range determining step of defining a specific range in the interface state density of a heterojunction composed of different kinds of nitride semiconductors,
A comparison step of comparing the interface state density derived in the interface state density deriving step with the specific range;
According to the result of the comparison step, (1) the heterojunction is determined to be acceptable when the interface state density is within the specific range, and (2) the interface state density is not within the specific range. In the case, further comprising a determination step of determining the heterojunction as a failure,
The evaluation method according to any one of claims 1 to 4, wherein:

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