JP6707922B2 - Physical quantity sensor - Google Patents

Description

The technology disclosed in the present specification relates to a physical quantity sensor.

A physical quantity sensor for measuring a physical quantity exemplified by pressure, acceleration, angular velocity, magnetic field or temperature has been developed, and one example thereof is disclosed in Patent Documents 1-3. This type of physical quantity sensor has a resistance change type detection unit whose resistance value changes according to the change of the physical quantity, and is configured to measure the physical quantity by acquiring the resistance change of the detection unit as a voltage change. Has been done.

JP-A-63-118629 JP-A-1-316974 JP, 2006-208145, A

In order to suppress the power consumption of the physical quantity sensor, the drive voltage is being reduced. In the conventional physical quantity sensor, when the driving voltage becomes lower, the output voltage proportional to the driving voltage also lowers, so that the measurement sensitivity lowers. There is a need for a physical quantity sensor that has high measurement sensitivity even at low drive voltage.

One embodiment of the physical quantity sensor disclosed in the present specification includes a detection unit, a pulse generation circuit, and a time difference measurement circuit. The detection unit has a first detection unit having a first resistance value and a second detection unit having a second resistance value. The detection unit determines that the relative value of the first time constant of the RC circuit including the first resistance value of the first detection unit and the second time constant of the RC circuit including the second resistance value of the second detection unit causes a change in the physical quantity. It is configured to change accordingly. The pulse generation circuit is configured to input a pulse signal to the common input terminal of the first detection unit and the second detection unit. The time difference measuring circuit is connected to the first output terminal of the first detector and the second output terminal of the second detector. The time difference measuring circuit generates a first delayed pulse signal by delaying a pulse signal propagating through the first detection unit based on a first time constant, and generates a pulse signal propagating through the second detection unit based on a second time constant. A delayed second pulse signal is generated. The time difference measuring circuit is further configured to measure the time difference between the first delayed pulse signal and the second delayed pulse signal.

The physical quantity sensor of the above embodiment converts a change in the relative value of the first time constant of the first detection unit and the second time constant of the second detection unit into the time difference between the first delayed pulse signal and the second delayed pulse signal. The physical quantity sensor according to the above-described embodiment measures a change in the relative value of the first time constant of the first detection unit and the second time constant of the second detection unit, that is, a change in the physical quantity by measuring the time difference. You can The physical quantity sensor of the above embodiment can obtain the time difference between the first delayed pulse signal and the second delayed pulse signal based on the first time constant of the first detection unit and the second time constant of the second detection unit. Therefore, the physical quantity sensor of the above embodiment can have high measurement sensitivity even at a low drive voltage.

It is a circuit block diagram which shows the outline of a physical quantity sensor. It is a circuit diagram which shows the outline of a physical quantity sensor. The timing chart of a physical quantity sensor is shown. FIG. 3 is a circuit diagram showing an example of a current control type inverter included in a buffer circuit. The circuit diagram of an example of the buffer circuit which has a current control type inverter is shown. The circuit diagram of another example of the current control type inverter which a buffer circuit has is shown. The circuit diagram of another example of the buffer circuit which has a current control type inverter is shown. The schematic of the principal part perspective view of a magnetic detection part is shown. The model top view of a magnetic sensing part is shown typically. The equivalent circuit schematic of a magnetic detection part is shown. The state of the electric current which flows through a magnetic detection part when a magnetic field acts is shown.

The features of the technology disclosed in this specification will be summarized below. The technical elements described below are technical elements that are independent of each other, and exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Absent.

One embodiment of the physical quantity sensor disclosed in the present specification may include a detection unit, a pulse generation circuit, and a time difference measurement circuit. The detection unit has a first detection unit having a first resistance value and a second detection unit having a second resistance value. The detection unit determines that the relative value of the first time constant of the RC circuit including the first resistance value of the first detection unit and the second time constant of the RC circuit including the second resistance value of the second detection unit causes a change in the physical quantity. It is configured to change accordingly. Regarding the first time constant and the second time constant, both time constants may be configured to change according to the change of the physical quantity, or one of the time constants may change according to the change of the physical quantity. And the other time constant may be fixed without depending on the change in the physical quantity. The detection unit may be a resistance change type or a capacitance change type. For example, when the detection unit is a resistance change type, even if the relative value of the first resistance value of the first detection unit and the second resistance value of the second detection unit is configured to change according to the change of the physical quantity. Good. In this case, regarding the first resistance value and the second resistance value, both resistance values may be configured to change according to the change in the physical quantity, or either one of the resistance values may change in the physical quantity. The resistance value of the other resistance may be fixed without depending on the change of the physical quantity. Examples of the physical quantity to be measured include pressure, acceleration, angular velocity, magnetic field, temperature, and the like. For example, the detector may include a MAGFET type magnetic detector to measure the magnetic field. The pulse generation circuit is configured to input a pulse signal to the common input terminal of the first detection unit and the second detection unit. The pulse signal may have an initial value of Lo or an initial value of Hi. The time difference measuring circuit is connected to the first output terminal of the first detector and the second output terminal of the second detector. The time difference measuring circuit generates a first delayed pulse signal by delaying a pulse signal propagating through the first detection unit based on a first time constant, and generates a pulse signal propagating through the second detection unit based on a second time constant. A delayed second pulse signal is generated. The time difference measuring circuit is further configured to measure the time difference between the first delayed pulse signal and the second delayed pulse signal.

In the physical quantity sensor of the above embodiment, the time difference measurement circuit is a first buffer circuit connected to the first output terminal of the first detection unit and a second buffer circuit connected to the second output terminal of the second detection unit. May have. In this case, the first buffer circuit shapes the first delayed pulse signal by shaping the first slowed pulse signal in which the edge speed of the pulse signal propagating through the first detection unit is slowed based on the first time constant. Is configured to generate. The second buffer circuit forms the second delayed pulse signal by shaping the second slowed-down pulse signal in which the edge speed of the pulse signal propagating through the second detector is slowed down based on the second time constant. Is configured. In the physical quantity sensor of this embodiment, the buffer circuit shapes the speed-down pulse signal to generate a delayed pulse signal. Therefore, the physical quantity sensor of this embodiment can have high resistance to minute noise that does not exceed the logical threshold value of the buffer circuit.

In the physical quantity sensor of the above embodiment, each of the first buffer circuit and the second buffer circuit may have a current control type inverter in which the operating current is limited depending on the voltage applied to the bias terminal. The physical quantity sensor of this embodiment operates so that the difference in delay time between the first buffer circuit and the second buffer circuit increases. Therefore, the time difference between the first delayed pulse signal and the second delayed pulse signal becomes large, and the physical quantity sensor of this embodiment can measure the physical quantity with higher sensitivity. In one example, the current control type inverter of the first buffer circuit has an n-channel MOS transistor whose gate is connected to the bias terminal, and the current control type inverter of the second buffer circuit has its gate connected to the bias terminal. It may have an n-channel MOS transistor that has been set up. In this case, the bias terminal of the current control type inverter of the first buffer circuit is connected to the first output terminal of the first detector. The bias terminal of the current control type inverter of the second buffer circuit is connected to the second output terminal of the second detector. In another example, the current-controlled inverter of the first buffer circuit has a p-channel MOS transistor whose gate is connected to the bias terminal, and the current-controlled inverter of the second buffer circuit is gated to the bias terminal. May be connected to the p-channel MOS transistor. In this case, the bias terminal of the current control type inverter of the first buffer circuit is connected to the second output terminal of the second detector. The bias terminal of the current control type inverter of the second buffer circuit is connected to the first output terminal of the first detector.

The physical quantity sensor of the above embodiment may further include a polarity determination circuit. The polarity determination circuit is configured to determine the polarity of change in the relative value of the first time constant and the second time constant based on the magnitude relationship between the first time constant and the second time constant. Here, the change polarity of the relative value of the first time constant and the second time constant is positive when the time constant of one is increased when the time constant of the other is increased with respect to the reference time constant. The polarity is negative and the case where the other time constant decreases with respect to the reference time constant is negative polarity. When the physical quantity sensor includes such a polarity determination circuit, for example, when the physical quantity of the measurement target is a magnetic field, the physical quantity sensor can determine the direction of the magnetic field.

In the physical quantity sensor of the above embodiment, the pulse generation circuit may include an oscillation circuit that generates a clock signal and a frequency divider circuit that frequency-divides the clock signal to generate a pulse signal. In this case, the time difference measuring circuit may include a counter circuit that counts the time difference between the first delay pulse signal and the second delay pulse signal based on the clock signal generated by the oscillation circuit. By using the clock signal generated by the oscillation circuit as the clock signal used in the counter circuit, it is not necessary to separately provide an oscillation circuit for generating the clock signal for the counter circuit.

As shown in FIG. 1, the physical quantity sensor 1 is an integrated circuit that is made into one chip, and includes a pulse generation circuit 2, a physical quantity detection unit 4, and a pulse signal processing circuit 8. The physical quantity detection unit 4 has a pressure detection unit 6 that utilizes the piezoresistive effect. The pressure detection unit 6 has a first detection unit 6A and a second detection unit 6B, and a change in pressure applied by the relative value of the resistance value of the first detection unit 6A and the resistance value of the second detection unit 6B It is configured to change accordingly.

As shown in FIG. 2, the pulse generation circuit 2 has an oscillation circuit 2A and a frequency dividing circuit 2B. The oscillator circuit 2A has a ring oscillator in which a plurality of CMOS inverters are connected in a ring shape, and is configured to generate a clock signal CLK. The clock signal CLK is, for example, a rectangular wave with a duty ratio of 50%. The frequency divider circuit 2B is configured to convert the clock signal CLK into a pulse signal V10 having a low frequency. The frequency dividing circuit 2B lowers the frequency of the clock signal CLK by 1/2048, for example.

In the pressure detection unit 6 of the physical quantity detection unit 4, the first detection unit 6A has a first resistance value R1 and the second detection unit 6B has a second resistance value R2. The increase and decrease of the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B change in the opposite direction with respect to the change of the acting pressure. That is, when the first resistance value R1 of the first detection unit 6A decreases with respect to the change in the acting pressure, the second resistance value R2 of the second detection unit 6B increases. When the first resistance value R1 of the first detection unit 6A increases with respect to the change in the acting pressure, the second resistance value R2 of the second detection unit 6B decreases. As described above, in the pressure detection unit 6, the relative value of the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B is configured to change in accordance with the change in the applied pressure. Has been done. For example, when the first resistance value R1 of the first detection unit 6A decreases when the acting pressure increases, the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B are When the relative value is defined as (R2-R1), the relative value (R2-R1) shows a positive change polarity with respect to an increase in acting pressure and a negative change with respect to a decrease in acting pressure. Indicates polarity. The pulse signal V10 is input to the common input terminal 6a of the first detection unit 6A and the second detection unit 6B. The first output terminal 6b of the first detection unit 6A and the second output terminal 6c of the second detection unit 6B are connected to the pulse signal processing circuit 8.

The physical quantity detection unit 4 further includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 is connected between the first output terminal 6b of the first detector 6A and the ground. The second capacitor C2 is connected between the second output terminal 6c of the second detector 6B and the ground. The capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 are the same. The first resistance value R1 of the first detection unit 6A and the first capacitor C1 form an RC circuit. Therefore, the pulse signal V10 propagating through the first detection unit 6A becomes the first slowing-down pulse signal V11 having a waveform whose rising edge is blunted based on the time constant of the RC circuit. The second resistance value R2 and the second capacitor C2 of the second detection unit 6B also form an RC circuit. Therefore, the pulse signal V10 propagating through the second detector 6B also becomes the second speed-down pulse signal V12 having a blunted rising edge based on the time constant of the RC circuit. The first capacitor C1 and the second capacitor C2 can be omitted if necessary. In this case, the input capacitances of the first buffer circuit 12 and the second buffer circuit 14, which will be described later, can replace the capacitors C1 and C2.

The pulse signal processing circuit 8 has a time difference measuring circuit 10 and a polarity determining circuit 20. Although details will be described later, the time difference measuring circuit 10 delays the pulse signal V10 propagating through the first detection unit 6A and delays the pulse signal V10 propagating through the second delay unit 6B and the first delayed pulse signal Vo1. It is configured to measure the time difference between the two delayed pulse signals Vo2. The polarity determination circuit 20 includes a time constant of an RC circuit configured by the first resistance value R1 of the first detection unit 6A and the first capacitor C1 and a second resistance value R2 of the second detection unit 6B and the second capacitor C2. The change polarity of the relative value (R2-R1) of the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B is determined based on the magnitude relationship of the time constants of the RC circuit. Is configured to.

The time difference measuring circuit 10 has a first buffer circuit 12, a second buffer circuit 14, an XOR circuit 16 and a counter circuit 18. The first buffer circuit 12 is configured by connecting a pair of CMOS inverters in series, the input terminal is connected to the first output terminal 6b of the first detector 6A, and the output terminal is one of the XOR circuits 16. It is connected to the input terminal. The first buffer circuit 12 forms the first delayed pulse signal Vo1 by delaying the pulse signal V10 by shaping the first slowdown pulse signal V11 propagated through the first detection unit 6A. The second buffer circuit 14 is also configured by connecting a pair of CMOS inverters in series, the input terminal is connected to the second output terminal 6c of the second detector 6B, and the output terminal is the other of the XOR circuits 16. It is connected to the input terminal. The second buffer circuit 14 forms the second delayed pulse signal Vo2 by delaying the pulse signal V10 by shaping the second speed reduction pulse signal V12 propagated through the second detection unit 6B.

The XOR circuit 16 generates a time difference pulse signal Vo3 which is an exclusive OR of the first delay pulse signal Vo1 and the second delay pulse signal Vo2. The time difference pulse signal Vo3 is a pulse signal having a length corresponding to the time difference between the rising edges of the first delay pulse signal Vo1 and the second delay pulse signal Vo2. The output terminal of the XOR circuit 16 is connected to the input terminal of the counter circuit 18. The counter circuit 18 is configured to measure the length of the time difference pulse signal Vo3 output from the XOR circuit 16 based on the clock signal CLK of the oscillation circuit 2A. The counter circuit 18 is, for example, a binary counter composed of a D-type flip-flop. The counter circuit 18 is configured to output the measured number of clocks as a digital output value OUT2.

The polarity determination circuit 20 has an inverter 22, an AND circuit 24, and an RS flip-flop circuit 26. The inverter 22 has an input terminal connected to the common input terminal 6a of the pressure detection unit 6, and an output terminal connected to the reset terminal of the RS flip-flop circuit 26. The inverter 22 is configured to generate a reset signal V10B by inverting the pulse signal V10 and input the reset signal V10B to the reset terminal of the RS flip-flop circuit 26. The AND circuit 24 has one input terminal connected to the output terminal of the first buffer circuit 12 and the other input terminal connected to the output terminal of the XOR circuit 16. The AND circuit 24 is configured to generate a set signal Vo4 which is a logical product of the first delay pulse signal Vo1 and the time difference pulse signal Vo3, and input the set signal Vo4 to the set terminal of the RS flip-flop circuit 26. .. The RS flip-flop circuit 26 determines the change polarity of the relative value (R2-R1) of the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B, as described later, The result is output to the output terminal Q as a digital output value OUT1.

FIG. 3 shows a timing chart of the physical quantity sensor 1. When the pulse signal V10 output from the pulse generation circuit 2 is input to the pressure detection unit 6, the first detection unit 6A generates the first speed reduction pulse signal V11, and the second detection unit 6B the second speed reduction pulse signal V12. To generate. In this example, the first resistance value R1 of the first detection unit 6A is configured to decrease when the acting pressure increases, and the second resistance value R2 of the second detection unit 6B increases the acting pressure. Are configured to increase when Therefore, when the pressure acting on the first detection unit 6A and the second detection unit 6B increases more than the preload, when the RC circuit including the first resistance value R1 of the first detection unit 6A and the first capacitor C1 is used. The constant is smaller than the time constant of the RC circuit configured by the second resistance value R2 of the second detector 6B and the second capacitor C2. Therefore, as shown in FIG. 3, the rising edge waveform (solid line) of the first slowing-down pulse signal V11 changes more rapidly than the rising edge waveform (solid line) of the second slowing-down pulse signal V12. In other words, the rising edge speed of the first slowing-down pulse signal V11 is faster than the rising edge speed of the second slowing-down pulse signal V12. The waveforms of the first slowing-down pulse signal V11 and the second slowing-down pulse signal V12, which are indicated by broken lines, indicate the case where the pressure acting on the first detection unit 6A and the second detection unit 6B is lower than the preload. ..

When the first speed reduction pulse signal V11 exceeds the logical threshold value of the first buffer circuit 12, the first buffer circuit 12 shapes the first speed reduction pulse signal V11 and generates the first delay pulse signal Vo1. When the second speed reduction pulse signal V12 exceeds the logical threshold value of the second buffer circuit 14, the second buffer circuit 14 shapes the second speed reduction pulse signal V12 and generates the second delay pulse signal Vo2. As described above, since the rising edge speed of the first slowing pulse signal V11 is faster than the rising edge speed of the second slowing pulse signal V12, the first delay pulse signal Vo1 precedes the second delay pulse signal Vo2. stand up. The XOR circuit 16 generates a time difference pulse signal Vo3 which is an exclusive OR of the first delay pulse signal Vo1 and the second delay pulse signal Vo2. The time difference pulse signal Vo3 corresponds to the time difference between the rising edges of the first delay pulse signal Vo1 and the second delay pulse signal Vo2.

The counter circuit 18 measures the length of the time difference pulse signal Vo3 based on the clock signal CLK. In this example, the number of clocks of the counter circuit 18 is measured as “N”. The counter circuit 18 outputs the measured clock number N as a digital output value OUT2.

As described above, the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B change according to the acting pressure. Furthermore, the rising edge speed of the first slowdown pulse signal V11 propagated through the first detection unit 6A depends on the time constant of the RC circuit configured by the first resistance value R1 of the first detection unit 6A and the first capacitor C1. To do. Therefore, the timing at which the first delay pulse signal Vo1 rises depends on the pressure acting on the first detection unit 6A. Similarly, the rising edge speed of the second slowdown pulse signal V12 propagated through the second detection unit 6B is set to the time constant of the RC circuit configured by the second resistance value R2 of the second detection unit 6B and the second capacitor C2. Dependent. Therefore, the timing at which the second delay pulse signal Vo2 rises depends on the pressure acting on the second detection unit 6B. Therefore, the time difference pulse signal Vo3 corresponding to the time difference between the rising edges of the first delay pulse signal Vo1 and the second delay pulse signal Vo2 depends on the pressure acting on the pressure detection unit 6. Thereby, the digital output value OUT2 of the counter circuit 18 reflects the magnitude of the pressure acting on the first detection unit 6A and the second detection unit 6B.

As described above, in this example, the first resistance value R1 of the first detection unit 6A is configured to decrease when the acting pressure increases, and the second resistance value R2 of the second detection unit 6B is It is arranged to increase as the pressure exerted increases. Further, the timing chart of FIG. 3 illustrates a case where the pressure acting on the first detection unit 6A and the second detection unit 6B increases more than the preload. Therefore, the set signal Vo4, which is the logical product of the first delay pulse signal Vo1 and the time difference pulse signal Vo3, becomes “Hi”. Therefore, the digital output value OUT1 of the RS flip-flop circuit 26 becomes "Hi". That is, when the digital output value OUT1 of the RS flip-flop circuit 26 is “Hi”, the relative value (R2-R1) of the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B. ) Indicates that the change polarity is positive, which means that the pressure acting on the first detection unit 6A and the second detection unit 6B is greater than the preload. On the other hand, when the digital output value OUT1 of the RS flip-flop circuit 26 is "Lo", the relative value (R2-R1) of the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B. ) Is negative, which means that the pressure acting on the first detection unit 6A and the second detection unit 6B is lower than the preload.

As described above, the physical quantity sensor 1 determines the magnitude of the relative value (R2-R1) of the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B as the first delayed pulse signal. It is converted into the time difference between Vo1 and the second delay pulse signal Vo2. By measuring the time difference, the physical quantity sensor 1 measures the relative value (R2-R1) of the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B, that is, The amount of pressure exerted can be measured. The physical quantity sensor 1 includes a time constant of an RC circuit configured by the first resistance value R1 of the first detection unit 6A and the first capacitor C1 and a second resistance value R2 of the second detection unit 6B and the second capacitor C2. The time difference between the first delayed pulse signal Vo1 and the second delayed pulse signal Vo2 can be obtained based on the time constant of the RC circuit. Therefore, the physical quantity sensor 1 can obtain the time difference between the first delay pulse signal Vo1 and the second delay pulse signal Vo2 without depending on the drive voltage. Therefore, the physical quantity sensor 1 can have high measurement sensitivity even at a low driving voltage.

Further, the physical quantity sensor 1 determines the change polarity of the relative value (R2-R1) of the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B as the first speed reduction pulse signal V11. Edge speed (that is, the time constant of the RC circuit configured by the first resistance value R1 and the first capacitor C1 of the first detection unit 6A) and the edge speed of the second speed-down pulse signal V12 (that is, the second detection unit). It can be determined from the magnitude relationship between the second resistance value R2 of 6B and the time constant of the RC circuit composed of the second capacitor C2. That is, the physical quantity sensor 1 can determine, based on these time constants, whether the pressure acting on the pressure detection unit 6 has increased or decreased from the preload. Therefore, the physical quantity sensor 1 can determine whether the pressure acting on the pressure detection unit 6 has increased or decreased from the preload, without depending on the drive voltage.

FIG. 4 is a modified example of the first buffer circuit 12 and the second buffer circuit 14, and shows a circuit diagram of the current control type inverter INV1 included in the first buffer circuit 12 and the second buffer circuit 14. Each of the first buffer circuit 12 and the second buffer circuit 14 is configured by connecting a plurality (a total of an even number) of the current control type inverters INV1 in series. The current-controlled inverter INV1 is characterized by including an n-channel MOS transistor Tr1 for control connected between an n-channel MOS transistor forming a CMOS inverter and the ground. The bias voltage VBn is input to the bias terminal corresponding to the gate of the n-channel MOS transistor Tr1 for control. The current control type inverter INV1 is characterized in that the operating current flowing through the CMOS inverter is limited by the n-channel MOS transistor Tr1 for control, so that the delay time between the input and the output is increased. The current control type inverter INV1 is characterized in that the larger the bias voltage VBn, the shorter the delay time between the input and the output, and the smaller the bias voltage VBn, the longer the delay time between the input and the output.

FIG. 5 shows a circuit configuration in the case where each of the first buffer circuit 12 and the second buffer circuit 14 has a current control type inverter INV1. The bias terminals of the plurality of current control type inverters INV1 included in the first buffer circuit 12 are connected to the first output terminal 6b of the first detection unit 6A. Further, each bias terminal of the plurality of current control type inverters INV1 included in the second buffer circuit 14 is connected to the second output terminal 6c of the second detector 6B.

The features of the first buffer circuit 12 and the second buffer circuit 14 will be described with reference to FIG. As described above, when the pressure acting on the first detection unit 6A and the second detection unit 6B increases more than the preload, the rising edge speed of the first slowdown pulse signal V11 is the rising edge of the second slowdown pulse signal V12. Greater than edge speed. Therefore, the voltage value of the first speed reduction pulse signal V11 is larger than the voltage value of the second speed reduction pulse signal V12 during the period in which these speed reduction pulse signals V11 and V12 rise. As described above, the first slowdown pulse signal V11 is input to the bias terminal of the first buffer circuit 12, and the second slowdown pulse signal V12 is input to the bias terminal of the second buffer circuit 14. Therefore, the delay speed of the current-controlled inverter INV1 of the first buffer circuit 12 becomes smaller than the delay speed of the current-controlled inverter INV1 of the second buffer circuit 14. As a result, the time difference between the rising edges of the first delay pulse signal Vo1 and the second delay pulse signal Vo2 becomes large, and the length of the time difference pulse signal Vo3 becomes long. Therefore, the physical quantity sensor 1 can measure pressure with higher sensitivity. Similarly, even when the pressure acting on the first detection unit 6A and the second detection unit 6B is lower than the preload, the time difference between the rising edges of the first delay pulse signal Vo1 and the second delay pulse signal Vo2 is As a result, the length of the time difference pulse signal Vo3 becomes longer. Even in this case, the physical quantity sensor 1 can measure the pressure with higher sensitivity. Further, when each of the first buffer circuit 12 and the second buffer circuit 14 has the current control type inverter INV1, as the number of stages of each of the first buffer circuit 12 and the second buffer circuit 14 increases, the first delay pulse signal Vo1 increases. And the time difference between the rising edges of the second delay pulse signal Vo2 increases, and the length of the time difference pulse signal Vo3 increases. Therefore, the physical quantity sensor 1 can measure pressure with higher sensitivity.

In the above description, the current control transistor connected to the current control inverter INV1 is the n-channel MOS transistor Tr1. Instead of this, as shown in FIG. 6, the current controlling transistor may be a p-channel MOS transistor Tr2. The control p-channel MOS transistor Tr2 is connected between the p-channel MOS transistor forming the CMOS inverter and the power supply terminal. The bias voltage VBp is input to the bias terminal corresponding to the gate of the control p-channel MOS transistor Tr2. FIG. 7 shows a circuit configuration when each of the first buffer circuit 12 and the second buffer circuit 14 has a current control type inverter INV2. The bias terminals of the plurality of current control type inverters INV1 included in the first buffer circuit 12 are connected to the second output terminal 6c of the second detector 6B. Further, the bias terminals of each of the plurality of current control type inverters INV1 included in the second buffer circuit 14 are connected to the first output terminal 6b of the first detection unit 6A. Also in this example, the time difference between the rising edges of the first delay pulse signal Vo1 and the second delay pulse signal Vo2 becomes large, as in the case of the current control type inverter INV1 described above, and the physical quantity sensor 1 detects the pressure with higher sensitivity. It is possible to measure

In the above, the case where the physical quantity sensor 1 has the pressure detection unit 6 for pressure measurement has been illustrated. The techniques disclosed herein may be utilized with a variety of other types of sensors. For example, as shown in FIG. 8A, the technique disclosed in this specification can be used for a physical quantity sensor including a magnetic detection unit 7 for measuring a magnetic field.

As shown in FIGS. 8A and 8B, the magnetic detection unit 7 is a MAGFET (MAGnetic Field Effect Transistor) type magnetic detection element, and is configured as an n-type MOSFET. The magnetic detection unit 7 has a source electrode 7s, a gate electrode 7g, and a pair of drain electrodes 7d1 and 7d2 arranged on the semiconductor substrate 7sub. Various semiconductor regions for forming an n-type MOSFET are formed on the semiconductor substrate 7sub. In the magnetic detection unit 7, the source electrode 7s and the gate electrode 7g are commonly arranged for each of the pair of drain electrodes 7d1 and 7d2. The first drain electrode 7d1, the gate electrode 7g, and the source electrode 7s form the first detection unit 6A (see FIG. 1). The second drain electrode 7d2, the gate electrode 7g, and the source electrode 7s form the second detection unit 6B (see FIG. 1).

FIG. 8C shows an equivalent circuit of the magnetic detector 7. As described above, in the magnetic detection unit 7, the first detection unit 6A constitutes an n-type MOSFET, the second detection unit 6B also constitutes an n-type MOSFET, and these are connected in parallel. The n-type MOSFET forming the first detection unit 6A and the n-type MOSFET forming the second detection unit 6B have the same channel length and channel width. A bias voltage (eg, power supply voltage) is input to the gates of these n-type MOSFETs.

Next, the operation of the magnetic detection unit 7 will be described with reference to FIG. 8D. In the magnetic detection unit 7, current flows from the pair of drain electrodes 7d1 and 7d2 to the source electrode 6s. At this time, when a magnetic field is applied in the direction perpendicular to the main surface of the semiconductor substrate 7sub, the electron carriers flowing in the channel induced by the gate electrode 7g are deflected by the Lorentz force. For example, when the magnetic field acts in the direction from the back surface to the front surface of the paper, the electron carriers flowing through the channel induced by the gate electrode 7g flow such that the amount flowing from the source electrode 7s to the first drain electrode 7d1 increases. On the other hand, when the magnetic field acts in the direction from the front side to the back side of the paper, the electron carriers flowing through the channel induced by the gate electrode 7g flow such that the amount flowing into the second drain electrode 7d2 from the source electrode 7s increases. As described above, in the magnetic detection unit 7, the relative value of the current value flowing through the first detection unit 6A and the current value flowing through the second detection unit 6B, that is, the current value flowing through the second detection unit 6B, depending on the strength and direction of the magnetic field acting by the Hall effect The relative value of the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B changes.

Such a magnetic detection unit 7 is used by replacing the pressure detection unit 6 of the physical quantity sensor 1 of FIG. However, as described above, the direction of the current flowing through the magnetic detection unit 7 is opposite to the direction of the current flowing through the pressure detection unit 6. For this reason, in the case where the physical quantity sensor 1 is replaced with the magnetic detector 7, the initial value of the pulse signal V10 is set to "Hi", and the number of CMOS inverters in each of the first buffer circuit 12 and the second buffer circuit 14 is odd. Set to individual. As a result, in the physical quantity sensor 1, the first speed reduction pulse signal V11 falls in synchronization with the fall of the pulse signal V10, and the first speed reduction pulse signal V11 falls below the logical threshold value of the first buffer circuit 12. The first delay pulse signal Vo1 rises when the first delay pulse signal Vo1 rises. Similarly, in the physical quantity sensor 1, the second speed reduction pulse signal V12 falls in synchronization with the fall of the pulse signal V10, and the second speed reduction pulse signal V12 falls below the logical threshold value of the second buffer circuit 14. The second delay pulse signal Vo2 is configured to rise at the time of the opening. Thereby, the pulse signal processing circuit 8 can operate similarly to the case of the pressure detection unit 6. Also in the physical quantity sensor 1 having the magnetic detection unit 7, the first buffer circuit 12 and the second buffer circuit 14 have the current control type inverter INV1 (FIG. 4) or the current control type inverter INV2 (FIG. 6). Good. However, in order to cope with the logic inversion, the wiring pattern of FIG. 7 is applied to the current control type inverter INV1 (FIG. 4), and the wiring pattern of FIG. 5 is applied to the current control type inverter INV2 (FIG. 6). To be done.

As described above, the physical quantity sensor 1 disclosed in the present specification can measure the acting magnetic field with high sensitivity by using the MAGFET (MAGnetic Field Effect Transistor) type magnetic detection unit 7. In the above description, an example in which the MAGFET type magnetic detecting element is used for the magnetic detecting unit 7 has been described. Alternatively, a Hall element type magnetic sensing element may be used.

In the above, the example in which the pressure detection unit 6 and the magnetic detection unit 7 are used as the physical quantity detection unit 4 has been illustrated. Both the pressure detection unit 6 and the magnetic detection unit 7 are resistance change type sensors. Instead of this example, both the first resistance value R1 of the first detection unit 6A and the second resistance value R2 of the second detection unit 6B are fixed with respect to changes in the physical quantity, and the capacitance value of the first capacitor C1 It may be configured so that the relative value of the capacitance value of the second capacitor C2 changes in accordance with the change of the physical quantity that acts. In this case, for example, it is realized by using a capacitive pressure sensor or inertial force sensor for the first capacitor C1 and the second capacitor C2.

Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. Further, the technical elements described in the present specification or the drawings exert technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technique illustrated in the present specification or the drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes has technical utility.

1: Physical quantity sensor 2: Pulse generation circuit 2A: Oscillation circuit 2B: Frequency divider circuit 4: Physical quantity detection unit 6: Pressure detection unit 7: Magnetic detection unit 6A: First detection unit 6B: Second detection unit 8: Pulse signal processing Circuit 10: Time difference measuring circuit 12: First buffer circuit 14: Second buffer circuit 16: XOR circuit 18: Counter circuit 20: Polarity determination circuit 22: Inverter 24: AND circuit 26: RS flip-flop circuit

Claims (4)

A physical quantity sensor,
A first detection unit having a first resistance value and a second detection unit having a second resistance value; and a first time constant of an RC circuit including the first resistance value of the first detection unit and the first detection unit. A detection unit configured such that the relative value of the second time constant of the RC circuit including the second resistance value of the two detection units changes according to the change of the physical quantity;
A pulse generation circuit configured to input a pulse signal to a common input terminal of the first detection unit and the second detection unit;
A time difference measuring circuit connected to the first output terminal of the first detection unit and the second output terminal of the second detection unit,
The time difference measuring circuit generates a first delayed pulse signal by delaying the pulse signal propagating through the first detection unit based on the first time constant, and outputs the pulse signal propagating through the second detection unit. It is configured to generate a second delay pulse signal delayed based on the second time constant, and measure a time difference between the first delay pulse signal and the second delay pulse signal,
The pulse generation circuit,
An oscillator circuit for generating a clock signal,
A divider circuit for dividing the clock signal to generate the pulse signal,
The time difference measuring circuit is to have a counter circuit for counting by using the clock signal a time difference between said first delayed pulse signal and said second delayed pulse signal with the clock signal is inputted,
The time difference measuring circuit,
A first buffer circuit connected to the first output terminal of the first detection unit;
A second buffer circuit connected to the second output terminal of the second detector,
The first buffer circuit shapes the first slowed-down pulse signal by slowing down the edge speed of the pulse signal propagating through the first detection unit based on the first time constant, thereby forming the first delayed pulse signal. Is configured to generate
The second buffer circuit shapes the second slowed-down pulse signal by slowing down the edge speed of the pulse signal propagating through the second detection unit based on the second time constant, thereby forming the second delayed pulse. Is configured to generate a signal,
Each of the first buffer circuit and the second buffer circuit has a current control type inverter in which an operating current is limited depending on a voltage applied to a bias terminal,
The current control type inverter of the first buffer circuit has a current control n-channel MOS transistor whose gate is connected to the bias terminal,
The current control type inverter of the second buffer circuit has a current control n-channel MOS transistor whose gate is connected to the bias terminal,
The bias terminal of the current control type inverter of the first buffer circuit is connected to the first output terminal of the first detection unit,
The physical quantity sensor , wherein the bias terminal of the current control type inverter of the second buffer circuit is connected to the second output terminal of the second detector . A physical quantity sensor,
A first detection unit having a first resistance value and a second detection unit having a second resistance value; and a first time constant of an RC circuit including the first resistance value of the first detection unit and the first detection unit. A detection unit configured such that the relative value of the second time constant of the RC circuit including the second resistance value of the two detection units changes according to the change of the physical quantity;
A pulse generation circuit configured to input a pulse signal to a common input terminal of the first detection unit and the second detection unit;
A time difference measuring circuit connected to the first output terminal of the first detection unit and the second output terminal of the second detection unit,
The time difference measuring circuit generates a first delayed pulse signal by delaying the pulse signal propagating through the first detection unit based on the first time constant, and outputs the pulse signal propagating through the second detection unit. It is configured to generate a second delay pulse signal delayed based on the second time constant, and measure a time difference between the first delay pulse signal and the second delay pulse signal,
The pulse generation circuit,
An oscillator circuit for generating a clock signal,
A divider circuit for dividing the clock signal to generate the pulse signal,
The time difference measuring circuit is to have a counter circuit for counting by using the clock signal a time difference between said first delayed pulse signal and said second delayed pulse signal with the clock signal is inputted,
The time difference measuring circuit,
A first buffer circuit connected to the first output terminal of the first detection unit;
A second buffer circuit connected to the second output terminal of the second detector,
The first buffer circuit shapes the first slowed-down pulse signal by slowing down the edge speed of the pulse signal propagating through the first detection unit based on the first time constant, thereby forming the first delayed pulse signal. Is configured to generate
The second buffer circuit shapes the second slowed-down pulse signal by slowing down the edge speed of the pulse signal propagating through the second detection unit based on the second time constant, thereby forming the second delayed pulse. Is configured to generate a signal,
Each of the first buffer circuit and the second buffer circuit has a current control type inverter in which an operating current is limited depending on a voltage applied to a bias terminal,
The current control type inverter of the first buffer circuit has a current control p-channel MOS transistor whose gate is connected to the bias terminal.
The current control type inverter of the second buffer circuit has a current control p-channel MOS transistor whose gate is connected to the bias terminal.
The bias terminal of the current-controlled inverter of the first buffer circuit is connected to the second output terminal of the second detector,
The physical quantity sensor , wherein the bias terminal of the current control type inverter of the second buffer circuit is connected to the first output terminal of the first detection unit . The relative value of the second resistance value of said first resistance value of said first detection portion and said second detection portion is configured so as to change according to the change of the physical quantity, according to claim 1 or 2 Physical quantity sensor. A polarity determination circuit configured to determine the polarity of change in the relative value of the first time constant and the second time constant based on the magnitude relationship between the first time constant and the second time constant. The physical quantity sensor according to claim 1, which is provided with the physical quantity sensor.

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