JP6703252B2 - A/D converter - Google Patents

Description

The present invention relates to an A/D converter that converts a signal from an image sensor into a digital value.

Conventionally, an A/D converter that converts a signal from the image sensor into a digital value of a plurality of bits has been used in the image sensor. For example, in Patent Document 1 below, a first cyclic A/D conversion circuit that receives an analog value from a column of an image sensor and generates a first digital value and a residual value of upper bits and its residual An A/D converter including a second cyclic A/D conversion circuit that receives a value and generates a second digital value of lower bits is disclosed. According to such an A/D converter, an A/D conversion circuit having lower precision than that of the first stage A/D conversion circuit can be applied to the second stage A/D conversion circuit.

Patent No. 5769178

In recent years, the higher speed of the A/D converter has been required along with the improvement in image quality of images. In order to meet such demands, it is apt to increase power consumption when attempting to realize high speed with the configuration of the conventional A/D converter.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an A/D converter capable of realizing high speed while suppressing power consumption.

In order to solve the above problems, an A/D converter according to one embodiment of the present invention is an A/D converter that is arranged in a column of an image sensor and that converts a signal from the image sensor into a digital value. , A cyclic first A/D conversion circuit that receives an analog value from the column and generates a first digital value and a residual value that represent the analog value, and cyclic first to M-2th (M is (An integer greater than or equal to 3) each of which receives the residual value from each of the A/D conversion circuits and also generates the second to (M-1)th digital values indicating the residual value and the residual second cyclic value. An M/A conversion circuit and an A/D conversion circuit that receives the residual value from the M-1 A/D conversion circuit and generates an Mth digital value indicating the residual value. , A non-cyclic M-th A/D conversion circuit for generating an M-th digital value by comparing a time-varying reference value and a residual value, and Each of the D conversion circuits includes a sub A/D conversion circuit that generates a digital value for each cycle, a logic circuit that receives the digital value from the sub A/D conversion circuit, and a D/A conversion circuit in response to a signal from the logic circuit. It has a D/A conversion circuit that generates a conversion value, an input, an output that provides a residual value, and a feedback path for cyclic A/D conversion that connects the output and the input, and receives the input. An operational amplifier that amplifies the input value and generates a difference between the amplified input value and the D/A converted value.

According to the A/D converter of the above aspect, in the first to M−1th A/D conversion circuits, the residual value that is the difference from the D/A conversion value is amplified while the signal from the image sensor is being amplified. The first to (M-1)th digital values are generated based on the residual value generated and the M-th A/D conversion is performed based on the residual value from the (M-1)th A/D conversion circuit. A Mth digital value is generated in the circuit. With such a configuration, the accuracy of A/D conversion required for the A/D conversion circuit on the subsequent stage side of the first to M−1th A/D conversion circuits and the Mth A/D conversion circuit can be improved to the former stage. As a result, the power consumption of the A/D conversion circuit as a whole can be reduced and the M-th A/D conversion circuit can be configured by adopting a non-recursive configuration. The power consumption of the circuit can be further reduced. Further, since the accuracy of the A/D conversion required for the A/D conversion circuit on the subsequent stage side can be lowered as compared with that on the preceding stage side, the speeding up of the A/D conversion process can be realized. As a result, it is possible to provide an A/D converter that can realize high speed while suppressing power consumption.

Here, in the A/D converter of the above-described embodiment, one of the A/D conversion circuits of the first to M−1th A/D conversion circuits outputs the first to M−1th digital values. The switching timing between the storage operation period for generating the constituent digital value and the calculation operation period for generating the residual value is set to the other A/D of the first to M−1th A/D conversion circuits. The conversion circuit may further include a timing control circuit for controlling the end of the storage operation period and the end of the arithmetic operation period. By doing so, it is possible to prevent the accuracy of the digital value and the residual value generated and output by the other A/D conversion circuit from being deteriorated due to the noise generated due to the influence of the operation of the one A/D conversion circuit.

Further, the timing control circuit in the A/D converter of the above-described aspect is configured such that, in the Mth A/D conversion circuit, the timing at which the digital value forming the Mth digital value sequentially generated from the residual value transits The end of the storage operation period for generating the digital values forming the first to (M-1)th digital values in the first to (M-1)th A/D conversion circuits, and the first to (M-1)th A/D conversions The circuit may be controlled so as to be removed from the end of the arithmetic operation period for generating the residual value in the circuit. In this case, the accuracy of the digital value and the residual value generated and output by the first to (M-1)th A/D conversion circuits is reduced due to the noise generated due to the influence of the operation of the Mth A/D conversion circuit. Can be prevented.

Further, the Mth A/D conversion circuit has a comparator that compares the residual value from the M−1th A/D conversion circuit with a reference voltage that changes sequentially, and based on the output of the comparator, It may be a successive approximation A/D conversion circuit configured to sequentially generate digital values that form the Mth digital value. In this case, the power consumption of the Mth A/D conversion circuit can be further reduced by adopting the successive approximation type configuration for the Mth A/D conversion circuit. Moreover, the accuracy of the M-th A/D conversion circuit can be made relatively low.

Further, the timing control circuit in the A/D converter of the above-described embodiment sets the clock timing for comparing the residual value and the reference signal in the Mth A/D conversion circuit to the A/D first to Mth A/D converters. Completion of the storage operation period for generating the digital values forming the first to M−1th digital values in the D conversion circuit, and calculation for generating the residual value in the first to M−1th A/D conversion circuits The control may be performed so that it is removed from the end of the operation period. In this case, the accuracy of the digital value and the residual value generated and output by the first to (M-1)th A/D conversion circuits is reduced due to the noise generated due to the influence of the operation of the Mth A/D conversion circuit. Can be prevented.

Furthermore, the Mth A/D conversion circuit compares the residual value from the (M−1)th A/D conversion circuit with a ramp signal that is a reference signal, and the timing of change in the output of the comparator. A single-slope A/D conversion circuit configured to generate the Mth digital value based on the output of the latch circuit. In this case, the power consumption of the Mth A/D conversion circuit can be further reduced by adopting the single slope type configuration for the Mth A/D conversion circuit. Moreover, the circuit configuration of the Mth A/D conversion circuit can be relatively simplified.

According to the present invention, speeding up can be realized while suppressing power consumption.

Part (a) is a diagram showing a circuit block of a CMOS image sensor circuit including an A/D converter according to the embodiment, and part (b) is a diagram schematically showing an example of A/D conversion characteristics in the first stage. is there. It is a figure which shows schematic structure of the A/D converter shown to (a) part of FIG. FIG. 3 is a circuit diagram showing a detailed configuration of a CDS circuit and first to second cyclic A/D conversion circuits of FIG. 2. FIG. 4 is a diagram showing a connection configuration of the first cyclic A/D conversion circuit of FIG. 3 during a storage operation and an arithmetic operation. FIG. 4 is a diagram showing a connection configuration of the second cyclic A/D conversion circuit of FIG. 3 during a storage operation and an arithmetic operation. It is a circuit diagram which shows the schematic structure of the 3rd non-cyclic A/D conversion circuit. It is a circuit diagram which shows the other structure of the 3rd non-cyclic A/D conversion circuit. It is a circuit diagram which shows the other structure of the 3rd non-cyclic A/D conversion circuit. 3 is a timing chart showing operation timing controlled by the control circuit of the A/D converter in FIG. 2. It is a figure which expands and shows a part of timing chart of FIG. 9 is a timing chart showing operation timing controlled by a control circuit of an A/D converter according to a modification. It is a figure which expands and shows a part of timing chart of FIG. It is a circuit diagram which shows the schematic structure of the 3rd non-cyclic A/D conversion circuit concerning a modification.

Hereinafter, preferred embodiments of an A/D converter according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same or corresponding parts will be denoted by the same reference symbols, without redundant description.

First, the configuration of a CMOS image sensor circuit including the A/D converter according to the embodiment will be described with reference to FIG.

Part (a) of FIG. 1 is a drawing schematically showing a circuit block of a CMOS image sensor circuit including an A/D converter 101 according to the embodiment. The vertical shift register 11 supplies the control signals Ri, Si, and TXi given to the pixels 13 forming the image array 12, and the signals due to the photocharges obtained in each pixel 13 are sent to the array 14 of the A/D converter 101. To transmit. The array 14 includes a plurality of A/D converters 101 and can process the signals from each pixel 13 in parallel. The control circuit (timing control circuit) 18 is connected in parallel to the plurality of A/D converters 101 and supplies control signals for controlling the timing of various operations of the A/D converters 101. The A/D conversion result for each 1H in the A/D conversion is stored in the data register 15 and read out after the A/D conversion by horizontal scanning according to the control signal from the horizontal shift register 16.

Referring to part (a) of FIG. 1, the A/D converter 101 is used in an image sensor circuit including pixels arranged in an array. The pixel 13 includes a sensor circuit 13a including a photodiode PDi and an amplifier circuit 13b that amplifies a sensor signal from the sensor circuit 13a. The pixel 13 receives the reset signal and initializes the internal state. After this initialization, the pixel 13 provides an electrical signal corresponding to the light received by the photodiode PDi. The electric signal includes not only a significant signal component but also a noise component such as reset noise. Each pixel 13 includes a photodiode PDi for converting light into an electric charge and several MOS transistors T1 to T4. Further, the transfer of charges is controlled by the transistor T1 responsive to the control signal TXi, the initialization of charges is controlled by the transistor T2 responsive to the control signal Ri, and the pixel selection is controlled by the transistor T3 responsive to the control signal Si. It Transistor T4 responds to the potential at junction J1 between transistors T1 and T2. In each pixel 13, reset noise is generated in response to the reset operation. In addition, the voltage output from each pixel 13 includes fixed pattern noise unique to each pixel. Random noise is generated by an element or the like connected to the input of the A/D converter 101. The pixels 13 are arranged in a matrix, and the signals from the pixels 13 are signals of a first signal level (signal VR) including a noise component and a signal of a second signal level including a signal component superimposed on the noise component. (Signal VS), which is transmitted to the array 14 of the A/D converter 101 via the signal line connected to the amplifier circuit 13b. In the A/D converter 101, by performing correlated double sampling, an input signal obtained by removing the reset level VR component from the signal level VS from the pixel 13 is input.

Next, a schematic configuration of the A/D converter 101 will be described. FIG. 2 is a schematic diagram of an A/D converter 101 that converts a signal from an image sensor into a digital value of Na+Nb+Nc=Nt bits (Na, Nb, and Nc are integers of 2 or more). The one-dimensional array of the A/D converter 101 is arranged in the column of the image sensor. The A/D converter 101 forming a one-dimensional array is connected to the column line COL of the image sensor and processes a signal from the amplifier circuit 13b (FIG. 1) of the pixel 13 connected to the column line COL. Each A/D converter 101 is not limited to being connected to one column of the image sensor, and may be connected to a plurality of columns, or a plurality of A/D converters 101 may be connected to one column. It may be connected to the column. This A/D converter 101 includes a correlated double sampling circuit (CDS circuit) 102, a first cyclic A/D conversion circuit 103, a second cyclic A/D conversion circuit 104, and a third cyclic A/D conversion circuit 104. And a non-cyclic A/D conversion circuit.

The CDS circuit 102 is connected between the column line COL and the first cyclic A/D conversion circuit 103, and outputs the input signal V _IN obtained by removing the reset level VR component from the signal level VS from the pixel 13. It is a circuit for generating. The first cyclic A/D conversion circuit 103 receives the input signal V _IN which is an analog value from the column line COL via the CDS circuit 102, and also the first digital of upper Na bits indicating the analog value. Generate a value and a residual value. The second cyclic A/D conversion circuit 104 receives the residual value from the first cyclic A/D conversion circuit 103 and receives the second digital value of the middle Nb bits indicating the residual value and the new value. Generate a residual value. The third non-cyclic A/D conversion circuit 105 receives the residual value from the second cyclic A/D conversion circuit 104 and generates a lower Nc-bit third digital value indicating the residual value. To do. Although the number of bits Na, Nb, and Nc can take various values, the accuracy required for the recursive A/D conversion circuit in the latter stage is lower, so that the recursive type in the latter stage is used to reduce the overall power consumption. It is preferable that the number of bits of the digital value generated by the A/D conversion circuit is larger. In this embodiment, for example, Na=3, Nb=6, and Nc=3 are designed. The first to third digital values generated by the first to second cyclic A/D conversion circuits 103 and 104 and the third non-cyclic A/D conversion circuit 105 are data conversion circuits 106a, It is output to the data register 15 (FIG. 1) via 106b and 106c. The data conversion circuit 106a synthesizes the first and second digital values output from the first and second cyclic A/D conversion circuits 103 and 104 and outputs the combined digital value to the data conversion circuit 106b. Outputs the first digital value and the second digital value to the data conversion circuit 106c by synthesizing the third digital value output from the third acyclic A/D conversion circuit 105. The data conversion circuit 106c converts the redundant representation digital value included in the digital value output from the data conversion circuit 106b into a non-redundant representation and outputs the non-redundant representation. In the present embodiment, since the first and second digital values output from the first and second cyclic A/D conversion circuits 103 and 104 are redundant representations that take three values, those digital values are It is converted into a non-redundant representation and output.

The A/D converter 101 shown in FIG. 2 is not limited to the configuration including the two cyclic A/D conversion circuits 103 and 104, and may include three or more cyclic A/D conversion circuits. Good. For example, the A/D converter 101 may include first to Nth (N is an integer of 3 or more) cyclic A/D conversion circuits and (N+1)th non-cyclic A/D conversion circuits. .. In such a case, the first cyclic A/D conversion circuit has the same configuration as the first cyclic A/D conversion circuit 103, and the second to Nth cyclic A/D conversion circuits are , And has the same configuration as the second cyclic A/D conversion circuit 104 except that the element sizes are different, and the N+1th non-cyclic A/D conversion circuit is the third non-cyclic A/D conversion circuit. It has the same configuration as the /D conversion circuit 105. Then, the second to N-th cyclic A/D conversion circuits receive the residual value from each of the first to N-1th cyclic A/D conversion circuits, and the second to second indicating the residual value. Generate N digital values and new residual values, respectively. The N+1th non-cyclic A/D conversion circuit receives the residual value from the Nth cyclic A/D conversion circuit, and generates the (N+1)th digital value indicating the residual value.

The configuration of the A/D converter 101 including the two cyclic A/D conversion circuits 103 and 104 will be described in detail below as an example. FIG. 3 is a circuit diagram showing a detailed configuration of the CDS circuit 102 and the first to second cyclic A/D conversion circuits 103 and 104.

The CDS circuit 102 includes an operational amplifier circuit 21, a capacitor 22 connected between the column line COL and the inverting input of the operational amplifier circuit 21, and a capacitor connected between the inverting input of the operational amplifier circuit 21 and the output. 23 and a reset switch 24, a capacitor 39 connected between the output of the operational amplifier circuit 21 and the input 31a of the first cyclic A/D conversion circuit 103, and between the capacitor 39 and the reference potential V _COM. And the connected switch 42. Such a CDS circuit 102 holds the reset level VR in the capacitor 22 by connecting the inverting input and the output of the operational amplifier circuit 21 with the reset switch 24, and thereafter disconnects the reset switch 24 and then the switch 42. The disconnection causes the capacitor 39 to sample the input potential V _IN corresponding to the difference between the signal level VS and the reset level VR.

The first cyclic A/D conversion circuit 103 includes a gain stage 31, a sub A/D conversion circuit 32, a logic circuit 33, and a D/A conversion circuit 34. The gain stage 31 includes an input 31a that receives an input signal V _IN that is converted to a digital value, and an output 31b that provides a calculated value for each cycle (residual value for each cycle) V _OP . The gain stage 31 also includes a single-end type operational amplifier circuit (operational amplifier) 35 and first to third capacitors 36 to 38. The operational amplifier circuit 35 has an inverting input terminal, a non-inverting input terminal, and an output terminal. For example, the non-inverting input terminal of the operational amplifier circuit 35 receives a reference potential _{V COM} is connected to a reference potential line _{L COM.} The sub A/D conversion circuit 32 generates a digital signal D that forms a first digital value according to the signal V _OP from the output 31b of the gain stage 31.

The sub A/D conversion circuit 32 can include, for example, two comparators 32a and 32b. The comparators 32a, 32b respectively compare the input analog signals with respective predetermined reference signals V _RCH , V _RCL and provide comparison result signals A ₁ , A ₀ . The digital signal D indicates an A/D conversion value for each cycle. The digital signal D has, for example, 2 bits (A ₀ , A ₁ ), and each bit (A ₀ , A ₁ ) can take “1” or “0”. Depending on the combination of bits (A ₀ , A ₁ ), the digital value for each cycle can take the first to third values (D=0, D=1, D=2). The logic circuit 33 receives the digital signal D having 2 bits (A ₀ , A ₁ ) from the sub A/D conversion circuit 32 and generates a control signal V _CONTa according to the digital signal D. If necessary, the sub A/D conversion circuit 32 compares the calculated value V _OP with a reference signal by using, for example, one comparator in a time division manner, and provides signals A ₁ and A ₀ indicating the comparison result. it can.

The gain stage 31 is configured to be able to execute a calculation operation and a storage operation. In the arithmetic operation, the arithmetic amplification circuit 35 and the first to third capacitors 36 to 38 generate the arithmetic value V _OP . In the storing operation, the calculated value V _OP is held in the first and second capacitors 36 and 37.

According to the first cyclic A/D conversion circuit 103, the first and second capacitors 36 and 37 output the two outputs of the D/A conversion circuit 34 via the switches 43a, 43b and 43c, respectively. It is connected to the. Further, the D/A conversion circuit 34 operates at least one of the voltage signals V _DA1a and V _DA2a by operating the switches 43a, 43b, 43c according to the control signal V _CONTa from the sub A/D conversion circuit 32. The first capacitor 36 can be provided, and at least one of the voltage signals V _DA1a and V _DA2a can be provided to the second capacitor 37. Therefore, in the arithmetic operation, the voltage signals V _DA1a and V _DA2a are switched and applied to one _ends of the capacitors 36 and 37, so that the gain stage 31 receives three types of D/A conversion values from the D/A conversion circuit 34. It operates as if it received the voltage signal. Specifically, in the first cyclic A/D conversion circuit 103, the D/A conversion circuit 34 responds to the first value (D=2) of the digital signals (A ₀ , A ₁ ), The voltage signal V _RH is provided to the capacitors 36 and 37. The D/A conversion circuit 34 provides the voltage signals V _RH and V _RL to the capacitors 36 and 37, respectively, in response to the second value (D=1) of the digital signal (A ₀ , A ₁ ). The D/A conversion circuit 34 provides the voltage signal V _RL to the capacitors 36 and 37 in response to the second value (D=0) of the digital signal (A ₀ , A ₁ ). According to the first cyclic A/D conversion circuit 103, when the first and second voltage signals of the D/A conversion circuit 34 are provided to the capacitors 36 and 37, two types of voltage signals are generated. , 37 through 37.

Part (b) of FIG. 1 shows conversion characteristics between the calculated value V _OP by the first cyclic A/D conversion circuit 103 and the digital value D for each cycle. The relationship between the digital value D and the range of the calculated value V _OP is as follows.
When D=0, V _RCL >V _OP ,
When D=1, V _RCH ≧V _OP ≧V _RCL ,
When D=2, V _OP >V _RCH ,
Becomes The sub A/D conversion circuit 32 generates a redundant code (a ternary digital signal) by comparing the calculated value V _OP from the gain stage 31 with two predetermined reference signals (storage operation). Then, the gain stage 31 generates the calculated value V _OP used in the next cycle according to the generated digital value D (calculation operation).

The gain stage 31 includes a plurality of switches for connecting the first to third capacitors 36 to 38 and the operational amplifier circuit 35. Although these switches are shown in FIG. 3, the arrangement of the switches 41 and 43 to 46 is an example. Control of these switches 41, 43 to 46 is performed by a control circuit (timing control circuit) 18 (see FIG. 1).

The second cyclic A/D conversion circuit 104 has substantially the same configuration as the first cyclic A/D conversion circuit 103 except that the size of each element is different. An A/D conversion circuit 52, a logic circuit 53, and a D/A conversion circuit 54 are provided. More specifically, the gain stage 51 includes an input 51a that receives the calculation value V _OP generated in the last cycle from the first cyclic A/D conversion circuit 103, and a calculation value for each cycle (residual value for each cycle). Output 51b which provides the difference value) V _OP . The gain stage 51 also includes a single-end type operational amplifier circuit (operational amplifier) 55 and first to third capacitors 56 to 58. The gain stage 51 differs from the gain stage 31 of the first cyclic A/D conversion circuit 103 in the connection configuration of the switches 63 and 67. In addition, the configurations of the sub A/D conversion circuit 52, the logic circuit 53, and the D/A conversion circuit 54 are the same as the sub A/D conversion circuit 32, the logic circuit 33, and the first cyclic A/D conversion circuit 103. The configuration is the same as that of the D/A conversion circuit 34. That is, the sub A/D conversion circuit 52 includes two comparators 52a and 52b.

FIG. 4 is a diagram showing a connection configuration of the above-described first cyclic A/D conversion circuit 103 during storage operation and arithmetic operation. Portions (a) and (b) of FIG. 4 show connection configurations during the CDS operation in which the input signal V _IN is input. During the CDS operation, the reference potential V _COM is held in the capacitor 39 of the CDS circuit 102 so that the reset level VR of the column line COL is canceled (part (a) of FIG. 4). After that, the capacitor 39 of the CDS circuit 102 is connected to the inverting input of the operational amplifier circuit 35, so that the input signal V _IN corresponding to the difference between the signal level VS of the column line COL and the reset level VR is sampled and the operational amplifier. _Is generated as the output V _OP (part (b) of FIG. 4).

In this CDS operation, the reset level VR (including reset noise) of the column line COL is canceled by resetting the pixel and simultaneously switching the switch 24 from the on (connected state) to the off (disconnected state). In addition, the input potential V _IN of the capacitor 39 is held at the reference potential V _COM . At this time, the switch 24 is switched by the clock signal (control signal) (φ _CDS =1→0) from the control circuit 18, the switch 42 is turned on by the clock signal (φ _S1 =1), and the clock signal (φ _Sa = 0, φ _2a =0, φ _1a =0, φ _Ra =0) makes the switches 43 to 46 non-conductive. Then, in order to generate the signal V _OP corresponding to the difference between the signal level VS and the reset level VR, the connection between the capacitor 39 and the reference potential V _COM is disconnected by the switch 42, and the capacitor 39 and the operational amplifier circuit 35 are inverted. The input terminal is connected via the switches 43 and 44. At this time, the switches 43 and 44 are turned on by the clock signal (control signal) (φ _Sa =1, φ _2a =1) from the control circuit 18, and the clock signals (φ _S1 =0, φ _1a =0, φ _Ra =0) makes the switches 42, 45, 46 non-conductive. By such a CDS operation, a voltage value V _OP as shown in the following equation is generated.
V _OP =(C _CDS3 /C ₂ )·(C _CDS1 /C _CDS2 )·(VS-VR)
This voltage value V _OP is a value in which noise caused by the operational amplifier circuit 21 which is a variable gain amplifier is canceled in addition to the reset noise of the pixel.

FIG. 4C shows the connection configuration during the storing operation. In the storing operation, the calculated value V _OP which is the output value of the operational amplifier circuit 35 is stored in the capacitors 36, 37 and 38. For storage, capacitors 36, 37 are connected in parallel with each other. In this storing operation, the calculated value V _OP is provided to the sub A/D conversion circuit 32 as an analog signal. In order to store the calculated value V _OP in the capacitors 36 and 37, the capacitors 36 and 37 are connected to the output 31b via the switches 41 and 43a, and the reference potential V _COM is supplied to the capacitors 36 and 37 via the switch 45. To do. At the same time, by disconnecting the switches 43 and 44, the connection between the capacitors 36, 37 and 39 and the inverting input terminal of the operational amplifier circuit 35 is released. At this time, the switches 41 and 43a are turned on by the clock signal (φ _3a =1, φ _DSa =1) from the control circuit 18, and the clock signals (φ _Sa =0, φ _2a =0, φ _Ra =0). Makes the switches 43, 44, 46 non-conductive. The capacitors 36 and 37 are separated from the input 31a by the switch 43, and the capacitors 36 and 37 are separated from the inverting input of the operational amplifier circuit 35 by the switch 44. During the storing operation of the gain stage 31, the inverting input of the operational amplifier circuit 35 becomes the reference potential V _COM .

In this storing operation, the sub A/D conversion circuit 32 receives the operation value V _OP and generates the digital signal D in response to the clock φ _ca. The digital signal D is provided to the logic circuit 33, and the logic circuit 33 generates the control signal V _CONTa that controls the D/A conversion circuit 34.

Part (d) of FIG. 4 shows the connection configuration during the arithmetic operation. In this arithmetic operation, the D/A conversion value is added to one end of the capacitors 36 and 37 according to the generated digital signal D, and amplification and residual value generation are performed. After performing the required number of cyclic operations in the first cyclic A/D conversion circuit 103, the residual value is provided to the second cyclic A/D conversion circuit 104. In this calculation operation, the gain stage 31 generates the calculation value V _OP by the calculation amplification circuit 35 and the capacitors 36 to 38. In the arithmetic operation, the capacitor 38 is connected between the output of the operational amplifier circuit 35 and the inverting input, and the capacitors 36 and 37 are connected between the D/A conversion circuit 34 and the inverting input of the operational amplifier circuit 35. .. In this way, a feedback path for the cyclic A/D conversion is formed between the output and the input of the operational amplifier circuit 35. The D/A conversion circuit 34 provides the voltage signal V _DA1 and/or V _DA2 to the gain stage 31 according to the value of the control signal V _CONTa . The calculated value V _OP is generated at the output 31b of the gain stage 31 in response to the application of the voltage signals V _DA1 and V _DA2 .
The generated operation value V _OP is represented by the following formula.
V _OP =(1+C ₁ /C ₂ )×V _IN −V _R ,
C ₁ =C _1a +C _1b
In the above formula, the value _{V R} is defined by the voltage signals _{V DA1, V DA2} from the D / A converter circuit 34 is expressed by the following equation.
When the condition D=2 is satisfied, V _R =(C _1a +C _1b )×V _RH /C ₂ .
When the condition D=1 is satisfied, V _R =(C _1a ×V _RH +C _1b ×V _RL )/C ₂ .
When the condition D=0 is satisfied, V _R =(C _1a +C _1b )×V _RL /C ₂ .

When the relation C _1a =C _1b =C ₂ /2 is satisfied, the above equations and relations can be rewritten as:
V _OP =2×V _IN −V _R
When the condition D=2 is satisfied, V _R =V _RH .
When the condition D=1 is satisfied, V _R =(V _RH +V _RL )/2.
When the condition D=0 is satisfied, V _R =V _RL .
That is, the D/A conversion circuit 34 generates three values of _VRH , _VRL or a voltage ( _VRH + _VRL )/2 at the midpoint thereof with respect to the three-valued A/D converted value.

In this operation, the deviation between the absolute values of the reference voltages V _RH and V _RL does not affect the linearity of the A/D conversion characteristic, and only the accuracy of generating the midpoint voltage affects the linearity. The capacitance ratio accuracy of the capacitor defines this midpoint voltage. In the semiconductor integrated circuit, the accuracy of the capacitance ratio is much higher than the accuracy of the resistance ratio, and a highly accurate cyclic A/D conversion circuit can be provided.

During this arithmetic operation, the capacitors 36 and 37 are connected to the inverting input of the operational amplifier circuit 35 via the switch 44 in order to generate the arithmetic value V _OP . At this time, the switch 44 is turned on by the clock signal (φ _2a =1) from the control circuit 18, and is switched by the clock signals (φ _3a =0, φ _Sa =0, φ _1a =0, φ _Ra =0). 41, 43, 45 and 46 are made non-conductive. One ends of the capacitors 36 and 37 are separated from the reference potential line L _COM by the switch 45, and the other ends of the capacitors 36 and 37 are separated from the output 31b by the switch 41.

After the CDS operation, the storage operation to the arithmetic operation are repeated to generate a column of digital signals D. This repetition is repeated until the A/D conversion result of the predetermined number of bits Na is obtained. For example, if the circuit is circulated L times, a digital signal D corresponding to approximately L+1 bits can be obtained.

FIG. 5 is a diagram showing a connection configuration of the second cyclic A/D conversion circuit 104 during storage operation and arithmetic operation. FIG. 5A shows the connection configuration during the initial storage operation when the operation value V _OP is input from the first cyclic A/D conversion circuit 103. In the initial storage operation, the calculated value V _OP is stored in the capacitors 56 to 58. Capacitors 56-58 are connected in parallel with each other for storage. Further, the initial calculated value V _OP is provided to the sub A/D conversion circuit 52.

In this initial storage operation, in order to store the initial calculated value V _OP in the capacitors 56 to 58, the capacitors 56 and 57 are connected to the input 51a via the switch 63, and the capacitor 58 is connected via the switches 61 and 63. The reference potential V _COM is supplied to the capacitors 56 and 57 via the switch 64 while being connected to the input 51a. At this time, the switches 61, 63, 63a, 64, by the clock signal (control signal) from the control circuit 18 (φ _3b =1, φ _Sb =1, φ _DSb =1, φ _2b =1, φ _Rb =1). While making 66 conductive, the switches 65 and 67 are made non-conductive by the clock signal (φ _1b =0, φ _4b =0). The capacitor 58 and the output 51b are separated by the switch 67, and the output 51b and the input 51a are separated by the switch 67. In the gain stage 51, the reference potential V _COM is generated at the output of the operational amplifier circuit 55 when the input and output of the operational amplifier circuit 55 are conducted. In this connection, the sub A/D conversion circuit 52 receives the initial operation value V _OP and generates the digital signal D in response to the clock φ _cb . The digital signal D is provided to the logic circuit 53, and the logic circuit 53 generates the control signal V _CONTb for controlling the D/A conversion circuit 54.

FIG. 5B shows the connection configuration during the arithmetic operation. In this arithmetic operation, the D/A conversion value is added to one end of the capacitors 56 and 57 according to the generated digital signal D, and amplification and further generation of a residual value are performed. After performing the necessary number of cyclic operations in the second cyclic A/D conversion circuit 104, the residual value is provided to the third non-cyclic A/D conversion circuit 105. In this calculation operation, the gain stage 51 generates the calculation value V _OP by the calculation amplification circuit 55 and the capacitors 56 to 58. The connection configuration in this arithmetic operation is the same as the configuration of the first cyclic A/D conversion circuit 103 (portion (d) of FIG. 4), and therefore description thereof will be omitted.

During this arithmetic operation, the capacitors 56 and 57 are connected to the inverting input of the operational amplifier circuit 55 via the switch 64 in order to generate the arithmetic value V _OP . At this time, the switches 64 and 67 are made conductive by the clock signal (φ _2b =1 and φ _4b =1) from the control circuit 18, and the clock signals (φ _3b =0, φ _Sb =0, φ _1b =0, φ _Rb =0) makes the switches 61, 63, 65, 66 non-conductive. One ends of the capacitors 56 and 57 are separated from the reference potential line L _COM by the switch 65, and the other ends of the capacitors 56 and 57 are separated from the output 51b by the switch 61.

Part (c) of FIG. 5 shows the connection configuration during the storage operation after the second patrol operation. In the storing operation, the calculated value V _OP on the output of the operational amplifier circuit 55 is stored in the capacitors 56, 57 and 58. Capacitors 56, 57 are connected in parallel with each other for storage. In this storing operation, the calculated value V _OP is provided to the sub A/D conversion circuit 52 as an analog signal. The connection configuration in this arithmetic operation is the same as the configuration of the first cyclic A/D conversion circuit 103 (portion (c) of FIG. 4 ). In order to store the calculated value V _OP in the capacitors 56, 57, the capacitors 56, 57 are connected to the output 51b via the switches 61, 63a, 67, and the reference potential V _{COM is applied} to the capacitors 56, 57 via the switch 65. To supply. At this time, the switches 61, 63a, 65, 67 are turned on by the clock signal (φ _1b =1, φ _DSb =1, φ _3b =1, φ _4b =1) from the control circuit 18, and the clock signal (φ _Sb =0, φ _2b =0, φ _Rb =0) renders the switches 63, 64, 66 non-conductive. The capacitors 56 and 57 are separated from the input 51a by the switch 63, and the capacitors 56 and 57 are separated from the inverting input of the operational amplifier circuit 55 by the switch 64. During the storing operation of the gain stage 51, the inverting input of the operational amplifier circuit 55 becomes the reference potential V _COM .

The storage operation to the arithmetic operation are repeated after the initial storage operation to the arithmetic operation to generate the series of digital signals D. This repetition is repeated until the A/D conversion result of the predetermined number of bits Nb is obtained.

FIG. 6 is a circuit diagram showing a schematic configuration of the third acyclic A/D conversion circuit 105. The third non-cyclic A/D conversion circuit 105 receives the calculated value V _OP which is the residual value from the second cyclic A/D conversion circuit 104, and receives a third digital value indicating the calculated value V _OP. To generate. Specifically, the third non-cyclic A/D conversion circuit 105 executes the non-cyclic A/D conversion by the comparison signal between the reference voltage (reference value) that changes with time and the calculated value V _OP. A /D conversion circuit, for example, a successive approximation A/D conversion circuit that performs A/D conversion by comparing a reference potential obtained by sequentially cutting by a switch means and the calculated value V _OP with a reference potential, , A single slope type A/D conversion circuit that performs A/D conversion by comparing a reference potential generated based on the ramp signal with time and a calculated value V _OP .

FIG. 6 shows an example of the configuration of the third acyclic type A/D conversion circuit 105 to which the successive approximation type A/D conversion circuit is applied. Third non-cyclic A / D conversion circuit 105, a comparator for comparing the sample and hold (S / H) circuit 71 for sampling / holding the input operation value _{V OP,} and a reference voltage and the operation value _{V OP} ( Comparator 72, a decoder 73 for selecting a reference voltage to be input to the comparator 72, a plurality of switches 76a to 76g controlled by the decoder 73, and a digital value based on the selection by the decoder 73 and the comparison signal by the comparator 72. It is composed of a register 74 for determining and storing, and a control circuit 75 for controlling the operations of the register 74 and the comparator 72. A plurality of reference voltages having stepwise voltages are input to the third acyclic A/D conversion circuit 105 from the voltage dividing circuit 77 commonly provided in the array of the A/D converters 101. , So that one reference voltage is selectively input to one input of the comparator 72 from among the plurality of reference voltages, the voltage dividing circuit 77 and one input of the comparator 72 are connected via the switches 76a to 76g. It is connected. Further, the calculated value V _OP is input to the other input of the comparator 72 via the S/H circuit 71.

The third non-cyclic A/D conversion circuit 105 as described above is configured to be capable of implementing, for example, a 3-bit A/D conversion operation as follows. Although the 3-bit A/D conversion processing is described here, an A/D conversion operation of an arbitrary bit can be realized by the same operation. That is, the control circuit 75 controls the register 74 and the decoder 73 so as to select the reference voltage of the middle value among the reference voltages of seven stages, and the register 74 receives the comparison voltage obtained from the comparator 72 as a result. Determine and store the most significant bit value based on the signal. Next, the control circuit 75 controls the register 74 and the decoder 73 in accordance with the comparison signal of the comparator 72, so that the reference value of the middle value is selected from the reference voltages of three steps which are higher or lower than the selected reference voltage. Controlled to select the voltage, register 74 determines and stores the intermediate bit value based on the resulting comparison signal from comparator 72. Further, similarly, the control circuit 75 controls the register 74 and the decoder 73 according to the comparison signal of the comparator 72, thereby controlling the one-step reference voltage higher or lower than the selected reference voltage. The register 74 determines and stores the least significant bit value based on the comparison signal obtained from the comparator 72 as a result. Then, finally, the digital value stored in the register 74 is output as the third digital value.

By employing the third non-cyclic A/D conversion circuit 105 having such a configuration, there is an advantage that the circuit area can be reduced. That is, since there is no capacitor except for the S/H circuit, noise generation due to the coupling between the wiring and the capacitor can be reduced, so that restrictions on the circuit layout of the LSI or the like are reduced.

FIG. 7 shows another example of the configuration of the third acyclic A/D conversion circuit to which the successive approximation A/D conversion circuit is applied. The third acyclic A/D conversion circuit 105A includes a comparator 72A that compares the input operation value V _OP with a reference voltage, a plurality of capacitors 81a to 81d connected to the input of the comparator 72A, and a capacitor 81a. To 81d, a plurality of switches 83a to 83d, 85a to 85d, 87b to 87d, a switch 89 connected between the input and output of the comparator 72A, and switches 85b to 85d and 87b to 87d are controlled. The register 91 stores the A/D conversion result. Although a configuration capable of performing 3-bit A/D conversion processing has been described here, an A/D conversion operation of an arbitrary bit can be realized with the same configuration.

In the third non-cyclic A/D conversion circuit 105A, the switches 83a to 83d and 89 are turned on by the clock signal (φ _S =1 and φ _Sd =1), so that the inverting input and output of the comparator 72A are obtained. And the calculated value V _OP is sampled in the capacitors 81a to 81d. At this time, the inverting input of the comparator 72A is set to the virtual ground potential. Next, the switches 83a to 83d and 89 are cut off by the clock signal (φ _S =0, φ _Sd =0), the 3-bit code is set in the register 91, and the code is set to the capacity array D/A conversion unit. The capacitors 81a to 81d are operated. Specifically, the 3-bit code is (D0, D1, D2) (D0 is the MSB, and D0 to D2 have a binary value of "0" or "1"), and D2="1". In the case of, the control signal D _2H =“1” and the control signal D _2L =“0” are set, and in the case of D ₂ =“0”, the control signal D _2H =“0” and the control signal D _2L =“1”. The control signals D _2H and D _2L that have been set are output from the register 91. It should be noted that when the calculation value V _OP is being sampled by the clock signal (φ _Sd =1), the control signal D _2H =“0” and the control signal D _2L =“0” are set.

The net charge Q _{NET at} the inverting input of the comparator 72A does not change between when the calculated value V _OP is sampled in the capacitors 81a to 81d and when the capacitors 81a to 81d are connected to the reference power source by the control of the register 91. According to this law of conservation of charge, the relationship between the voltage Vs at the inverting input of the comparator 72A, the calculated value V _OP, and the reference power supply is obtained by the following equation.

Here, ΔV _R =V _RH −V _RL , V _RL is a voltage value input to the capacitors 81 a to 81 d via the switches 85 a to 85 d, and V _RH is a capacitor 81 b to via the switches 87 b to 85 d. It is the voltage value input to 81d. To summarize this, the following formula;

Is obtained. That is, Vs is given by the difference between the calculated value V _OP and the output of the capacitance array D/A converter.

The register 91 of the third acyclic A/D conversion circuit 105A is set so that the resolution is improved by 1 bit as the operation proceeds. For example, in the first step, the 3-bit code is set as (D0, D1, D2)=(1, 0, 0). At this time, the comparator 72A compares the calculated value V _OP with V _RL +0.5ΔV _R =0.5(V _RH +V _RL ). That is, the comparator 72A sets the AD conversion range as the range from the voltage V _RH to the voltage V _RL and compares the central value with the calculated value V _OP . If the calculated value V _OP is larger than 0.5 (V _RL +V _RH ), the register 91 determines D0=“1”. If the calculated value V _OP is smaller than 0.5 (V _RL +V _RH ), the register 91 determines D0=“0”. Next, the register 91 sets (D0, D1, D2)=(1, 1, 0) in the second step if D0=“1” is determined. Thereby, the second bit is determined by comparing the calculated value V _OP with V _RL +0.75ΔV _R =0.75V _RH +0.25V _RL . By repeating such an operation up to the third step, the third acyclic A/D conversion circuit 105A can realize the successive approximation A/D conversion having a resolution of 3 bits.

FIG. 8 shows another example of the configuration of the third non-cyclic A/D conversion circuit to which the successive approximation A/D conversion circuit is applied. The third non-cyclic A/D conversion circuit 105B shown in FIG. 8 includes an S/H circuit 71, a three-input comparator 101a for comparing the operation value V _OP and a reference voltage, and a reference voltage input to the comparator 101a. A logic circuit 103a to 103d for generating V _R1 and V _R2 based on the output of the voltage dividing circuit 77 and switches 105a to 105d and 107a to 107d, and a register 109 for deciding and storing a digital value based on a comparison signal from the comparator 101a. Composed of and. Although a configuration capable of performing 3-bit A/D conversion processing has been described here, an A/D conversion operation of an arbitrary bit can be realized with the same configuration.

In the third non-cyclic A/D conversion circuit 105B, similar to the non-cyclic A/D conversion circuit 105 shown in FIG. 6, 3-bit successive approximation type A/D conversion is possible. That is, according to the bit codes (D1, D2) set by the register 109, the logic circuits 103a to 103d and the switches 105a to 105d and 107a to 107d generate two reference voltages V _R1 and V _R2 from the voltage dividing circuit 77. It is selected and input to the two input terminals 1- and 2- of the comparator 101a, and according to the set bit code (D0), two reference voltages V _R1 and V _{R2 are} converted into the following formulas inside the comparator 101a. A reference voltage V _Ref as shown in is generated.
V _Ref =V _R1 +V _R2 /2 (when A0="0"),
V _Ref =V _R1 (when A0=“1”)
Then, in the comparator 101a, the bit voltages (D0, D1, D2) are sequentially determined by comparing the sequentially generated reference voltage V _Ref with the calculated value V _OP .

In the acyclic A/D conversion circuit 105B of 3 having the above configuration, the number of reference voltages input from the voltage dividing circuit 77 can be reduced, so that the overall circuit scale can be made relatively small.

Next, an operation procedure of the A/D converter 101 described above will be described. FIG. 9 is a timing chart showing the operation timing controlled by the control circuit 18 of the A/D converter 101, and FIG. 10 is an enlarged view showing a part of the timing chart of FIG. 9 and 10, (a) shows the horizontal period of the signal to be processed for pixel signal transfer, (b) shows the timing of the control signal Ri, and (c) shows the control signal TXi. Timing is shown, (d) shows the timing of charge output from the pixel, (e) shows the timing of correlated double sampling by the control signal φ _CDS , and (f) and (g) show the control signal. The timings of φ _S1 and φ _Sa are shown. Further, (h) shows the horizontal period of the signal to be processed by the first cyclic A/D conversion circuit 103, and (i) shows the A/D of the first cyclic A/D conversion circuit 103. The timing of the conversion storage operation and the arithmetic operation is shown, and the timing of the control signal φ _Sb is shown in (j). Further, (k) shows the horizontal period of the signal to be processed by the second cyclic A/D conversion circuit 104, and (l) shows the A/D of the second cyclic A/D conversion circuit 104. The timing of the storage operation and the operation of the conversion are shown, the timing of the control signal φ _Sc is shown in (m), and the signal to be processed by the third acyclic A/D conversion circuit 105 is shown in (n). Is shown, and the timing of successive comparison of A/D conversion of the third non-cyclic A/D conversion circuit 105 is shown in (o).

As shown in FIG. 9, the first to second cyclic A/D conversion circuits 103 and 104 and the third non-cyclic A/D conversion circuit 105 have a function of sampling/holding a signal to be processed. Therefore, pipeline processing in parallel with each other can be executed. That is, the first cyclic A/D conversion circuit 103 completes the A/D conversion processing for the Nth horizontal period and outputs the calculated value V _OP to the second cyclic A/D conversion circuit according to the control signal φ _Sb. Immediately after being held at 104, the A/D conversion process for the (N+1)th horizontal period is started. Similarly, the second cyclic A/D conversion circuit 104 completes the A/D conversion processing for the Nth horizontal period and outputs the calculated value V _OP to the third non-cyclic A/D conversion signal in accordance with the control signal φ _Sc. Immediately after being held by the conversion circuit 105, the A/D conversion process for the (N+1)th horizontal period is started.

Since the pipeline processing is executed in this manner, the control circuit 18 controls the timing of each control signal so as to deviate from the predetermined timing in order to ensure the accuracy of A/D conversion (timing control). That is, the control circuit 18 switches the timing of switching between the storage operation period and the arithmetic operation period in one of the first and second cyclic A/D conversion circuits 103 and 104 (A/D conversion circuit). The transition period) is controlled so as to be excluded from the end of the storage operation period and the end of the arithmetic operation period in the other A/D conversion circuit of the first and second cyclic A/D conversion circuits 103 and 104. Further, the control circuit 18 sets the timing (transition period) at which the bit code generated by the successive comparison in the third non-cyclic A/D conversion circuit 105 transits (transition period) to the first and second cyclic A/D conversion circuits. It is controlled so as to be removed from the end of the storage operation period of 103 and 104 and the end of the calculation operation period. In particular, it is important from the viewpoint of improving accuracy that the transition period of the A/D conversion circuit on the rear stage side is excluded from the end of the storage operation period and the end of the arithmetic operation period of the A/D conversion circuit on the front stage side.

Such timing control will be described with reference to FIG. 10(i) and 10(l) show the timing of the storage operation period and the calculation operation period for each digital value by the A/D conversion processing for each bit, for example, the m-th bit (m=1 to 9). The storage operation period and the calculation operation period of) are indicated by "Sm" and "Am". Further, in (o) of FIG. 10, the timing of successive approximation of each digital value in the A/D conversion process is indicated by “Dm” (m=10 to 12). Then, the transition timing of the storage operation period and the arithmetic operation period in the cyclic A/D conversion processing, and the transition timing of the transition of the bit code of the non-cyclic A/D conversion are indicated by dotted line squares. Further, the timings (control target timings) that are desired to be removed so that these transition timings do not overlap in time are shown by being surrounded by solid line squares. The control target timing includes the following (1) Timing when the switch 42 is turned on and off by the control signal φ _S1 and the reset level is held (P1, FIG. 4A to FIG. 4B). )).
(2) Timing at which the switches 43 and 44 are turned on and off by the control signal φ _Sa and the control signal φ _{2 a} and the difference between the reset level and the signal level is held (P2, FIGS. 4B to 4C). ..
(2′) Timing at which the switch 63 is turned on and off by the control signal φ _Sb and the calculated value V _OP is held (P2′, FIG. 5A to FIG. 5B).
(3) Timing when the calculated value V _OP is generated and then the switches 44 and 64 are turned on and off to hold the calculated value V _OP (P3, FIG. 4D to FIG. 4C, FIG. 5B). )-FIG.5(c)).
(4) Timing at which A/D conversion is performed on the held calculation value V _OP , the switches 41, 45, 61, 65 are turned from ON to OFF, and a transition is made to the calculation operation (P4, FIG. 4C to FIG. 4C). 4(d), FIG. 5(c) to FIG. 5(b)).
(5) Timing at which each bit code is generated in the non-cyclic A/D conversion (P5).
The control circuit 18 generates a control signal so that the transition timing in A/D conversion deviates from these control target timings. In particular, in the cyclic A/D conversion circuit on the upper stage side, removing the controlled object timings (1) to (4) from the transition timing is highly effective in improving accuracy. This is because the former stage side has a lower amplification factor of the input signal, so that it is possible to effectively improve the conversion accuracy by preventing noise mixing.

According to the A/D converter 101 described above, in the first and second cyclic A/D conversion circuits 103 and 104, the signal from the image sensor is amplified and is a difference from the D/A conversion value. A residual value is generated, first to second digital values are generated based on the residual value, and a third non-value is generated based on the residual value from the second cyclic A/D conversion circuit 104. The cyclic A/D conversion circuit 105 generates a third digital value. With such a configuration, the A required for the A/D conversion circuit on the subsequent stage side of the first to second cyclic A/D conversion circuits 103 and 104 and the third non-cyclic A/D conversion circuit 105 As a result that the accuracy of the A/D conversion can be made lower than that of the preceding stage side, the overall power consumption of the A/D conversion circuit can be reduced, and the third non-cyclic A/D conversion circuit 105 has a non-cyclic configuration. By doing so, the power consumption of the third non-cyclic A/D conversion circuit 105 can be further reduced. Further, since the accuracy of the A/D conversion required for the A/D conversion circuit on the subsequent stage side can be lowered as compared with that on the preceding stage side, the speeding up of the A/D conversion process can be realized. As a result, it is possible to provide an A/D converter that can realize high speed while suppressing power consumption.

The accuracy of the A/D conversion required for the A/D conversion circuit on the post-stage side can be made lower than that on the pre-stage side, and as a result, the power consumption of the A/D conversion circuit on the post-stage side can be reduced as follows. First, the first reason will be described. In general, a transistor or a capacitor can be relatively improved in accuracy even if the dimension varies in the LSI manufacturing process by increasing the dimension. Therefore, when the required accuracy is high, the dimension is increased. Then, the charging/discharging current to the capacitor increases, the bias current of the transistor increases, and the power consumption increases. Conversely, if the required accuracy is low, the size can be reduced, and the bias current and the charge/discharge current can be reduced, so that the power consumption can be reduced. There is also an advantage that the element area can be reduced. Next, the second reason will be described. When high accuracy is required for A/D conversion, a large amount of current needs to be passed in order to shorten the time until settling within that accuracy, resulting in high power consumption. If the accuracy requirement for settling is low, the current required to achieve the same settling time is low and power consumption can be low. Further, as a third reason, if the required accuracy of A/D conversion is low and the offset voltage of the amplifier may be large, the size of the transistor can be reduced, and thus the power consumption can be reduced. And the fourth reason will be described. In order to reduce the 1/f noise of the transistor, it is necessary to increase the size of the transistor. On the contrary, if the required accuracy of the A/D conversion is low, the 1/f noise of the transistor may be large, and the size of the transistor can be reduced, so that the power consumption can be reduced.

Here, in the A/D converter 101, in the first to second cyclic A/D conversion circuits 103 and 104, the transition timing between the storage operation period and the arithmetic operation period in one circuit is set to the other. The circuit is controlled so as to be removed from the end of the storage operation period and the end of the arithmetic operation period. By doing so, the digital signal generated and output by the other A/D conversion circuit due to noise (for example, noise that enters the hold node via parasitic capacitance or the like) generated due to the operation of the one A/D conversion circuit. It is possible to prevent the accuracy of the value and the residual value from decreasing. As a result, the accuracy of A/D conversion can be improved.

Further, in the A/D converter 101, the timing at which the bit code sequentially generated from the residual value in the third non-cyclic A/D conversion circuit 105 transitions is set to the first or second cyclic A/D. The D conversion circuits 103 and 104 are controlled so as to be excluded from the end of the storage operation period and the end of the arithmetic operation period. In this case, the first to second cyclic A/D due to noise (for example, noise mixed into the hold node via parasitic capacitance or the like) generated due to the influence of the operation of the third non-cyclic A/D conversion circuit 105. It is possible to prevent the accuracy of the digital value and the residual value generated and output by the D conversion circuits 103 and 104 from decreasing. As a result, the accuracy of A/D conversion can be improved.

In particular, in order to set the timing for determining one bit by A/D conversion to the timing at which the bit signal by another A/D conversion does not transit, a non-cyclic A/D conversion circuit is adopted at the final stage. Is effective. This is because in the successive approximation type A/D conversion, the timing per bit that must be shifted is half that of the cyclic type in which there are two operation stages, a store operation and an arithmetic operation.

The present invention is not limited to the above embodiments. The above embodiment may be modified to the following configurations.

For example, in the third acyclic A/D conversion circuit 105, the S/H circuit 71 may be omitted. 11 is a timing chart showing the operation timing of the A/D converter according to the modified example not including the S/H circuit, and FIG. 12 is an enlarged view showing a part of the timing chart of FIG. 11. .. The difference between the operation of the present modified example and the operation of the A/D converter 101 is that the operation period “A9” of the last cyclic operation in the second cyclic A/D conversion circuit 104 is the third non-cyclic type. The point is that the A/D conversion circuit 105 is controlled to continue during the periods “D10”, “D11”, and “D11” during which the A/D conversion process is being performed. Also in this modification, the control circuit 18 controls the transition timing in the A/D conversion so as to deviate from the control target timing (FIG. 12 ).

Further, in the above-described embodiment, the third non-cyclic A/D conversion circuit 105 of successive approximation type is adopted, but a single slope type A/D conversion circuit may be adopted. FIG. 13 shows the configuration of the third non-cyclic A/D conversion circuit 105C according to the modification.

The third acyclic type A/D conversion circuit 105C shown in FIG. 13 is a single slope type A/D conversion circuit. The third non-cyclic A/D conversion circuit 105C uses the S/H circuit 71 that samples/holds the calculated value V _OP from the second cyclic A/D conversion circuit 104, and the calculated value V _OP as a reference signal. A comparator 111 for comparing with a certain ramp signal, a flip-flop (FF) circuit 113, a latch circuit 115 for holding a change timing of the output of the comparator 111, and a conversion circuit 117 are included. The third non-cyclic A/D conversion circuit 105C is provided with a ramp signal generation circuit 119, a gray code counter 121, and a control circuit 123 commonly to the array. The latch circuit 115 receives the count value counted by the gray code counter 121 based on the clock from the control circuit 123. The ramp signal generation circuit 119 generates a ramp signal according to the control signal from the control circuit 123. The comparator 111 receives the final operation value V _OP of the second cyclic A/D conversion circuit 104 at one input, receives the ramp signal from the ramp signal generation circuit 119 at the other input, and receives these signals. The comparison signal that is compared is output. Further, the comparator 111 provides the comparison signal to the storage control input LOAD of the latch circuit 115 via the FF 113. In response to this comparison signal, the latch circuit 115 latches the gray code count value at that time. The latched Gray code count value is generated and output as an A/D conversion value (third digital value) via the conversion circuit 117.

Also in the modified example in which the third acyclic A/D conversion circuit 105C is adopted, the control circuit 18 also generates a control signal so that the transition timing in A/D conversion deviates from the control target timing. However, the timing (clock timing by the control circuit 123) for latching the gray code coefficient value after comparing the calculated value V _OP and the reference signal in the third acyclic A/D conversion circuit 105C is A/D conversion. Is controlled so as to deviate from the end of the storage operation period and the end of the arithmetic operation period in the cyclic A/D conversion. As a result, the first to second cyclic A/D due to noise (for example, noise mixed into the hold node via parasitic capacitance or the like) generated due to the influence of the operation of the third non-cyclic A/D conversion circuit 105C. It is possible to prevent the accuracy of the digital value and the residual value generated and output by the D conversion circuits 103 and 104 from decreasing. Further, by using such a single slope type A/D conversion circuit in the final stage, the degree of freedom of A/D conversion timing can be increased. That is, in the case of A/D conversion of a small number of bits (3 or 4 bits or less), the transition timing that must be shifted from other A/D conversions is about 16 times at most.

101... A/D converter, 103... First cyclic A/D conversion circuit, 104... Second cyclic A/D conversion circuit, 105... Third non-cyclic A/D conversion circuit, 33, 53... Logic circuit, 32, 52... Sub A/D conversion circuit, 34, 54... D/A conversion circuit, 35, 55... Operational amplifier circuit (operational amplifier), 18... Control circuit (timing control circuit), 72, 72A, 101, 111... Comparator, 115... Latch circuit.

Claims (4)

An A/D converter which is arranged in a column of the image sensor and converts a signal from the image sensor into a digital value,
A cyclic first A/D conversion circuit that receives an analog value from the column and generates a first digital value and a residual value indicating the analog value;
Residual values are received from each of the cyclic-type first to M-2 (M is an integer of 3 or more) A/D conversion circuits, and the second to M-1th digital values indicating the residual values are received. And cyclic-type second to M−1th A/D conversion circuits for respectively generating residual values and
An A/D conversion circuit that receives a residual value from the (M-1)th A/D conversion circuit and generates an Mth digital value indicating the residual value, the reference value changing with time, and An acyclic M-th A/D conversion circuit for generating the M-th digital value by comparison with a residual value ;
A timing control circuit for controlling operation timings of the first to Mth A/D conversion circuits;
Equipped with
Each of the first to M-1th A/D conversion circuits includes:
A sub A/D conversion circuit that generates a digital value for each cycle,
A logic circuit that receives the digital value from the sub A/D conversion circuit;
A D/A conversion circuit that generates a D/A conversion value in response to a signal from the logic circuit;
An input, an output that provides the residual value, and a feedback path for cyclic A/D conversion that connects the output and the input, and amplifies the input value received by the input, an operational amplifier for generating a difference between the amplified input value and the D / a conversion value, was closed,
The timing control circuit,
In one of the first to (M-1)th A/D conversion circuits, a storage operation period for generating a digital value that constitutes the first to (M-1)th digital values, and The timing of switching between the calculation operation period for generating the residual value and the end of the storage operation period in the other A/D conversion circuit of the first to M−1th A/D conversion circuits is And controlling so as to remove from the end of the arithmetic operation period and the timing of generation of the Mth digital value of the Mth A/D conversion circuit,
In the M-th A/D conversion circuit, the transition timings of the digital values forming the M-th digital value sequentially generated from the residual value are set to the first to M-1th A/D conversion circuits. In the end of the storage operation period in, and control to be removed from the end of the arithmetic operation period,
A/D converter. The Mth A/D conversion circuit includes a comparator that compares the residual value from the M−1th A/D conversion circuit with a reference voltage that changes sequentially, and based on the output of the comparator. A successive approximation A/D conversion circuit configured to sequentially generate digital values that form the Mth digital value,
The A/D converter according to claim 1 . The timing control circuit may set a clock timing for comparing the residual value and a reference signal in the M-th A/D conversion circuit to the first clock in the first to (M-1)th A/D conversion circuits. -End of the storage operation period for generating the digital value forming the (M-1)th digital value, and the end of the arithmetic operation period for generating the residual value in the first to (M-1)th A/D conversion circuits Control to remove from
The A/D converter according to claim 1 . The Mth A/D conversion circuit compares a residual value from the M−1th A/D conversion circuit with a ramp signal that is the reference signal, and a change in output of the comparator. A single-slope A/D conversion circuit configured to generate a Mth digital value based on an output of the latch circuit, the latch circuit holding a timing.
The A/D converter according to claim 3 .