JP6697162B2 - Amusement machine - Google Patents

Description

  The present invention relates to an effect control device for controlling an effect device in a game machine, and more particularly to an effect control device for an effect machine which is characterized by transmitting control information to the effect device.

  In general, gaming machines such as slot machines and pachinko machines are provided with a display device using LEDs, a liquid crystal display device, a sound generating device, and the like, and depending on the gaming state. Various performances are performed. The operation of these effect devices is performed by the effect control device by controlling lighting / blinking display of LEDs, display of various symbols on the liquid crystal display device, and sound generation from the sound generation device. For this reason, the effect control device is provided with software that operates on the CPU, and this software performs light emission control of the LEDs, effect control of symbols on the liquid crystal display device, and effect control by sound from the sound generation device.

  A display device using an LED, which is one of the production devices, includes a plurality of LEDs and a light emitting production member that emits light by receiving illumination from the plurality of LEDs to perform a production display, and each of the plurality of LEDs is controlled to emit light. By doing so, the corresponding light-emission effect member is caused to emit light to perform a desired effect. For this reason, the effect control device needs to individually control the lighting / blinking control of the plurality of LEDs. In the gaming machine, a large number of LEDs are arranged corresponding to the positions of a plurality of light emitting effect members provided at various positions, and a plurality of LED control circuits for controlling the light emission of these LEDs are provided in the light emitting effect members. Correspondingly provided. The effect control device and the LED control circuits arranged at these various positions are connected via a predetermined connection interface, and the light emission brightness control information of the LEDs is transmitted to each LED control circuit.

  A large number of electromagnetic components that generate inductive noise according to the operation are used in the gaming machine, and the inductive noise from these electromagnetic components flows through a connection interface between the effect control device and the LED control circuit (emission brightness. There is a possibility that an incorrect light emission brightness control information signal is sent from the effect control device to each LED by being superimposed on the control information signal). For this reason, it is necessary to devise a connection interface that connects the effect control device and the LED control circuit away from the electromagnetic component, or use a connection interface that is less susceptible to the inductive noise from the electromagnetic component.

  The effect control device is configured by being provided with a CPU and storage elements such as ROM and RAM, and these are connected by a parallel bus to transmit and receive various information. Therefore, it is easy to use the parallel bus connection for the connection interface between the effect control device and each peripheral circuit such as the LED control circuit, but there is a problem that the number of connection lines becomes too large. Therefore, it is common practice to connect the effect control device and various peripheral circuits via a serial interface (also called a serial bus). As this serial interface, an I2C bus (also called an I2C serial interface) or a three-wire serial interface is used not only in game machines but also in various general devices.

The I2C bus is an interface that uses two types of signal lines, a clock line and a data line, and the three-line serial interface is an interface that uses three types of signal lines: an enable line, a clock line, and a data line. A signal is sent by each of the. Therefore, there is a possibility that the induction noise from the electromagnetic components in the gaming machine is superimposed on the signal sent through each signal line to generate an erroneous signal. On the other hand, there is an LVDS interface (an interface that uses an LVDS signal) as a connection interface that is less susceptible to such inductive noise. The LVDS interface is a serial interface that transmits a clock signal, a data signal, etc. in the form of a differential voltage between two lines, and even if inductive noise is superimposed on these two lines in phase, the differential voltage is not affected. Is.

  Patent Document 1 discloses an example of a connection device configuration of such a gaming machine. In the device of Patent Document 1, the main CPU and the sub control circuit are connected via a serial interface of the I2C bus. In the sub control circuit, the information sent from the main CPU through the I2C serial interface, for example, the LED emission brightness control information is converted into an LVDS signal, and the LDVS serial interface is used to generate the LED sound board (here, the LED control circuit is used). Comprises)). The LED sound board performs LED control by converting the received LVDS signal into an LED control signal (LED emission brightness control).

JP2012-170790A

  Generally, the connection interface between the effect control device and the peripheral circuit including the LED control circuit is not limited to the game machine, but it is preferable to use an I2C bus used as a standard serial interface or a three-wire serial interface. However, it is necessary to consider that it is preferable to connect an LVDS interface, which is less susceptible to this influence, to a place that is easily affected by the inductive noise from the electromagnetic components arranged in the gaming machine. Therefore, an LED control circuit that uses a standard serial interface connection (3-wire serial or I2C interface connection) where it is unlikely to be affected by inductive noise from an electromagnetic component and uses an LVDS interface connection when passing near an electromagnetic component is preferable. When such an LED control circuit is used, a plurality of LED control circuits are provided in the gaming machine, and each of the plurality of LED control circuits has a plurality of LEDs to be controlled by its own LED control circuit at a predetermined cycle. It is conceivable to configure so as to perform lighting / blinking control of. If the LED control circuit performs lighting / blinking control of a plurality of LEDs to be controlled at the same timing, a large current change occurs during the lighting / blinking control, so that switching noise occurs from the LED control circuit and the LED control is performed. Propagates to devices around the circuit and may cause malfunction of surrounding devices. Therefore, there arises a problem that another device cannot be arranged in the vicinity of the LED control circuit.

  The present invention has been made in view of the above circumstances, and provides a gaming machine capable of suppressing switching noise generated when the effect output control unit controls the emission brightness of a plurality of LEDs. The purpose is to

In order to achieve such an object, the gaming machine according to the present invention performs the lottery by satisfying the lottery trigger, and in the gaming machine which can give a profit based on the lottery result, the gaming machine corresponds to the lottery result. Main control means for transmitting a lottery result signal (for example, the main control board 60, main CPU 61, main control board 200, main CPU 201, control device CD of the embodiment) and a lottery result signal transmitted from the main control means. Determines the contents of the effect control, and transmits an effect control signal corresponding to the determined effect control contents in the first communication mode (for example, the sub-main control board 70A, the sub-main CPU 71, the effect of the embodiment). Control board 300, sub-main CPU 301, control device CD) and reception control signal of the first communication mode (for example, I2C bus, 3-wire serial interface, standard serial interface of the embodiment) transmitted from the sub control means. It is possible to perform the effect control by performing the effect control, and it is also possible to convert the effect control signal into the effect control signal of the second communication mode (for example, the LVDS interface of the embodiment) and transmit the effect. A first effect control means capable of performing effect control by receiving an effect control signal transmitted from the first effect control means in the second communication mode; The production control means and the second production control means are connected to an input unit for receiving a production control signal, and are capable of receiving a signal of the first communication form (for example, an input of the embodiment). circuit IC1, IC 2, IC 2) and, a second input means capable of receiving signals of the second communication mode connected to the input section (e.g., a differential input circuit DIC 1, DIC2 embodiment), first Input means and third input means for switching and setting the operation of the second input means (for example, the mode designation terminal MODE of the embodiment), and the first effect control means includes the third input means. The first input means is operated by the second input means to receive the effect control signal of the first communication form from the sub control means, and in the second effect control means, the third input means causes the second input means. Is operated to receive the effect control signal of the second communication form from the one effect control means, and the first effect control means and the second effect control means are M (M is a positive integer). It has a PWM phase control circuit which have the M number of the drive pin which can control the number of presentation components (e.g., LED control circuit LC embodiments), PWM phase control circuit driving the M A gaming machine having an individual control function capable of setting output start time timings of the respective driving terminals with a fixed time difference from each other .

  The present invention has been made in view of the above circumstances, and it is possible to suppress switching noise that occurs when the effect output control unit controls the emission brightness of a plurality of LEDs, and the device configuration is simple. Therefore, the device design becomes easy, and the cost of the device can be reduced.

FIG. 3 is a front view of the slot machine according to the first embodiment. It is a control block diagram of the slot machine. It is a function lock figure of a LED control circuit. It is a connection explanatory view showing an example of connection of a control device and a LED control circuit. It is a connection explanatory view showing another example of connection of a control device and a LED control circuit. It is a connection explanatory view showing a multi-drop connection example and a cascade connection example of a plurality of LED control circuits. 7 is a time chart showing changes over time of an enable signal, a clock signal, and a data signal of a 3-wire serial interface. 6 is a time chart showing a time change of a clock signal and a data signal of the LVDS interface. It is a time chart which shows the time change of each signal in order to show the 3-wire-> 2-wire bridge function from the 3-wire serial interface to the LVDS interface. It is a time chart which shows the time change of each signal in order to show the 2 wire-> 2 wire repeater function from an LVDS interface to an LVDS interface. It is the mimetic diagram which shows the byte constitution and bit constitution of production control information. It is a schematic diagram which shows the light emission luminance value of an LED control circuit, and the relationship of PWM control. It is a schematic diagram which shows the individual control of the PWM phase control of an LED control circuit. It is a schematic diagram which shows the group control of the PWM phase control of an LED control circuit. It is a schematic diagram which shows the group control of the PWM phase control of an LED control circuit. (A) is a time chart showing the initialization pattern 1. (B) is a time chart showing the initialization pattern 2. It is a front view of a pachinko game machine according to the second embodiment. It is a rear view of the pachinko game machine. It is a control block diagram of the pachinko game machine.

[First Embodiment]
Hereinafter, a slot machine (see FIG. 1) as one embodiment of a gaming machine according to the present invention will be described. First, the configuration of the slot machine will be described with reference to FIGS.

<Appearance of slot machine>
As shown in FIG. 1, the slot machine according to the present embodiment includes a front door 2 that is openably and closably attached to the front surface of a main body housing. The panel assembly 10, the middle panel assembly 20, the lower panel assembly 30, and the saucer assembly 40 are attached.

  A display screen 11a of an image display device (liquid crystal display device) 11 (see FIG. 2) arranged on the back side of the upper panel assembly 10 is arranged in the central portion of the upper panel assembly 10 so as to face the front, and its peripheral portion. The first effect lamp 12, the second effect lamps 13a and 13b, and the third effect lamps 14a and 14b are arranged in the. A pair of upper speakers 15a and 15b are arranged on the left and right below the display screen 11a. Each of these effect lamps is composed of a lamp display section (effect display member) visually recognized from the outside and an LED provided on the back side thereof, and the lamp display section emits light by illumination from the LED. Also called an LED lamp. That is, the first effect lamp 12, the second effect lamps 13a and 13b, and the third effect lamps 14a and 14b have an LED lamp structure, and the light emission control of the LED controls the light emission of the lamp display section.

  A display window W facing the surfaces of three reels 3a, 3b, 3c arranged side by side in the main body housing is provided at the center of the middle panel assembly 20, and below the display window W. Is a medal slot 21 for inserting a game medal (game medium), a 1-BET switch 22 for betting one game medal within the credited range, a maximum bet allowable number (for example, three) MAX-BET switch 23 for betting game medals at one time, clearing switch 24 for paying out bet game medals and / or credited game medals, all reels 3a, 3b, 3c (reel Is also referred to as a "revolving cylinder"), and a start lever (start switch) 25 operated when starting rotation, and three stop switches 26a, 26b for individually stopping rotation of the reels 3a, 3b, 3c, 26c (the stop switch 26a on the left side in the figure corresponds to the reel 3a, the stop switch 26b in the center corresponds to the reel 3b, the stop switch 26c on the right side corresponds to the reel 3c) and the medal slot 21 A reject switch 27 for returning the accumulated game medals is provided.

  The inside of the medal insertion slot 21 is provided in the case where the inserted game medal is effectively accepted and the receiving passage through which the game medal passes (which leads to the hopper 50 described later) and when the inserted game medal cannot be accepted. The game medal passes through a return passage (which leads to a game medal payout opening 41 to be described later) through which a blocker 48 (see FIG. 2) is provided. The blocker 48 guides the game medals inserted into the medal insertion slot 21 to the receiving passage during the period in which the inserted game medals are effectively accepted, and is inserted into the medal insertion slot 21 during the other periods. In order to guide the game medal to the return passage, the receiving passage and the return passage can be selectively opened, one of which can be opened and the other of which can be closed. In the following description, the blocker 48 being in the ON state means that the game medals inserted in the medal insertion slot 21 are guided to the receiving passage (the state in which the game medals can be received), and the blocker 48 being in the OFF state means that the medals are inserted. It is assumed that the game medals inserted into the mouth 21 are guided to the return passage (game medals cannot be accepted).

  Inside the medal insertion slot 21, three insertion medal sensors 28a, 28b, 28c (see FIG. 2) for detecting game medals are provided. The inserted medal sensor 28a detects that a game medal has been inserted into the medal insertion slot 21, and is located on the upstream side of the position where the blocker 48 is installed on the passage through which the inserted game medal flows down. It is installed in the position. The inserted medal sensor 28b detects that the game medal inserted into the medal insertion slot 21 is guided to the receiving passage and is effectively received, and is located downstream of the position where the blocker 48 is installed (described later). It is arranged at a position near the hopper 50). The insertion medal sensor 28c detects that the game medal inserted into the medal insertion slot 21 has passed through the branch portion between the receiving passage and the return passage, and the vicinity of the branch portion (the position where the blocker 48 is installed). It is arranged at a position slightly closer to the inserted medal sensor 28b).

  When both the inserted medal sensor 28a and the inserted medal sensor 28b detect a game medal, it means that the game medal has been inserted into the medal insertion slot 21 and that the inserted game medal has been effectively accepted. On the other hand, when the inserted medal sensor 28a detects the game medal but the inserted medal sensor 28b does not detect the game medal, the game medal is inserted into the medal insertion slot 21, but the inserted game medal is effectively accepted. It means that the item was returned without being returned. When the three inserted medal sensors 28a, 28b, 28c detect the passage of the game medals in a different order from the predetermined order (the order of 28a, 28c, 28b) or when some of the inserted medal sensors detect the passage of the game medals. If not, it means that an abnormal passage such as backflow of the game medal has occurred.

  The display window W is configured such that when all the three reels 3a to 3c are stopped, three symbols for each reel, a total of nine symbols, are displayed so that the player can visually recognize them. The pay line 29 that connects the symbol display areas in the middle tiers of the reels 3a to 3c horizontally (horizontal straight line) is a pay line that is activated by betting a specified number of game medals, and the activated pay line Whether or not a game combination is established is determined based on the symbol combination stopped and displayed on 29. Hereinafter, the activated winning line 29 will be appropriately referred to as an “effective line 29”.

  Various display lamps are arranged in the slot machine. In the present embodiment, as the display lamp, the MAX-BET switch display lamp 46a, the BET number display lamp 46b, the insertable display lamp 46c, the game start display lamp 46d, the re-game display lamp 46e, the status display lamp 46f, and the number display lamp. 46 g, a stored number display lamp 46 h, and a payout number display lamp 46 j are provided. These display lamps are configured to be controlled by a main control board 60 (main control means 100) described later. Each of these display lamps also has an LED lamp configuration including a lamp display portion (effect display member) visually recognized from the outside and an LED provided on the back side thereof. Done.

  The MAX-BET switch display lamp 46a is lit under the condition that a game medal can be bet, is arranged inside the MAX-BET switch 23, and when lit, the MAX-BET switch 23 is partially or entirely. It is designed to shine. The other display lamps are arranged on the side or the lower part of the display window W in the middle panel assembly 20.

  The BET number display lamp 46b (hereinafter also referred to as "BET lamp 46b") displays the number of betted game medals, and is a 1-BET display lamp that is turned on when the number of betted game medals is one. 46bA, a 2-BET display lamp 46bB that is turned on when there are two sheets, and a 3-BET display lamp 46bC that is turned on when there are three sheets. The insertable display lamp 46c is turned on under the condition that a game medal can be inserted. The game start display lamp 46d is turned on under the condition that the game can be started by operating the start lever 25. The re-play display lamp 46e is turned on when a re-play combination described below is established in an arbitrary game and a game medal is automatically bet by an automatic bet process described below.

  The status display lamp 46f is turned on when the accumulated medals are settled. The accumulated number display lamp 46h (hereinafter also referred to as "CRE lamp 46h") displays the number of accumulated (credited) game medals in 7 segments. The payout amount display lamp 46j (hereinafter also referred to as "WIN lamp 46j") displays the number of game medals to be paid out when a small winning combination described later is established, in 7 segments.

  The WIN lamp 46j is also configured to display a character (alphabet) indicating the type of error when an abnormality (error) occurs in the slot machine. The errors set in this embodiment include HP error, HE error, H0 error, CE error, CP error, CH error, C0 error, C1 error, FE error, E1 error, E5 error, E6 error, E7 error, etc. There is. The HP error is an error when it is determined that there is an abnormality in the passage of the game medal by the payout sensor of the medal detection unit 51 described later, and the HE error is when the game medal in the hopper 50 described later is determined to be empty. Is an error (hopper empty error), and the H0 error is an error when it is determined that there is an abnormal input to the payout sensor. The CE error is an error (game medal retention error) when it is determined by the inserted medal sensor that the game medals have accumulated, and the CP error is an error when it is determined that the inserted game medals have been illegally passed. The C0 error is an error when it is determined that there is an abnormal input to the inserted medal sensor, and the C1 error is an error when it is determined that there is an abnormality in passing through the inserted medal sensor. The FE error is an error when it is determined that the auxiliary storage 85 described later is full (an auxiliary storage full error), the E1 error is an error when the power supply cannot be restored normally, and the E5 error is all It is an error when the combination of symbols at the time of spinning cylinder stop becomes abnormal (corresponding symbols constituting the winning combination other than the winning combination winning combination are stopped), and the E6 error is the setting value for defining the winning combination determination probability is out of range. The E7 error is an error when an abnormality in the update state of the random number used in each lottery or the like is detected. Each error of E1, E5, E6, and E7 (these are collectively referred to as “E system error”) is canceled by a setting change described later, and other errors are canceled by an operation of a reset switch 82 described later. It is like this.

  The WIN lamp 46j also has a function of displaying a navigation number, which will be described later, indicating the operation order (pushing order) of the stop switches 26a to 26c. Hereinafter, the WIN lamp 46j when displaying the navigation order number will be appropriately referred to as a "main side push order indicator".

  A transparent lower panel cover 31 is attached to the central portion of the lower panel assembly 30, and decorative lamps 32a and 32b are arranged on both left and right ends thereof. On the back surface side of the lower panel cover 31, a semi-transparent lower panel base provided with a predetermined pattern and a lower panel illumination light (neither of which is shown) are attached, and the lower panel illumination light is turned on. Thus, the design of the lower panel base is configured to be illuminated from the rear surface side. Each of the decorative lamps 32a and 32b also has an LED lamp configuration including a lamp display portion (effect display member) visually recognized from the outside and an LED provided on the back side thereof. Control is performed.

  The tray assembly 40 has a game medal payout opening 41 for paying out game medals, and a game medal storage tray 42 for accumulating game medals so as to face the game medal payout opening 41. An ashtray 43 is provided on the left of the game medal storage tray 42. On the left and right of the game medal payout opening 41, speaker openings 45a, 45b composed of a large number of small holes are provided so as to face the front surfaces of a pair of lower speakers 44a, 44b (see FIG. 2) arranged on the back side of the tray assembly 40. Are formed.

  A hopper 50 (see FIG. 2) for paying out game medals obtained when a predetermined winning mode is formed as a result of the game is provided in the main body housing, and the hopper 50 is provided with the game medals. A medal detection unit 51 (see FIG. 2) for detecting the is provided. The hopper 50 has a function of physically storing the game medals that have been thrown in and effectively accepted. An auxiliary storage 85 (see FIG. 2) for storing the game medals overflowing from the hopper 50 is provided in the vicinity of the hopper 50, and the auxiliary storage 85 is full (from the auxiliary storage 85 to the game medals). A full detection unit 86 (see FIG. 2) is provided to detect whether or not there is a possibility of overflow.

<Reel>
Each reel 3a, 3b, 3c is configured to rotate by driving a stepping motor 35a, 35b, 35c (see FIG. 2). Each reel 3a, 3b, 3c is made of a translucent member, and a translucent reel tape having a plurality of types of symbols (see FIG. 3) is attached to the outer peripheral surface thereof. Has been. Back lamps 38a, 38b, 38c (see FIG. 2) are provided on the inner surfaces of the reels 3a, 3b, 3c. By turning on the back lamps 38a, 38b, 38c, the interior of the display window W is reduced. Illuminates the area of each reel 3a, 3b, 3c facing the entire surface from the inner surface side, or a predetermined symbol combination stopped and displayed on each reel 3a, 3b, 3c (for example, on the effective line 29 or the effective line). It is configured to illuminate only a partial area of each reel 3a, 3b, 3c so that the corresponding symbols of the game roles arranged on the winning line different from the above 29) are conspicuous. LEDs are used for these Bop lamps.

<Basic operations for playing games>
To play a game on the slot machine, first place a game medal into the medal insertion slot 21 to bet, or operate either the 1-BET switch 22 or the MAX-BET switch 23 to within the credit range. By betting a specified number of game medals at, the winning line 29 of the plurality of winning lines is activated. In this embodiment, the prescribed number of game medals required to activate the pay line 29 is three in each of the non-RT, RT1 to RT5, BB-A, and BB-B game states described later. Is set to. However, the specified number is not limited to this, and can be changed as appropriate, such as setting the specified number to a different value according to the RT state and the like. The activated pay line may be changed according to the number of bets on the game medal.

Next, when the player operates the start lever 25, the bet number is fixed (the betted game medals are used for the game), and a combination determination process described later is performed, and then the minimum game time ( The time that must be secured at least from the start of rotation of all reels in one game to the start of rotation of all reels in the next game (eg 4.1
After confirming that each of the reels 3a to 3c starts to rotate, a plurality of types of symbols displayed on the outer peripheral surface of the reels 3a to 3c are vertically moved in the display window W (normally). , From top to bottom) is displayed. Then, when the rotation of the reels 3a to 3c reaches a predetermined speed and becomes a constant speed rotation, the respective stop switches 26a to 26c are activated (the operation of the stop switches can be effectively accepted), and the player stops the switch 26a. Is operated to stop the rotation of the reel 3a, the stop switch 26b is operated to stop the rotation of the reel 3b, and the stop switch 26c is operated to stop the rotation of the reel 3c.

  Here, if the symbol combination stopped and displayed on the activated line 29 is in a predetermined winning mode (corresponding symbol of a gaming role that can obtain a game medal), the number of coins corresponding to each winning mode Game medals are paid out by the hopper 50 or added as credits.

<Connection between control board and each device>
In this embodiment, as main control boards for controlling the slot machine, as shown in FIG. 2, three control boards, that is, a main control board 60, a sub-main control board 70A, and a sub-sub-control board 70B are provided (sub-main board). The control board 70A and the sub-sub-control board 70B are collectively referred to as the sub-control board 70). Main control relating to the progress of the game (including drive control of reels 3a to 3c, winning combination determination processing, etc.) is performed by a control circuit provided on the main control board 60, and illumination by lamps such as back lamps 38a to 38c. The control and the like are configured to be performed by the lamp control circuit 18 provided on the sub-main control board 70A. The effect image display control by the image display device 11 and the sound generation control from the speakers such as the upper speakers 15a and 15b are mainly configured to be performed by the control circuit arranged on the sub-sub control board 70B. Information can be transmitted between the main control board 60 and the sub-control board 70 in only one direction from the main control board 60 to the sub-main control board 70A. Information can be transmitted to and from 70B in both directions.

  On the main control board 60, there are a main CPU 61 that performs various kinds of arithmetic processing related to games, a ROM 62 that is a read-only storage device that stores control programs and the like, and a RAM 63 that is a storage device that can write and read information. The slot machine is provided with the control program stored in the ROM 62, and each drive circuit operates to control the progress of the game in the slot machine. The ROM 62 and the RAM 63 are non-volatile storage devices, and are configured to retain the stored information even when power is not supplied. The main CPU 61 and the ROM 62 and the RAM 63 are connected to each other via a parallel bus to exchange information.

  The main CPU 61 is used for a clock pulse generator 64 for generating a drive pulse, a frequency divider 65 for frequency-dividing a drive pulse generated by the clock pulse generator 64, a role determination process (role lottery), and the like. A random number generator 66 for generating a random number and a sampling circuit 67 for sampling the random numbers generated by the random number generator 66 and performing a lottery are connected. The clock pulse generator 64 and the frequency divider 65 are configured to also function as an interval timer for the main CPU 61 to generate an interrupt at every predetermined time. The main CPU 61 is configured to execute a predetermined interrupt process, update or reset the clock data of various timers that have been set, according to the pulse (clock signal) from the interval timer. The parallel bus of the main control board 60 is connected to the interface circuit 68, and the interface circuit 68 has a parallel bus extension function and an interface conversion function of the parallel bus and the three-wire serial bus. A parallel bus connection is made between the main control board 60 and the peripheral circuit (motor drive circuit 36a, switch board 90, display lamp control circuit 47, hopper drive circuit 52, reel position detection circuit 37a). , 37b, 37c, the payout detection signal circuit 53, and the storage state signal circuit 87) are connected by a three-wire serial interface by an interface conversion function. Therefore, the main CPU 61 sends a signal to the sub-main CPU 71 using the parallel bus connection. Further, the main CPU 61 sends signals to the motor drive circuit 36a, the display lamp control circuit 47, and the hopper drive circuit 52 by using the three-wire serial interface connection, and also the reel position detection circuits 37a, 37b, 37c, the switch board. 90, the payout detection signal circuit 53, and the storage state signal circuit 87. Although a three-wire serial interface connection configuration is used to connect the main control board 60 to the peripheral circuits, an IC2 bus (I2C serial interface) connection may be used instead. Further, the signal transmission from the main CPU 61 to the sub main CPU 71 is not limited to the parallel bus connection. Signals may be transmitted from the main CPU 61 to the sub-main CPU 71 using a 3-line serial interface connection.

The motor drive circuit 36a is a circuit for controlling the rotation / stop of the stepping motors 35a, 35b, 35c for rotationally driving the reels 3a, 3b, 3c, respectively, and the display lamp control circuit 47 is for the above-mentioned various display. It is a circuit for controlling the lamp for use. As described above, in the connection with the display lamp control circuit 47, the interface circuit 68 performs interface conversion into a three-line serial interface, so that the display lamp control circuit 47 emits the LED light emitted in the form of a three-line serial interface signal. The control information signal is converted into an LED control signal, and the light emission control of the display lamps 46a to 46h, 46j is performed. However, the LVDS interface connection is also used in consideration of the influence of the inductive noise from the electromagnetic components on the wiring portion reaching the display lamps 46a to 46h, 46j, which will be described later. The reel position detection circuits 37a, 37b, 37c detect the rotational positions of the reels 3a, 3b, 3c based on the respective detection signals from the reel sensors (not shown) installed on the reels 3a, 3b, 3c, respectively. (The detection circuit 37a corresponds to the reel 3a, the detection circuit 37b corresponds to the reel 3b, and the detection circuit 37c corresponds to the reel 3c). The hopper drive circuit 52 is a circuit for driving the hopper 50 to pay out the game medals when the small winning combination is established, and the payout detection signal circuit 53 shows that the game medals have been paid out from the hopper 50. It is a circuit that sends a payout detection signal to the main control board 60 when it is detected by the medal detection unit 51. Further, the storage state signal circuit 87 is a circuit that transmits a storage state signal indicating whether or not the auxiliary storage case 85 is in the full state to the main control board 60 according to the detection result of the full state detection unit 86. ..

  Electric power from the power supply device 80 is supplied to the slot machine via the main control board 60. A power switch 81, a reset switch 82 and a setting key type switch 83 are connected to the power supply device 80, and signals from these switches are transmitted to the main CPU 61 via the interface circuit 68. ing. The main CPU 61 is configured to receive a signal from the setting change switch 84 via the interface circuit 68.

  The power switch 81 is a switch that accepts power-on and power-off operations from the power supply device 80 to the slot machine, and the reset switch 82 causes a predetermined error (errors other than the above E-system error) in the slot machine. In this case, the switch is operated by a game shop staff or the like when the cause of the error is removed and the error is resolved. By operating this reset switch 82, the information of the error occurrence stored in the main control board 60 and the sub control board 70 is cleared, and accordingly, the processing at the time of error elimination is performed in the main control board 60 and the sub control board 70. Executed. The setting key type switch 83 is a switch operated when confirming and changing the setting of the winning combination determination probability (probability of winning a game combination) and the like, and the setting change switch 84 sets the winning combination determination probability and the like (setting value). ) Is a switch for changing, for example, in 6 steps.

  When the front door 2 is open (hereinafter referred to as "door open state") and the slot machine is supplied with power (power switch 81 is on), the setting key type switch 83 is operated to be on. By doing so, the setting can be confirmed. When the door is open and the slot machine is not supplied with power (power switch 81 is off), the setting key type switch 83 is turned on, and the power switch 81 is turned on in that state. By changing the setting (power is turned on to the slot machine), the setting can be changed. The setting key type switch 83 is adapted to be switched between an ON state and an OFF state by inserting a predetermined key member (setting key) into a predetermined lock member provided on the main body side and rotating the lock member. The setting confirmation cannot be executed while the game is being executed (the state where the game medals are bet (including the case where the automatic bet is included) and the state where the reels are rotating), and the state where the game is waiting It can be executed only in.

The power from the power supply device 80 is supplied to the sub-main control board 70A via the main control board 60 and further to the sub-sub control board 70B via the sub-main control board 70A (the power supply apparatus 80. Power may be directly supplied to the sub-main control board 70A and the sub-sub control board 70B. A supply voltage monitoring circuit for monitoring the voltage supply state is provided on the circuit that supplies power from the power supply device 80 to the main control board 60 and on the circuit that supplies power to the sub-main control board 70A via the main control board 60. (Not shown) are provided respectively. Each supply voltage monitoring circuit determines that the power supply is cut off when the supply voltage drops to a predetermined voltage value, and outputs a power supply cutoff detection signal to the main CPU 61 and a sub-main CPU 71 described later. Each supply voltage monitoring circuit supplies power when the supply voltage returns to a predetermined voltage value (a value different from the voltage value for power-off determination (for example, a high value), but may be the same value). It is determined that the power is turned on and a power-on detection signal is output to the main CPU 61 and the sub-main CPU 71. The voltage value when detecting the power failure of the main control board 60 is set to a value higher than the voltage value when detecting the power failure of the sub-main control board 70A, and the main control is performed before the sub-main control board 70A. The substrate 60 is configured to perform a process (power-off process) programmed to be executed when the power is turned off (the same may be applied to power-on).

  The main CPU 61 has a reel stop signal circuit 91 connected to the switch board 90 or mounted on the switch board 90, a start lever 25, inserted medal sensors 28a, 28b, 28c, 1-BET switch 22, and MAX. Each signal from the -BET switch 23 and the settlement switch 24 is input through the interface circuit 68.

  A blocker 48 is connected to the main CPU 61 via an interface circuit 68, and is configured to control ON / OFF of the blocker 48. In the following description, a signal for controlling ON / OFF of the blocker 48 will be appropriately referred to as a “blocker signal”. Although illustration is omitted, the slot machine is provided with a door sensor for detecting the open / closed state of the front door 2, and a signal from this door sensor is input to the main CPU 61 via the interface circuit 68. Has become. The main CPU 61 is adapted to determine whether the front door 2 is in a closed state (hereinafter referred to as “door closed state”) or an open state (door open state) based on a signal from the door sensor.

Although illustration is omitted, the main CPU 61, when in a predetermined game state (for example, an AT mode or a bonus game state described later), is connected to a data counter, a hall computer or the like via an external connection terminal board or the like. A predetermined signal (hereinafter, appropriately referred to as an “outer end signal”) is output, and the outer end signal can be used to manage the number of times set in a predetermined game state or to present it to the player. Has been done.

  On the sub-main control board 70A, a sub-main CPU 71 that mainly performs various kinds of arithmetic processing relating to production management, a ROM 72 that is a read-only storage device that stores control programs and the like, and a writable and readable information storage A RAM 73, which is a device, is provided, and each drive circuit and the like operate in accordance with a control program stored in the ROM 72 to control image production and voice production management in the slot machine and lamp production (LED production). It is designed to be controlled. The ROM 72 and the RAM 73 are non-volatile storage devices, and are configured to retain the stored information even when power is not supplied. The sub-main CPU 71 and the ROM 72 and the RAM 73 are connected by a parallel bus. A clock pulse generator and a frequency divider (not shown) are connected to the sub-main CPU 71. The clock pulse generator and the frequency divider generate an interrupt to the sub-main CPU 71 at predetermined time intervals. It is also configured to function as an interval timer of. The sub-main CPU 71 is adapted to execute a predetermined interrupt processing, update or reset the clock data of various timers set in accordance with the pulse (clock signal) from the interval timer.

The sub-main CPU 71 is configured to receive various signals from the main control board 60 via the interface circuit 74 and transmit the signals to the lamp control circuit 18. The lamp control circuit 18 is a circuit that controls lighting of lamps (LEDs) such as the back lamps 38a to 38c. The interface circuit 74 has a parallel bus extension function and a parallel bus connection and interface conversion function of a three-wire serial interface.
The parallel bus extension function is used by the sub main CPU 71 to receive signals from the main CPU 61 of the main control board. The interface conversion function is used by the sub-main CPU 71 to transmit a light emission control information signal to the lamp control circuit 18. The lamp control circuit 18 converts the LED light emission control information signal sent in the form of a three-line serial interface signal into an LED control signal, and produces effect lamps 12, 13a, 13b, 14a, 14b, and decorative lamps 32a, 32b. The emission control of the back lamps 38a to 38c is performed. However, an LVDS interface connection is also used in consideration of the influence of induction noise from the electromagnetic components on these wiring portions, which will be described later.

  The sub-main CPU 71 is configured to transmit various signals to the sub-sub control board 70B and receive various signals from the sub-sub control board 70B via the interface circuit 74. Hereinafter, a signal transmitted from the main control board 60 to the sub-main control board 70A is referred to as a "control command", and a signal transmitted from the sub-main control board 70A to the sub-sub control board 70B is referred to as a "production command". The signal transmitted from the sub-sub control board 70B to the sub-main control board 70A is also referred to as a "state command".

  On the sub-sub control board 70B, a sub-sub CPU 75 that mainly performs various kinds of arithmetic processing relating to control of image production and audio production, a ROM 76 that is a read-only storage device that stores a control program, and information can be written and read. A RAM 77, which is a storage device, is provided, and each drive circuit and the like operate in accordance with a control program stored in the ROM 76 to perform control related to image effects and sound effects. The ROM 76 and the RAM 77 are non-volatile storage devices, and are configured to retain the stored information even when power is not supplied.

  The sub-sub CPU 75 receives the notification signal or the effect signal from the sub-main control board 70A via the interface circuit 78, transmits the signal to the display device control circuit 16 and the speaker control circuit 17, and at the same time, the sub-main control board. It is configured to send a status signal to 70A. The display device control circuit 16 is a circuit that controls the image display device 11 to display a predetermined effect image, and the speaker control circuit 17 determines the type and volume of sound generated from speakers such as the upper speakers 15a and 15b. It is a circuit that controls. The image display device 11 is configured to also function as a push indicator (hereinafter, appropriately referred to as “sub-side push order indicator”) that displays the operation order (push order) of the stop switches 26a to 26c. There is.

<Production control of the lamp control circuit by the control board>
Next, the configuration of communication (light emission control communication) between the main control board 60 and the display lamp control circuit 47, and the configuration of communication between the sub-main control board 70A and the lamp control circuit 18 will be described. First, the lamp effect control of the display lamp control circuit 47 and the display lamps 46a to 46h, 46j from the main control board 60 will be described. The main CPU 61 of the main control board 60 operates the software stored in the ROM 62 to determine and display effect control information for controlling the emission brightness of the display lamps 46a to 46h, 46j according to the gaming state of the gaming machine. The production control information is transmitted to the lamp control circuit 47.

The display lamps 46a to 46h, 46j have an LED lamp configuration including the lamp display section (effect display member) and the LEDs provided on the back side thereof as described above. As the LEDs, there are monochromatic LEDs that emit light in a single color or color LEDs that are composed of LED elements of three primary colors, and one or a plurality of LEDs are used for each of the display lamps 46a to 46h and 46j depending on their sizes. .. The single-color LEDs include a red LED, a green LED, and a blue LED, which perform light emission luminance control and perform effect control in which the brightness changes. A color LED is composed of a combination of a red LED element, a green LED element and a blue LED element.
The emission brightness of the device is controlled to emit various colors including white. In this control, the ratio of the emission luminance values of the red LED element, the green LED element, and the blue LED element is changed to control the emission color, and the brightness value is controlled by controlling the magnitude of the luminance value. To do. The main CPU 61 determines the content of the effect control of each LED lamp and transmits it as effect control information to the display lamp control circuit 47, and the display lamp control circuit 47 displays the display lamp 46a based on the effect control information from the main CPU 61. The light emission brightness of the LEDs that form 46h to 46j is controlled. In this way, the display lamp control circuit 47 has an LED control circuit. Although one display lamp control circuit 47 is shown in FIG. 2, a large number of LEDs are used for the display lamps 46a to 46h and 46j, and the display lamp control is performed in order to control the emission brightness of these LEDs. The circuit 47 is composed of a plurality of LED control circuits. Each LED control circuit is provided at a position corresponding to the display lamp.

  Next, lamp effect control of the effect lamps 12, 13a, 13b, 14a, 14b, the decorative lamps 32a, 32b, and the back lamps 38a, 38b, 38c by the lamp control circuit 18 of the sub-main control board 70A will be described. These lamps are also LED lamps that emit light by illumination from LEDs, and monochromatic LEDs or color LEDs are used. The number of LEDs used for these lamps is large, and one lamp control circuit 18 is shown in FIG. 2, but a plurality of LED control circuits for controlling light emission of these many lamps are arranged here. When a control command including a winning combination lottery result by the main control board 60 is transmitted to the sub-main control board 70A, the sub-main control board 70A, based on the control command received from the main control board 60, the CPU 71, the ROM 72, the RAM 73, etc. By using, the effect control information for controlling the emission brightness of the LED is created. Specifically, in order to inform the player of the winning combination, there is a method of using an LED that emits light in a color reminiscent of a combination (for example, in the case of a small combination composed of a lemon pattern, the LED is set as the corresponding color. Emits yellow light). In this case, the light emission pattern to be executed may be determined from the plurality of light emission patterns based on the LED lighting control table to create the effect control information, or the light emission mode may be determined on a one-to-one basis with the winning combination. good. Thereby, for example, even when the LEDs are made to emit light of the same color, by providing a light emitting pattern for turning on only some of the LEDs, a light emitting pattern for turning on a plurality of LEDs, etc. Can be changed.

<Control board connection interface>
Information indicating the gaming state of the gaming machine such as inserting medals, operating the start lever, operating the stop switch, etc. is stored in the RAM 63, and the software operating on the main CPU 61 is triggered by the information indicating the gaming state of these gaming machines. The effect control information of the display lamp to be controlled is read from the ROM 62. On the main control board 60, the main CPU 61, the ROM 62, and the RAM 63 are generally connected by an 8-bit parallel bus. As will be described later, the main control board 60 and the peripheral circuits are connected by a serial interface instead of an 8-bit parallel bus. The 8-bit parallel bus is connected to the interface circuit 68. The interface conversion function of the interface circuit 68 converts an 8-bit parallel bus interface into a serial interface. An 8-bit parallel bus interface transmits / receives 8-bit signals to / from 8 signal lines simultaneously in the time of 1 clock signal, but in the serial interface, 1 bit in 1 signal line at the time of 1 clock signal Signal is transmitted, and an 8-bit signal is transmitted / received at the time of 8 clock signals. The effect control information read from the ROM 62 via the 8-bit parallel bus is converted into a data signal of the serial interface by the interface circuit 68 and transmitted to the display lamp control circuit 47. As described above, the display lamp control circuit 47 has a plurality of LED control circuits, and the three-line serial interface connection and the LVDS serial interface connection are used between these LED controls, which will be described later.

The software operating on the main CPU 61 uses the effect lamps 12, 13a, 13b, 14
When the effect contents of a, 14b, decoration lamps 32a, 32b, and back lamps 38a, 38b, 38c are determined, an effect command is transmitted from the main control board 60 to the sub-main control board 70A via an 8-bit parallel bus. On the sub-main control board 70A, a sub-main CPU 71 that mainly performs various kinds of arithmetic processing relating to production management, a ROM 72 that is a read-only storage device that stores control programs and the like, and a writable and readable information storage A RAM 73, which is a device, is provided, and each drive circuit operates according to a control program stored in the ROM 72, so that control relating to management of image effects and voice effects, control related to LED lamp effects, and the like are performed. Is becoming The effect control information regarding the LED lamp effect is transmitted from the ROM 72 connected to the parallel bus to the interface circuit 74. The interface circuit 74 converts the 8-bit parallel bus interface into a serial interface. The effect control information read from the ROM 72 via the 8-bit parallel bus is converted into a data signal of the serial interface by the interface circuit 74 and transmitted to the lamp control circuit 18. As described above, the lamp control circuit 18 has a plurality of LED control circuits, and a 3-wire serial interface connection and an LVDS serial interface connection are used between these LED controls, which will be described later.

  An 8-bit parallel bus corresponding to the number of input / output processing bits of the CPU is used between the CPU and the ROM / RAM on the main control board 70 and the sub-main control board 70A. However, if various kinds of information are transmitted and received between the control circuit board on which the CPU is mounted and the peripheral circuits while keeping the 8-bit parallel bus, a huge number of interface lines are required. For example, hundreds of LEDs are arranged in the game machine, but each LED requires an 8-bit data line, that is, eight data lines, and hundreds of LEDs in the control board and the game machine. The number of interface lines for connecting with is enormous. For this reason, the interface of the 8-bit parallel bus is converted into a serial interface by the interface circuit 68 or the interface circuit 74, and various control information is transmitted from the control board to the peripheral circuits. A standard serial interface such as an I2C bus (also called an I2C serial interface), a three-wire serial interface, or the like is used as the serial interface between the control board and the peripheral circuits. The standard serial interface is not limited to gaming machines, but is a standardized interface for connecting a control board on which a CPU is mounted to peripheral circuits in a general control device that uses a CPU. It is preferable to use these standard serial interfaces. The I2C bus was standardized in 1992, and since then the speed has been gradually increased to 3.4 Mbps, but in many cases, it is used at a communication speed of 100 kbps and 400 kbps in relation to the connection distance length. The 3-wire serial interface is capable of high-speed communication up to several tens of Mbps. A large number of LEDs, for example, hundreds of LEDs are used in the gaming machine. A three-wire serial interface is preferable to the I2C bus in order to control the emission brightness of each of these LEDs in a predetermined cycle.

  In this embodiment, a three-wire serial interface is used for connection for transmission from the serial interface circuit 68 of the main control board 60 and the serial interface circuit 74 of the sub-main control board 70A. However, the present embodiment is not limited to the 3-wire serial interface, and an I2C bus may be used. A serial interface other than the 3-wire serial interface or the I2C bus may be used.

The main control board 60 (main CPU 61) performs a lottery using software stored in the ROM 62, and the sub-main control board 70A (sub-main CPU 71) uses software stored in the ROM 72 to determine effect control information based on the lottery result. However, in the following description, the main control board 60 (main CPU 61) and the sub-main control board 70A (sub-main CPU 71) are also simply referred to as "control device". The display lamp control circuit 47 and the lamp control circuit 18 receive the effect control contents from the control device and control the light emission brightness of the LEDs constituting the LED lamp (the plurality of LED control circuits as described above). ), And in the following description, the display lamp control circuit 47 and the lamp control circuit 18 will be referred to as “LED control circuits”. Also, the display lamps 46a to 46h, 46j controlled by the display lamp control circuit 47 and the lamp control circuit 18, the effect lamps 12, 13a, 13b, 14a, 14b, the decorative lamps 32a, 32b, the back lamps 38a, 38b, 38c. Each have one or a plurality of LEDs, and the LED control circuit controls the emission brightness of each of these LEDs. Further, for simplification and clarity of explanation, the main CPU 61 and the sub-main CPU 71 of the main control board 60 and the sub-main control board 70A are simply referred to as “CPU”.

  As can be seen from the above description, in the present embodiment, the LED effect control information created by the control device and sent via the 8-bit parallel bus is converted into a 3-line serial interface by the interface circuits 68 and 74. Then, it is transmitted to the LED control circuit through a three-wire serial interface connection. After this, an LVDS serial interface connection is also used, which will be described later.

<Connecting interface between control device and LED control circuit>
In response to the LED effect control information sent in this way, the LED control circuit controls the light emission brightness of the LEDs arranged in the gaming machine. The light emission brightness control of the LED is generally a light emission brightness control in which a constant current is supplied to the LED at a predetermined cycle, and the light emission brightness value is changed by changing the pulse width of a PWM pulse that causes the constant current to flow within the predetermined cycle. .. An LED control circuit for performing PWM pulse control with a constant current value for this purpose is required, and one LED control circuit is provided for each of a plurality of LEDs, for example, for every 24 LEDs, and emission brightness control is performed. Is configured to. Generally, since several hundreds of LEDs are used in the gaming machine, the number of LED control circuits arranged in the gaming machine is several tens to one hundred or more. Here, the control device is preferably connected to the peripheral circuit by a standard serial interface. Conventionally, the connection between the control device and each LED control circuit, and further the connection between the LED control circuits are performed by an I2C serial interface, or It was connected using a standard serial interface such as a 3-wire serial interface. In this embodiment, a 3-line serial interface is used as the standard serial interface, and a configuration using the 3-line serial interface will be described below.

  If all of the dozens to hundreds of LED control circuits are directly connected to the control device using the 3-wire serial interface, the control device requires a huge number of 3-wire serial interface connection lines. Therefore, one or several LED control circuits are directly connected to the control device as the first-stage LED control circuit, and the remaining LED control circuits are sequentially connected. For example, the remaining some are connected to the LED control circuit of the first stage as the LED control circuit of the second stage, and some of the remaining are connected to the LED control circuit of the second stage as the LED control circuit of the third stage. As described above, sequential connection (cascade connection) is often performed. With such a connection configuration, it is possible to reduce the number of connection lines of the 3-wire serial interface provided in the control device.

The connection between the control device and the peripheral circuit is basically based on the use of a standard three-wire serial interface. The 3-line serial interface has three signal lines for transmitting an enable signal, a clock signal, and a data signal, respectively. As described above, when the performance control information for driving and controlling the LEDs is transmitted using the 3-wire serial interface, the induction noise from the electromagnetic components in the gaming machine causes the enable signal, clock signal, and data signal signal lines, respectively. , And the signal may be disturbed. Therefore, it is conceivable to replace the connection between the control device and the peripheral circuit with a three-wire serial interface and use a connection interface that is not easily affected by inductive noise. However, the control device and peripheral circuits (for example, the motor drive circuit 36a, the switch substrate 90, the display lamp control circuit 47, the hopper drive circuit 52, the reel position detection circuits 37a, 37b, 37c, the payout detection signal circuit 53, and the storage state signal). Circuit 87, etc.), a 3-wire serial interface has been conventionally used, and the first connection (first stage connection) from the control device to the peripheral circuit uses the 3-wire serial interface. Is desirable. From this, for example, the LED control circuit of the first stage is connected to the control device using a 3-wire serial interface, and the LED control circuit of the first stage and the LED control circuits of the second and subsequent stages are guided from the outside. It is conceivable to connect using an LVDS interface that is not easily affected by noise. The LVDS interface is a low-voltage differential signal, and is a standard standardized mainly for transmitting and receiving image information as ANSI / TIA / EIA-644. Two signal lines are used for the clock signal and the data signal, and the differential voltage of the two lines is used for transmission. In this case, even if the induced noise from the electromagnetic component is induced in the two lines of the clock signal and the data signal in the same phase, the clock signal and the data signal, which are the differential voltage, are not affected, and there is a possibility of malfunction. Low.

  As described above, in the present embodiment, the control device and the first-stage LED control circuit are connected using the 3-wire serial interface, and the first-stage LED control circuit and the second-stage LED control circuit are connected. Are connected using the LVDS interface, and the interconnections of the LED control circuits in the second and subsequent lower stages are connected using the LVDS interface. In such a configuration, the LED control circuit of the first stage has an input terminal of the 3-wire serial interface and the output terminal of the LVDS signal, and the LED control circuits of the second and subsequent stages have the input terminal of the LVDS interface and the output of the LVDS interface. Will have terminals. In this case, if one LED control circuit is configured to be operable as the LED control circuit of the first stage and the LED control circuit of the second and subsequent stages, the LED control circuits of the same configuration can be used in the first stage. The LED control circuit can also be used as the LED control circuit of the second stage and thereafter, which is preferable.

  FIG. 3 shows an LED control circuit configured so that it can be used in both the first stage and the second stage. The configuration of the LED control circuit LC will be described below with reference to FIG. The LED control circuit LC has four input terminals DCI1, DCI2, DDI1, and DDI2 located on the left side of the figure for receiving signals of a three-wire serial interface or an LVDS interface. It is provided with four output terminals DCO1, DCO2, DDO1 and DDO2 which output signals of the interface. Further, a mode designation terminal MODE located on the left side, input terminals A5-A0 for address matching also located on the left side, and 24 output terminals for controlling the emission brightness of the 24 LEDs located on the upper side. LOUT1 to LOUT24.

  When receiving the signal of the LVDS interface, the differential clock signal and the differential data signal are received from the four signal input terminals DCI1, DCI2, DDI1, DDI2 of the LED control circuit LC. The differential clock signals received from the differential input terminals DCI1 and DCI2 are input to the differential input circuit DIC1, and the differential data signals received from the differential input terminals DDI1 and DDI2 are input to the differential input circuit DIC2. Each of the differential input circuits DIC1 and DIC2 is a circuit that detects a differential voltage at the input terminals of two lines. The respective outputs of the differential input circuits DIC1 and DIC2 are input to the clock terminal and the data terminal of the shift register SR1. The shift register SR1 takes in the data signal input to the data terminal into the shift register at the timing of the rising edge of the clock signal input to the clock terminal, that is, latches the data signal.

Of the four input terminals DCI1, DCI2, DDI1, DDI2, three input terminals DCI1, DCI2, DDI1 are also used as input terminals of a three-wire serial interface. When receiving an input signal of the 3-wire serial interface, a clock signal, an enable signal, and a data signal are received from each of the three input terminals DCI1, DCI2, and DDI1 and input to each of the input circuits IC1, IC2, and IC3. To be done. The outputs of the input circuits IC1, IC2, and IC3 are input to the clock terminal, enable terminal, and data terminal of the shift register SR2. When the enable terminal is in the low signal state, the shift register SR2 determines that the signal input to the clock terminal and the data terminal is a valid signal, and converts the signal into the data signal at the timing of the rising edge of the clock signal input to the clock terminal. The input data signal is taken into the shift register SR2. That is, the data signal is latched.

  The outputs of the clock terminals and the data terminals of the shift registers SR1 and SR2 are connected to the selectors SEL1 and SEL2 as shown in the figure. The mode terminal MODE is connected to the shift registers SR1 and SR2 and is set to supply either a high signal or a low signal to them. When the mode designation terminal MODE is set to the high signal, each of the selectors SEL1 and SEL2 selects the clock signal and the data signal from the shift register SR2 as the input signal of the selectors SEL1 and SEL2. When the mode terminal MODE is set to the low signal, each of the selectors SEL1 and SEL2 selects the clock signal and the data signal from the shift register SR1 as the input signal of the selectors SEL1 and SEL2.

  The output terminals of the selectors SEL1 and SEL2 are connected to the input terminal of the register circuit LD1 and the input terminals of the differential output circuits DOC1 and DOC2. The clock signal and the data signal input from the selectors SEL1 and SEL2 to the differential output circuits DOC1 and DOC2 are converted into a differential clock signal and a differential data signal by the differential output circuits DOC1 and DOC2. Therefore, a total of four output terminals from the differential output circuits DOC1 and DOC2 output signals of the LVDS interface. Thus, the differential clock signals are output from the output terminals DCO1 and DCO2, and the differential data signals are output as LVDS signals from the output terminals DDO1 and DDO2. As described above, the LED control circuit is configured to output the input signal of the three-wire serial interface or the LVDS interface as the output signal of the LVDS interface. That is, the configuration has a 3-wire serial-LVDS change function (referred to as a first conversion function) and an LVDS-LVDS conversion function (referred to as a second conversion function).

  As described above, the output terminals of the selectors SEL1 and SEL2 are also connected to the register circuit LD1. The register circuit LC1 stores the effect control information received through the input terminals DCI1, DCI2, DDI1, and DDI2 using the 3-line serial interface or the LVDS interface. The effect control information is included in the data signal of each interface, and as described later, the effect control information includes information that specifies the device address of the LED control circuit, information that specifies the register address, and information that specifies the emission brightness value. Included and stored in REG1, REG2, REG3, respectively.

The LED control circuit LC collates the 6-bit address information set from the six input terminals A5-A0 for address collation with the device address information included in the performance control information, and the LED control circuit LC of its own It is determined whether or not it is effect control information for controlling the LED to be controlled. The register address designation REG2 of the register circuit LD1 designates which register address the effect control information to be received is stored, and the light emission luminance value information included in the effect control information is stored at the address specified by REG2. In the PWM control circuit LD2 connected to the register circuit LD1, the register address specified by the register address REG2 specifies the output terminals of the 24 LED drive terminals LOUT1 to LOUT24. The PWM control circuit LD2 creates a PWM pulse corresponding to the duty ratio of the PWM pulse based on the light emission luminance value information. The constant current circuit LD3 sets the constant current value of the PWM pulse signal output from the 24 LED drive terminals LOUT1 to LOUT24. These register circuits LD1
Based on the information of the PWM control circuit LD2 and the constant current circuit LD3, the constant current PWM output terminal LD4 outputs constant current PWM pulse signals to the 24 LED drive terminals LOUT1 to LOUT24 to control the emission brightness of 24 LEDs. Is configured to do.

<LED control circuit>
A detailed operation of receiving a signal from the input terminal and outputting a signal from the output terminal of the LED control circuit configured as described above will be described. For example, an LED control circuit (display lamp control circuit 47) for driving the LEDs of the display lamps 46a, 46h, and 46j arranged near the control device CD (main control board 68, sub-main control board 70A). (A part of) is connected to the control device CD by using a 3-line serial interface as the first stage LED control circuit LC1 directly connected to the control device CD (see FIG. 4). The LED control circuit disposed at a position distant from the control device CD, for example, the LED control circuit for controlling the emission brightness of the remaining display lamps 46b, 46c, 46d, 46e, and 46f is the LED control circuit of the second and subsequent stages. Used as LC2, LC3, etc. In this case, using the LVDS interface, the LED control circuit in the first stage is the LED control circuit in the second stage, the LED control circuit in the second stage is the LED control circuit in the third stage, and the LED control from the higher order to the lower order is performed. The circuits are connected. The LED control circuits LC2 and LC3 in the first and second stages are shown as a display lamp control circuit 47 in FIG.

  As described above, the LED control circuit LC has a 3-wire serial-to-LVDS conversion function (first conversion function) having a 3-wire serial interface as an input interface and an LVDS interface as an output interface, and an LVDS interface as an input interface. It has an LVDS-LVDS conversion function (second conversion function) using the interface as an output interface. The first conversion function is used when operating the LED control circuit LC as the first-stage LED control circuit LC1 and the second conversion function when operating as the second-stage and subsequent LED control circuits LC2 and LC3. The conversion function is used.

  The first conversion function of the LED control circuit LC is exhibited by setting the mode designation terminal MODE shown in FIG. 3 to a high signal. The clock signal input to the clock signal input terminal SCLK of the 3-line serial interface signal is input to the input circuit IC1, the enable signal input to the enable signal input terminal SEN is input to the input circuit IC2, and the data signal input terminal SD is input. The input data signal is input to the input circuit IC3. The outputs of the input circuits IC1, IC2, IC3 are input to the clock terminal, enable terminal, and data terminal of the shift register SR2. Here, since the mode designation terminal MODE is set to the high signal, the clock signal and the data signal from the shift register SR2 are selected and input to each of the selector SEL1 and the selector SEL2.

  The second conversion function of the LED control circuit LC is exhibited by setting the mode designation terminal MODE shown in FIG. 3 to a low signal. The differential clock signals input to the differential clock signal input terminals DCI1 and DCI2 of the LVDS interface are input to the differential input circuit DIC1, and the differential data signals input to the differential data signal input terminals DDI1 and DDI2 are differential. It is input to the input circuit DIC2. The outputs of the differential input circuits DIC1 and DIC2 are input to the clock terminal and data terminal of the shift register SR1. Here, since the mode designation terminal is set to the low signal, the clock signal from the shift register SR1 and the data signal are selected and input to each of the selectors SEL1 and SEL2.

Whether the first conversion function of the LED control circuit LC is used or the second conversion function is used, the LED control circuit LC uses the differential clock signal and the differential data signal of the LVDS interface. Is output. Specifically, the clock signal and the data signal of the 3-line serial interface or the LVDS interface input to the selectors SEL1 and SEL2 are input to the differential output circuits DOC1 and DOC2 from the selectors SEL1 and SEL2, respectively. The differential output circuit DOC1 outputs differential clock signals from the differential clock signal output terminals DCO1 and DCO2, and the differential output circuit DOC2 outputs differential data signals from the differential data signal output terminals DDO1 and DDO2. These differential clock signals and differential data signals are signals output from the differential output circuits DCO1 and DCO2 via the shift registers SR1 and SR2 in the LED control circuit and the selectors SEL1 and SEL2. Alternatively, even if the signal at the input terminal of the LVDS interface is a signal on which induction noise is superimposed, it is a signal output as a waveform-shaped differential clock signal or differential data signal. It also outputs a differential clock signal and a differential data signal output at a time delayed from the clock signal and the data signal of the input terminal of the 3-wire serial interface or the LVDS interface. That is, the first conversion function operates as a 3-wire-2 wire bridge function in which the input signal of the 3-wire serial interface is waveform-shaped and output as the output signal of the LVDS interface, and the second conversion function operates as the input signal of the LVDS interface. Operates as a 2-wire-2 wire repeater function in which the waveform is shaped and output as an output signal of the LVDS interface.

  As described above, the LED control circuit LC of the present embodiment operates the first conversion function by setting the mode designation terminal MODE to the high signal or the low signal, and the LED control circuit LC1 of the first stage is operated. It is configured so that it can be used as the LED control circuits LC2, LC3, etc. of the second and subsequent stages by operating the second conversion function. The mode specifying terminal MODE may be set to a low signal when operating the LED control circuit with the first conversion function, and the mode specifying terminal MODE may be set to a high signal when operating with the second conversion function. Good.

<Connection configuration between control device and LED control circuit>
A first connection example of the control device CD and the first-stage LED control circuit LC1 will be described with reference to FIG. Since the control device CD is connected to the peripheral circuits by the 3-wire serial interface, in this example, the control device CD and the plurality of LED control circuits are connected in parallel and directly connected by the 3-wire serial interface. This connection type is called multi-drop connection, and these LED control circuits are referred to as the first-stage LED control circuit LC1. As described above, since the 3-wire serial interface is easily affected by the inductive noise from the electromagnetic component, it is preferable to dispose the 3-wire serial interface as close to the control device CD as possible or so as to pass away from the electromagnetic component. desirable. As described above, when the three-line serial interface connection is made to the input terminals DCI1, DCI2, DDI1 of the LED control circuit LC1, based on the control signal sent from the control device CD, as described with reference to FIG. A light emission drive signal is sent from the LED drive terminals LOUT1 to LOUT24 of the respective LED control circuits LC1 to the corresponding LEDs, and the light emission control of these LEDs is performed. Further, the LVDS signal is sent from the output terminals DCO1, DCO2, DDO1, DDO2 of each LED control circuit LC1 to the LED control circuit on the subsequent stage side. As can be seen from this, the plurality of first-stage LED control circuits LC1 shown here are used by using the mode designation terminal MODE as a high signal so as to exhibit the first conversion function (3-wire serial-LVDS conversion function). Be done. In FIG. 4, a plurality of first-stage LED control circuits LC1 are connected to the control device CD (multidrop connection configuration), but one first-stage LED control circuit LC1 is connected to the control device CD. May be connected to.

Next, with reference to FIG. 5, a configuration in which the second-stage LED control circuit LC2 is connected in addition to the control device CD and the first-stage LED control circuit LC1 will be described. Here, an example is shown in which the LED control circuit LC1 of the first stage is arranged on the substrate (main control substrate 60, sub-main control substrate 70A in FIG. 2) of the control device CD. The control device CD and the first-stage LED control circuit LC1 are connected using a 3-line serial interface as in FIG. The first-stage LED control circuit LC1 on the substrate of the control device CD is connected to the plurality of second-stage LED control circuits LC2.
Multi-drop connection is performed using a VDS interface, and each of these second-stage LED control circuits LC2 is connected to a lower LED control circuit (not shown) using an LVDS interface. In the configuration of FIG. 5, the first-stage LED control circuit LC1 is used so as to exhibit the first conversion function (3-line serial-LVDS conversion function) by using the mode designation terminal MODE as a high signal, and a plurality of two-stages are used. The LED control circuit LC2 of the eye is used so that the mode designation terminal MODE is used as a low signal to exhibit the second conversion function (LVDS-LVDS conversion function). Each of the LED control circuits LC1 and LC2 sends a light emission drive signal to the corresponding LED from each of the LED drive terminals LOUT1 to LOUT24 based on the control signal sent from the control device CD, and the light emission of these LEDs is performed. Control is performed.

<Interconnection between multiple LED control circuits>
A plurality of LED control circuits LC (second to fifth stage LED control circuits LC2 to LC5) are added to the first stage LED control circuit LC1 shown in FIGS. 4 and 5 using FIG. An example of a connection configuration for sequentially connecting will be described. This will be described with reference to the display lamps 46a to 46h, 46j shown in FIG. 1 as an example. Since the display lamp 46h is arranged in the vicinity of the control device CD (main control board 60) and is located at a position where it is almost unaffected by the inductive noise from the electromagnetic components, the LED control for controlling the emission brightness of the display lamp 46h is performed. The circuit LC is used as the first-stage LED control circuit LC1 and is connected to the control device CD using a 3-line serial interface. That is, the LED control circuit LC1 is used by using the mode designation terminal MODE as a high signal to exhibit the first conversion function (3-line serial-LVDS conversion function). Since the display lamps 46a and 46j are arranged at the same distance from the display lamp 46h, the LED control circuit for controlling each of the display lamps 46a and 46h is the second-stage LED control circuit LC2. , And the LED control circuit LC1 are respectively connected in multi-drop connection. On the other hand, the LED control circuits for controlling the display lamps 46c, 46e, 46f, 46g arranged on the right side peripheral portion of the middle panel assembly 20 are sequentially connected in cascade from the LED control circuit LC2 to the third to fifth stages. The LED control circuits LC3 to LC5 are used for the eyes. In this case, the LED control circuits LC3 to LC5 of the third to fifth stages are used such that the mode designating terminal MODE is used as a low signal to exert the second conversion function (LVDS-LVDS conversion function). Also in this case, each of the LED control circuits LC1 to LC5 sends a light emission drive signal to the corresponding LED from each of the LED drive terminals LOUT1 to LOUT24 based on the control signal sent from the control device CD, and the LEDs are driven. Light emission control is performed.

  In the above description, the light emission control connection configuration of the display lamps 46a to 46h, 46j is described as an example. In this case, the LED control circuits LC1 to LC5 of the first to fifth stages of FIG. 2 corresponds to the display lamp control circuit 47 shown in FIG. A configuration similar to this is also used in the lamp control circuit 18, and the first to fifth stage LED control circuits LC1 to LC5 in FIG. Light emission control is performed.

  In FIG. 6, the connection configuration in which the LED control circuits LC1 and LC3 of the second and subsequent stages are multi-drop connected and cascade-connected to the LED control circuit LC1 of the first stage is described. The connection configuration of the circuit LC is not limited to the connection configuration illustrated in FIG. For example, the plurality of second-stage LED control circuits LC2 may be arranged relatively close to each other, and the third-stage and fourth-stage LED control circuits LC3 and LC4 may be arranged apart from each other. . In such a case, a plurality of second-stage LED control circuits LC2 arranged at relatively close positions are connected in a multi-drop manner, and third-stage and fourth-stage arranged at mutually distant positions. It is preferable to connect the LED control circuits LC to each other by appropriately combining the multi-drop connection and the cascade connection such that the LED control circuits LC3 and LC4 are sequentially connected in cascade.

<Signal conversion between 3-wire serial interface and LVDS interface>
The signal format differs between the 3-wire serial interface and the LVDS interface. A method for transmitting effect control information using each signal format will be described with reference to FIGS. 7 to 10. Signal conversion by the first-stage LED control circuit LC1 used to perform the first conversion function (3-line serial-LVDS conversion function) with the mode designation terminal MODE as a high signal, and the mode designation terminal MODE as a low signal The signal conversion by the LED control circuits LC2 to the second and subsequent stages used to exhibit the second conversion function (LVDS-LVDS conversion function) will be described with reference to FIGS. 7 to 10.

<3-wire serial interface>
In the present embodiment, the control device CD transmits the light emission luminance information of the LEDs controlled by each of the plurality of LED control circuits LC in the gaming machine as the production control information. In the case of the display lamp control circuit 47 shown in FIG. 2, the control device CD sends the light emission luminance information of the LEDs used for all the display lamps 46a to 46h, 46j to the display lamp control circuit 47. This display lamp control circuit will be described as having the connection configuration shown in FIG. 6. Since the LED control circuits LC1 to LC5 that control the light emission of all the LEDs of the display lamps 46a to 46h and 46j perform the light emission brightness control. First, the effect control information is transmitted to the LED control circuit LC1 in the first stage. This effect control information is transmitted from the control device CD to the LED control circuit LC1 in the first stage by using the 3-line serial interface.

  The three-line serial interface uses three types of signal lines: an enable signal line, a clock signal line, and a data signal line. The enable signal line is a signal indicating that a valid signal is input to the clock signal line and the data signal line. Specifically, as shown in FIG. 7, while the enable signal of the low signal is transmitted to the enable signal line, the valid clock signal and the data signal are transmitted to the clock signal line and the data signal line. Indicates. The effect control information is transmitted bit by bit on the data signal line. In the example illustrated in FIG. 7, 8-bit data forming the first byte is transmitted in the order of bit7 to bit0, then 8-bit data forming the second byte is transmitted until the last byte bit0. Data signal is transmitted. A clock signal in which a low signal and a high signal are repeated at a constant clock cycle is transmitted on the clock signal line. The state of the data signal being transmitted on the data signal line at the time of the rising edge at which the clock signal changes from the low signal to the high signal is latched as a data signal in the LED control circuit. That is, if the data signal line is a high signal, it is latched in the LED control circuit as data 1, and if the data signal line is a low signal, it is data 0. The details of the effect control information transmitted on the data signal line will be described later.

  The enable signal line, clock signal line, and data signal line of the 3-line serial interface from the control device CD are input from the input terminals DCI1, DCI2, DDI1 of the LED control circuit LC shown in FIG. It is connected to the terminal SCLK and the data signal input terminal SD. When the enable signal of the enable signal input terminal SEN changes from the high signal to the low signal, the enable signal terminal of the shift register SR2 is set to the low signal via the input circuit IC2. When the enable signal terminal of the shift register SR2 is set to a low signal, the clock signal input terminal SCLK and the clock signal and data signal input to the data signal input terminal SD pass through the input circuits IC1 and IC3, respectively. Are input to the clock signal terminal and the data signal terminal of the shift register SR2. Here, the data signal of the data signal terminal of the shift register SR2 at the timing of the rising edge of the clock signal of the clock signal terminal of the shift register SR2 is taken into the shift register SR2 as a data signal. Inputting and taking in the data signal to the shift register SR2 in this manner is referred to as latching the data signal.

<LVDS interface>
The signal input to the input terminal of the LVDS interface will be described with reference to FIG. As described above, the effect control information of the LEDs controlled by all the LED control circuits LC in the gaming machine is transmitted from the control device CD to the first-stage LED control circuit LC1 using the three-wire serial interface. The first-stage LED control circuit LC1 is adapted to use the mode designation terminal MODE as a high signal so as to exhibit the first conversion function (3-line serial-LVDS conversion function). The first-stage LED control circuit LC1 is used. The effect control information transmitted by the control device CD is sequentially transmitted from the circuit LC1 to the second and subsequent lower LED control circuits LC2, LC3, etc. using the LVDS interface. In the LVDS interface, the differential clock signal and the differential data signal are transmitted using the two differential clock signal lines and the differential data signal lines, respectively.

  This will be described with reference to the LED control circuit LC in FIG. 3. In the case of the first-stage LED control circuit LC1 exhibiting the first conversion function (3-line serial-LVDS conversion function), the input terminals DCI1, DCI2 , 3-line serial signals input to DDI1 are converted into LVDS signals here, and differential clock signal output terminals DCO1 and DCO2 and differential data signal output terminals DDO1 and DDO2 to differential clock signal lines of the LVDS interface, differential The effect control information that has become the LVDS signal is output to the data signal line. In the second-stage LED control circuit LC2 that exhibits the second conversion function (LVDS-LVDS conversion function), the differential clock signal line and the differential data signal line described above are differential signals of the LED control circuit LC of FIG. The clock signal input terminals DCI1 and DCI2 and the differential data signal input terminals DDI1 and DDI2 are connected. Since the LVDS interface is a low voltage differential signal, a differential clock signal and a differential data signal in which the differential voltage between the two signal lines of the differential clock signal line and the differential data signal line is effective. Become.

  FIG. 8 shows a differential voltage between two signal lines, a differential clock signal line and a differential data signal line. Unlike the 3-wire serial interface, the LVDS interface does not use the enable signal. Therefore, a signal indicating the header condition and the final clock signal is used to indicate the time when the valid clock signal and data signal are transmitted. The header condition is a signal in which the differential data signal input terminals DDI1 and DDI2 change from a high signal to a low signal when the differential clock signal input terminals DCI1 and DCI2 are high signals. Following the header condition, a differential clock signal and a differential data signal are input. Performance control information is transmitted bit by bit on the differential data signal lines. In the example shown in FIG. 8, 8-bit data forming the first byte is transmitted in the order of bit7 to bit0, then 8-bit data forming the second byte is transmitted until the last byte bit0. Data signal is transmitted. A clock signal in which a low signal and a high signal are repeated at a constant clock cycle is transmitted on the differential clock signal line. The differential clock signal and the differential data signal input from the input terminal of the 3-wire serial interface are input to the clock signal terminal and the data signal terminal of the shift register SR2 as described above, and the clock signal changes from the low signal to the high signal. The state of the data signal at the time of the rising edge that changes to is latched as a data signal in the shift register SR1.

  When the valid differential clock signal and differential data signal are completed, the final clock signal is input from the upper LED control circuit LC using the LVDS interface. The final clock signal indicates that it is the final clock signal by setting the differential clock signal input terminals DCI1 and DCI2 in the high signal state. The signal input of the differential clock signal and the differential data signal input from the upper LED control circuit LC to the input terminals of the LED control circuit LC using the LVDS interface has been described with reference to FIGS. 3 and 8. Signal output when outputting the differential clock signal and the differential data signal from the differential clock signal output terminals DCO1 and DCO2 and the differential data signal output terminals DDO1 and DDO2 of the LVDS interface to the lower LED control circuit Is also the same.

<3-wire to 2-wire bridge function>
Referring to FIG. 9, in the first-stage LED control circuit LC1 that exhibits the first conversion function, the enable signal, the clock signal, and the data signal input using the 3-wire serial interface are the differential clock signals of the LVDS interface. The 3-wire → 2-wire bridge function of converting to a differential data signal and outputting the signal will be described.

  In the 3-wire → 2-wire bridge function, the mode designating terminal MODE is set to a high signal, whereby the input signal of the 3-wire serial interface is taken into the LED control circuit LC. As described in the section of <3-line serial interface>, the input clock signal and data signal are latched by the input circuits IC1 and IC2 and subsequently to the clock terminal and data terminal of the shift register SR2, and the selectors SEL1 and SEL2 are latched. Entered in. The clock signal and the data signal input to the selectors SEL1 and SEL2 are input to the input terminals of the differential output circuits DOC1 and DOC2. Here, the change of the enable signal of the 3-wire serial interface from the high signal to the low signal is a signal indicating that a valid signal is input to the clock signal and the data signal, and is a high signal of the enable signal of the 3-wire serial interface. To the low signal, the header condition is output from the LVDS interface. That is, the differential clock signal in the high signal state is output to the differential clock signal output terminals DCO1 and DCO2 of the differential output circuit DOC1, and the high signal is output to the differential data signal output terminals DDO1 and DDO2 of the differential output circuit DOC2. The header condition is output by outputting a differential data signal that changes to a low signal.

  Subsequently, the input of the clock signal and the data signal of the 3-line serial interface is as described in the above section <3-line serial interface>, and the data signal is input to the clock signal terminal and the data signal terminal of the shift register SR2. Are latched in the shift register SR2. Here, since the mode designation terminal MODE is a high signal, the clock signal input to the shift register SR2 and the data signal latched in the shift register SR2 are sequentially input to the selectors SEL1 and SEL2.

  The clock signal input to the selector SEL1 is input to the differential output circuit DOC1 from the selector SEL1, and the data signal input to the selector SEL2 is input to the differential output circuit DOC2 from the selector SEL2. The outputs of the differential output circuit DOC1 and the differential output circuit DOC2 are output as differential clock signals and differential data signals from the output terminals of the LVDS interface. The transmission timings of the differential clock signal and the differential data signal of the LVDS signal are as follows. Transmission of differential data signals is started from the differential data signal output terminals DDO1 and DDO2 of the LVDS interface at the timing of the rising edge of the clock signal of the clock signal input terminal SCLK of the 3-wire serial interface. The differential data signal is data from the first byte, bit7 to bit0, the second byte, and the last byte, bit0, like the data signal input from the three-wire serial interface. The differential clock signal output terminals DCO1 and DCO2 are sent so that the differential clock signals are sent such that the rising edge timing of the differential clock signals is the timing at which the data of the differential data signals is stable. It

When the control device CD finishes transmitting the effect control information using the 3-line serial interface, that is, when the transmission of all data signals is finished, the enable signal input terminal SEN of the 3-line serial interface changes from a low signal to a high signal. .. The change of the enable signal to the high signal causes the LVDS interface to transmit the final clock signal. The final clock signal is a signal that changes the differential clock signal output terminals DCO1 and DCO2 of the output terminal of the LVDS interface to the high signal state. In this way, the enable signal, the clock signal, and the data signal for transmitting the effect control information, which are input by using the 3-wire serial interface, are L by the 3-wire → 2-wire bridge function that exhibits the first conversion function.
It is converted into a differential clock signal and a differential data signal of the VDS interface and transmitted to the lower LED control circuit LC by using the LVDS interface. It should be noted that, because of this configuration, even if inductive noise is superimposed on each of the enable signal line, clock signal line, and data signal line of the three-wire serial interface, the noise is transmitted to the lower LED control circuit LC. The signal waveforms on the differential clock signal line and the differential data signal line of the LVDS interface are waveform-shaped signal waveforms on which induction noise is not superimposed.

<2-line to 2-line repeat function>
In the LED control circuit LC of the second stage and thereafter that exhibits the second conversion function using FIG. 10, the differential clock signal and the differential data signal input as the signal of the LVDS interface are repeated as the output signal of the LVDS interface. The 2-line → 2-line repeat function transmitted to the lower LED control circuit LC will be described.

  In the 2-wire → 2-wire bridge function, the input signal of the LVDS interface is taken into the LED control circuit LC by setting the mode designation terminal to the low signal. The operation is as described in the section of <LVDS interface> described above. It is latched by the terminals and input to the selectors SEL1 and SEL2. The clock signal and the data signal input to the selectors SEL1 and SEL2 are input to the input terminals of the differential output circuits DOC1 and DOC2.

  Here, the header condition is output from the output terminal of the LVDS interface based on the header condition input from the input terminal of the LVDS interface. Following the header condition, valid differential clock signals and differential data signals are input to the differential clock signal input terminals DCI1 and DCI2 and the differential data signal input terminals DDI1 and DDI2. The differential data signal is a signal from bit7 of the first byte to bit0 of the last byte. A differential clock signal is input together with the differential data signal and is input to the clock terminal and the data terminal of the shift register SR1. The differential data signal is input to the shift register SR1 and latched at the timing of the rising edge of the differential clock signal. The clock signal and the data signal input to the shift register SR1 are input to the selectors SEL1 and SEL2 by selecting the clock signal and the data signal output of the shift register SR1 because the mode specifying terminal MODE is set to the low signal. To be done.

  The clock signal input to the selector SEL1 is input to the differential output circuit DOC1 from the selector SEL1. The data signal input to the selector SEL2 is input to the differential output circuit DOC2. Subsequently, the differential output circuit DOC1 and the differential output circuit DOC2 output the differential clock signal and the differential data signal of the LVDS interface. The transmission timing of the differential clock signal and the differential data signal of the LVDS interface is as follows. The differential data signal output terminals DDO1 and DDO2 of the LVDS interface start transmitting differential data signals at the timing of the rising edges of the clock signals of the differential clock signal input terminals DCI1 and DCI2 of the LVDS interface. The differential clock signal output terminals DCO1 and DCO2 output the differential clock signal output terminals so that the timing of the rising edge of the differential clock signal is the timing at which the data of the differential data signal is stable. Differential clock signals are sent from DCO1 and DCO2.

When the effect control information has been input to the differential data signal input terminals DDI1 and DDI2, the final clock signal is input to the differential clock signal input terminals. The final clock signal is a state in which the differential data signals at the differential data signal input terminals DDI1 and DDI2 remain in a high signal state and the differential clock signals at the differential clock signal input terminals DCI1 and DCI2 rise from a low signal to a high signal. Is the signal. When the final clock signal is input to the input terminal of the LVDS signal, the final clock signal is output from the output terminal of the LVDS interface. The final clock signal is a signal that causes the differential data signal output terminals DDO1 and DDO2 of the LVDS interface to remain in the high signal state and changes the differential clock signal output terminals DCO1 and DCO2 from the low signal state to the high signal state. In this way, the differential clock signal and the differential data signal input to the input terminals of the LVDS interface are transferred to the lower LED control circuit LC by the 2-line to 2-line repeater function. It is transmitted as a motion data signal. With this configuration, even if inductive noise of the same phase is superposed on each of the differential clock signal line and the differential data signal line of the LVDS interface, they are transmitted to the lower LED control circuit LC. The waveform on each of the two lines of the differential clock signal line and the differential data signal line of the LVDS interface is a waveform-shaped differential clock signal and differential data signal on which induction noise is not superimposed.

  As described with reference to FIGS. 3 and 7 to 10, the LED control circuit LC of the present embodiment exhibits the first conversion function and can operate as the LED control circuit LC1 of the first stage. When it receives an input signal of the interface, it has a 3-wire → 2-wire bridge function of outputting the output signal of the LVDS interface to the lower LED control circuit LC. Further, it can perform the second conversion function and operate as the LED control circuits LC2, LC3, etc. of the second and subsequent stages, and when receiving the input signal of the LVDS interface, it outputs the output signal of the LVDS interface to the lower LED control circuit LC. It has a two-line to two-line repeater function for outputting. In any of the 3-wire → 2-wire bridge and 2-wire → 2-wire repeater functions, the output waveform of the output signal of the LVDS interface is an output waveform that is waveform-shaped in the LED control circuit LC. Therefore, even if it is affected by induction noise from the electromagnetic components arranged in the gaming machine, it becomes possible to connect to the lower LED control circuit with the waveform-shaped output waveform, and the LED control circuit is arranged. The effect that the degree of freedom in designing the installation position is improved is obtained.

<Direction control information>
Next, a method in which the control device CD transmits effect control information to a specific LED control circuit LC in the gaming machine will be described with reference to FIGS. 3 and 11. The control device CD, for each of the lamp control circuit 18 and the display lamp control circuit 47, produces control information for all the LED control circuits LC from the LED control circuit LC1 in the first stage through the LED control circuits in the subsequent stage. To send. Therefore, the light emission luminance information of the LED to be controlled by the lower LED control circuit LC is also transmitted via the LED control circuit LC1 in the first stage. As described above, each LED control circuit LC can control the emission brightness of 24 LEDs, but the control device CD transmits the emission brightness value information for controlling the emission brightness of 24 LEDs. Alternatively, the emission luminance value information of some LEDs may be transmitted. In order to enable such control, the effect control information transmitted from the control device CD to the LED control circuit LC has a byte structure as shown in FIG. The effect control information transmitted from the control device CD to the LED control circuit LC has a data length of the first byte to the (2 + p) th byte (p is a positive integer where p ≦ 24).

Bit7 of the first byte of the effect control information is a PWM phase control bit described later. BIT6 is an output enable designating bit that designates whether or not the output is transmitted from the LED control circuit LC. Bit5-0 is an LED control circuit address bit that specifies the addresses of a plurality of LED control circuits LC arranged in the gaming machine. The LED control circuit LC has six addressing terminals A5-A0 for setting addressing. The LED control circuit address included in the first byte Bit5-0 of the effect control information transmitted from the control device CD to the LED control circuit LC is input to the register REG1 in the register circuit LD1. Address matching is performed to determine whether or not the value of BiT5-0 stored in the register REG1 and the address set from the address designation terminals A5-A0 match. For example, when the device address of the LED control circuit LC for controlling the emission brightness of the display lamp 46c of FIG. 1 is set to 3, the address designation terminals A5-A0 are set to 000011. The control device CD designates the first byte, bit5-bit0, of the effect control information to be transmitted to the LED control circuit LC as 000011. By thus performing the address collation, the control device CD accurately receives the performance control information in the designated LED control circuit LC even through the LED control circuits LC1 to LC1 in the first stage and the subsequent stages. It is possible.

  When the address collations match, the subsequently received second byte data is input to the register REG2 of the register circuit LD1. The second byte data specifies the register address of the register REG3 that stores the subsequently input third byte data. The data after the third byte is the light emission luminance value information of the LED controlled by the LED control circuit. FIG. 11 shows an example in which the data value of the second byte stored in the register REG2 is 1 and the register address 1 is designated. The third byte of data is stored in register address 1 of register REG3. When the third byte of data is stored in register address 1, register REG2 increments the register address by one. Therefore, when the fourth byte of data is subsequently received, the received fourth byte of data is stored in the register address 2 of the register REG3. In this way, when the final byte of the effect control information is the (2 + p) th byte, the register REG2 specifies the register address p, and the data of the (2 + p) th byte of the final byte is the register address p of the register REG3. Memorized in. In this way, the data from the third byte to the (2 + p) th byte of the effect control information is stored in the register address 1 to the register address p sequentially designated by the second byte.

  In FIG. 11, an example in which the control device CD transmits light emission luminance value information for performing light emission luminance control of p LEDs to an LED control circuit capable of controlling light emission luminance of 24 LEDs, for example. Showing. For example, one LED control circuit can control the emission brightness of 24 LEDs, and the register address of the register REG3 is from register address 1 to register address 24. The control device CD can also transmit the emission luminance value information of the 24 LEDs by transmitting the production control information once.

  The register REG3 has 24 register addresses from the register address 1 to the register address 24, and each of the register address 1 to the register address 24 stores the light emission luminance value information of 24 LEDs to be controlled by the LED control circuit LC. To do. The light emission luminance value information is an 8-bit data value. Register address 1 stores the 256-step emission brightness value of the LED driven from the LED drive terminal LOUT1, and register address 2 stores the 256-step emission brightness value of the LED driven from the LED drive terminal LOUT2. In the following order, the register address 24 stores the emission brightness value of 256 levels of the LED driven from the LED drive terminal LOUT24.

<LED effect control>
The 256-step emission brightness value control of 24 LEDs will be described with reference to FIG. In the register address 1 to the register address 24 of the register REG3, 256 levels of light emission luminance value information output from the LED drive terminals LOUT1 to LOUT24 are stored. The LED control circuit LC has a PWM control circuit LD2, and controls the pulse width of the PWM signal output from the LED drive terminals LOUT1-LOUT24 with 256-step pulse width based on the light emission luminance value information stored in the register REG3. .. The PWM control circuit LD2 performs PWM control, for example, every 290 μs cycle based on the light emission luminance value information stored in the register address 1 to the register address 24 of the register REG3. When the emission brightness value of the emission brightness information is 255, the ON signal period of the PWM pulse is output from the LED drive terminals LOUT1 to LOUT24 as a PWM pulse having a duty ratio of 255/256, for example. When the light emission luminance value is 254, a PWM pulse having a duty ratio of 254/256 is output from the LED drive terminals LOUT1 to LOUT24. Hereinafter, when the light emission luminance value is small, the ON signal period of the PWM pulse is short, and when the light emission luminance value is 0, the LED drive terminal LOU
The PWM pulse output from T1-LOUT24 turns off and the LED turns off.

  As described with reference to FIG. 12, the LED control circuit LC controls the light emission luminance of the LED to be controlled by each LED control circuit LC with the duty ratio of the 256-step PWM pulse. Here, for example, an example in which the effect lamp 12 arranged in the upper panel assembly 10 of FIG. 1 is controlled in various color tones will be described. It is assumed that the plurality of LEDs that form the effect lamp 12 are, for example, a plurality of color light emitting LEDs that are a combination of three LEDs that emit light in the three primary colors. The sub-main CPU 71 of the gaming machine emits each of the plurality of color light emitting LEDs in different color tones according to the gaming state of the gaming machine. For example, it is assumed that the left part of the effect lamp 12 emits green light so that the brightness changes, and the right part of the effect lamp 12 emits blue light so that the brightness changes. As described with reference to FIG. 12, the PWM control circuit LD2 of the LED control circuit LC is configured to control the emission brightness of each of the 24 LEDs to be controlled at a cycle of 290 μs. The three LED driving terminals of the 24 LED driving terminals LOUT1 to LOUT3 correspond to the three primary color LEDs of the color light emitting LEDs on the left side of the effect lamp 12, that is, the red LED, the green LED, and the blue LED, respectively, and drive the LED. The three LED drive terminals of the terminals LOUT22 to LOUT24 correspond to the three primary color LEDs of the color light emitting LEDs on the right side of the effect lamp 12, that is, the red LED, the green LED, and the blue LED. In such a configuration, the duty ratio of the PWM pulse for driving the green LED of LOUT2 at the three LED drive terminals LOUT1 to LOUT3 is set to the red corresponding to the LED drive terminals LOUT1 and LOUT3. If the light emission luminance value information is changed and controlled in a cycle of 290 μs at a duty ratio higher than the duty ratio of the PWM pulse for driving the LED and the blue LED, the left side portion of the effect control lamp 12 emits green light and is bright. The emission brightness can be controlled so that Similarly, in the three LED drive terminals LOUT22 to LOUT24 that control the right side portion of the effect lamp 12, the duty ratio of the PWM pulse of LOUT22 for driving the red LED drives the green LED and the blue LED. If the duty ratio of the PWM pulse is higher than the duty ratio of the PWM pulse and is controlled in a cycle of 290 μs, the light emission luminance control can be performed so that the right side portion of the effect lamp 12 emits red light and the brightness changes.

  In the above description, the control example in which the brightness is changed by using the color three primary color LEDs while the color tones are green and red is described. It is possible to control so that the color tone is initially green and changes to a reddish color tone with the passage of time. Alternatively, it is possible to control so as to control the brightness by using a single color LED. By controlling the light emission brightness of the LED using the LED control circuit LC shown in FIG. 3, it is possible to perform various effect controls in the gaming machine so as to enhance the interest of the player.

<LED individual control, group control>
The LED control circuit of the present embodiment, for example, controls the emission brightness of 24 LEDs, but is configured to be able to perform individual control or group control when performing the emission brightness control of these 24 LEDs. ing. When the PWM pulse is ON-controlled at the same timing for 24 LEDs controlled by one LED control circuit LC, a large current change of 24 times occurs at a time as compared with the case where one LED is controlled for driving. To do. Therefore, switching noise is generated in the peripheral circuit, which is likely to cause malfunction of the peripheral circuit. For this reason, the LED control circuit LC of the present embodiment is configured to be able to drive and control each of the 24 LEDs at different phase timings. Alternatively, a group is formed by three LEDs, and the LEDs can be drive-controlled at different phase timings for each group. Therefore, the bit 7 of the first byte of the effect control information specifies whether to individually control each of the LED drive terminals LOUT1 to LOUT24 at different phase timings or perform group control by grouping each of the three LED drive terminals. This is a PWM phase control bit.

  Individual control of the PWM phase of each of the 24 LEDs will be described with reference to FIG. When bit7 of the first byte of the production control information is set to 0 and individual control is performed, the ON signal transmission start timing of the PWM pulse at the LED drive terminal LOUT1, the ON signal transmission start timing of the LED drive terminal LOUT2, the LED The ON signal transmission start timing of the drive terminal LOUT3 is different from each other by a fixed delay time. Thereafter, similarly, the PWM pulse ON signal transmission start timing is shifted to the LED drive terminal LOUT24 with a fixed delay time. Therefore, each of the LED drive terminals LOUT1 to LOUT24 drive-controls 24 LEDs in a PWM phase different by a fixed delay time.

  Group control of 24 LEDs will be described with reference to FIGS. 14 and 15. Bit 7 of the first byte of the effect control information is set to 1 to perform group control. The 24 LED drive terminals LOUT1 to LOUT24 are divided into groups for each of the three LED drive terminals, and each group starts sending an ON signal at a different timing by a fixed delay time. In FIG. 14, the group 1 including the LED drive terminals LOUT1 to LOUT3 and the group 2 including the LED drive terminals LOUT4 to LOUT6 start sending ON signals at different timings by a fixed delay time.

  As shown in FIG. 15, one group of three LED driving terminals LOUT1 to LOUT3 are connected in parallel to drive and control one LED. With this configuration, one LED is driven with a constant current by the three LED drive terminals. Therefore, the current value flowing through the LED is three times the current value when one LED is driven and controlled by one LED drive terminal. By performing the group control in this way, it becomes possible to control the light emission of the LEDs with a light emission luminance three times as high as that in the case of the individual control. Unlike the example shown in FIG. 15, another LED may be drive-controlled from each of the three LED drive terminals of one group. Alternatively, two LED drive terminals may be arranged in parallel to drive and control one LED, and the remaining one LED drive terminal may drive and control another LED.

<Initialization of LED control circuit>
At the amusement store, power is turned on to the amusement machine every day before opening. When the power is turned on, the effect control information of the previous day may remain stored in the register circuit LD1 of the LED control circuit LC. In this case, there is a possibility that the LED of the gaming machine may be controlled in emission brightness based on the effect control information of the previous day stored in the LED control circuit LC when the power is turned on. Therefore, it is preferable to initialize the effect control information of the previous day that may be stored in the LED control circuit LC when the power is turned on.

  A method of initializing the effect control information already stored in all the LED control circuits LC in the gaming machine from the control device when the gaming machine is powered on will be described with reference to FIG. In order to initialize the effect control information in the LED control circuit LC, an initialization pattern is sent from the control device CD to the LED control circuit LC1 in the first stage. There are two ways to send the initialization pattern.

The initialization pattern 1 will be described with reference to FIG. The LED control circuit LC1 of the first stage receives a pulse signal whose enable signal is Active-Low from the control device CD. The pulse signal of Active-Low is a pulse signal that changes from a high signal to a low signal and then changes to a high signal at a timing of minimum 200 μs. When receiving the Active-Low pulse signal, the LED control circuit LC1 in the first stage determines that the initialization signal is received from the control device CD. Specifically, the LED control circuit LC1 of the first stage receives an enable signal from the control device CD in which the enable signal input terminal SEN of the 3-wire serial interface changes from a high signal state to a low signal. When the enable signal input terminal SEN changes from a high signal to a low signal, the differential data signal output terminals DDO1 and DDO2 of the LVDS interface output a signal changing from a high signal to a low signal. Since the clock signal input terminal SCLK and the data signal input terminal SD of the 3-wire serial interface remain high signals and do not change, the differential clock signal output terminals DCO1 and DCO2 of the LVDS interface do not change and remain high signals. The signal conversion from the signal used in the 3-wire serial interface to the signal used in the LVDS interface is the same as the transmission of the header condition in the 3-wire → 2-wire bridge function.

  Then, the enable signal input terminal SEN changes from a low signal to a high signal at a timing of a minimum of 200 μs, so that the LED control circuit LC1 of the first stage determines that this Active-Low pulse is an initialization signal. In the LVDS interface, before transmitting the initialization pattern, the differential data signal at the differential data signal output terminals DDO1 and DDO2 is changed from a low signal to a high signal, and the differential clock signal at the differential clock signal output terminals DCO1 and DCO2 is changed. Is changed from a high signal to a low signal for a predetermined time. Then, the initialization pattern is transmitted from the output terminal of the LVDS interface. The initialization pattern is a signal pattern in which the differential clock signal output terminals DCO1 and DCO2 change from a low signal state to a high signal state when the differential data signal output terminals DDO1 and DDO2 are in a high signal state. In this way, the first-stage LED control circuit LC1 transmits the initialization pattern in the LVDS interface to the lower-order second-stage LED control circuit LC2 based on the initialization signal received from the control device CD. It is configured.

  Using the initialization pattern 1, it is possible to initialize the LED control circuit LC from the control device CD. However, the initialization pattern 1 is a signal for transmitting an Active-Low signal of minimum 200 μs as an enable signal. Since the enable signal line of the three-wire serial interface is a single wire, induction noise may be superimposed from electromagnetic components in the gaming machine, and this induction noise may be erroneously received as an Active-Low signal. is there. Therefore, it is conceivable to send the initialization pattern 2 which is less likely to malfunction than the initialization pattern 1 due to the influence of inductive noise.

  The initialization pattern 2 will be described with reference to FIG. The LED control circuit LC1 of the first stage receives from the control device CD only eight clock signals and the first byte of which all data values are high signals. The LED control circuit of the first stage receives only the first byte, which is a high signal, and determines that the initialization signal has been received from the control device. Specifically, when the enable signal input terminal SEN of the 3-wire serial interface receives an enable signal that changes from a high signal state to a low signal, the LVDS interface of the LVDS interface as well as the sending of the header condition in the 3-wire → 2-wire bridge function is received. The differential data signal output terminals DDO1 and DDO2 output a data signal that changes from a high signal to a low signal. In the initialization pattern 2, subsequently, only the first byte whose all data values are high signals is received. That is, eight clock signals are received from the clock signal input terminal SCLK of the 3-wire serial interface, and the data signal input terminal SD remains a high signal. After receiving the eight clock signals, the enable signal input terminal SEN changes from a low signal state to a high signal state. Therefore, the first-stage LED control circuit LC1 can determine that all the data values have received only the first byte, which is a high signal.

When the first byte is received from the input terminal of the 3-wire serial interface, the first byte of data received from the differential clock signal output terminals DCO1 and DCO2 and the differential data output terminals DDO1 and DDO2 of the LVDS interface is output. The time chart of the transmission / reception of the data of the first byte is the same as the time chart of the 3-wire → 2-wire bridge shown in FIG. The enable signal input terminal SEN changes from the low signal to the high signal at the timing of receiving the first byte. Therefore, the LED control circuit 1 of the first stage has received the high signal for all the data values of the first byte. It is determined that the initialization signal has been received from, and the initialization pattern is transmitted from the LVDS interface as follows. Before the initialization pattern is transmitted from the output terminal of the LVDS interface, the differential clock signals at the differential clock signal output terminals DCO1 and DCO2 are changed from a high signal to a low signal for a predetermined time. Then, the initialization pattern is transmitted. The initialization pattern is a signal pattern in which the differential clock output terminals DCO1 and DCO2 change from a low signal state to a high signal state when the differential data signal output terminals DDO1 and DDO2 are in a high signal state. In this way, the first-stage LED control circuit LC1 transmits the initialization pattern in the LVDS interface to the lower-order second-stage LED control circuit LC2 based on the initialization signal received from the control device CD. It is configured.

  When the LED control circuits LC of the second and subsequent stages receive the initialization pattern of the LVDS interface from the upper LED control circuit LC, the initialization pattern is sent from the output terminal of the LVDS interface to the lower LED control circuit LC. .. In this way, the initialization pattern transmitted from the control device CD to the first-stage LED control circuit LC1 is sequentially transferred to the second-stage LED control circuit LC2 and then to the third-stage effect control hand LC3. , To the lower LED control circuit LC. With this configuration, when the initialization signal is transmitted from the control device to the first-stage LED control circuit LC1, the initialization pattern is transmitted to all the LED control circuits LC in the gaming machine, and all the LEDs are transmitted. The control circuit LC can be initialized.

[Second Embodiment]
Next, the general configuration of the pachinko gaming machine PM as the second embodiment of the gaming machine according to the present invention will be outlined.

<Basic configuration of pachinko machine>
First, the basic structure of the front side of the pachinko gaming machine PM will be described with reference to FIG. As shown in FIG. 17, the pachinko gaming machine PM (also simply referred to as “gaming machine PM”) is aligned with the opening front surface of the outer frame 101 which is a vertically oriented fixed holding frame configured to have an outer rectangular frame size. A front frame 102, which has a rectangular frame size and serves as an open / close mounting frame, is laterally opened, opened, and detachably attached by an upper and lower hinge mechanism 103 provided on the front left edge of each other. The front frame 102 is always held in a closed state in which the front frame 102 is engaged and connected with the outer frame 101 by using a locking device 4 called a double lock provided on the front right side edge portion.

  To the front frame 102, a rectangular glass frame 105 that fits in the upper front area of the front frame 102 is attached by means of the upper and lower hinge mechanisms 103 so that it can be opened / closed sideways and detachably. The glass frame 105 is always held in a closed state by using the locking device 104 so as to cover the front surface of the front frame 102. The game board 120 is detachably set and held on the front frame 102, and the game area PA in front of the game board 120 is visibly visible through the multi-layer glass of the glass frame 105 which is closed and held.

On the front surface side of the glass frame 105, a frame lamp (LED lamp) 110 that emits light according to the development situation of the game and a speaker 111 that generates a sound effect according to the development situation of the game are provided. At the bottom of the glass frame 105, upper and lower ball plates (upper ball plate 108 and lower ball plate 109) for storing game balls are provided, and the front center of the upper ball plate 108 is pressed by the player. A button (effect switch) 115 is provided, and a firing handle 112 for performing a game ball firing operation is provided on the front right side of the lower ball plate 109. In the following, the operation input means for effect is referred to as “effect button 115”, but the effect button (effect switch) 115 in this example is an on / off operation type button type switch, depending on the direction of operation input. Cross-shaped switch (cross-shaped key, cross-shaped button) for output, tilt-operated lever-type switch, rotary-operated dial switch, proximity switch for output when player's hand approaches or touches , Touch sensor, touch panel, etc.

  The game board 120 is configured with a substrate formed in a rectangular flat plate shape using a synthetic resin material such as an acrylic resin, a polycarbonate resin, or an ABS resin as a base. On the front surface of the game board 120, an outer rail 141 and an inner rail 142 are fixed in an arc shape, and a substantially circular game area PA in which a game ball can roll is defined. A guide passage (not shown) for guiding the game ball to the game area PA is formed by the outer rail 141 and the inner rail 142, and a position near the exit opening of the game ball in this guide passage (the tip of the inner rail 142). In addition, a ball return prevention valve 143 is provided to prevent the game balls released from the outlet opening into the game area PA from returning to the guide passage again. In this game area PA, along with a windmill and a large number of game nails, various types such as a first starting opening 151, a second starting opening 152, an operating gate 153, a special winning opening 154, a general winning opening 161, 162, 163, 164, etc. Other than the winning opening, such as the first special symbol display device 171, the second special symbol display device 172, the first special symbol hold lamp 173, the second special symbol hold lamp 174, the normal symbol display device 175, the universal symbol hold lamp 176, etc. Various display devices are provided. A center ornament 121 is arranged in the approximate center of the game area PA, and the screen of the effect display device 170 is visibly provided through the center opening of the center ornament 121. The game area PA has a left side area PA1 which is an area on the left side of the center decoration 121 (a board surface area corresponding to a left hit) and a right area of the center decoration 121 (which corresponds to a right hit) with the center decoration 121 at the center as a reference. And a right side area PA2 which is a board surface area). A top plate portion 122 that is opposed to the outer rail 141 in a substantially vertical direction is integrally formed on the upper portion of the center ornament 121. In the extension of the guide passage, the top plate portion 122 and the outer rail 141 are formed. An introduction passage 144 through which the game ball can pass to the right side area PA2 is formed. At the lower end of the game area PA, there is provided an outlet 129 for discharging the rolling-down game balls to the back side of the game board 120 without entering the respective winning ports. Hereinafter, each component provided on the game board 120 will be described in order.

  The first starting port 151 is provided as a starting winning port corresponding to the first special symbol game, and is provided with a first starting port switch 511 for detecting the entry of a game ball. The entry of the game ball into the first starting opening 151 is a trigger for the first special symbol lottery.

  The second starting port 152 is provided as a starting winning port corresponding to the second special symbol game, and is provided with a second starting port switch 521 for detecting the entry of a game ball. The entry of the game ball into the second starting port 152 is a trigger for the second special symbol lottery. The second starting port 152 includes an ordinary electric accessory 522 and an ordinary electric accessory solenoid 523 for opening and closing the ordinary electric accessory 522. The normal electric accessory 522 is changed between a closed state in which the game ball is hard to enter the second starting port 152 and an open state in which the game ball is easier to enter than the above state. Here, the second starting port 152 has a structure in which a game ball is difficult to enter unless the ordinary electric accessory 522 is opened. On the other hand, when the normal electric accessory 522 is opened, the ease with which the ball can enter the second starting opening 152 increases.

  The operation gate 153 is provided as a starting winning opening corresponding to a normal symbol game, and is provided with an operation gate switch 531 for detecting passage of a game ball. The passage of the game ball to the operation gate 153 serves as a trigger for the ordinary symbol lottery for determining whether or not to expand the ordinary electric accessory 522 of the second starting opening 152.

The special winning opening 154 is formed as a horizontal rectangular winning opening that is opened when a big hit or a small hit is made in the winning / no winning lottery of the first special symbol or the second special symbol. The special winning opening 154 is provided with a special winning opening switch 541 for detecting the entry of a game ball, and a special electric accessory 542 called a so-called attacker device and for opening and closing the special electric accessory 542. And a special winning opening solenoid 543. The special electric auditors product 542 changes into a normal state in which the game ball cannot enter or difficult to enter the special winning opening 154 and an open state in which the game ball can enter or can easily enter. In this example, the special winning opening 154 is the right side area PA in the game area PA.
It is provided in 2. Therefore, in the special game state (big hit game state), when the game ball is shot toward the game area PA, by hitting the right area PA2, that is, by so-called right hitting, the special winning opening 154 is entered. The sphere has become easier.

  The general winning openings 161 to 163 are arranged in a left side area PA1 which is a board area corresponding to left-handed play, and a game ball flowing down the left side area PA1 can enter. The general winning openings 161 to 163 are provided with a left general winning opening switch 611 for detecting the entrance of a game ball. The left general winning opening switch 611 is configured as a common sensor (single sensor) for the three general winning openings 161 to 163 from the viewpoint of cost reduction and the like. Incoming balls can also be detected. The general winning opening 164 is arranged in the right area PA2 which is a board surface area corresponding to right-handed play, and a game ball flowing down from the right area PA2 can enter. The general winning opening 164 is provided with a right general winning opening switch 641 for detecting the entry of a game ball. The entry of the game ball into each of the general winning openings 161 to 164 does not trigger the lottery of the special symbol or the ordinary symbol, but it triggers the winning of the prize ball like other winning orifices (excluding the operating gate 153). .

  The first special symbol display device 171 performs the variable display and the fixed display of the first special symbol when the game ball enters the first starting opening 151. The first special symbol display device 171 has a lamp display section for displaying the first special symbol visually recognized from the outside, and an LED lamp configuration including an LED provided on the back surface thereof, by controlling the blinking pattern of the LED. The lamp display section performs a variable display of the first special symbol, and a fixed display of the first special symbol is performed by the LED lighting display.

  The second special symbol display device 172 performs the variable display and the fixed display of the second special symbol when the game ball enters the second starting opening 152. The second special symbol display device 172 is an LED lamp configuration including a lamp display section for displaying a second special symbol visually recognized from the outside and an LED provided on the back surface thereof, and by controlling the blinking pattern of the LED. The lamp display section performs a variable display of the second special symbol, and the final display of the second special symbol is performed by the lighting display of the LED.

  The first special figure holding lamp 173 and the second special figure holding lamp 174 have an LED lamp configuration including a lamp display section and a plurality of LEDs provided on the back surface thereof, and the LED of each LED lamp is turned on. -The number of operation-holding balls (up to 4) of the first special symbol and the second special symbol is expressed by blinking display. The number of operation reserved balls of the first special symbol is a number relating to a random number value obtained based on the ball entering the first starting opening 151 during the change of the first special symbol or the second special symbol or the execution of the special game. Yes, it indicates the number for which the obtained random number is suspended, that is, the acceptance determination is suspended until the acceptance determination permission condition (variation start condition) is satisfied for the acquired random value. Similarly, the operation holding ball number of the second special symbol is a random number value obtained based on the ball entering the second starting port 152 during the change of the first special symbol or the second special symbol or the execution of the special game. This is the number concerned, and indicates the number for which the acceptance judgment is once suspended until the acquired random number value is suspended, that is, until the acceptance judgment permission condition (variation start condition) is satisfied for the acquired random value. There is.

  The normal symbol display device 175 is an LED lamp configuration including a lamp display section and a plurality of LEDs provided on the back surface of the lamp display section, and performs variable display and confirmation display of normal symbols. The universal figure holding lamp 176 is an LED lamp configuration including a lamp display section and a plurality of LEDs provided on the back surface thereof, and the number of the lamps to be lit is normally the number of symbols to be held (not yet executed). It usually corresponds to the number of symbol variations). On the left side of the normal symbol display device 175, a round display 177 for displaying the number of round games (unit games) in the special game (the number of rounds: the number of times the special electric auditors product 542 continuously operates) is provided. ..

  The effect display device 170 mainly displays an effect image including a notice effect that suggests or informs a decorative pattern that fluctuates and stops changing in conjunction with the first special symbol or the second special symbol and the expectation degree of a big hit in advance. While doing, hold display of the first special symbol and the second special symbol is performed. Specifically, on the screen of the effect display device 170, the decorative symbol display unit 700 for performing variable display and notice effect display of the decorative symbol, and the first special symbol in synchronization with the first special symbol holding lamp 173. 1st special figure reservation display section 701 where the reservation display of is executed, and 2nd special figure reservation display section 702 where the reservation display of the 2nd special design is executed in synchronization with the 2nd special figure reservation lamp 174 Has been. In this embodiment, a liquid crystal display device is used as the effect display device 170. In the decorative symbol display portion 700, three columns of display regions (left display region Z1, middle display region Z2, right display region Z3) that are variable display regions of the decorative symbol are provided on a predetermined effective line (not shown). The left design symbol corresponding to the left display area Z1, the middle design symbol corresponding to the middle display area Z2, and the right design symbol corresponding to the right display area Z3 are stopped and displayed. It has become so. In the normal display mode, the special image holding display portions 701 and 702 display a white circled holding image when an operation holding ball of a special symbol is generated, while the operation holding ball is consumed. The held image is erased. This reserved image is displayed in order according to the generation order (the order of entering balls) of the operation reserved balls of the special symbol, and it is possible to display a maximum of four on each of the reserved display portions 701 and 702.

  The center decoration 121 is installed around the effect display device 170, and has functions such as a flow path for a game ball, protection of the screen of the effect display device 170, and decoration. The center ornament 121 is provided with a movable accessory 124 that executes a performance operation according to the development situation of the game. The movable accessory 124 includes a motor M (for example, a stepping motor) as a drive source. The game board 120 is provided with a board lamp (LED lamp) 180 that emits light in accordance with the development status of the game. The board lamp 180 includes lightning-shaped prize notification lamps 181 to 183 arranged near the general winning openings 161 to 163 and star-shaped prize notification lamps 184 arranged near the general winning opening 164. Be done. In the following description, for the sake of convenience, the frame lamp 110 and the board lamp 180 (including the prize notification lamps 181 to 184) are collectively referred to as “effect lamp LP”. The effect lamp LP has an LED lamp configuration including a lamp display portion visually recognized from the outside and an LED provided on the back surface thereof. By controlling the light emission of the LED, the board lamp 180 allows the game machine to be deployed. Accordingly, the light emission effect is performed, and the winning notification lamps 181 to 184 perform the winning notification.

  Subsequently, the basic structure of the back side of the pachinko gaming machine PM will be described with reference to FIG. On the back side of the front frame 102, a back set board 130, which has a window which communicates with the front and rear in the center and which is based on a base frame body formed in the shape of a rectangular frame which is slightly smaller than the front frame 102, is arranged on the upper and lower sides. A hinge mechanism 103 is connected to the rear side of the front frame 102 so as to be capable of lateral opening / closing and attachment / detachment. A back set cover 130C in the form of a rectangular box with an open front is detachably attached to the back set board 130, and is normally disposed so as to cover the back side of the game board 120 attached to the front frame 102. (Thus, the main control board 200, the effect control board 300, and the image control board 400, which will be described later, are covered by the back set cover 130C).

  In each part of the back set board 130, a storage tank 131 that stores a large number of game balls, a tank rail 132 that extends from the storage tank 131 to the right with a gentle downward slope, a lower end connected to the right end of the tank rail 132. A ball supply passage portion 133, a prize ball payout unit 134 for paying out the game ball guided by the ball supply passage portion 133, and a prize for guiding the game ball paid out from the prize ball payout unit 134 to the upper ball plate 106. A ball passage portion 135 and the like are provided.

On the back side of the game board 110, a main control board 200 that comprehensively controls the operation of the pachinko game machine PM, a production control board 300 that controls overall production, image display according to game development, and control of sound effects. An image control board 400 for performing the above is attached. On the other hand, on the back side of the back set board 130, a payout control board 500 for controlling the launch and payout of game balls, and power from the gaming facility side to supply power to various control boards and electric / electronic parts. A power supply board 600 and the like are attached. These control boards are installed in predetermined positions on the back of the game board 120 or the back of the back set board 130 in an assembled state housed in a board case made of a transparent resin having a caulking structure and a sealing structure to prevent unauthorized modification. To be done. The control board and the electric / electronic parts of each part of the pachinko gaming machine PM are mutually connected via a harness (connector cable), and the pachinko gaming machine PM is configured to be operable.

<Control configuration of Pachinko game machine>
Next, with reference to FIG. 19 additionally, each control board mounted on the pachinko gaming machine PM according to the present embodiment will be described. FIG. 19 is a control block diagram showing a control configuration of the pachinko gaming machine PM.

  The main control board 200 is a main CPU 201 that performs various arithmetic processing related to games, a ROM 202 that stores control programs and various data, a RAM 203 that functions as a work area or a buffer memory that is a temporary storage area, peripheral boards and each A main control microcomputer (one-chip microcomputer) 210 including an I / O port circuit 204 that inputs and outputs signals to and from a device is mounted, and a main CPU 201 plays a game according to a control program stored in a ROM 202. It is configured to execute the main control related to the progress. In addition, although not shown, the main control board 200 is reset by a clock circuit that divides a clock signal from a crystal oscillator to generate an internal system clock, and when the main CPU 201 malfunctions or runs out of control. The WDT circuit for returning to a normal state, the CTC circuit for enabling real-time interrupt generation and time measurement, and the program processing (software random number) by the main CPU 201 operate as a separate system to generate a predetermined random number (internal random number) A random number generation circuit and the like are mounted, and these are connected to each other via an internal bus.

  The main CPU 201 executes various processes related to the main control of the game by reading out various control programs stored in the ROM 202 and performing arithmetic processing based on the detection information from each switch. The RAM 203 is a backup RAM serving as a non-volatile storage unit that is backed up by a backup power supply generated on the power supply board 600. The backup area of the RAM 103 is an area for storing data such as stack pointers and registers held when the power is cut off when the power is cut off. ) Indicates that the state of the gaming machine is restored to the state before the power is turned off based on the information in the backup area.

  The main control board 200 is electrically connected to a first starting opening switch 511, a second starting opening switch 521, an operating gate switch 531, a special winning opening switch 541, a left general winning opening switch 611, a right general winning opening switch 641 and the like. The detection signals from various switches are input to the main CPU 201 via the I / O port circuit 204. The main control board 200, the first special symbol display device 171, the second special symbol display device 172, the first special symbol holding lamp 173, the second special symbol holding lamp 174, the normal symbol display device 175 and the general symbol holding lamp 176. The control signal from the main CPU 201 is electrically connected to the ordinary electric accessory solenoid 523 and the special electric accessory solenoid 543, and displays various control signals from the main CPU 201 via the I / O port circuit 204. And send to various solenoids.

The main control board 200 and the effect control board 300 are connected by eight parallel signal lines and one strobe line, and communication is performed only in a single direction from the main control board 200 to the effect control board 300. Various control commands are transmitted from the main control board 200 to the effect control board 300. Data cannot be transmitted from the production control board 300 to the main control board 200, and the main control board 200 cannot be requested to transmit data. In addition, the connection between the main control board 200 and the effect control board 300 is not limited to the connection of eight parallel signal lines and one strobe line. It may be connected by a 3-wire serial interface.

  The effect control board 300 is a sub-main CPU 301 that performs various arithmetic processing related to game effect based on the effect control command from the main control board 200, a ROM 302 that stores effect control programs and various data, a work area that serves as a temporary storage area, A performance control microcomputer (one-chip microcomputer) 310 including a RAM 303 functioning as a buffer memory and an I / O port circuit 304 for inputting / outputting signals to / from a peripheral board or each device is mounted. The sub-main CPU 301 is configured to execute main control relating to game effects according to a control program stored in the ROM 302. In addition, although not shown, the production control board 300 is reset when a clock circuit that divides a clock signal from a crystal oscillator to generate an internal system clock and the sub-main CPU 301 malfunctions or runs out of control. Circuit for returning various states based on the system clock, an interrupt controller for activating various interrupts such as timer interrupts based on signals from the TPU circuit, for inputting / outputting serial data A serial communication circuit and the like are mounted, and these are connected to each other via an internal bus.

  The effect control board 300, in the effect control process based on the effect control command from the main control board 200, an image control command for instructing an image and a sound to the image control board 400, and a lamp control signal for controlling the lamp connection board 191. (Lamp data), a drive control signal (drive data) for controlling the motor driver 192, and the like are generated. The effect control board 300 is connected to the image control board 400 so as to be able to perform two-way communication, and while the image control commands related to images and sound are transmitted from the effect control board 300 to the image control board 400, as a response thereto, A response command (ACK command) indicating that the image control command is normally received is transmitted from the image control board 400 to the effect control board 300.

  The production control board 300 is electrically connected to a lamp connection board 191 equipped with production output control means for controlling light emission of a plurality of LEDs, and a lamp for controlling the lamp connection board 191 via a serial communication circuit. Send a control signal (ramp data). In this example, the production control board 300 and the lamp connection board 191 employ clock-synchronized serial communication, and a clock transmitted by a signal line (clock line) different from the data line for lamp data transmission. The lamp control signal is transmitted bit by bit through the data line in synchronization with the signal. The lamp connection board 191 has a built-in LED driver that functions by receiving a lamp control signal for driving an LED transmitted from the effect control board 300, and switches on / off a switch in the circuit based on the lamp control signal. Thus, control is performed to supply or cut off the drive current to the effect lamp LP and turn on or off the effect lamp LP.

  Furthermore, the production control board 300 is electrically connected to the plurality of motor drivers 192, and sends a drive control signal (drive data) for controlling the motor driver 192 to the motor driver 192 via the I / O port circuit 304. Send. The motor driver 192 supplies a drive current to the stepping motor of each movable accessory 124 by turning on / off a switch in the circuit based on a drive control signal for driving an accessory that is transmitted from the effect control board 300. Alternatively, the control is performed by shutting off and operating each movable accessory 124. A parallel communication method is adopted for data transmission to the motor driver 192.

The image control board 400 includes a sub-sub CPU 401 that performs various arithmetic processes related to image effects based on an image control command from the effect control board 300, a ROM 402 that stores an image control program and various data, and a work area that serves as a temporary storage area. An image control microcomputer (one-chip microcomputer) 410 including a RAM 403 that functions as a buffer memory and an I / O port circuit 404 that inputs and outputs signals to and from a peripheral board and each device is mounted. The sub-sub CPU 401 is configured to execute main control relating to image effects according to a control program stored in the ROM 402. In addition, although not shown in the figure, the VDP that generates image data according to the effect content based on the control signal acquired from the sub-sub CPU 401 and the effect content based on the control signal acquired from the sub-sub CPU 401 are provided on the image control board 400. A sound source IC for generating acoustic data is mounted. The VDP is a so-called image processor, which reads the image data stored in the image ROM according to an instruction from the sub-sub CPU 401, and transmits a video signal (image data) generated by performing image processing to the image data to the effect display device 170. .. A high-speed VRAM used for developing and processing the image data read from the image ROM is connected to the VDP. The sound source IC reads the acoustic data stored in the audio ROM in response to an instruction from the sub-sub CPU 401, and outputs the acoustic data generated by performing a synthesis process to the speaker 111 via an amplifier (digital amplifier).

  The payout control board 500 mainly includes a payout CPU 501, a ROM 502, and a RAM 503. The payout control board 500 is connected to the main control board 200 so as to be capable of bidirectional communication, and is a control for driving the prize ball payout unit 134 based on a payout control command from the main control board 200 to payout prize balls. While executing, the ball feed mechanism 113 and the firing mechanism 114 are synchronously driven based on the operation amount of the firing handle 112 to control the firing of the game ball.

  Although not shown in detail, the power supply board 600 is a backup power supply and a normal power supply circuit for generating a normal power supply used in each control board based on the primary power supply supplied from the power supply facility of the game island. A power supply required for electronic / electrical parts such as control boards and amusement machines, which is configured to include a backup power supply circuit for generating To supply. A power switch for starting a power circuit is connected to the power board 600, and when the power switch is turned on, assuming that the primary power is supplied from the power supply device of the game island, the power board is turned on. Predetermined power is supplied to each control board or the like from the 600 normal power circuit. The power supply board 600 is configured to be able to detect that the power supply from the power supply device of the game island has been cut off, and at the time of detecting the power supply cutoff, a power cutoff signal (NMI signal) for notifying this is sent to the main control board 200. , To the effect control board 300 and the payout control board 500. The backup power supply circuit is configured to be charged when power is supplied to the pachinko gaming machine PM from the power supply device on the game island. A RAM clear switch (not shown) for temporarily erasing the temporarily stored contents of the RAM 203 of the main control board 200 and setting an initial value when the power of the pachinko gaming machine PM is turned on is connected to the power supply board 600. . The RAM clear switch may be connected to, for example, the main control board 200 instead of the power supply board 600.

<Production control of the lamp control circuit by the control board>
Next, the first special symbol display device 171, the second special symbol display device 172, the normal symbol display device 175, the first special symbol reservation lamp 173, the second special symbol reservation lamp 174, the general symbol reservation from the main control board 200. The lamp effect control of the lamp 176 will be described. The main control board 200 is provided with a main CPU 201, a ROM 202, and a RAM 203. The main CPU 201 operates software stored in the ROM 202, and based on the gaming state of the gaming machine, the first special symbol display device 171. In order to control the light emission brightness of the LED of each of the second special symbol display device 172, the ordinary symbol display device 175, the first special symbol holding lamp 173, the second special symbol holding lamp 174, and the general symbol holding lamp 176. The effect control contents of the 1st special symbol display device 171, the 2nd special symbol display device 172, the normal symbol display device 175, the 1st special figure reservation lamp 173, the 2nd special figure reservation lamp 174, the general figure reservation lamp The effect control information is transmitted to each LED control circuit of 176.

  Each of the first special symbol display device 171, the second special symbol display device 172, the normal symbol display device 175, the first special symbol holding lamp 173, the second special symbol holding lamp 174, the general symbol holding lamp 176 is a lamp display portion ( (Effect display member) and an LED provided on the back side of the LED lamp, and an LED control circuit is provided for each LED lamp. As the LEDs, there are a monochromatic LED that emits a single color or a color LED that is composed of LED elements of three primary colors. The first special figure holding lamp 173, the second special figure holding lamp 174, and the general figure holding lamp 176 have respective sizes. Depending on the type, one or more LEDs are used. The single-color LEDs include red LEDs, green LEDs, and blue LEDs, and perform emission control of light emission to perform effect control in which the brightness changes. The main control board 200 determines the content of the effect control of each LED lamp, and as the effect control information, the first special symbol display device 171, the second special symbol display device 172, the normal symbol display device 175, the first special symbol hold lamp. 173, the second special figure holding lamp 174, and the universal figure holding lamp 176, and each of these devices controls the light emission brightness of the LEDs constituting the display lamp of each device based on the performance control information from the main control board 200. To do. In FIG. 19, each of the first special symbol display device 171, the second special symbol display device 172, the normal symbol display device 175, the first special symbol holding lamp 173, the second special symbol holding lamp 174, the general symbol holding lamp 176, respectively. Although shown as a single device. A large number of LEDs are used in each of these devices, and in order to control the emission brightness of these devices, a plurality of LED control circuits are provided in positions corresponding to the display lamps in each of these devices. There is.

  Further, lamp effect control of the lamp connection board 191 and the effect lamp LP from the effect control board 300 will be described. The LED control circuit is arranged on the lamp control board 191, the main control board 200 determines the effect control content according to the gaming state of the gaming machine, and the effect control command is transmitted to the effect control board 300. The effect control board 300 creates effect control information for controlling the emission brightness of the LED based on the effect control command received from the main control board 200. The effect control board 300 transmits effect control information to the lamp connection board 191 which is an LED control circuit, and the lamp connection board 191 controls the emission brightness of the effect lamp LP. Here, the effect lamp LP is an LED lamp, and a plurality of single color LEDs or a plurality of three primary color LEDs are used. By controlling the emission brightness of the single-color LED, it is possible to perform effect control in which the brightness of white of the single-color LED lamp changes. When the three primary color LEDs are used, various effect control can be performed by periodically changing the light emission brightness values of the red LED, the green LED, and the blue LED to perform the light emission brightness control. In addition, the effect lamps LP are arranged separately at various positions around the center decoration 121 as described with reference to FIG. For this reason, it is preferable that the lamp connection board 191 is composed of a plurality of LED control circuits and is arranged in the vicinity of each of the LEDs forming the effect lamp LP.

<Control board connection interface>
Information indicating the gaming state of the gaming machine is stored in the RAM 203, and the software operating on the main CPU 201 is triggered by the information indicating the gaming state of these gaming machines, the first special symbol display device 171 to be controlled, The production control information of the second special symbol display device 172, the normal symbol display device 175, the first special symbol reservation lamp 173, the second special symbol reservation lamp 174, the general symbol reservation lamp 176 is read from the ROM 202. On the main control board 200, the main CPU 201, the ROM 202, and the RAM 203 are generally connected by an 8-bit parallel bus. As will be described later, the main control board 200 and the peripheral circuits are connected by a serial interface instead of an 8-bit parallel bus. The main control board 200 is provided with an I / O port circuit 204 for converting an 8-bit parallel bus interface into a serial interface, and the main control board 200 and peripheral circuits are connected using a serial interface. In an 8-bit parallel bus interface, an 8-bit signal is transmitted / received simultaneously using 8 signal lines at the time of 1 clock signal, but in a serial interface, 1 signal line is sent at the time of 1 clock signal. A 1-bit signal is transmitted, and an 8-bit signal is transmitted / received in the time of 8 clock signals. The effect control information read from the ROM 202 via the 8-bit parallel bus is converted into a data signal of a serial interface, and each LED control circuit (first special symbol display device 171, second special symbol display device 172, ordinary) It is transmitted to the symbol display device 175, the first special figure reservation lamp 173, the second special figure reservation lamp 174, the general figure reservation lamp 176).

  When the software operating on the main CPU 201 determines the effect contents of the effect lamp LP, the main control board 200 transmits the effect command to the effect control board 300 via the 8-bit parallel bus. On the effect control board 300, a sub-main CPU 301 that mainly performs various kinds of arithmetic processing related to effect management, a ROM 302 that is a read-only storage device that stores a control program, and a storage device that can write and read information. The RAM 303 is provided, and each drive circuit operates in accordance with the control program stored in the ROM 302 to perform control related to management of image effects and sound effects, control related to LED lamp effects, and the like. ing. The effect control information on the LED lamp effect is converted from the ROM 302 connected to the 8-bit parallel bus into a signal of the serial interface by the I / O port circuit 304 in the effect control board 300, and transmitted to the lamp control board 191. Since the main control board 200 and the effect control board 300 are not limited to 8-bit parallel connection as described above, the main control board 200 transmits the effect command to the effect control board 300 via the 3-wire serial interface. May be.

  An 8-bit parallel bus corresponding to the number of input / output processing bits of the CPU is used between the CPU and the ROM / RAM on the main control board 200 and the effect control board 300. However, if various kinds of information are transmitted and received between the control circuit board on which the CPU is mounted and the peripheral circuits while keeping the 8-bit parallel bus, a huge number of interface lines are required. Therefore, as described in the slot machine according to the first embodiment, in the main control board 200 and the effect control board 300, various control information is transmitted from the control board to the peripheral circuits by being converted into a serial interface. . As the serial interface, an I2C bus and a 3-wire serial interface are standardized as standard serial interfaces. In the following description of this embodiment, a three-wire serial interface will be used. However, the present embodiment is not limited to the 3-wire serial interface, and an I2C bus may be used. A serial interface other than the 3-wire serial interface or the I2C bus may be used.

  In the following description of the present embodiment, the main control board 200 (main CPU 201) performs the lottery by the software stored in the ROM 202, and the effect control board 300 (sub-main CPU 301) performs the lottery result by the software stored in the ROM 302. Although the effect control information is determined based on, the main control board 200 (main CPU 201) and the effect control board 300 (sub-main CPU 301) are simply referred to as "control device" in the following description. The first special symbol display device 171, the second special symbol display device 172, the normal symbol display device 175, the first special symbol holding lamp 173, the second special symbol holding lamp 174, the universal symbol holding lamp 176 constitutes respective LED lamps. An LED control circuit is provided for controlling the emission brightness of the LED element. The lamp connection board 191 is an LED control circuit, and these are collectively referred to as an “LED control circuit”. Moreover, the first special symbol display device 171, the second special symbol display device 172, the normal symbol display device 175, the first special symbol holding lamp 173, the second special symbol holding lamp 174, the general symbol holding lamp 176, the production lamp LP. Each LED lamp is composed of a plurality of LED elements, and these LED elements are simply referred to as “LED” in the following description. The main control board 200 and the main CPU 201 and the sub-main CPU 301 of the effect control board 300 are simply referred to as “CPU”.

  As can be seen from the above description, in the present embodiment, the effect control information is transmitted from the control device to the LED control circuit via the 3-wire serial interface.

<Connecting interface between control device and LED control circuit>
Similar to the first embodiment, also in the present embodiment, a large number of display and effect LEDs are attached to the gaming machine. Hundreds of LEDs are used in the game machine, and the number of LED control circuits is tens to hundreds or more. Conventionally, the connection between the control device and each LED control circuit, or the connection between a plurality of LED control circuits has been performed using a standard serial interface such as an I2C serial interface or a three-wire serial interface.

  Similar to the first embodiment, if all of a large number of LED control circuits are directly connected to the control device by using the 3-wire serial interface, the control device requires a huge number of 3-wire serial interface connection lines. Therefore, one or several LED control circuits are directly connected to the control device as the first-stage LED control circuit, and the remaining LED control circuits are sequentially connected. For example, the second-stage LED control circuit is connected to the first-stage LED control circuit, and the third-stage LED control circuit is connected to the second-stage LED control circuit. Is. With such a connection configuration, it is possible to reduce the number of connection lines of the 3-wire serial interface provided in the control device.

A three-wire serial interface, which is a standard serial interface, is used to connect the control device and peripheral circuits. As can be seen from the description in the first embodiment, the connection between the control device and the peripheral circuits, that is, the connection between the main control board 200 and various peripheral circuits illustrated in FIG. 19, the effect control board 300 and various peripheral circuits. There are two types of LED control circuits that are connected to the LED control circuit, that is, the LED control circuit in the first stage and the LED control circuits in the second and subsequent stages. Specifically, a three-wire serial interface is used to connect the LED control circuit in the first stage and the control device, and the LED control circuits in the second and subsequent stages are connected to the LED control circuit from the outside from the outside. It uses an LVDS interface that is less susceptible to induced noise.

  At this time, as in the first embodiment, the control circuit LC shown in FIG. 3 is used for all of the LED control circuits in the first stage and the LED control circuits in the second and subsequent stages. As described above, the LED control circuit LC shown in FIG. 3 can receive both the signal of the three-wire serial interface and the signal of the LVDS interface from the input terminal, and the received signal is output as the signal of the LVDS interface. Since it is output from, such a use is possible.

  Specifically, as shown in FIG. 17, a first special symbol display device 171, a second special symbol display device 172, a normal symbol display device 175, a first special symbol holding lamp 173, a second special symbol holding lamp 174, The universal figure holding lamp 176, the effect lamp LP, and the prize lamps 181 to 183 constituting the effect lamp LP, the board lamp 180 including the prize notification lamp 184, and the frame lamp 110 are arranged in the gaming machine, respectively. Correspondingly, a plurality of LED control circuits LC are provided. These LED control circuits are multi-connected and cascade-connected as shown in FIGS.

  The large number of LED controls used for each lamp by these LED control circuits and the contents described with reference to FIGS. 7 to 16 are the same for the pachinko machine, and therefore the description thereof will be omitted to avoid duplication.

The effects of the first and second embodiments described above will be described.
<First effect of the present embodiment>
According to the present embodiment, the sub-control means (sub-main CPU) can transmit effect control information to a plurality of effect output control means (LED control circuits) by a signal of the first communication mode (3-line serial interface). The production output control means (LED control circuit) switches between the first input means for receiving the signal of the first communication form and the second input means for receiving the signal of the second communication form (LVDS interface). Is configured. Therefore, the production output control means (LED control circuit LC) having the same configuration can be operated as the production output control means (LED control circuit LC1) in the first stage, and the production output control means (LED control circuit in the second and subsequent stages). LC2, LC3, etc.) and can be arranged at various positions in the gaming machine. It is possible to obtain an effect that communication can be performed with a signal having a communication mode suitable for each installation position.

  The effect control information preferably includes, for a plurality of LEDs, light emission brightness value information that controls the LEDs with a plurality of light emission brightness values. The effect output control means (LED control circuit LC) can perform various effect controls based on the light emission luminance value information in a plurality of stages, and an effect that it is possible to perform control that enhances the entertainment of the gaming machine can be obtained.

  It is preferable that the performance control information includes address information for designating the performance output control means (LED control circuit LC) and light emission luminance value information of a plurality of LEDs. The effect that the effect control information for controlling the emission brightness of the LED can be transmitted to the effect output control means (LED control circuit) not directly connected to the sub control means (sub main CPU) is also obtained.

  The second form of communication is preferably an LVDS interface. Even if a source of induction noise exists in the gaming machine, the induction output affects the production output control means (LED control circuit LC) arranged at various positions in the gaming machine from the sub-control means. It is possible to obtain the effect that it is possible to transmit the production control information without the need.

<Second effect of the present embodiment>
According to the present embodiment, the effect output control means (LED control circuit LC) receives the signal of the first communication form (3-wire serial interface) and converts it into the signal of the second communication form (LVDS interface). The first effect output control means (LED control circuit LC1) that outputs as a result, or the second output mode that receives the signal of the second communication form and shapes the received input waveform and outputs the signal of the second communication form. Of the production output control means (LED control circuits LC2, LC3, etc.). The sub-control means (sub-main CPU) is designed to be connected to another device by using the first communication mode. However, the sub-control means of the second communication mode, which is resistant to induced noise, is used while using the conventional sub-control means. Since the production output control unit (LED control circuit) using the signal is connected by using the waveform-shaped signal, the signal waveform is weakened even if the number of connection stages of the production output control unit (LED control circuit) is increased. Alternatively, the effect that the signal waveform is not disturbed can be obtained.

  For shaping the input waveform, it is preferable that the effect control information of the data signal is received in synchronization with the clock signal of the input terminal, and the effect control information of the data signal is transmitted in synchronization with the clock signal of the output terminal. Even if the number of connection stages from the first stage effect output control means (LED control circuit LC1) to the final stage effect output control means (LED control circuit LC) increases, the lower order effect output control means (LED control circuit LC). The effect that it is possible to transmit a signal whose waveform has been nicely shaped is obtained.

<Third effect of this embodiment>
According to the present embodiment, the effect output control means (LED control circuit LC) that receives the effect control information from the sub control means (sub main CPU) of the gaming machine receives the signal of the communication form of the signal of the 3-wire serial interface. Then, it is preferable to have a bridge function for converting into a signal of the communication form of the LVDS interface and transmitting it to the lower-order effect output control means (LED control circuit LC). There is an effect that it is possible to use the conventional sub-control means for communicating with the peripheral circuit by the communication form of the three-wire serial interface as it is and connect it to the production output control means (LED control circuit).

  The header condition is sent from the output terminal of the LVDS interface based on the change of the enable signal of the 3-wire serial interface of the input terminal, the data signal is latched at the rising edge timing of the clock signal of the 3-wire serial interface, and the latched data It is preferable to transmit the signal as a stable data signal at the timing of the rising edge of the clock signal at the output terminal. The conventional auxiliary control means for communicating with peripheral circuits can be used as it is by the communication form of the 3-wire serial interface, and the production output control means (LED control circuit) can be connected by communication using the LVDS interface that is strong against inductive noise. The effect of being is obtained.

<Fourth effect of this embodiment>
According to the present embodiment, the effect output control means (LED control circuit LC) has M drive terminals for controlling a plurality of effect parts, and the output start timing of each of the M drive terminals is set to another drive. It is different from the output start timing from the pin. If all LEDs are driven and controlled from the M drive terminals at the same timing, it becomes a noise source that generates switching noise in other circuits and adversely affects other circuits, but the output start timing of the M drive terminals is different. As a result, the effect of reducing the occurrence of switching noise can be obtained.

  The effect control information transmitted from the sub-control means (sub-main CPU) to the effect output control means (LED control circuit LC) includes the setting information of the PWM phase control mode, and the individual control or the group control is performed depending on the setting information. It preferably works. The production output control means (LED control circuit LC) operates by individual control that does not adversely affect other circuits, or by controlling the emission brightness of three drive terminals as one group, as compared with the case of individual control. As a result, the effect of controlling the light emission brightness with triple the light emission brightness can be obtained.

  Both the individual control and the group control are preferably output from the drive terminal at a start timing deviated by a fixed delay time. The effect that the switching noise can be reduced can be obtained without using particularly complicated means.

<Fifth effect of this embodiment>
According to the present embodiment, the effect output control means (LED control circuit LC) receives the initialization signal of the first communication mode (3-wire serial interface) or the second communication mode (LVDS interface), and the lower-order effect. The initialization signal of the second communication form is transmitted to the output control means (LED control circuit LC). Therefore, if the sub-control means (sub-main CPU) sends an initialization signal to the production output control means (LED control circuit LC) directly connected to the sub-control means, all production output control means (LEDs in the gaming machine). The effect that the initialization signal can be transmitted to the control circuit LC) is obtained.

Upon receiving the initialization signal, the effect output control means (LED control circuit LC) initializes the register. The game machine powers on the game machine every day, but the effect control information of the previous day may be stored in the effect output control means (LED control circuit LC). It is possible to initialize all the subordinate production output control means (LED control circuits) by a simple means of transmitting an initialization signal from the sub control means to the first stage production output control means (LED control circuit). The effect that it becomes possible is obtained.

  The production output control means (LED control circuit LC) receives the first initialization signal or the second initialization signal of the first communication mode, and the first initialization signal is an enable signal which is an active low signal. Preferably. By using a simple initialization signal, the sub-control means has the effect of being able to initialize the lower-order effect output control means (LED control circuit LC).

It is preferable that the sub control means transmits the second initialization signal whose 8-bit data value is a data signal of only 1 byte of the high signal. Although the above-mentioned first initialization signal may erroneously receive the induced noise from another device as the first initialization signal, the use of this second initialization signal causes induction noise from another device. It is possible to obtain an effect that it is unlikely that noise is erroneously received as the second initialization signal.

  In the above-described embodiment, the slot machine and the pachinko game machine are illustrated and described as an example of the game machine to which the present invention is applied, but the invention is not limited to this, and for example, an arrangement ball and a sparrow ball game. The same effects can be obtained by applying the same to machines and the like. In the description of the present embodiment, the signals of the three-wire serial interface and the LVDS interface are described using the high signal and the low signal, but the present invention is not limited to the description of the present embodiment. The high signal may be changed to a low signal and the low signal may be changed to a high signal.

1 slot machine 18 lamp control circuit 47 display lamp control circuit 60 main control board 68 interface circuit 70 sub control board 74 interface circuit 191 lamp connection board 200 main control board 300 production control board A5-A0 address designation terminal CD controller DCI1 difference Dynamic clock signal input terminal DCI2 Differential clock signal input terminal DCO1 Differential clock signal output terminal DCO2 Differential clock signal output terminal DDI1 Differential data signal input terminal DDI2 Differential data signal input terminal DDO1 Differential data signal output terminal DDO2 Differential Data signal output terminal LC production output control means (LED control circuit)
LOUT1 to LOUT24 LED drive terminal MODE mode specification terminal PM Pachinko game machine SCLK 3-wire serial interface clock signal input terminal SD 3-wire serial interface data signal input terminal SEN 3-wire serial interface enable signal input terminal

Claims (1)

In gaming machines that perform lottery by satisfying the lottery opportunity and can give profit based on the lottery result,
The gaming machine is
Main control means for transmitting a lottery result signal corresponding to the lottery result,
Sub control means for receiving the lottery result signal transmitted from the main control means to determine the content of the effect control, and transmitting an effect control signal corresponding to the determined content of the effect control in the first communication form,
The production control can be performed by receiving the production control signal of the first communication form transmitted from the sub control unit, and the production control signal is converted into the production control signal of the second communication form. A first effect control means capable of transmitting,
Second effect control means capable of performing the effect control by receiving the effect control signal transmitted in the second communication form from the first effect control means,
Equipped with
The first effect control means and the second effect control means,
First input means that is connected to an input unit for receiving the effect control signal and can receive the signal of the first communication mode;
Second input means connected to the input section and capable of receiving the signal of the second communication mode;
Third input means for switching and setting the operation of the first input means and the second input means,
Have
In the first effect control means, the third input means actuates the first input means to receive an effect control signal of the first communication form from the sub-control means,
In the second effect control means, the second input means is operated by the third input means to receive the effect control signal of the second communication form from the first effect control means. Composed,
The first effect control means and the second effect control means,
M (M is a positive integer) has a PWM phase control circuit for have a drive terminal of the pieces of the M capable of controlling the effect component,
The PWM phase control circuit has an individual control function capable of setting output start time timings of the M drive terminals with a fixed time difference from each other .

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