JP6680176B2 - Evaluation apparatus and semiconductor chip evaluation method - Google Patents

Description

  The present invention relates to an evaluation device and a semiconductor chip evaluation method.

  When evaluating the electrical characteristics of a semiconductor wafer, the mounting surface of the semiconductor wafer is fixed to the surface of the chuck stage by vacuum suction. In this state, a contact probe for inputting and outputting an electric signal is brought into contact with the non-installed surface of the semiconductor wafer for evaluation. Conventionally, the contact probe has been increased in number of pins to meet the demand for application of large current and high voltage.

Japanese Patent Laid-Open No. 61-127146

  In the evaluation involving application of a large current and a large voltage, the object to be measured may be damaged or defective due to a partial discharge phenomenon or the like. When the semiconductor wafer is damaged or defective, the individual semiconductor chips formed on the semiconductor wafer cannot be used in the subsequent steps. If the semiconductor wafer is damaged during the evaluation, the surface of the chuck stage may be roughened. In addition, a part of the damaged semiconductor wafer may adhere to or be embedded in the surface of the chuck stage. Defects on the chuck stage surface reduce the adhesion between the semiconductor wafer and the chuck stage. Further, a defect on the surface of the chuck stage may cause damage such as scratches or chips on the semiconductor wafer. At this time, the evaluation accuracy and the yield may be reduced. Therefore, it is important to properly protect the surface of the chuck stage.

  Patent Document 1 discloses a failure analysis jig capable of inspecting semiconductor chips separated from a semiconductor wafer by using an auto-prober for the semiconductor wafer. According to this method, a failure analysis jig is provided on the surface of the chuck stage. The semiconductor chip is evaluated in a state where the semiconductor chip is placed on the failure analysis jig. Therefore, the surface of the chuck stage is protected during evaluation. Further, since the semiconductor chips can be handled collectively, workability is improved.

  Here, Patent Document 1 does not disclose an evaluation method in which the temperature is variable. Further, in the failure analysis jig disclosed in Patent Document 1, it may be difficult to efficiently and accurately change the temperature of the semiconductor chip due to heat radiation from the front surface and the side surface. Further, it may be difficult to evaluate the temperature of the semiconductor chip to be stable and maintain a constant temperature. Further, the failure analysis jig of Patent Document 1 has a structure in which a vacuum pump is connected to one location on the lower surface of the jig to perform vacuum chucking. Therefore, it is difficult to divert the chuck stage for semiconductor wafers.

  The present invention has been made to solve the above problems, and an object of the present invention is to obtain an evaluation device and a semiconductor chip evaluation method that easily stabilize the temperature of a semiconductor chip.

Evaluation apparatus according to the present invention, a stage having a vacuum suction mechanism, a first surface is a surface opposite to the first surface and a second surface opposite to the stage, the first surface Is a test jig in which a plurality of first recesses capable of accommodating semiconductor chips are formed, and a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface is formed, and an upper portion of the test jig. a plurality of probes provided on, comprising a plurality of evaluation unit supplies a current to the probe, provided on said first surface, and a low thermal conductivity insulating section than the test fixture, the heat insulation parts are Ru provided between the pair of first recesses adjacent one of the first recess at least plurality of.
The evaluation apparatus according to the present invention has a stage having a vacuum suction mechanism, a first surface, and a second surface opposite to the first surface and facing the stage, and the first surface is provided on the first surface. Is a test jig in which a plurality of first recesses capable of accommodating semiconductor chips are formed, and a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface is formed, and an upper portion of the test jig. And a plurality of probes provided on the first surface, an evaluation unit that supplies a current to the plurality of probes, and a heat insulating unit that is provided on the first surface and has a thermal conductivity lower than that of the test jig. By forming the second concave portion on the first surface of the jig, a first heat insulating space surrounded by the test jig and the heat insulating portion is provided.
The evaluation apparatus according to the present invention has a stage having a vacuum suction mechanism, a first surface, and a second surface opposite to the first surface and facing the stage, and the first surface is provided on the first surface. Is a test jig in which a plurality of first recesses capable of accommodating semiconductor chips are formed, and a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface is formed, and an upper portion of the test jig. A plurality of probes provided on the first surface, an evaluation unit that supplies a current to the plurality of probes, and a heat insulating unit that is provided on the first surface and has a thermal conductivity lower than that of the test jig. By forming the third concave portion on the surface of the portion that contacts the test jig, the second heat insulating space surrounded by the test jig and the heat insulating portion is provided.
The evaluation apparatus according to the present invention has a stage having a vacuum suction mechanism, a first surface, and a second surface opposite to the first surface and facing the stage, and the first surface is provided on the first surface. Is a test jig in which a plurality of first recesses capable of accommodating semiconductor chips are formed, and a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface is formed, and an upper portion of the test jig. A plurality of probes provided on the first surface, an evaluation unit that supplies a current to the plurality of probes, and a heat insulating unit that is provided on the first surface and has a thermal conductivity lower than that of the test jig. The part includes a shielding part that covers at least one of the plurality of first recesses.
An evaluation apparatus according to the present invention has a stage having a vacuum suction mechanism, a first surface, and a second surface opposite to the first surface and facing the stage, and the first surface is provided on the first surface. Is a test jig in which a plurality of first recesses capable of accommodating semiconductor chips are formed, and a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface is formed, and an upper portion of the test jig. A plurality of probes provided on the first surface, an evaluation unit that supplies a current to the plurality of probes, and a heat insulating unit that is provided on the first surface and has a thermal conductivity lower than that of the test jig. The part is divided into a plurality of parts, and at least one of the plurality of parts is a shielding part that covers at least one of the plurality of first recesses.
The evaluation apparatus according to the present invention has a stage having a vacuum suction mechanism, a first surface, and a second surface opposite to the first surface and facing the stage, and the first surface is provided on the first surface. Is a test jig in which a plurality of first recesses capable of accommodating semiconductor chips are formed, and a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface is formed, and an upper portion of the test jig. A plurality of probes provided on the first surface, an evaluation unit that supplies a current to the plurality of probes, and a heat insulating unit that is provided on the first surface and has a thermal conductivity lower than that of the test jig. The suction mechanism includes a suction groove that connects the plurality of through-holes, and the suction groove is divided into a plurality of regions by a dividing wall.
The evaluation apparatus according to the present invention has a stage having a vacuum suction mechanism, a first surface, and a second surface opposite to the first surface and facing the stage, and the first surface is provided on the first surface. Is a test jig in which a plurality of first recesses capable of accommodating semiconductor chips are formed, and a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface is formed, and an upper portion of the test jig. A plurality of probes provided on the first surface, an evaluation unit that supplies a current to the plurality of probes, and a heat insulating unit that is provided on the first surface and has a thermal conductivity lower than that of the test jig. A heat insulating part having a lower thermal conductivity than the test jig, and a fourth recess is formed on a surface of the heat insulating part in contact with the heat insulating part. A third heat insulating space surrounded by the heat insulating portion is provided.

A method for evaluating a semiconductor chip according to the present invention has a first surface and a second surface opposite to the first surface, and the first surface has a first recess capable of accommodating a semiconductor chip. A plurality of heat insulating layers having a lower thermal conductivity than that of the test jig on the first surface of the test jig in which through holes extending from the bottom surface of each of the plurality of first recesses to the second surface are formed. A step of providing a portion, a step of arranging a semiconductor chip on at least one of the through holes of the plurality of first recesses, and a stage provided with a vacuum suction mechanism so that the stage and the second surface face each other. So as to arrange the test jig containing the semiconductor chip, an adsorption step of adsorbing the semiconductor chip from the through hole by the vacuum adsorption mechanism, and a temperature of the semiconductor chip after the adsorption step. The heat insulating section is provided after the temperature step of changing the temperature and the adsorption step. Comprising contacting a probe from the top of the test fixture to the semiconductor chip, later than said temperature step, in a state in which the probe and the semiconductor chip are in contact, and supplying a current to the probe, and the heat insulating unit, Ru provided between the pair of first recesses adjacent one of the first recess at least plurality of.

  In the evaluation device according to the present invention, a heat insulating portion having a lower thermal conductivity than that of the test jig is provided on the first surface of the test jig. Therefore, heat radiation from the test jig is suppressed, and the temperature of the semiconductor chip is easily stabilized.

  The semiconductor chip evaluation method according to the present invention includes a step of providing a heat insulating portion having a lower thermal conductivity than that of the test jig on the first surface of the test jig. Therefore, heat radiation from the test jig is suppressed, and the temperature of the semiconductor chip is easily stabilized.

FIG. 3 is a front view of the evaluation device according to the first embodiment. FIG. 3 is a plan view of a test jig and a heat insulating unit according to the first embodiment. FIG. 3 is a cross-sectional view of a test jig and a heat insulating unit according to the first embodiment. FIG. 3 is a plan view of a first recess according to the first embodiment. FIG. 3 is a cross-sectional view of a test jig and a heat insulating unit according to the first embodiment. FIG. 3 is a diagram illustrating a probe according to the first embodiment. FIG. 7 is a cross-sectional view of a test jig and a heat insulating section according to a first modified example of the first embodiment. FIG. 8 is a cross-sectional view perpendicular to the y-axis of a test jig according to a second modified example of the first embodiment. FIG. 9 is a cross-sectional view perpendicular to the x axis of a test jig according to a second modification of the first embodiment. FIG. 8 is a cross-sectional view of a test jig and a heat insulating section according to a third modification of the first embodiment. FIG. 9 is a cross-sectional view of a test jig and a heat insulating section according to a fourth modification of the first embodiment. FIG. 11 is a cross-sectional view of a test jig and a heat insulating section according to a fifth modified example of the first embodiment. FIG. 6 is a cross-sectional view of a test jig and a heat insulating unit according to the second embodiment. FIG. 7 is a plan view of a test jig and a heat insulating portion according to the third embodiment. FIG. 9 is a cross-sectional view of a test jig and a heat insulating section according to the third embodiment. FIG. 11 is a plan view of a stage according to the third embodiment. FIG. 16 is a cross-sectional view of a test jig and a heat insulating section according to a first modification of the third embodiment. FIG. 16 is a cross-sectional view of a test jig and a heat insulating section according to a second modification of the third embodiment. FIG. 9 is a plan view of a test jig and a heat insulating portion according to the fourth embodiment. FIG. 10 is a cross-sectional view perpendicular to the y axis of a test jig and a heat insulating unit according to the fourth embodiment. FIG. 11 is a cross-sectional view perpendicular to the x axis of a test jig and a heat insulating unit according to the fourth embodiment. It is sectional drawing of the test jig and heat insulation part which concern on Embodiment 5. FIG. 11 is a front view of a test jig and a heat insulating unit according to a fifth embodiment.

  An evaluation device and a semiconductor chip evaluation method according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1.
FIG. 1 is a front view of the evaluation device according to the first embodiment. The evaluation device 1 according to the present embodiment includes a stage 3. The stage 3 is a chuck stage equipped with a vacuum suction mechanism. A test jig 7 is provided on the stage 3. The stage 3 is a pedestal for fixing the test jig 7. The test jig 7 is fixed to the stage 3 by the vacuum suction mechanism. The test jig 7 accommodates semiconductor chips to be evaluated. A plurality of probes 10 are provided on the test jig 7. The plurality of probes 10 are connected to the insulating plate 16. One end of the signal line 6A is connected to the insulating plate 16 via the connecting portion 8A. The other end of the signal line 6A is connected to the evaluation unit 4.

  The evaluation unit 4 supplies a current to the plurality of probes 10. The evaluation unit 4 includes a control unit that controls the current passed through the semiconductor chip. The evaluation unit 4 applies a current to the semiconductor chip via the probe 10 and measures the electrical characteristics of the semiconductor chip. The upper surface of the stage 3 is in a plated state and has conductivity. The upper surface of the stage 3 becomes an electrode. This electrode is connected to one end of the signal line 6B via a connecting portion 8B provided on the side surface of the stage 3. The other end of the signal line 6B is connected to the evaluation unit 4.

  The probe 10 is supposed to apply a large current. Here, the large current is, for example, a current of 5 A or more. A plurality of probes 10 are provided for each semiconductor chip in order to pass a large current through the semiconductor chip. Each probe 10 and the signal line 6A are connected, for example, via a metal plate provided on the insulating plate 16 and the connecting portion 8A.

  Here, the wiring distance between the connection portion 8A and the connection portion 8B is set to be the same regardless of which probe 10 is used. This makes it possible to match the current densities flowing through the respective probes 10. It is desirable that the wiring distance from the probe 10 to the connecting portion 8A is equal to the wiring distance from the probe 10 to the connecting portion 8B.

  The probe base body 2 including the probe 10, the insulating plate 16, and the connecting portion 8A can be moved in any direction by the moving arm 9. In this embodiment, one moving arm 9 holds the probe base body 2. On the other hand, the probe base body 2 may be held by a plurality of moving arms 9. Thereby, the probe base 2 can be stably held. Alternatively, the stage 3 and the test jig 7 may be moved by using a moving mechanism provided separately.

  The stage 3 includes a temperature varying mechanism (not shown) inside. The temperature varying mechanism changes the temperature of the semiconductor chip housed in the test jig 7. The temperature variable mechanism includes, for example, a heater. The evaluation device 1 also includes a wafer transfer mechanism 17. The wafer transfer mechanism 17 is a mechanism for handling a semiconductor wafer.

  FIG. 2 is a plan view of the test jig and the heat insulating unit according to the first embodiment. FIG. 2 is a diagram showing a state in which the semiconductor chip is not stored in the test jig 7. A heat insulating portion 26 is provided on the test jig 7. The heat insulating section 26 has a lower thermal conductivity than the test jig 7. The test jig 7 is circular. The test jig 7 has the same shape as a general semiconductor wafer. Further, the heat insulating portion 26 is a circle having the same diameter as the test jig 7.

  FIG. 3 is a cross-sectional view of the test jig and the heat insulating unit according to the first embodiment. FIG. 3 is a sectional view obtained by cutting the test jig 7 and the heat insulating section 26 shown in FIG. 2 along the line I-II. The test jig 7 has a first surface 71 and a second surface 72 which is a surface opposite to the first surface 71. The second surface 72 is a surface facing the stage 3. The test jig 7 is installed on the stage 3 so that the second surface 72 and the upper surface of the stage 3 are in contact with each other.

  A plurality of first recesses 20 capable of accommodating semiconductor chips are formed on the first surface 71 of the test jig 7. A through hole 21 is provided on the bottom surface 24 of each of the plurality of first recesses 20. The through hole 21 extends from the bottom surface 24 to the second surface 72. A second recess 27 is formed on the first surface 71 of the test jig 7. By forming the second concave portion 27, the first heat insulating space 81 surrounded by the test jig 7 and the heat insulating portion 26 is provided. The first heat insulating space 81 is an air layer.

  A frame portion 22 is provided on the outer peripheral portion of the second surface 72 of the test jig 7. The stage 3 is a device for placing and picking up a semiconductor wafer. Semiconductor wafers are generally flexible. When the semiconductor wafer is vacuum-sucked, the semiconductor wafer is flexibly attached to the stage 3 so as to be fixed thereto. On the other hand, in the present embodiment, the test jig 7 is arranged on the stage 3. The test jig 7 is a thin metal plate. A metal thin plate is less likely to bend than a semiconductor wafer, and adsorption leakage may occur at the outer peripheral portion of the thin plate.

  The frame portion 22 is provided to prevent suction leakage between the test jig 7 and the stage 3. The frame portion 22 has flexibility. The frame 22 is a thin material. The frame 22 is preferably a sealing tape material such as Teflon (registered trademark), but is not limited to this.

  Next, the heat insulating unit 26 will be described. The heat insulating portion 26 is provided on the first surface 71 of the test jig 7. An opening 80 is formed in each of the plurality of first recesses in the heat insulating portion 26. The opening 80 is provided at a position overlapping the first recess 20. The width of the opening 80 is the same as the width of the first recess 20. At this time, the entire first recess 20 is exposed from the opening 80. The width of the opening 80 may be equal to or larger than the width of the first recess 20.

  The evaluation device 1 includes a detachable unit. The attachment / detachment portion fixes the test jig 7 and the heat insulating portion 26. In the present embodiment, the attachment / detachment portion includes the second convex portion 32. The second convex portion 32 is formed on the first surface 71 of the test jig 7. A hole 82 is formed on the surface of the heat insulating portion 26 that contacts the test jig 7. The second protrusion 32 fits into the hole 82. As shown in FIG. 2, two attachment / detachment portions are provided on the outer peripheral portion of the test jig 7 and the heat insulating portion 26.

  The heat insulating unit 26 and the test jig 7 can be attached and detached by the attaching and detaching unit. The second convex portion 32 provided on the test jig 7 may be provided by cutting or the like in the manufacturing process of the test jig 7. The structure of the attachment / detachment portion is not limited to this. The test jig 7 may be provided with a screw hole, the second convex portion 32 may be a component provided with a screw, and the second convex portion 32 may be fixed to the test jig 7 with a screw. In this case, the manufacturing time of the test jig 7 can be shortened.

  As a modified example of the attachment / detachment portion, the hole portion 82 may be formed on the first surface 71 of the test jig 7, and the second convex portion 32 may be formed on the surface of the heat insulating portion 26 in contact with the test jig 7. In the present embodiment, the entire first surface 71 excluding the first concave portion 20 and the second convex portion 32 is covered with the heat insulating portion 26.

  FIG. 4 is a plan view of the first recess according to the first embodiment. The through hole 21 is formed at a position displaced from the center of the bottom surface 24. FIG. 5 is a cross-sectional view obtained by cutting FIG. 4 along the line III-IV. Note that FIG. 5 shows a state in which the semiconductor chip 5 is installed in the first recess 20.

  The first recess 20 is a counterbore. The first recess 20 is composed of a bottom surface 24 and a side wall 25. The semiconductor chip 5 is positioned and installed on the bottom surface 24 of the first recess 20. The bottom surface 24 is preferably cleaned or polished to ensure a flat surface. As a result, the occurrence of burrs and protrusions is suppressed, and damage to the installation surface of the semiconductor chip 5 can be prevented.

  In the present embodiment, the semiconductor chip 5 is a semiconductor device having a vertical structure. In a semiconductor device having a vertical structure, a current flows in the vertical direction of the chip. That is, a current flows between the connection pad of the chip and the back surface electrode. At the time of evaluation, the connection pad of the semiconductor chip 5 and the probe 10 come into contact with each other. Further, the back surface electrode of the semiconductor chip 5 and the upper surface of the stage 3, which is an electrode, are in contact with each other via the test jig 7.

  The semiconductor chip 5, which is the object to be measured, is arranged on the through hole 21 of the first recess 20. The vacuum suction mechanism provided on the surface of the stage 3 communicates with the through hole 21, so that the semiconductor chip 5 is sucked through the through hole 21. As a result, the semiconductor chip 5 comes into close contact with the bottom surface 24 and is fixed. Further, the test jig 7 and the surface of the stage 3 are in close contact with each other. Since the semiconductor chip 5 and the bottom surface 24 are in close contact with each other, the electric resistance component between the semiconductor chip 5 and the stage 3 can be suppressed. Therefore, the measurement accuracy can be improved.

  In the present embodiment, through hole 21 is formed at a position close to one of the corners of bottom surface 24. The semiconductor chip 5 is arranged close to the corner close to the through hole 21 among the four corners of the bottom surface 24. As a result, the semiconductor chip 5 smaller than the size of the first recess 20 can be vacuum-sucked. Therefore, the test jig 7 can be used to evaluate the semiconductor chips 5 of various sizes.

  A groove 23 is formed on the outer periphery of the bottom surface 24 of the first recess 20. In the semiconductor chip 5 diced from a semiconductor wafer, foreign substances are often attached to the edges and the vicinity thereof. The groove portion 23 is a portion for accommodating a foreign matter. This can prevent foreign matter from entering between the installation surface of the semiconductor chip 5 and the bottom surface 24. Therefore, it is possible to reduce defects and defects due to the foreign matter such as damage to the chip due to the foreign matter and deterioration of accuracy of electrical characteristics.

  Moreover, the side wall 25 is inclined from the direction perpendicular to the bottom surface 24. As a result, the semiconductor chip 5 can be installed so as to slide the surface of the side wall 25 using the inclined side wall 25 as a guide. Therefore, the semiconductor chip 5 can be easily installed. In addition, when the semiconductor chip 5 is installed in the first recess 20, the impact that the semiconductor chip 5 receives can be reduced. Therefore, damage to the semiconductor chip 5 can be prevented especially when the semiconductor chip 5 is thin.

  The through hole 21 has a tapered structure in which the cross-sectional area increases as it approaches the second surface 72 of the test jig 7. The through hole 21 is connected to the vacuum suction mechanism of the stage 3. The large cross-sectional area of the through-hole 21 on the second surface 72 side facilitates alignment with the vacuum suction mechanism. Further, if the probe 10 contacts the semiconductor chip 5 in the upper part of the through hole 21, the semiconductor chip 5 may be damaged. In the present embodiment, the cross-sectional area of the through hole 21 is small on the bottom surface 24 side. Therefore, it is possible to reduce the possibility that the tip of the probe 10 and the position of the through hole 21 are aligned with each other. Therefore, the possibility of damage to the semiconductor chip 5 can be reduced.

  In the present embodiment, evaluation of the semiconductor chip 5 having a vertical structure is assumed. Therefore, electrical conduction between the semiconductor chip 5 and the stage 3 is necessary. Therefore, the test jig 7 is made of a metal material such as copper or aluminum. On the other hand, the semiconductor chip 5 may be a semiconductor device having a horizontal structure. A semiconductor device having a horizontal structure inputs and outputs current on the upper surface of the chip. In this case, the test jig 7 does not need conductivity. At this time, the test jig 7 may be formed of an insulating material such as a resin material.

  A method of manufacturing the test jig 7 will be described. In the test jig, a metal material is subjected to counterboring to form the first recess 20. Further, the through hole 21 is formed by machining. When the test jig 7 is made of a resin material, it can be manufactured by molding.

  FIG. 6 is a diagram for explaining the probe according to the first embodiment. The probe 10 includes a base mounting portion 14. The base mounting portion 14 is fixed to the insulating plate 16. The probe 10 also includes a tip 12. The tip portion 12 includes a contact portion 11 that contacts a connection pad 18 provided on the surface of the semiconductor chip 5. The connection pad 18 is an electrode of the semiconductor chip 5. The contact portion 11 is electrically connected to the connection pad 18. The tip portion 12 is attached to the tip of the pushing portion 13. A spring member such as a spring is incorporated inside the pushing portion 13. The spring member enables the pushing portion 13 and the tip portion 12 to slide when the contact portion 11 and the connection pad 18 come into contact with each other.

  An electrical connection portion 15 is electrically connected to the tip portion 12. The electrical connection portion 15 serves as an output end of the current to the outside and an input end from the outside. The probe 10 is formed of a conductive metal material such as copper, tungsten, or rhenium tungsten. The material of the probe 10 is not limited to these. The surface of the contact portion 11 may be coated with gold, palladium, tantalum, platinum or the like from the viewpoint of improving conductivity and durability.

  Next, the operation of the probe 10 will be described. From the initial state of FIG. 6A, the probe 10 is lowered toward the connection pad 18 along the z axis. As a result, the connection pad 18 and the contact portion 11 come into contact with each other as shown in FIG. Then, when the probe 10 is further lowered, as shown in FIG. 6C, the pushing portion 13 is pushed into the base body mounting portion 14 via the spring member. As a result, the connection pad 18 and the probe 10 are in strong contact with each other. As a result, stable contact between the connection pad 18 and the probe 10 is obtained.

  In the present embodiment, the probe 10 is of a spring type having slidability in the z-axis direction. The probe 10 is not limited to this, and may be a cantilever type probe. Further, the probe 10 may be a laminated probe or a wire probe. The laminated probe and the wire probe have slidability in the Z-axis direction.

  Next, a method for evaluating the semiconductor chip 5 according to this embodiment will be described. First, the semiconductor chip 5 is housed in the first recess 20. Here, the semiconductor chip 5 may not be housed in all the first recesses 20. The semiconductor chip 5 may be housed in at least one of the plurality of first recesses 20.

  In this embodiment, the through hole 21 is provided at a position close to the corner of the bottom surface 24. When the semiconductor chip 5 is stored in the first recess 20, the test jig 7 is tilted in the direction of the corner of the bottom surface 24 that is located near the through hole 21. In this state, the semiconductor chip 5 is arranged in the first recess 20 so that the semiconductor chip 5 is brought closer to the through hole 21 side. Thereby, even when the semiconductor chip 5 is smaller than the first recess 20, the semiconductor chip 5 can be arranged on the through hole 21.

  Next, the heat insulating section 26 is attached to the first surface 71 of the test jig 7. Here, the heat insulating portion 26 may be attached to the test jig 7 before the semiconductor chip 5 is arranged. Specifically, the second protrusion 32 is passed through the hole 82 to integrate the two. Next, the test jig 7 is set on the surface of the stage 3 using the wafer transfer mechanism 17. The test jig 7 is arranged so that the stage 3 and the second surface 72 face each other. At this time, the test jig 7 is arranged at a position where the through hole 21 and the vacuum suction mechanism of the stage 3 are connected.

  Next, an adsorption process is performed. In the suction step, the semiconductor chip 5 is sucked from the through hole 21 by the vacuum suction mechanism. As a result, the test jig 7 and the semiconductor chip 5 are fixed. Here, the first recess 20 in which the semiconductor chip 5 is not housed is not vacuum-adsorbed. The first recess 20 for adsorbing the semiconductor chip 5 is selected on the stage 3 side.

  Next, a temperature process is implemented. In the temperature step, the stage 3 is heated to the evaluation temperature. As a result, the temperature of the semiconductor chip 5 is changed to the evaluation temperature. Here, the temperature is raised by the temperature varying mechanism provided in the stage 3. Further, the temperature of the semiconductor chip 5 may be changed by an external temperature changing mechanism. Further, the temperature varying mechanism may lower the temperature of the semiconductor chip 5.

  Next, the probe 10 is lowered from the upper part of the test jig 7. As a result, the connection pad 18 of the semiconductor chip 5 and the probe 10 come into contact with each other. In this state, a current is supplied to the probe 10 to evaluate the electric characteristics. After the evaluation is completed, the probe 10 is separated from the connection pad 18. Next, the probe 10 is moved to the upper part of another semiconductor chip 5, and the probe 10 is lowered so as to come into contact with the connection pad 18 again.

  When all the semiconductor chips 5 installed on the test jig 7 have been evaluated, the test jig 7 is removed from the stage 3 by using the wafer transfer mechanism 17. Next, another test jig 7 accommodating the semiconductor chip 5 to be evaluated next is placed on the stage 3.

  The outer shape of the test jig 7 according to the present embodiment has the same shape as a general semiconductor wafer, and is circular in a plan view. Therefore, the test jig 7 can be transferred to the stage 3 by using the wafer transfer mechanism 17. Further, the stage 3 for semiconductor wafer can be used. In the present embodiment, since the device for semiconductor wafer can be used, it is not necessary to prepare the transfer device for semiconductor chip 5 and the chuck stage. Therefore, the cost can be reduced. Furthermore, since a plurality of semiconductor chips 5 can be transported at once, the preparation time for evaluation can be shortened.

  The size of the test jig 7 differs depending on the size of the semiconductor wafer to which the wafer transfer mechanism 17 and the stage 3 correspond. As shown in FIG. 2, the test jig 7 according to the present embodiment includes 32 first recesses 20, but the number of the first recesses 20 is not limited to this. The number of the first recesses 20 may be increased or decreased depending on the size of the test jig 7.

  In the present embodiment, the first surface 71 of the test jig 7 is covered with the heat insulating section 26. The heat insulating portion 26 has a higher heat insulating property than the test jig 7. That is, the heat insulating section 26 has a lower thermal conductivity than the test jig 7. As the heat insulating portion 26, for example, a ceramic plate such as alumina or mullite can be used. The material of the heat insulating portion 26 is not limited to this, and any material having a higher heat insulating property than the test jig 7 may be used.

  Thereby, in the evaluation in which the temperature of the semiconductor chip 5 is changed, heat radiation from the first surface 71 of the test jig 7 is suppressed. Therefore, the temperature variation of the semiconductor chip 5 is suppressed, and the temperature of the semiconductor chip 5 is easily stabilized. Therefore, it becomes possible to easily and efficiently maintain the evaluation temperature. Moreover, the temperature of the semiconductor chip 5 can be changed in a short time. From the above, the power for changing the evaluation temperature and maintaining the temperature can be reduced. Further, the waiting time for changing and stabilizing the temperature can be reduced, so that the evaluation time can be shortened. Therefore, the evaluation can be performed at low cost.

  A second recess 27 is formed on the first surface 71 of the test jig 7. As a result, the first heat insulating space 81 is formed. By forming the first heat insulating space 81, the contact area between the test jig 7 and the heat insulating portion 26 decreases. Further, an air layer having a high heat insulating property is formed between the test jig 7 and the heat insulating portion 26. Therefore, the heat transfer from the test jig 7 to the heat insulating section 26 can be suppressed by the first heat insulating space 81. Therefore, the heat radiation from the test jig 7 is further suppressed, and the temperature of the semiconductor chip 5 is easily stabilized.

  The second recess 27 can be formed in the step of forming the first recess 20 in the test jig 7. Therefore, there is no need to provide a new process for forming the second recess 27. Therefore, the second recess 27 can be formed at low cost.

  Further, since the test jig 7 is arranged on the stage 3, the surface of the stage 3 can be protected. As a result, it is possible to prevent the surface of the stage 3 from becoming rough and dirty due to the evaluation. Therefore, in the evaluation of the semiconductor wafer, it is possible to prevent the semiconductor wafer from being damaged when mounted on the stage 3. In addition, it is possible to suppress a decrease in adhesion between the semiconductor wafer and the stage. Therefore, it is possible to prevent a decrease in test accuracy.

  FIG. 7 is a cross-sectional view of a test jig and a heat insulating section according to a first modification of the first embodiment. The test jig 107 according to the first modification is different from the test jig 7 in the shape of the first recess 120. The structure other than this is the same as that of the test jig 7. A part of the sidewall 125 forming the first recess 120 on the first surface 71 side is inclined with respect to the direction perpendicular to the bottom surface 24. The second surface 72 side of the side wall 125 is perpendicular to the bottom surface 24.

  By reducing the inclined portion of the side wall 25, the processing time of the test jig 107 can be shortened. Thereby, the manufacturing cost of the test jig 107 can be reduced. Further, as compared with the case where the side wall does not have the inclined structure, the impact on the chip when the semiconductor chip 5 is installed can be suppressed. For example, the test jig 7 having a high effect of preventing damage is used for evaluating the thin semiconductor chip 5, and the test jig 107 having low manufacturing cost is used for the semiconductor chip 5 having large thickness. As a result, the effect of reducing the manufacturing cost and the effect of preventing damage to the semiconductor chip 5 can be efficiently obtained.

  FIG. 7 shows the structure of the vacuum suction mechanism provided on the stage 3. The vacuum suction mechanism includes a suction groove 30 and a suction hole 31. The suction groove 30 is a groove formed on the upper surface of the stage 3. The suction groove 30 is a groove extending in the xy plane in FIG. 7. The suction groove 30 connects the plurality of through holes 21. One end of the suction hole 31 is connected to the bottom surface of the suction groove 30. The suction holes 31 extend in the z-axis direction. A vacuum pump (not shown) is connected to the other end of the suction hole 31.

  As shown in FIG. 7, the through hole 21 is arranged on the suction groove 30. When the suction hole 31 is evacuated by the vacuum pump, the semiconductor chip 5 is sucked through the suction groove 30 and the through hole 21. The structure of the vacuum suction mechanism is the same for the evaluation device 1 according to the present embodiment.

  FIG. 8 is a cross-sectional view perpendicular to the y axis of the test jig according to the second modified example of the first embodiment. FIG. 9 is a cross-sectional view perpendicular to the x axis of the test jig according to the second modification of the first embodiment. The test jig 7 had one through hole 21 formed in one first recess 20. On the other hand, a plurality of through holes 21 may be formed in one first recess 20. In the test jig 207 according to the second modification, two through holes 221 are formed in one first recess 220. The number of through holes 221 formed in the first recess 220 may be three or more.

  The first recess 220 formed in the test jig 207 according to the second modification is larger than the semiconductor chip 5. The semiconductor chip 5 is housed in the first recess 220 while being brought close to the through hole 221 side. Thereby, even if the semiconductor chip 5 is smaller than the first recess 220, the semiconductor chip 5 can be arranged on the through hole 221. Therefore, the semiconductor chip 5 can be vacuum-sucked.

  The test jig 207 according to the second modification includes a connecting groove portion 229 on the second surface 72 of the test jig 207. The connection groove portion 229 is a groove extending in the xy plane. The connection groove portion 229 is connected to the two through holes 221. The connection groove portion 229 is connected to the suction groove 30 of the stage 3. In the present embodiment, a plurality of connecting groove portions 229 are formed in the test jig 207, and each connecting groove portion 229 and a plurality of through holes 221 are connected. Further, one connection groove portion 229 may be formed in the test jig 207, and all the through holes 221 and one connection groove portion 229 may be connected.

  In the second modification, the vacuum suction of the semiconductor chip 5 can be performed if any portion of the connection groove portion 229 is in contact with the suction groove 30. Therefore, the positions of the through hole 221 and the suction groove 30 do not have to match. Therefore, the degree of freedom of the position of the through hole 221 is improved. Therefore, the design of the test jig 207 becomes easy. Further, it becomes easy to use the stage 3 for semiconductor wafer.

  FIG. 10 is a cross-sectional view of a test jig and a heat insulating portion according to a third modification of the first embodiment. In the third modified example, the heat insulating portion 26 is provided on the first surface 71 of the test jig 7. Further, a laminated heat insulating section 226 is provided on the heat insulating section 26. The laminated heat insulating section 226 has a lower thermal conductivity than the test jig 7. An opening 280 is formed in the laminated heat insulating portion 226 at a position overlapping with each of the plurality of openings 80 provided in the heat insulating portion 26.

  In addition, the laminated heat insulating portion 226 is provided with a fourth recess 242 on a surface in contact with the heat insulating portion 26. By forming the fourth recess 242, the third heat insulating space 281 surrounded by the heat insulating portion 26 and the laminated heat insulating portion 226 is provided.

  In the third modification, a plurality of heat insulating parts are stacked and installed. The laminated heat insulating section 226 may be made of a material different from that of the heat insulating section 26. Further, the laminated heat insulating section 226 may be made of the same material as the heat insulating section 26. In the third modified example, the heat dissipation from the test jig 7 can be further suppressed by stacking the plurality of heat insulating parts. In addition, by using a heat insulating portion formed of an inexpensive material in combination, a heat insulating effect can be obtained at low cost.

  The third heat insulating space 281 is an air layer. By forming the third heat insulating space 281, the contact area between the heat insulating portion 26 and the laminated heat insulating portion 226 is reduced. Further, an air layer having a high heat insulating property is formed between the heat insulating portion 26 and the laminated heat insulating portion 226. The heat transfer from the heat insulating section 26 to the laminated heat insulating section 226 can be suppressed by the third heat insulating space 281. The fourth recess 242 may not be provided depending on the target heat insulating property. Further, three or more heat insulating parts may be laminated.

  FIG. 11 is a cross-sectional view of a test jig and a heat insulating section according to a fourth modification of the first embodiment. In the fourth modification, the heat insulating material 50 is provided in the second recess 27 formed in the test jig 7. The heat insulating material 50 is, for example, glass wool. As a result, heat transfer from the test jig 7 to the heat insulating section 26 can be further suppressed.

  FIG. 12 is a cross-sectional view of a test jig and a heat insulating section according to a fifth modification of the first embodiment. The heat insulating unit 26 according to the present embodiment has an opening 80 having the same size as the first recess 20 in a plan view, at a position overlapping the first recess 20. Here, the size of the opening 80 is not limited to this. An opening 380 is formed in the upper part of the semiconductor chip 5 in the heat insulating section 326 according to the fifth modified example. The opening 380 is formed at a position overlapping the semiconductor chip 5. The width of the opening 380 is the same as the width of the semiconductor chip 5.

  The width of the opening 380 may be equal to or larger than the width of the semiconductor chip 5. However, the width of the opening 380 is smaller than the width of the first recess 20. At this time, the heat insulating portion 326 has the eaves 351 protruding above the first recess 20. By reducing the size of the opening 380, heat dissipation from the surfaces of the test jig 7 and the semiconductor chip 5 can be further suppressed.

  These modifications can be appropriately applied to the evaluation device and the semiconductor chip evaluation method according to the following embodiments. Since the evaluation device and the semiconductor chip evaluation method according to the following embodiments have many common points with the first embodiment, the differences from the first embodiment will be mainly described.

Embodiment 2.
FIG. 13 is a cross-sectional view of the test jig and the heat insulating portion according to the second embodiment. In the heat insulating section 426 according to the present embodiment, an opening 480 is formed above the connection pad 18 which is an electrode included in the semiconductor chip 5. The opening 480 is formed at a position overlapping the connection pad 18. The width of the opening 480 is the same as the width of the connection pad 18.

  The width of the opening 480 may be equal to or larger than the width of the connection pad 18. However, the width of the opening 480 is smaller than the width of the semiconductor chip 5. At this time, the heat insulating portion 426 has the eaves 451 protruding above the first recess 20. The opening 480 of the heat insulating portion 426 according to the present embodiment is smaller than the opening 380 of the heat insulating portion 326. By reducing the size of the opening 480, the heat insulating property can be improved as compared with the heat insulating portion 326.

  If the portion of the semiconductor chip 5 that contacts the probe 10 is exposed from the heat insulating portion 426, the evaluation using the probe 10 can be performed. Therefore, the opening 480 may be formed in the upper portion of the connection pad 18 in contact with the probe 10. Further, the width of the opening 480 may be larger than the width of the probe 10.

  A method of evaluating the semiconductor chip 5 according to this embodiment will be described. In this embodiment, the width of the semiconductor chip 5 is larger than the width of the opening 480. Therefore, it is necessary to attach the heat insulating portion 426 to the test jig 7 after the semiconductor chip is stored in the first recess 20. The other points are the same as those in the first embodiment.

Embodiment 3.
FIG. 14 is a plan view of a test jig and a heat insulating unit according to the third embodiment. In this embodiment, the heat insulating section 526 is provided on the test jig 507. The heat insulating part 526 is divided into a plurality of parts. In this embodiment, the heat insulating section 526 is divided into four. The heat insulating portion 526 includes a first portion 561, a second portion 562, a third portion 563 and a fourth portion 564.

  Each of the first portion 561, the second portion 562, the third portion 563, and the fourth portion 564 has a hole 582 formed in the outer peripheral portion. The test jig 507 has a second protrusion 532 formed at a position overlapping the hole 582. The test jig 507 is formed with four second convex portions 532. Each of the second protrusions 532 fits into each of the holes 582. In the present embodiment, the attachment / detachment portion includes the hole portion 582 and the second convex portion 532. Each of the first portion 561, the second portion 562, the third portion 563, and the fourth portion 564 is fixed to the test jig 507 by the attachment / detachment portion. The structure of the test jig 507 other than the second convex portion 532 is the same as that of the test jig 7.

  A plurality of openings 580 are formed in each of the first portion 561, the second portion 562, and the fourth portion 564. The opening 580 is formed at a position overlapping the first recess 20 formed in the test jig 507. The shape of the opening 580 is similar to that of the opening 80. No opening is formed in the third portion 563. The third portion 563 is a shield that covers at least one of the plurality of first recesses 20. In the present embodiment, the eight first recesses 20 are covered by the third portion 563. In FIG. 14, for reference, the position of the first recess 20 covered by the third portion 563 is indicated by a broken line.

  FIG. 15 is a cross-sectional view of a test jig and a heat insulating unit according to the third embodiment. FIG. 15 is a cross-sectional view obtained by cutting the test jig 507 and the heat insulating portion 526 shown in FIG. 14 along the line V-VI.

  FIG. 16 is a plan view of the stage according to the third embodiment. In FIG. 16, the positions of the test jig 507, the first recess 20, and the through hole 21 are indicated by broken lines for reference. In the present embodiment, the first recess 20 shielded by the third portion 563 is not vacuumed. The area for vacuum suction is switched by the vacuum suction mechanism of the stage 3. The stage 3 according to the present embodiment includes suction grooves 30 that are connected to the through holes 21 formed in each first recess 20. The suction groove 30 extends like a mesh in the xy plane. One end of a plurality of suction holes 31 extending in the z-axis direction is connected to the suction groove 30. A vacuum pump (not shown) is connected to the other end of the suction hole 31.

  The suction groove 30 is divided into a plurality of regions by a dividing wall 34. For this reason, by switching the suction holes 31 that are evacuated by the vacuum pump, it is possible to select a region to be vacuum-sucked. A region separated by the vacuum suction suction hole 31 and the dividing wall 34 is not vacuum-sucked.

  At the time of evaluation, the semiconductor chip 5 may not be housed in a part of the plurality of first recesses 20. In the present embodiment, the first recess 20 that does not house the semiconductor chip 5 is covered by the shield. In the present embodiment, it is possible to suppress heat radiation from the first recess 20 that does not house the semiconductor chip 5. Further, by providing the shielding portion, the area covered by the heat insulating portion 526 increases. Therefore, heat radiation from the test jig 507 can be further suppressed. Therefore, it is easy to stabilize the temperature of the semiconductor chip 5. Moreover, power consumption for temperature adjustment can be suppressed.

  Further, the heat insulating section 526 is divided into a plurality of pieces. Therefore, if a part of the heat insulating portion 526 has a defect, only the defective part can be replaced. Therefore, the cost for maintaining the heat insulating unit 526 can be reduced. Although the heat insulating portion 526 is divided into four in the present embodiment, the heat insulating portion 526 may be divided into portions other than four.

  FIG. 17 is a cross-sectional view of a test jig and a heat insulating unit according to a first modification of the third embodiment. A heat insulating portion 626 is provided on the first surface 71 of the test jig 607 according to the first modification. The heat insulating portion 626 includes a third portion 663 that is a shielding portion. The third portion 663 includes a first convex portion 633. The first convex portion 633 projects toward the bottom surface 24 of the first concave portion 20. The first convex portion 633 closes the through hole 21 below the third portion.

  The heat insulating portion 626 according to the first modification blocks the through hole 21 below the shielding portion. Therefore, the first recess 20 in which the semiconductor chip 5 is not housed is not evacuated. Therefore, suction leakage in the area where the semiconductor chip 5 is not housed is prevented. At this time, the vacuum suction mechanism of the stage 3 does not have to switch the region for vacuum suction.

  Further, the heat insulating portion 626 has a third recess 628 formed on the surface in contact with the test jig 607. The test jig 607 does not include the second recess 27. By forming the third recess 628, a second heat insulating space 681 surrounded by the test jig 607 and the heat insulating portion 626 is provided. The second heat insulating space 681 is an air layer. By forming the second heat insulating space 681, the contact area between the test jig 607 and the heat insulating portion 626 is reduced. Further, an air layer having a high heat insulating property is formed between the test jig 607 and the heat insulating portion 626. The second heat insulating space 681 can suppress heat transfer from the test jig 607 to the heat insulating portion 626.

  The third recess 628 can be formed in the step of forming the opening 80 in the heat insulating portion 626. Therefore, there is no need to provide a new process for forming the third recess 628. Therefore, the third recess 628 can be formed at low cost.

  FIG. 18 is a cross-sectional view of a test jig and a heat insulating section according to a second modification of the third embodiment. In the second modification, the heat insulating material 50 is provided in the third recess 628 formed in the heat insulating portion 626. The heat insulating material 50 is, for example, glass wool. Thereby, the heat transfer from the test jig 607 to the heat insulating section 626 can be further suppressed.

  As another modification of the present embodiment, the heat insulating section 626 may be provided on the test jig 7. At this time, both the first heat insulating space 81 and the second heat insulating space 681 are formed between the test jig 7 and the heat insulating portion 626. Therefore, heat transfer from the test jig 7 to the heat insulating section 626 can be further suppressed. Further, when the heat insulating portion 626 is thin and it is difficult to form the third recess 628, the third recess 628 may be omitted and only the second recess 27 may be formed.

  Further, in the present embodiment, one part of the heat insulating part 626 divided into a plurality of parts is the shielding part. On the other hand, two or more portions may be shielding portions. In addition, in this embodiment, the heat insulating portion 626 is evenly divided. On the other hand, the heat insulating section 626 may not be divided evenly. Further, the shielding part may cover at least one of the plurality of first recesses 20. Further, the heat insulating section 626 may not be divided. In this case, a part of the heat insulating portion 626 serves as a shielding portion that covers at least one of the plurality of first recesses 20.

Fourth Embodiment
FIG. 19 is a plan view of a test jig and a heat insulating unit according to the fourth embodiment. The attachment / detachment unit according to the present embodiment includes a clamp unit 735. The clamp part 735 sandwiches the heat insulating part 726 and the test jig 707. In this embodiment, the heat insulating portion 726 is fixed to the test jig 707 by the clamp portion 735.

  The test jig 707 and the heat insulating portion 726 are provided with recesses 737 at the ends for inserting the clamp portions 735. The recesses 737 are provided at four places. By inserting the clamp part 735 into the recess 737, the clamp part 735 can be stored in the recess 737 when the heat insulating part 726 and the test jig 707 are sandwiched by the clamp part 735. Therefore, it is possible to prevent the clamp portion 735 from protruding from the side surface of the test jig 707.

  FIG. 20 is a cross-sectional view perpendicular to the y axis of the test jig and the heat insulating unit according to the fourth embodiment. FIG. 21 is a cross-sectional view perpendicular to the x axis of the test jig and the heat insulating unit according to the fourth embodiment. 20 is a cross-sectional view obtained by cutting the test jig 707 and the heat insulating portion 726 shown in FIG. 19 along the line VII-VIII. 21 is a cross-sectional view obtained by cutting the test jig 707 and the heat insulating section 726 shown in FIG. 19 along the line IX-X.

  A groove portion 736 is formed on the second surface 72 of the test jig 707. The lower portion of the clamp portion 735 is housed in the groove portion 736. Therefore, it is possible to prevent the clamp portion 735 from protruding from the second surface 72 of the test jig 707. Further, a groove portion 739 is formed on the upper surface of the heat insulating portion 726. The clamp part 735 has a protrusion 738 at the tip of the upper part. The protruding portion 738 fits into the groove portion 739. This can prevent the clamp portion 735 from being displaced and from coming off.

  Note that in FIG. 19, the right clamp portion 735 in FIG. 19 is omitted in order to clarify the structures of the groove portion 739 and the recess portion 737. In this embodiment, four clamp parts 735 are provided. On the other hand, the number of the clamp parts 735 may be increased or decreased according to the size of the test jig 707, for example. In this embodiment, the heat insulating portion 726 can be easily attached and detached by attaching and detaching the clamp portion 735.

  The clamp part 735 is formed of a metal material or a resin material. Further, in order to fit the protrusion 738 into the groove 739, the clamp 735 is made of a material that is not a rigid body. That is, the clamp part 735 is formed of a material having flexibility or spring properties. The thickness of the clamp portion 735 is about 1 mm. In addition, when fixing the heat insulation part 726 using the clamp part 735, the frame part 22 shall be installed avoiding the clamp part 735.

Embodiment 5.
FIG. 22 is a cross-sectional view of a test jig and a heat insulating section according to the fifth embodiment. A notch 841 is formed on the side surface of the test jig 807. The heat insulating section 826 includes an upper surface section 843 that covers the first surface 71 of the test jig 807. A side surface portion 844 that covers a side surface of the test jig 807 is provided at an end portion of the upper surface portion 843. The heat insulating unit 826 according to the present embodiment covers at least a part of the side surface of the test jig 807.

  Further, a claw portion 840 extending inside the cutout portion 841 is formed at the lower end of the side surface portion 844. The claw portion 840 fits into the cutout portion 841. By fitting the claw portion 840 and the cutout portion 841 into each other, the installation position of the heat insulating portion 826 can be determined. Further, the heat insulating portion 826 can be fixed to the test jig 807 by fitting the claw portion 840 and the cutout portion 841. The claw portion 840 allows the test jig 807 and the heat insulating portion 826 to be detachable. In the present embodiment, the attachment / detachment portion includes the claw portion 840.

  FIG. 23 is a front view of a test jig and a heat insulating unit according to the fifth embodiment. The heat insulating portion 826 is provided with a gap on both sides of the portion where the claw portion 840 is formed. This makes it easier to insert the claw portion 840 into the cutout portion 841. Therefore, the heat insulating portion 826 can be easily attached and detached.

  The cutout portion 841 is formed on the second surface 72 of the test jig 807 by cutting or the like. Since the claw portion 840 has a structure projecting inward, it is difficult to form the heat insulating portion 826 at the same time. For this reason, the claw portion 840 is attached by adhesion or fitting after the upper surface portion 843 and the side surface portion 844 are molded. Since the claw portion 840 fits into the cutout portion 841, stress is applied when the heat insulating portion 826 is attached and detached. Therefore, in consideration of durability, it is desirable to manufacture the metal material such as iron.

  In the present embodiment, the heat insulating section 826 covers at least a part of the side surface of the test jig 807. Therefore, heat radiation from the side surface of the test jig 807 can be suppressed. Note that the technical features described in the embodiments may be combined as appropriate.

1 Evaluation device, 3 stages, 71 1st surface, 72 2nd surface, 5 semiconductor chip, 20, 120, 220 1st recessed part, 24 bottom surface, 21, 221 through hole, 7, 107, 207, 507, 607, 707 , 807 test jig, 10 probe, 4 evaluation part, 26, 326, 426, 526, 626, 726, 826 heat insulating part, 80, 280, 380, 480, 580 opening, 351, 451 eaves, 27 second recess, 81 1st heat insulation space, 50 heat insulation material, 628 3rd recessed part, 681 2nd heat insulation space, 633 1st convex part, 82, 582 hole part, 32, 532 2nd convex part, 841 notch part, 840 claw part, 735 clamp part, 30 adsorption groove, 34 dividing wall, 22 frame part, 226 laminated heat insulating part, 242 fourth concave part, 281 third heat insulating space

Claims (25)

A stage equipped with a vacuum suction mechanism,
A first surface and a second surface opposite to the first surface and facing the stage, wherein the first surface has a plurality of first recesses capable of accommodating semiconductor chips, A test jig having a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface;
A plurality of probes provided on the upper part of the test jig,
An evaluation unit that supplies a current to the plurality of probes,
A heat insulating portion provided on the first surface and having a thermal conductivity lower than that of the test jig;
Equipped with
The heat insulating unit, evaluation unit, characterized in Rukoto provided between the pair of first recesses adjacent ones of at least the plurality of first recesses.   The evaluation device according to claim 1, wherein the heat insulating portion has an opening formed in an upper portion of an electrode included in the semiconductor chip, the opening having a width equal to or larger than a width of the electrode.   The evaluation unit according to claim 1 or 2, wherein the heat insulation part has an opening formed in an upper portion of the semiconductor chip, the opening having a width equal to or larger than a width of the semiconductor chip.   The said heat insulation part is formed with the opening whose width is more than the width | variety of the said 1st recessed part in at least 1 upper part of the said 1st recessed part, The any one of Claims 1-3 characterized by the above-mentioned. The evaluation device according to item.   The said heat insulation part has the eaves which protruded at least one upper part of the said several 1st recessed part, The evaluation apparatus in any one of Claims 1-3 characterized by the above-mentioned. The heat insulating unit, the evaluation device according to any one of claim 1 to 5, characterized in that formed in the ceramic plate. The heat insulating unit, the evaluation device according to any one of claim 1 to 6, characterized in that covers at least a portion of the side surface of the test fixture. Evaluation apparatus according to any one of claim 1 to 7, characterized in that it comprises a detachable part for fixing the heat insulating portion and the test fixture. The detachable part is
A hole formed on the surface of the heat insulating portion that contacts the test jig,
A second protrusion formed on the first surface of the test jig and fitted into the hole;
The evaluation device according to claim 8 , further comprising: The detachable part is
A second convex portion formed on a surface of the heat insulating portion in contact with the test jig;
A hole formed on the first surface of the test jig and fitted with the second convex portion;
The evaluation device according to claim 8 , further comprising: The test jig has a notch formed on the side surface,
The evaluation device according to claim 8 , wherein the attachment / detachment portion includes a claw portion that is formed in the heat insulating portion and that fits into the cutout portion. The evaluation device according to claim 8 , wherein the attachment / detachment portion includes a clamp portion that sandwiches the heat insulating portion and the test jig. The heat insulating unit, the evaluation device according to any one of claim 1 to 12, characterized in that it is divided into a plurality of portions. A frame portion provided on an outer peripheral portion of the second surface of the test jig;
Evaluation apparatus according to any one of claim 1 to 13, characterized in that with the frame portion flexibility. Wherein on the insulating section, the evaluation device according to any one of claim 1 to 14, characterized in that it comprises a low thermal conductivity laminated heat insulating portion than the test fixture.   A stage equipped with a vacuum suction mechanism,
  A first surface and a second surface opposite to the first surface and facing the stage, wherein the first surface has a plurality of first recesses capable of accommodating semiconductor chips, A test jig having a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface;
  A plurality of probes provided on the upper part of the test jig,
  An evaluation unit that supplies a current to the plurality of probes,
  A heat insulating portion provided on the first surface and having a thermal conductivity lower than that of the test jig;
  Equipped with
  An evaluation device characterized in that a second heat insulating space surrounded by the test jig and the heat insulating portion is provided by forming a second recess in the first surface of the test jig.   The evaluation device according to claim 16, wherein a heat insulating material is provided in the second recess.   A stage equipped with a vacuum suction mechanism,
  A first surface and a second surface opposite to the first surface and facing the stage, wherein the first surface has a plurality of first recesses capable of accommodating semiconductor chips, A test jig having a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface;
  A plurality of probes provided on the upper part of the test jig,
  An evaluation unit that supplies a current to the plurality of probes,
  A heat insulating portion provided on the first surface and having a thermal conductivity lower than that of the test jig;
  Equipped with
  An evaluation device characterized in that a second heat insulating space surrounded by the test jig and the heat insulating portion is provided by forming a third concave portion on a surface of the heat insulating portion in contact with the test jig.   The evaluation device according to claim 18, wherein a heat insulating material is provided in the third recess.   A stage equipped with a vacuum suction mechanism,
  A first surface and a second surface opposite to the first surface and facing the stage, wherein the first surface has a plurality of first recesses capable of accommodating semiconductor chips, A test jig having a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface;
  A plurality of probes provided on the upper part of the test jig,
  An evaluation unit that supplies a current to the plurality of probes,
  A heat insulating portion provided on the first surface and having a thermal conductivity lower than that of the test jig;
  Equipped with
  The said heat insulation part is equipped with the shielding part which covers at least 1 of the said several 1st recessed part, The evaluation apparatus characterized by the above-mentioned.   21. The evaluation device according to claim 20, wherein the shielding portion includes a first convex portion that closes the through hole below the shielding portion.   A stage equipped with a vacuum suction mechanism,
  A first surface and a second surface opposite to the first surface and facing the stage, wherein the first surface has a plurality of first recesses capable of accommodating semiconductor chips, A test jig having a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface;
  A plurality of probes provided on the upper part of the test jig,
  An evaluation unit that supplies a current to the plurality of probes,
  A heat insulating portion provided on the first surface and having a thermal conductivity lower than that of the test jig;
  Equipped with
  The heat insulation part is divided into a plurality of parts,
  At least one of the plurality of portions is a shielding portion that covers at least one of the plurality of first recesses.   A stage equipped with a vacuum suction mechanism,
  A first surface and a second surface opposite to the first surface and facing the stage, wherein the first surface has a plurality of first recesses capable of accommodating semiconductor chips, A test jig having a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface;
  A plurality of probes provided on the upper part of the test jig,
  An evaluation unit that supplies a current to the plurality of probes,
  A heat insulating portion provided on the first surface and having a thermal conductivity lower than that of the test jig;
  Equipped with
  The vacuum suction mechanism includes a suction groove connecting between the plurality of through holes,
  The evaluation device is characterized in that the suction groove is divided into a plurality of regions by dividing walls.   A stage equipped with a vacuum suction mechanism,
  A first surface and a second surface opposite to the first surface and facing the stage, wherein the first surface has a plurality of first recesses capable of accommodating semiconductor chips, A test jig having a through hole extending from the bottom surface of each of the plurality of first recesses to the second surface;
  A plurality of probes provided on the upper part of the test jig,
  An evaluation unit that supplies a current to the plurality of probes,
  A heat insulating portion provided on the first surface and having a thermal conductivity lower than that of the test jig;
  Equipped with
  On the heat insulating part, a laminated heat insulating part having a lower thermal conductivity than the test jig is provided,
  An evaluation device characterized in that a third heat insulating space surrounded by the heat insulating portion and the laminated heat insulating portion is provided by forming a fourth recess on a surface of the laminated heat insulating portion in contact with the heat insulating portion. It has a first surface and a second surface opposite to the first surface, and a plurality of first concave portions capable of accommodating semiconductor chips are formed on the first surface. Providing a heat insulating portion having a lower thermal conductivity than that of the test jig on the first surface of the test jig in which a through hole extending from each bottom surface to the second surface is formed.
Disposing a semiconductor chip on at least one of the through holes of the plurality of first recesses;
Disposing the test jig containing the semiconductor chip on a stage having a vacuum suction mechanism so that the stage and the second surface face each other;
A suction step of sucking the semiconductor chip from the through hole by the vacuum suction mechanism,
A temperature step of changing the temperature of the semiconductor chip after the adsorption step,
A step of bringing the probe into contact with the semiconductor chip from the upper part of the test jig provided with the heat insulating section after the adsorption step;
After the temperature step, in a state where the probe and the semiconductor chip are in contact with each other, a step of supplying a current to the probe,
Equipped with
The heat insulating unit, the evaluation method of a semiconductor chip according to claim Rukoto provided between the pair of first recesses adjacent ones of at least the plurality of first recesses.

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