JP6676468B2 - Imaging apparatus, operation method thereof, and electronic apparatus - Google Patents

Description

One embodiment of the present invention relates to an imaging device, an operation method thereof, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacturer, or a composition (composition of matter). Therefore, as a technical field of one embodiment of the present invention disclosed in this specification, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, a storage device, a driving method thereof, Manufacturing method can be mentioned as an example.

A display device has been proposed in which a transistor having a small leak current is used as a pixel transistor to reduce the frequency of rewriting image data (for example, Patent Document 1). In rewriting the image data, the image data of the difference detection frame and the image data of the reference frame are compared by digital processing using difference processing, and it is determined whether or not the image data needs to be rewritten based on the digital processing result. . By reducing the frequency at which image data is rewritten, power consumption of the display device is reduced.

U.S. Patent Application Publication No. 2011/0090204

In order to further reduce the power consumption of the imaging device, it is desired to further reduce the frequency of rewriting the imaging data. In addition, when the imaging data is stored in the storage device, the storage capacity can be reduced.

An object of one embodiment of the present invention is to provide a novel imaging device, a method for operating the novel imaging device, a novel electronic device, and the like.

Another object of one embodiment of the present invention is to provide an imaging device or the like with a novel structure which can reduce power consumption. Another object of one embodiment of the present invention is to provide an imaging device or the like having a novel structure that can determine whether image data needs to be rewritten while holding imaging data written to a pixel. Another object of one embodiment of the present invention is to provide an imaging device or the like having a novel structure in which the storage capacity of a storage device for storing imaging data can be saved.

Another object of one embodiment of the present invention is to provide a novel operation method of an imaging device or the like which can reduce power consumption. Another object of one embodiment of the present invention is to provide a novel operation method of an imaging device and the like which can determine whether image data needs to be rewritten while holding imaging data written to a pixel. . Another object of one embodiment of the present invention is to provide a novel operation method of an imaging device and the like which can save the storage capacity of a storage device for storing imaging data.

Note that the object of one embodiment of the present invention is not limited to the above objects. The tasks listed above do not disturb the existence of other tasks. The other issues are the issues described in the following description and not mentioned in this item. Problems not mentioned in this section can be derived from the description in the specification or the drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above-described descriptions and / or other problems.

One embodiment of the present invention includes a pixel, a first circuit, a second circuit, a third circuit, a fourth circuit, a fifth circuit, a sixth circuit, and a seventh circuit And an imaging device having: The pixels are arranged in a matrix to form a pixel array; the first circuit has a function of selecting a row of the pixel array; the second circuit has a function of selecting a column of the pixel array; Has a function of calculating the difference between the image data of the first frame and the image data of the second frame of the pixel selected by the first circuit and the second circuit. The fourth circuit has a function of outputting a row address of a pixel subjected to difference calculation, and the fifth circuit has a function of outputting a column address of a pixel subjected to difference calculation. Further, the sixth circuit has a function of storing a row address and a column address which define a designated pixel array area, and the seventh circuit has a function of storing the row address and the column address stored in the sixth circuit. It is characterized in that it has a function of comparing coordinates included in a defined area with coordinates composed of a row address and a column address of a pixel for which a difference has been detected.

In addition, the imaging device of one embodiment of the present invention provides the imaging device of the third frame in a case where the coordinates including the row address and the column address of the pixel whose difference has been detected are included in the area stored in the sixth circuit. It may have a function of acquiring imaging data and outputting the imaging data to an external device.

Further, in the imaging device of one embodiment of the present invention, two row addresses and two column addresses of the designated pixel array are stored in the sixth circuit to form four coordinates, and the row of the pixel in which the difference is detected is provided. When the coordinates composed of the address and the column address are included in the rectangle enclosed by the four coordinates stored in the sixth circuit, the imaging data of the third frame is obtained, and the imaging data is obtained. It may have a function of outputting to an external device.

In the imaging device of one embodiment of the present invention, a pixel may include a transistor and a photoelectric conversion element. In the transistor, the active layer includes an oxide semiconductor. The oxide semiconductor includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). And may be provided.

Further, the photoelectric conversion element may include selenium or a compound containing selenium in the photoelectric conversion layer.

The operation method of the imaging device is also one embodiment of the present invention. In the operation method, in a first step, image data of a first frame is obtained, in a second step, image data of the first frame is output to an external device, and in a third step, the image data of the first frame is obtained. It is determined whether or not to return to the first step, and if not to return to the first step, after acquiring the imaging data of the second frame, in the fourth step, the imaging data of the third frame is obtained. Is obtained, the difference calculation between the image data of the second frame and the image data of the third frame is performed for each pixel, and the row address and column address of the pixel subjected to the difference calculation are further calculated. Is calculated. If no difference is detected, the process returns to the fourth step. If a difference is detected in the fourth step, it is determined in a fifth step whether or not the imaging data is output to an external device. When the imaging data is not output to the external device, the process returns to the fourth step. When the imaging data is output to the external device, the imaging data of the fourth frame is obtained in the sixth step, and the seventh step is performed. After outputting the imaging data of the fourth frame to the external device in, the process returns to the fourth step.

In addition, in the operation method of the imaging device of one embodiment of the present invention, it is determined that no difference is detected by the difference calculation in the fourth step and / or that the imaging data is not output to the external device in the fifth step. In this case, the process may return to the fourth step after acquiring the imaging data of the second frame.

In addition, in the operation method of the imaging device of one embodiment of the present invention, a region of a pixel array formed by arranging a plurality of pixels is specified, and coordinates including a row address and a column address of a pixel where a difference is detected are displayed. When the image data is included in the area of the pixel array, the imaging data of the fourth frame may be obtained in the sixth step, and the imaging data may be output to the external device in the seventh step.

Further, in the operation method of the imaging device of one embodiment of the present invention, four coordinates are designated by designating two row addresses and two column addresses of the pixel array, and the inside of the rectangle surrounded by the four coordinates is specified. It may be a region of a pixel array.

The external device may be a display device and / or a storage device.

An electronic device including the imaging device of one embodiment of the present invention and a display device is also one embodiment of the present invention.

One embodiment of the present invention can provide a novel imaging device, a novel operation method of the imaging device, a novel electronic device, and the like.

Alternatively, one embodiment of the present invention can provide an imaging device or the like with a novel structure which can reduce power consumption. Alternatively, one embodiment of the present invention can provide an imaging device and the like with a novel structure which can determine whether image data needs to be rewritten while holding imaging data written to pixels. Alternatively, according to one embodiment of the present invention, an imaging device or the like with a novel structure which can save the storage capacity of a storage device for storing imaging data can be provided.

Alternatively, one embodiment of the present invention can provide a novel operation method of an imaging device or the like which can reduce power consumption. Alternatively, one embodiment of the present invention can provide a novel operation method of an imaging device and the like which can determine whether image data needs to be rewritten while holding imaging data written to pixels. Alternatively, one embodiment of the present invention can provide a novel operation method of an imaging device and the like in which the storage capacity of a storage device for storing imaging data can be saved.

Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not disturb the existence of other effects. The other effects are effects which will be described in the following description and which are not mentioned in this item. The effects not mentioned in this item can be derived from the description in the specification or the drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and / or other effects. Therefore, one embodiment of the present invention does not have the above-described effects in some cases.

FIG. 2 is a block diagram of an imaging device. FIG. 2 is a block diagram of an imaging device. 9 is a flowchart illustrating operation of an imaging device. FIG. 7 is a diagram for describing output determination of imaging data to an external device. FIG. 4 illustrates a pixel circuit of an imaging device. 6 is a timing chart illustrating an imaging operation. 6 is a timing chart illustrating an imaging operation. FIG. 4 illustrates a pixel circuit of an imaging device. FIG. 4 illustrates a pixel circuit of an imaging device. FIG. 4 illustrates a pixel circuit of an imaging device. FIG. 4 illustrates a pixel circuit of an imaging device. FIG. 4 illustrates a pixel circuit of an imaging device. FIG. 4 illustrates a pixel circuit of an imaging device. FIG. 4 is a diagram illustrating operations of a rolling shutter system and a global shutter system. FIG. 4 illustrates a pixel circuit of an imaging device. FIG. 4 illustrates a pixel circuit of an imaging device. FIG. 4 illustrates a difference detection circuit of an imaging device. 9 is a timing chart illustrating a difference detection operation of the imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. 4A and 4B are a cross-sectional view and a circuit diagram illustrating a configuration of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 2 is a cross-sectional view illustrating a structure of an imaging device. FIG. 4 illustrates a curved imaging device. FIG. 4 illustrates a pixel circuit of a display device. FIG. 4 illustrates a pixel circuit of a display device. 7A to 7C are a top view and cross-sectional views illustrating a transistor. 7A to 7C are a top view and cross-sectional views illustrating a transistor. FIG. 4 illustrates a cross section of a transistor in a channel width direction. 7A to 7C are a top view and cross-sectional views illustrating an oxide semiconductor layer. 7A to 7C are a top view and cross-sectional views illustrating a transistor. 7A to 7C are a top view and cross-sectional views illustrating a transistor. FIG. 4 illustrates a cross section of a transistor in a channel width direction. FIG. 4 illustrates a cross section of a transistor in a channel length direction. FIG. 4 illustrates a cross section of a transistor in a channel length direction. 7A to 7C are a top view and cross-sectional views illustrating a transistor. FIG. 13 is a top view illustrating a transistor. 6A and 6B illustrate a structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD, and a diagram illustrating a selected-area electron diffraction pattern of the CAAC-OS. 14A and 14B are a cross-sectional TEM image, a planar TEM image, and an image analysis image of the CAAC-OS. 4A and 4B illustrate an electron diffraction pattern of an nc-OS and a cross-sectional TEM image of the nc-OS. 14 is a cross-sectional TEM image of an a-like OS. 7A and 7B each show a change in a crystal part of an In-Ga-Zn oxide due to electron irradiation. 2A and 2B are a perspective view and a cross-sectional view of a package containing an imaging device. 2A and 2B are a perspective view and a cross-sectional view of a package containing an imaging device. FIG. 2 illustrates a configuration of a monitoring device. The figure explaining the use of a monitoring device. 7A to 7C illustrate electronic devices. FIG. 4 is a view for explaining a measurement result of an XRD spectrum of a sample. 7A and 7B illustrate a TEM image of a sample and an electron diffraction pattern. The figure explaining the EDX mapping of a sample.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated in some cases. In addition, hatching of the same element configuring a drawing may be appropriately omitted or changed between different drawings.

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale. Note that the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, it may include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing shift.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and current flows through the drain, the channel region, and the source. Can be done.

Here, since the source and the drain change depending on the structure, operating conditions, and the like of the transistor, it is difficult to limit which is the source or the drain. For this reason, the terms "source" and "drain" can be interchanged with each other depending on the case or the situation.

Note that ordinal numbers “first”, “second”, and “third” used in this specification are added to avoid confusion of constituent elements, and are not limited in number. I do.

Further, in this specification and the like, when it is explicitly described that X and Y are connected, a case where X and Y are electrically connected and a case where X and Y function It is assumed that a case where X and Y are directly connected and a case where X and Y are directly connected are disclosed in this specification and the like. Therefore, the connection relation is not limited to the predetermined connection relation, for example, the connection relation shown in the figure or the text, and it is assumed that anything other than the connection relation shown in the figure or the text is also described in the figure or the text.

Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive layers, layers, and the like).

As an example of a case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) capable of electrically connecting X and Y is used. Elements, light emitting elements, loads, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitors, inductors, etc.) that enable electrical connection between X and Y , A resistance element, a diode, a display element, a light-emitting element, a load, etc.) are connected via X and Y.

As an example of a case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) capable of electrically connecting X and Y is used. One or more elements, light-emitting elements, loads, etc.) can be connected between X and Y. Note that the switch has a function of being turned on and off. That is, the switch is in a conductive state (on state) or non-conductive state (off state), and has a function of controlling whether a current flows or not. Alternatively, the switch has a function of selecting and switching a path through which current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of a case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, or the like)) that enables a functional connection between X and Y, a signal conversion Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit for changing signal potential level, etc.), voltage source, current source, switching Circuits, amplifier circuits (circuits that can increase signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, storage circuits, control circuits, etc.) One or more can be connected in between. Note that, as an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. I do. Note that a case where X and Y are functionally connected includes a case where X and Y are directly connected and a case where X and Y are electrically connected.

In addition, when it is explicitly described that X and Y are electrically connected, when X and Y are electrically connected (that is, when X and Y are separately connected). And X and Y are functionally connected to each other (that is, when X and Y are functionally connected to each other with another circuit interposed therebetween). In this specification, and the case where X and Y are directly connected (that is, the case where X and Y are connected without interposing another element or another circuit). It shall be disclosed in written documents. In other words, when it is explicitly described that it is electrically connected, the same content as when it is explicitly described only that it is connected is disclosed in this specification and the like. It is assumed that

Note that, for example, the source (or the first terminal or the like) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Via (or without) an electrical connection to Y, or a source of a transistor (or a first terminal or the like) directly connected to a portion of Z1 and another portion of Z1 Is directly connected to X, the drain of the transistor (or the second terminal or the like) is directly connected to a part of Z2, and another part of Z2 is directly connected to Y Then, it can be expressed as follows.

For example, “X and Y, a source (or a first terminal or the like) of a transistor, and a drain (or a second terminal or the like) are electrically connected to each other. Terminal, etc.), the drain of the transistor (or the second terminal, or the like), and Y are electrically connected in this order. " Or "the source (or the first terminal or the like) of the transistor is electrically connected to X, the drain (or the second terminal or the like) of the transistor is electrically connected to Y, X is the source (or the source of the transistor). Or the first terminal), the drain of the transistor (or the second terminal), and Y are electrically connected in this order. " Alternatively, “X is electrically connected to Y through a source (or a first terminal or the like) and a drain (or a second terminal or the like) of the transistor, and X is a source (or a first terminal or the like) of the transistor. Terminals), the drain of the transistor (or the second terminal), and Y are provided in this connection order. " By specifying the connection order in the circuit configuration using the same expression method as in these examples, the source (or the first terminal or the like) and the drain (or the second terminal) of the transistor are distinguished from each other. Alternatively, the technical scope can be determined.

Alternatively, as another expression method, for example, “a source (or a first terminal or the like) of a transistor is electrically connected to X via at least a first connection path, and the first connection path is The second connection path does not include a second connection path, and the second connection path is provided between a source (or a first terminal or the like) of the transistor and a drain (or the second terminal or the like) of the transistor via the transistor. And the first connection path is a path through Z1, and a drain (or a second terminal or the like) of the transistor is electrically connected to Y through at least a third connection path. Connected, the third connection path does not have the second connection path, and the third connection path is a path via Z2. " Or, "the source (or the first terminal or the like) of the transistor is electrically connected to X via Z1 by at least a first connection path, and the first connection path is a second connection path. And the second connection path has a connection path via a transistor, and the drain (or the second terminal or the like) of the transistor is connected via at least a third connection path via Z2. , Y, and the third connection path does not have the second connection path. " Or "the source (or first terminal or the like) of the transistor is electrically connected to X via at least a first electric path via Z1, and the first electric path is connected to the second electric path. Not having an electrical path, wherein the second electrical path is an electrical path from a source (or a first terminal, etc.) of the transistor to a drain (or a second terminal, etc.) of the transistor; A drain (or a second terminal or the like) of the transistor is electrically connected to Y via at least a third electric path via Z2, and the third electric path is connected to a fourth electric path. And the fourth electric path is an electric path from the drain (or the second terminal or the like) of the transistor to the source (or the first terminal or the like) of the transistor. " Can . By specifying the connection path in the circuit configuration using the same expression method as in these examples, the source (or the first terminal or the like) and the drain (or the second terminal) of the transistor are distinguished from each other. , The technical scope can be determined.

In addition, these expression methods are examples, and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive layers, layers, and the like).

Note that, even when independent components are illustrated as being electrically connected to each other on the circuit diagram, one component has functions of a plurality of components. There is also. For example, in the case where part of a wiring has a function as an electrode, one conductive layer has a function of both components of the wiring and a function of the electrode. Therefore, the term “electrically connected” in this specification also includes the case where one conductive layer also has the function of a plurality of components.

Note that in this specification, terms such as “above” and “below” that indicate arrangement are used for convenience to describe the positional relationship between components with reference to the drawings. Further, the positional relationship between the components changes as appropriate according to the direction in which each component is described. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately paraphrased according to the situation.

The arrangement of each circuit block in the block diagram in the drawings specifies a positional relationship for the purpose of explanation. Even if different circuit blocks are shown to realize different functions, the same circuit block is used in an actual circuit block. In some cases, the functions are provided so as to realize different functions. Further, the function of each circuit block in the drawings specifies a function for explanation, and even if it is shown as one circuit block, processing performed by one circuit block in an actual circuit block is performed by a plurality of circuit blocks. In some cases.

Note that the term “film” and the term “layer” can be interchanged with each other in some cases or depending on circumstances. For example, in some cases, the term “conductive layer” can be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

(Embodiment 1)
The structure of the imaging device of one embodiment of the present invention will be described with reference to drawings.

In this specification and the like, an imaging device refers to any device having an imaging function. Alternatively, a circuit having an imaging function or an entire system including the circuit is referred to as an imaging device.

In this specification and the like, a display device refers to any device having a display function. The display device includes a plurality of pixels, a circuit for driving the pixels, and the like. Further, the display device may include a control circuit, a power supply circuit, a signal generation circuit, and the like in some cases.

FIG. 1 is a block diagram illustrating a configuration of an imaging device of one embodiment of the present invention. The imaging device 10 includes a pixel 11, a circuit 13, a circuit 14, a circuit 15, a circuit 16, a circuit 17, a circuit 18, a circuit 19, a circuit 21, and a circuit 22. The pixels 11 are arranged in a matrix to form a pixel array 12 of n rows and m columns (n and m are natural numbers).

Further, external devices such as the display device 23 and the storage device 24 can be provided outside the imaging device 10. As the storage device 24, any nonvolatile memory such as a hard disk, a magnetic disk, a magneto-optical disk (MO; Magneto-Optical disk), a flash memory, and the like can be used.

The circuit 13 can have a function as a row driver for selecting a row of the pixel array 12. The circuit 14 can function as a first column driver that selects a column of the pixel array 12. The circuit 15 can have a function as an A / D conversion circuit.

The circuit 16 can have a function of performing data processing on imaging data that is analog data output from each pixel 11. The circuit 17 can have a function as a second column driver that selects a pixel 11 in a column on which data processing by the circuit 16 is performed.

The circuit 18 can have a function of calculating a row address of the pixel 11 in a row selected by the circuit 13. The circuit 19 can have a function of calculating a column address of the pixel 11 in the column selected by the circuit 17. The circuit 21 can have a function of storing a row address and a column address that define a designated area of the pixel array 12. The circuit 22 generates a signal based on the signal output from the circuit 16, the row address output from the circuit 18, the column address output from the circuit 19, and the row address and the column address stored in the circuit 21. A function of determining whether to output imaging data to an external device can be provided.

Here, the area of the pixel array 12 means a set of coordinates of the pixels 11. The coordinates are a set of numerical values indicating the number of a row and the number of a pixel arranged in the pixel array 12, and are defined by a row address and a column address. For example, the pixel 11 [1, 1] indicates the pixel 11 arranged in the first row and the first column. The pixel 11 [n, m] indicates the pixel 11 arranged in the n-th row and the m-th column.

Various circuits, such as a decoder and a shift register, are used for the circuits 13, 14, and 17.

Note that the circuit 14 and the circuit 17 may have the same circuit configuration or different circuit configurations. Further, as shown in FIG. 2, the circuit 14 and the circuit 17 may be shared to form a circuit 25.

Next, the operation of the imaging device 10 shown in FIG. 1 will be described using a flowchart shown in FIG. Note that the imaging device 10 can operate in the first mode or the second mode.

First, imaging is performed in the first mode (S1). In this mode, the imaging data 31 is acquired by all the pixels 11. The acquired imaging data 31 is converted into digital data by the circuit 15 and then output to an external device (S2).

That is, the first mode is an imaging mode in which imaging data is acquired and output to an external device.

Next, it is determined whether to switch to the second mode (S3). If the switching condition set in advance is not satisfied, S1 to S3 are performed again. Note that the switching conditions include, for example, the passage of a designated time or the input of a signal for switching to the second mode.

When the switching condition is satisfied, acquisition of the imaging data of the reference frame and acquisition of the imaging data of the difference detection frame are performed in the second mode. In this mode, one pixel 11 is selected by selecting a row of the pixel array 12 by the circuit 17 while selecting a row of the pixel array 12 by the circuit 13. Then, after the image data of the reference frame is obtained by the selected pixel 11 and output to the circuit 16, the image data of the difference detection frame is obtained by the selected pixel 11 and output to the circuit 16.
Thereafter, a difference calculation is performed between the imaging data of the reference frame and the imaging data of the difference detection frame (S4). Also, the circuit 16 generates the signal 36. When a difference is detected, the signal 36 is activated, and when no difference is detected, the signal 36 is deactivated. Note that the difference data representing the result of the difference calculation can be stored in the pixel 11.

That is, the second mode is a difference detection mode for detecting a difference between the image data of the reference frame and the image data of the difference detection frame.

Here, making the signal 36 active means, for example, outputting a signal of “H” (also referred to as a high-potential signal). Conversely, making the signal 36 inactive means, for example, outputting an “L” signal (also referred to as a low-potential signal). The logic of signal 36 may be reversed.

In this specification, “L” can be, for example, a ground potential.

As a method of calculating the difference by the circuit 16, a method of determining the presence or absence of a difference based on a difference between a current value caused by the imaging data of the reference frame output from the pixel 11 and a current value caused by the imaging data of the difference detection frame. Etc. can be used. If there is a difference between the current values, it is determined that there is a difference, and if not, it is determined that there is no difference. The specific circuit configuration and operation of the circuit 16 for implementing the method will be described later.

Further, the circuit 18 calculates the row address 32 constituting the coordinates of the pixel 11 subjected to the difference calculation, and the circuit 19 calculates the column address 33. Then, the row address 32 and the column address 33 are output to the circuit 22 as address signals. By supplying the clock signal 34 to the circuit 13 and the circuit 18, the selection of the row of the pixel array 12 by the circuit 13 and the calculation of the row address 32 by the circuit 18 can be performed in synchronization. Further, by supplying the clock signal 35 to the circuit 17 and the circuit 19, the selection of the column of the pixel array 12 by the circuit 17 and the calculation of the column address 33 by the circuit 19 can be performed in synchronization.

Note that in one embodiment of the present invention, the row address 32 is calculated by the circuit 18 and the column address 33 is calculated by the circuit 19 for all the pixels 11 for which the difference calculation is performed regardless of the presence or absence of the difference. Only the row address 32 and the column address 33 of the detected pixel 11 may be calculated.

When the difference is not detected and the signal 36 becomes inactive, the process returns to S4 to acquire the imaging data of the difference detection frame again and calculate the difference between the reference frame and the difference detection frame. .

In the second mode, for example, the pixel 11 in the first row and the first column is selected to calculate the difference, and then the pixel 11 in the first row and the second column is selected and the difference is calculated. The difference calculation is performed by sequentially selecting up to 11. For the pixels 11 in the second and subsequent rows, the difference calculation is performed sequentially from the pixels 11 in the first column to the pixels 11 in the m-th column in the same procedure as the pixels 11 in the first row. When the difference calculation is performed for the pixel 11 in the n-th row and the m-th column, the difference calculation is sequentially performed again for the pixel 11 in the first row and the first column to the pixel 11 in the n-th row and the m-th column. The signal 36 becomes active when a difference is detected between the image data of the reference frame and the image data of the difference detection frame in any of the pixels 11.

Note that the imaging data of the reference frame can be stored in the circuit 16. Therefore, when the difference is not detected in the difference calculation and the operation in the second mode is performed again, the imaging data of the reference frame may or may not be obtained. When acquiring the imaging data of the reference frame, a highly accurate difference calculation can be performed even if the held imaging data has changed due to elapse of time or the like. When the imaging data of the reference frame is not acquired, power consumption can be reduced and the operation can be speeded up.

When the difference is detected and the signal 36 becomes active, the circuit 22 determines whether or not to output the imaging data to the external device (S5). Hereinafter, an example of the operation in S5 will be described in detail.

Prior to operating the imaging device 10, the circuit 21 stores a row address 37 and a column address 38 that define a region 41 (see FIG. 4) in the pixel array 12. The storage of the row address 37 and the column address 38 in the circuit 21 may be performed during the operation of the imaging device 10.

When a difference is detected between the image data of the reference frame and the image data of the difference detection frame in the area 41, image data is newly acquired in the first mode and output to the external device. Note that a plurality of row addresses 37 and column addresses 38 can be respectively specified to define an area. For example, an area surrounded by connecting the coordinates specified by each address can be set as the area 41. Further, for example, the coordinates specified by each address may be connected by a straight line or a line segment, and the area on the straight line or the line segment may be used as the area 41. Further, for example, the coordinates specified by each address can be used as the area 41.

When the difference is detected in S4 and the signal 36 becomes active, the coordinates of the area 41 and the pixel in which the difference is detected (the difference calculation was performed by the circuit 16 immediately before the signal 36 became active) are detected. The circuit 22 compares the coordinates 42 composed of the eleven row addresses 32 and the column addresses 33. The area 41 and the coordinates 42 are not shown in FIG. Then, the circuit 22 generates the signal 39, and when the coordinates 42 are included in the area 41, the signal 39 is activated, assuming that the condition for outputting the imaging data to the external device is satisfied. When the coordinates 42 are not included in the area 41, the signal 39 is deactivated because it is determined that the output condition of the imaging data to the external device is not satisfied.

Here, the fact that the coordinates 42 are included in the area 41 means that the coordinates 42 match one of the coordinates of the area 41. The fact that the coordinates 42 are not included in the region 41 means that the coordinates 42 do not coincide with any of the coordinates of the region 41.

To make the signal 39 active means to output, for example, a signal of “H”, like the signal 36. Conversely, making the signal 39 inactive means, for example, outputting an “L” signal. The logic of signal 39 may be reversed.

Note that the imaging device 10 may have a structure without the circuit 21. In this case, the row address 37 and the column address 38 are supplied directly to the circuit 22.

Next, a specific example of the above-described determination of output of imaging data to an external device will be described with reference to FIG.

In the pixel array 12, the coordinates of the upper left pixel 11 are [1, 1], and the coordinates of the lower right pixel 11 are [n, m]. Then, “xmin” and “xmax” are stored in the circuit 21 as the row address 37, and “ymin” and “ymax” are stored in the circuit 21 as the column address 38, respectively. Here, 1 ≦ xmin ≦ xmax ≦ n (xmin is 1 or more and xmax or less, xmax is xmin or more and n or less), and 1 ≦ ymin ≦ ymax ≦ m (ymin is 1 or more and ymax or less and ymax is ymin or more and m or less). . Further, xmin, xmax, ymin and ymax are natural numbers.

In this case, as shown in FIG. 4, for example, the area 41 is an area inside a square surrounded by four points of coordinates [xmin, ymin], [xmin, ymax], [xmax, ymin], and [xmax, ymax]. It can be. When the coordinates 42 are [x1, y1] (x1 is a natural number between xmin and xmax, y1 is a natural number between ymin and ymax), the signal 39 can be activated assuming that the coordinates 42 are included in the area 41. . For example, if the coordinates 42 are [x2, y2] (x2 is a natural number from xmax to n and y2 is a natural number from ymin to ymax), the signal 39 is deactivated because the coordinates 42 are not included in the area 41. be able to. Further, for example, when the coordinates 42 are [x, y] (x and y are natural numbers), x is less than or equal to xmin, x is greater than or equal to xmax, y is less than or equal to ymin, and y is greater than or equal to ymax. Signal 39 can be deactivated assuming that coordinates 42 are not included in region 41.

Note that the area 41 may be a rectangular external area surrounded by four points of coordinates [xmin, ymin], [xmin, ymax], [xmax, ymin], and [xmax, ymax]. In this case, for example, when the coordinate 42 is [x2, y2] or [x, y], the signal 39 is activated assuming that the coordinate 42 is included in the area 41, and when the coordinate 42 is [x1, y1], for example. The coordinates 42 can be deactivated because they are not included in the area 41.

Although the region 41 is described as a square in FIG. 4, the region 41 can have various shapes. For example, it is also possible to store the row address 37 and the column address 38 in the circuit 21 three by three, designate three coordinates, and use the inside or outside of a triangle formed by connecting the coordinates with a straight line as the area 41. . In addition, the area 41 can be inside or outside the circle defined by the row address 37 and the column address 38. Further, the area 41 can be inside or outside the polygon defined by the row address 37 and the column address 38.

Note that the coordinates on the boundary between the inside and the outside of the region 41 can be included inside the region 41 or outside.

The case where the area 41 is a plane has been described above, but the area 41 may be a line or a point. When the area 41 is a line, for example, the circuit 21 stores two row addresses 37 and two column addresses 38 each, designates two coordinates, connects each coordinate with a straight line or a line segment, and sets the coordinate 42 as the straight line. The signal 39 can be activated when it is located on or on the line segment, and the signal 39 can be deactivated when the straight line or the line segment does not pass through the coordinates 42. When the straight line or the line segment does not pass through the coordinates 42, the signal 39 may be activated, and when the coordinates 42 are located on the straight line or the line segment, the signal 39 may be deactivated.

When the area 41 is a point, for example, one or a plurality of row addresses 37 and one or a plurality of column addresses 38 are stored in the circuit 21 to specify one or a plurality of coordinates, and the coordinates 42 indicate the specified coordinates (the area 41). ), The signal 39 can be made active, and if different from the designated coordinates (area 41), it can be made inactive. The row address 37 and the column address 38 are stored in the circuit 21 to specify the coordinates. If the coordinates 42 are different from the specified coordinates (area 41), the signal 39 is activated, and the same as the specified coordinates (area 41). , It can be deactivated.

Further, one or more row addresses 37 and / or column addresses 38 are stored in the circuit 21, and when the coordinates 42 include one or both of the row addresses 37 and the column addresses 38, the signal 39 is activated, and the row addresses 37 and / or When neither of the column addresses 38 is included, the signal 39 can be made inactive. Further, one or a plurality of row addresses 37 and / or column addresses 38 are stored in the circuit 21. If the coordinates 42 do not include both the row address 37 and the column address 38, the signal 39 is activated, and the row address 37 or the column address When one or both of the addresses 38 are included, the signal 39 can be made inactive.

Further, all of the row address and column address stored in the circuit 21 may be used for defining the area 41, or a part may be used for defining the area 41. When a part is used for defining the area 41, for example, a signal is supplied to the circuit 21 so that the row address 37 and / or the column address 38 used for defining the area 41 are stored in the circuit 21. It can be specified from among row addresses and / or column addresses.

The methods for defining the region 41 described above can be used in appropriate combinations.

In S5, when the signal 39 becomes inactive, the process returns to S4, where the imaging data of the reference frame and the imaging data of the frame for detecting the difference are acquired again in the second mode, and based on the acquired imaging data. And calculate the difference. As described above, when the imaging data of the reference frame is held in the circuit 16 or the like, the acquisition of the imaging data of the reference frame may be omitted.

When the signal 39 becomes active, the mode is switched to the first mode, and the imaging data 31 is obtained in the same procedure as in S1 (S6). Then, the imaging data 31 is output to the external device in the same procedure as in S2 (S7).

After execution of S7, the process returns to S4, switches to the second mode, again acquires the imaging data of the difference detection frame, and calculates the difference between the reference frame and the difference detection frame. After execution of S7, it may be determined whether to return to S4 to perform the operation in the second mode or to return to S6 to continue the imaging in the first mode. Further, it may be determined whether to return to S1. As in the case of S3, the determination condition includes, for example, elapse of a specified time or input of a signal for switching to the second mode. The above is the operation of the imaging device of one embodiment of the present invention.

As described above, in the imaging device 10 shown in FIG. 1, in the second mode, processing that consumes enormous power such as A / D conversion is not performed. Further, it is only necessary to perform a minimum process for generating a signal 36 having a function of transmitting whether or not a difference is detected to another circuit. For this reason, power consumption can be reduced as compared with the case of detecting the difference between the reference frame and the difference detection frame with A / D conversion or the like.

In addition, even when a difference is detected in the second mode, it is determined whether or not the imaging data is to be output to the external device, and the imaging data 31 is captured in the first mode only when the output condition is satisfied. Output to external device. For this reason, the output frequency of the imaging data 31 can be reduced as compared with the case where the imaging data 31 is unconditionally imaged and output to an external device when a difference is detected. Thus, for example, when the display device 23 is connected to the imaging device 10 as an external device, the frequency of rewriting image data in the display device 23 can be reduced. In a period during which image data is not rewritten, the operation of the circuit of the display device 23 can be stopped by using the display device 23 having the structure described in Embodiment 6, so that power consumption can be reduced. Further, for example, when the storage device 24 is connected to the imaging device 10 as an external device, the amount of data to be stored can be reduced. For this reason, the storage capacity of the storage device 24 can be saved, and not only can imaging be performed for a longer time, but also required data can be easily searched from stored data.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, an example of a pixel 11 included in the imaging device 10 and an operation thereof will be described with reference to drawings.

FIG. 5 is a circuit diagram of the pixel 11. The pixel 11 includes a photoelectric conversion element 120, a transistor 131, a transistor 132, a transistor 133, a transistor 134, a transistor 135, a capacitor 141, and a capacitor 142. Note that in FIG. 5, the transistors 131 to 135 are all n-ch transistors.

In the pixel 11 in FIG. 5, one terminal of the photoelectric conversion element 120 is electrically connected to one of the source and the drain of the transistor 131. The other of the source and the drain of the transistor 131 is electrically connected to one of the source or the drain of the transistor 132 and one terminal of the capacitor 141. One of a source and a drain of the transistor 133 is electrically connected to the other terminal of the capacitor 141, one terminal of the capacitor 142, and the gate of the transistor 134. One of a source and a drain of the transistor 134 is electrically connected to one of a source and a drain of the transistor 135.

The other terminal of the photoelectric conversion element 120 is electrically connected to the wiring 151 (VPD). The other of the source and the drain of the transistor 132 is electrically connected to the wiring 152 (VR). The other of the source and the drain of the transistor 133 is electrically connected to the wiring 153 (VAZ). The other terminal of the capacitor 142 is electrically connected to the wiring 154 (VSS). The other of the source and the drain of the transistor 135 is electrically connected to the wiring 155 (VPI). The other of the source and the drain of the transistor 134 is electrically connected to the wiring 156 (VOUT). The gate of the transistor 131 is electrically connected to the wiring 161 (TX). The gate of the transistor 132 is electrically connected to the wiring 162 (RES). The gate of the transistor 133 is electrically connected to the wiring 163 (AZ). The gate of the transistor 135 is electrically connected to the wiring 165 (SEL).

Here, the wiring 151 (VPD), the wiring 152 (VR), the wiring 153 (VAZ), the wiring 154 (VSS), and the wiring 155 (VPI) can function as power supply lines. The wiring 161 (TX), the wiring 162 (RES), the wiring 163 (AZ), and the wiring 165 (SEL) can function as signal lines.

In the above structure, a node to which the other of the source and the drain of the transistor 131, the one of the source and the drain of the transistor 132, and the one terminal of the capacitor 141 are connected is referred to as FD1. A node to which one of the source and the drain of the transistor 133, the gate of the transistor 134, the other terminal of the capacitor 141, and one terminal of the capacitor 142 are connected is referred to as FD2.

In the pixel 11, the photoelectric conversion element 120 is a light receiving element, and can have a function of generating a current according to light incident on the pixel 11. The transistor 131 can have a function of controlling charge accumulation or release from the photoelectric conversion element 120 to or from the node FD1. The transistor 132 can have a function of resetting the potential of the node FD1. The transistor 133 can have a function of resetting the potential of the node FD2. The transistor 134 can function as an amplification transistor that outputs a signal corresponding to the potential of the node FD2. The transistor 135 can function as a selection transistor that controls selection of the pixel 11 at the time of reading. In addition, the wiring 156 (VOUT) can have a function of outputting imaging data obtained by the pixel 11 as a signal.

The operation of the pixel 11 in the first mode will be described in detail with reference to a timing chart shown in FIG. The timing chart in FIG. 6 illustrates the potentials of the wiring 161 (TX), the wiring 162 (RES), the wiring 163 (AZ), the wiring 165 (SEL), the node FD1, and the node FD2. Note that the operation of turning on or off each transistor is performed by supplying a potential to turn on or off the transistor to a wiring connected to the gate of each transistor.

Note that the wiring 151 (VPD) is “L”, the wiring 152 (VR) is “H”, the wiring 153 (VAZ) is “H”, the wiring 154 (VSS) is “L”, and the wiring 155 (VPI) is “H”. However, the wiring can be operated by applying another potential to the wiring.

At the time T1, the wiring 131 (TX), the wiring 162 (RES), and the wiring 163 (AZ) are set to “H”, so that the transistors 131, 132, and 133 are turned on. Further, the transistor 135 is turned off by setting the wiring 165 (SEL) to “L”. Thus, the potential of the node FD1 is set to the potential “VR” of the wiring 152 (VR), and the potential of the node FD2 is set to the potential “VAZ” of the wiring 153 (VAZ).

At the time T2, the potential of the wiring 162 (RES) and the wiring 163 (AZ) is set at "L", whereby the transistors 132 and 133 are turned off. Thus, the potential of the node FD1 decreases.

Here, assuming that the potential drop of the node FD1 is “ΔV1”, the potential of the node FD1 becomes “VR−ΔV1”. The node FD2 is formed by capacitive coupling of the capacitor 141 (capacitance "C1"), the combined capacitance of the capacitor 142 (capacitance "C2"), and the gate capacitance (capacitance "Cg") of the transistor 134. Also decreases. Here, assuming that the potential drop of the node FD2 is “ΔV2”, “ΔV2 = ΔV1 · C1 / (C1 + C2 + Cg) = ΔV1 · α”, and the potential of the node FD2 is “VAZ−ΔV2”. Note that “α = C1 / (C1 + C2 + Cg)”.

Note that in order to make “ΔV1” and “ΔV2” as equal as possible, it is preferable that the capacitance of the capacitor 141 be larger than the sum of the capacitance of the capacitor 142 and the gate capacitance of the transistor 134.

The higher the illuminance of light applied to the photoelectric conversion element 120, the more the potential of the node FD1 drops. Therefore, the potential of node FD2 also drops significantly.

At the time T3, the wiring 131 (TX) is set to "L", whereby the transistor 131 is turned off. Thus, the potentials of the nodes FD1 and FD2 are held.

At a time T4, the wiring 135 (SEL) is set to “H”, whereby the transistor 135 is turned on. Accordingly, a signal corresponding to imaging data is output to the wiring 156 (VOUT) in accordance with the potential of the node FD2. Note that the lower the potential of the node FD2, the lower the potential of the signal output from the wiring 156 (VOUT). That is, the higher the illuminance of light applied to the photoelectric conversion element 120, the lower the potential of the wiring 156 (VOUT).

At the time T5, the wiring 135 (SEL) is set at "L", whereby the transistor 135 is turned off. The above is the operation of the pixel 11 in the first mode.

Next, the operation in the second mode will be described with reference to FIG.

The period from time T01 to time T06 corresponds to a period in which the imaging data of the reference frame is obtained and output. At the time T01, the wiring 131 (TX), the wiring 162 (RES), and the wiring 163 (AZ) are set to "H", so that the transistors 131, 132, and 133 are turned on. Further, the transistor 135 is turned off by setting the wiring 165 (SEL) to “L”. Accordingly, the potential of the node FD1 is reset to the potential “VR” of the wiring 152 (VR), and the potential of the node FD2 is reset to the potential “VAZ” of the wiring 153 (VAZ).

At the time T02, the wiring 132 (RES) is set at "L", whereby the transistor 132 is turned off. Thus, the potential of the node FD1 decreases. At the time T03, the wiring 131 (TX) is set at "L", whereby the transistor 131 is turned off. Thus, the potential of the node FD1 is held. Note that the interval between time T02 and time T03 is T.

Assuming that the potential drop of the node FD1 from the time T02 to the time T03 is “ΔV1”, the potential of the node FD1 becomes “VR−ΔV1”. The higher the illuminance of light applied to the photoelectric conversion element 120, the more the potential of the node FD1 drops. Note that the potential of the node FD2 does not change.

Then, at a time T04, the wiring 133 (AZ) is set at "L", whereby the transistor 133 is turned off. As described above, the imaging data of the reference frame is obtained.

At a time T05, the wiring 135 (SEL) is set at "H", whereby the transistor 135 is turned on. Accordingly, a signal corresponding to imaging data is output to the wiring 156 (VOUT) in accordance with the potential of the node FD2.

At the time T06, the wiring 135 (SEL) is set at "L", whereby the transistor 135 is turned off. The above is the operation of acquiring and outputting the imaging data of the reference frame.

Time T11 to time T15 correspond to a period during which difference data is obtained by obtaining and outputting image data of the difference detection frame when there is no difference between the image data of the reference frame and the image data of the difference detection frame. I do. This corresponds to the case where the illuminance of the light applied to the photoelectric conversion element 120 from time T12 to time T13 described later is equal to the illuminance of the light applied from time T02 to time T03.

At the time T11, the wiring 161 (TX) and the wiring 162 (RES) are set at "H", so that the transistors 131 and 132 are turned on. As a result, the potential of the node FD1 changes from “VR−ΔV1” to “VR”. That is, the potential increases by the amount of the potential decrease “ΔV1” from time T02 to time T03. Further, the potential of the node FD2 also increases. Here, assuming that the potential increase of the node FD2 is “ΔV2”, “ΔV2 = ΔV1 · α”. That is, the potential of the node FD2 changes from “VAZ” to “VAZ + ΔV2”.

At the time T12, the wiring 132 (RES) is set at "L", whereby the transistor 132 is turned off. Accordingly, the potential of the node FD1 decreases, and the potential of the node FD2 also decreases.

At a time T13, the wiring 131 (TX) is set to "L", whereby the transistor 131 is turned off. Thus, the potentials of the nodes FD1 and FD2 are held.

Here, assuming that the interval between the time T12 and the time T13 is T, the light having the same illuminance as that of the time T02 to the time T03 is applied to the photoelectric conversion element 120, so that the potential drop of the node FD1 decreases from the time T02 to the time T03. It is equal to the potential drop “ΔV1”. That is, the potential decrease of the node FD1 from the time T12 to the time T13 is equal to the potential increase of the node FD1 at the time T11. Further, the potential drop of the node FD2 is equal to the potential rise “ΔV2” at the time T11. Therefore, the potential of the node FD2 becomes “VAZ”. That is, the potential is equal to the potential of the wiring 153 (VAZ).

At the time T14, the wiring 135 (SEL) is set at "H", so that the transistor 135 is turned on. Accordingly, a signal corresponding to imaging data is output to the wiring 156 (VOUT) in accordance with the potential of the node FD2. Note that the potential of the signal is equal to the potential of the signal from time T05 to time T06.

At the time T15, the wiring 135 (SEL) is set at "L", whereby the transistor 135 is turned off. The above is the operation of acquiring and outputting the imaging data of the difference detection frame when there is no difference between the reference frame and the difference detection frame.

Time T21 to time T25 correspond to a period in which difference data is acquired by acquiring and outputting image data of the difference detection frame when there is a difference between the image data of the reference frame and the image data of the difference detection frame. I do. This corresponds to the case where the illuminance of the light applied to the photoelectric conversion element 120 from time T22 to time T23 described later is higher than the illuminance of the light applied from time T12 to time T13.

The operation of the transistor 131, the transistor 132, the transistor 133, and the transistor 135 from time T21 to time T25 is similar to the operation of each transistor from time T11 to time T15.

At the time T21, the potential of the node FD1 becomes "VR". That is, the potential rises by the potential decrease “ΔV1” from time T12 to time T13. On the other hand, the potential of the node FD2 also increases by the potential decrease “ΔV2” from the time T12 to the time T13. That is, the potential of the node FD2 becomes “VAZ + ΔV2”.

At the time T22, the potential of the node FD1 decreases, and the potential of the node FD2 also decreases.

At the time T23, the potentials of the nodes FD1 and FD2 are held. Assuming that the interval between the time T22 and the time T23 is T, the illuminance of the light applied to the photoelectric conversion element 120 is higher than the illuminance of the light applied to the photoelectric conversion element 120 from the time T12 to the time T13. ΔV1 ′ ″ is larger than the potential drop “ΔV1” from time T12 to time T13 (ΔV1 ′> ΔV1). Also, the potential drop “ΔV2 ′ = ΔV1 ′ · α” of the node FD2 is larger than the drop “ΔV2” from the time T12 to the time T13 (ΔV2 ′> ΔV2). Therefore, the potential “VAZ + ΔV2−ΔV2 ′” of the node FD2 is lower than the potential “VAZ” of the wiring 153 (VAZ).

At time T24, a signal corresponding to imaging data is output to the wiring 156 (VOUT) in accordance with the potential of the node FD2. Note that the potential of a signal output from the wiring 156 (VOUT) decreases as the illuminance of light applied to the photoelectric conversion element 120 from time T22 to time T23 increases, so that the potential of the output signal changes from the time T14 to the time T15. It becomes lower than the potential of the output signal.

The time T31 to the time T35 are obtained by acquiring and outputting the difference detection frame imaging data when there is no difference between the reference frame imaging data and the difference detection frame imaging data as in the case of the time T11 to the time T15. , Which corresponds to a period during which difference data is acquired.

The operation of the transistor 131, the transistor 132, the transistor 133, and the transistor 135 from time T31 to time T35 is similar to the operation of each transistor from time T11 to time T15.

From the time T31 to the time T32, the potential of the node FD1 becomes “VR”. That is, the potential increases by the potential decrease “ΔV1” ”from the time T22 to the time T23. On the other hand, the potential of the node FD2 also rises by the potential decrease “ΔV2 ′” from the time T22 to the time T23. That is, the potential of the node FD2 becomes “V2 + ΔV2”.

Assuming that the interval between the time T32 and the time T33 is T, the light having the same illuminance as that at the time T12 to the time T13 is irradiated on the photoelectric conversion element 120, so that the potential drop of the node FD1 decreases at the time T12 to the time T13. ΔV1 ″. Further, the potential drop of the node FD2 is also equal to the potential drop “ΔV2” from the time T12 to the time T13. Therefore, the potential of the node FD2 becomes “VAZ”. That is, the potential is equal to the potential of the wiring 153 (VAZ).

Time T41 to time T45 correspond to a period during which difference data is acquired by acquiring and outputting the difference detection frame imaging data when there is a difference between the reference frame imaging data and the difference detection frame imaging data. I do. This corresponds to the case where the illuminance of the light applied to the photoelectric conversion element 120 from time T42 to time T43 described later is lower than the illuminance of the light applied from time T32 to time T33.

The operation of the transistor 131, the transistor 132, the transistor 133, and the transistor 135 from time T41 to time T45 is similar to the operation of each transistor from time T31 to time T35.

At the time T41, the potential of the node FD1 becomes “VR”. That is, the potential rises by the potential decrease “ΔV1” from time T32 to time T33. On the other hand, the potential of the node FD2 also increases by the potential decrease “ΔV2” from the time T32 to the time T33. That is, the potential of the node FD2 becomes “VAZ + ΔV2”.

At the time T42, the potential of the node FD1 decreases, and the potential of the node FD2 also decreases.

At the time T43, the potentials of the nodes FD1 and FD2 are held. Assuming that the interval between the time T42 and the time T43 is T, the illuminance of light applied to the photoelectric conversion element 120 is lower than the illuminance of the light applied to the photoelectric conversion element 120 from time T32 to time T33, so that the potential of the node FD1 decreases. ΔV1 ″ ″ is smaller than the potential drop “ΔV1” from time T32 to time T33 (ΔV1 ″ <ΔV1). Also, the potential drop “ΔV2 ″ = ΔV1 ″ · α” of the node FD2 is smaller than the drop “ΔV2” from the time T32 to the time T33 (ΔV2 ″ <ΔV2). Therefore, the potential “VAZ + ΔV2−ΔV2 ″” of the node FD2 is higher than the potential “VAZ” of the wiring 153 (VAZ).

At a time T44, a signal corresponding to imaging data is output to the wiring 156 (VOUT) in accordance with the potential of the node FD2. Note that the potential of the signal output from the wiring 156 (VOUT) increases as the illuminance of light emitted to the photoelectric conversion element 120 from time T42 to time T43 decreases, so that the potential of the output signal changes from the time T34 to the time T35. It becomes higher than the potential of the output signal.

The example of the operation of the pixel 11 in the second mode has been described above.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, a modified example of the pixel 11 included in the imaging device 10 will be described with reference to the drawings.

The pixel 11 included in the imaging device 10 of one embodiment of the present invention is not limited to the structure illustrated in FIG. The configuration shown in FIG. 8 may be employed. FIG. 8 illustrates a structure in which all of the transistors 131 to 135 illustrated in FIG. 5 are p-ch transistors. The operation in the first mode can be referred to FIG. 6 and the operation in the second mode can be referred to FIG. 7 by reversing the magnitude relationship of the potentials as necessary. Note that some of the transistors 131 to 135 may be replaced with p-ch transistors. Alternatively, a CMOS configuration may be used.

Although the transistor 135 is provided between the transistor 134 and the wiring 155 (VPI) in FIG. 5, the transistor 134 may be provided between the transistor 135 and the wiring 155 (VPI) as shown in FIG. Good.

The pixel 11 included in the imaging device 10 of one embodiment of the present invention may have a structure illustrated in FIG. FIG. 10 illustrates a configuration in which the connection direction of the photoelectric conversion element 120 in the pixel 11 is opposite to that in FIG. In this case, the wiring 151 (VPD) is set to “H” and the wiring 152 (VR) is set to “L”. FIG. 6 can be referred to for the operation in the first mode, and FIG. 7 can be referred to for the operation in the second mode. In this case, the higher the illuminance of the light applied to the photoelectric conversion element 120 is, the higher the nodes FD1 and FD1 are. The potential of FD2 increases. Therefore, in the circuit configuration in FIG. 10, the higher the illuminance of light applied to the photoelectric conversion element 120, the higher the potential of the output signal output from the wiring 156 (VOUT).

FIG. 11A illustrates a structure in which the transistor 132 is removed from the pixel 11 illustrated in FIG. In this case, the wiring 151 (VPD) has a structure in which the wiring 151 (VPD) can change between “L” and “H”. The reset operation of the node FD1 can be performed by setting the wiring 151 (VPD) to “H”. When the wiring 151 (VPD) is set to “H” in a predetermined period, a forward bias is applied to the photoelectric conversion element 120. Therefore, the potential of the node FD1 can be set to the potential “VPD” of the wiring 151 (VPD).

In addition, when acquiring imaging data, the wiring 151 (VPD) is set to “L”. When the wiring 151 (VPD) is set to “L”, a reverse bias is applied to the photoelectric conversion element 120; therefore, charge can be released from the node FD1 to the wiring 151 (VPD) in accordance with the illuminance of light. In this case, the higher the illuminance of the light applied to the photoelectric conversion element 120, the lower the potential of the node FD1 and, accordingly, the potential of the node FD2. Therefore, in the circuit configuration in FIG. 11A, the higher the illuminance of light applied to the photoelectric conversion element 120, the lower the potential of the output signal output from the wiring 156 (VOUT).

As another mode of the pixel 11 included in the imaging device 10 of one embodiment of the present invention, a structure without the transistor 131 as illustrated in FIG. 11B may be employed. Further, a structure without the capacitor 142 as illustrated in FIG. 11C may be employed.

In FIG. 11, some of the wirings are omitted.

Further, in FIG. 5, the wirings that give the same potential are illustrated as different wirings, but may be the same wiring. For example, as in the pixel 11 illustrated in FIG. 12A, the wiring 152 (VR) to which “H” is applied, the wiring 153 (VAZ), and the wiring 155 (VPI) may be the same wiring. Alternatively, as in the pixel 11 illustrated in FIG. 12B, the wiring 151 (VPD) and the wiring 154 (VSS) to which “L” is applied may be the same wiring.

FIG. 13A illustrates a structure in which the transistors 131 to 135 in the pixel 11 in FIG. 5 are transistors whose active layers or regions are formed using an oxide semiconductor (hereinafter, referred to as OS transistors).

In this specification, unless otherwise specified, an off-state current refers to a drain current when a transistor is in an off state (also referred to as a non-conductive state or a cut-off state). Unless otherwise specified, the off state refers to a state in which the voltage “Vgs” between the gate and the source is lower than the threshold voltage “Vth” in an n-channel transistor, and the gate and the source in a p-channel transistor. The state in which the voltage “Vgs” is higher than the threshold voltage “Vth”. For example, the off-state current of an n-channel transistor may mean a drain current when a voltage “Vgs” between a gate and a source is lower than a threshold voltage “Vth”.

The off-state current of the transistor sometimes depends on “Vgs”. Therefore, that the off-state current of the transistor is equal to or less than “I” may mean that there is a value of “Vgs” at which the off-state current of the transistor is equal to or less than “I”. The off-state current of the transistor is an off-state at a predetermined “Vgs”, an off-state at “Vgs” within a predetermined range, or an off-state at “Vgs” at which a sufficiently reduced off-state current is obtained. May refer to

As an example, when the threshold voltage “Vth” is 0.5 V, the drain current when “Vgs” is 0.5 V is 1 × 10 ⁻⁹ A, and the drain current when “Vgs” is 0.1 V is 1 × 10 ⁻¹³ A, the drain current at “Vgs” of −0.5 V is 1 × 10 ⁻¹⁹ A, and the drain current at “Vgs” at −0.8 V is 1 × 10 ⁻²² A. Assume an n-channel transistor. The drain current of the transistor is less than or equal to 1 × 10 ⁻¹⁹ A when “Vgs” is −0.5 V or “Vgs” is in a range of −0.5 V to −0.8 V; In some cases, the off-state current is 1 × 10 ⁻¹⁹ A or less. Since there is “Vgs” in which the drain current of the transistor is 1 × 10 ⁻²² A or less, the off-state current of the transistor may be 1 × 10 ⁻²² A or less.

In this specification, the off-state current of a transistor having a channel width W may be represented by a current value flowing around the channel width W in some cases. In addition, it may be represented by a current value flowing around a predetermined channel width (for example, 1 μm). In the latter case, the unit of the off-state current may be represented by a unit having a current / length dimension (for example, A / μm).

The off-state current of a transistor may depend on temperature. In this specification, the off-state current may refer to off-state current at room temperature, 60 ° C, 85 ° C, 95 ° C, or 125 ° C unless otherwise specified. Alternatively, at a temperature at which reliability of a semiconductor device or the like including the transistor is guaranteed, or at a temperature at which the semiconductor device or the like including the transistor is used (for example, any one of 5 ° C. to 35 ° C.) Off current. The off-state current of a transistor is equal to or lower than "I" when room temperature, 60 ° C, 85 ° C, 95 ° C, 125 ° C, a temperature at which reliability of a semiconductor device including the transistor is guaranteed, or A case in which the value of “Vgs” at which the off-state current of the transistor is lower than or equal to “I” exists at a temperature at which the included semiconductor device or the like is used (for example, any temperature of 5 ° C. to 35 ° C.) There is.

The off-state current of the transistor may depend on the voltage “Vds” between the drain and the source in some cases. In this specification, “Vds” is 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 3.3 V, 10 V, and 12 V unless otherwise specified. , 16V, or 20V. Alternatively, the term may refer to “Vds” at which reliability of a semiconductor device or the like including the transistor is guaranteed or “Vds” used in a semiconductor device or the like including the transistor. The off-state current of the transistor is equal to or less than “I” when “Vds” is 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 3.3 V, 10 V, and 12 V , 16 V, 20 V, Vds at which the reliability of the semiconductor device including the transistor is guaranteed, or “Vds” used in a semiconductor device including the transistor, etc., the off-state current of the transistor is “I” or less. In some cases, it indicates that a value of “Vgs” exists.

In this specification, the term “leakage current” may be used in the same meaning as the off-state current.

In this specification, for example, an off-state current may refer to a current flowing between a source and a drain when a transistor is off.

When the OS transistor is used for the pixel 11, the dynamic range of imaging can be expanded. In the circuit configuration illustrated in FIG. 5, when the illuminance of light incident on the photoelectric conversion element 120 is high, the potential of the node FD1 decreases, and therefore, the potential of the node FD2 also decreases. Since the off-state current of the OS transistor is extremely low, even when the potential of the node FD2 (the gate potential of the transistor 134) is extremely small, a current corresponding to the gate potential can be accurately output. Therefore, the illuminance range that can be detected, that is, the dynamic range can be expanded.

Further, the period during which charge can be held at the nodes FD1 and FD2 can be extremely long due to the low off-state current characteristics of the transistor. Therefore, it is possible to apply a global shutter method in which image data is simultaneously acquired in all pixels without complicating a circuit configuration and an operation method.

In general, in an imaging device in which pixels are arranged in a matrix, a rolling shutter method which is a driving method of performing an imaging operation 201, a data holding operation 202, and a reading operation 203 for each row shown in FIG. Can be In the case of using the rolling shutter system, the synchronization of imaging is lost, so that when the subject moves, the image is distorted.

Therefore, in one embodiment of the present invention, it is preferable to use a global shutter system in which the imaging operation 201 can be performed simultaneously in all rows and the reading operation 203 can be sequentially performed in each row as illustrated in FIG. By using the global shutter method, it is possible to ensure the simultaneousness of imaging in each pixel of the imaging device, and it is possible to easily obtain an image with small distortion even when the subject moves.

Further, the OS transistor has a smaller temperature dependence of electric characteristics fluctuation than a transistor whose active layer or active region is formed of silicon (hereinafter, referred to as a Si transistor), and thus can be used in an extremely wide temperature range. Therefore, the imaging device and the semiconductor device including the OS transistor are suitable for being mounted on an automobile, an aircraft, a spacecraft, or the like.

Further, a transistor connected to one of the node FD1 and the node FD2 is required to have low noise. A transistor including a two-layer or three-layer oxide semiconductor layer described later has a channel of a buried type and has extremely noise-resistant characteristics. Therefore, an image with less noise can be obtained by using the transistor.

In particular, with the structure illustrated in FIG. 13A, a pixel can be formed using a photoelectric conversion element formed of silicon and an OS transistor. With such a configuration, it is not necessary to form a Si transistor in a pixel, and thus it is easy to increase the effective area of the photoelectric conversion element. Therefore, the imaging sensitivity can be improved.

Further, peripheral circuits such as the circuit 13, the circuit 14, the circuit 15, the circuit 16, the circuit 17, the circuit 18, the circuit 19, the circuit 21, and the circuit 22 as well as the pixel 11 may be formed using OS transistors. A structure in which the peripheral circuit is formed only of the OS transistors does not require a step of forming a Si transistor, and is effective in reducing the cost of the imaging device. In addition, a structure in which a peripheral circuit is formed using only an OS transistor and a p-type Si transistor does not require a step of forming an n-type Si transistor, which is effective in reducing the cost of an imaging device. Further, since the peripheral circuit can be a CMOS circuit, it is effective in reducing the power consumption of the peripheral circuit, that is, the power consumption of the imaging device.

FIG. 13B shows a modification of the circuit diagram of the pixel 11 which is a further modification of FIG. 13A. In the pixel 11 illustrated in FIG. 13B, the transistor 134 and the transistor 135 are configured to be Si transistors.

The Si transistor has such a characteristic that it has better field-effect mobility than the OS transistor. Therefore, the value of current flowing through the transistor functioning as an amplification transistor or a selection transistor can be increased. For example, the current flowing through the transistor 134 and the transistor 135 can be increased in accordance with the charge stored in the node FD2 in FIG.

Note that in the circuit diagrams illustrated in FIGS. 13A and 13B, “OS” is added to a circuit symbol of the OS transistor to clearly indicate that the transistor is an OS transistor.

The transistor used for the pixel 11 may have a structure in which a back gate is provided for the transistor 131, the transistor 132, and the transistor 133 as illustrated in FIG. FIG. 15A illustrates a structure in which a constant potential is applied to the back gate, and the threshold voltage can be controlled. FIG. 15B illustrates a structure in which the same potential as that of the front gate is applied to the back gate, so that the on-state current can be increased. Note that as illustrated in FIG. 15C or FIG. 15D, a structure in which a back gate is provided for the transistors 131 to 135 may be employed.

Further, as shown in FIG. 15E, a structure in which the same potential as the front gate is applied to the back gate and a structure in which a constant potential is applied to the back gate are applied to a transistor included in one pixel as necessary. It may be a combination configuration. Furthermore, a configuration in which a back gate is not provided may be arbitrarily combined as needed. Note that in the structure in which a constant potential is applied to the back gate, a structure in which the same potential is applied to all the back gates can be employed, for example, as illustrated in FIG.

Note that some of the wirings are omitted in FIG.

Since the OS transistor has lower on-state current than the Si transistor, it is particularly preferable to provide a back gate for the OS transistor. For example, as illustrated in FIG. 13A, in the case where an OS transistor is used for the transistors 131 to 135, a back gate is preferably provided for the transistors 131 to 135. In the case where an OS transistor is used for the transistors 131 to 133, as illustrated in FIG. 13B, a back gate is preferably provided for the transistors 131 to 133.

Further, the pixel 11 may have a configuration in which the transistor 132, the transistor 133, the transistor 134, and the transistor 135 are shared by a plurality of pixels as illustrated in FIG. Note that FIG. 16 illustrates an example in which a plurality of pixels in the vertical direction share the transistor 132, the transistor 133, the transistor 134, and the transistor 135. However, the transistor 132 and the transistor 133 are used in a plurality of pixels in the horizontal or horizontal direction. , Transistor 134 and transistor 135 may be shared. With such a structure, the number of transistors per pixel can be reduced.

Note that FIG. 16 illustrates a mode in which the transistor 132, the transistor 133, the transistor 134, and the transistor 135 are shared by four pixels; however, a mode in which two, three, or five or more pixels are shared may be employed.

With the above structure, an imaging device having a highly integrated pixel array can be formed. Further, it is possible to provide an imaging device capable of obtaining high-quality imaging data.

Note that the configurations shown in FIGS. 5, 8 to 13, 15, and 16 can be arbitrarily combined.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, an example of a configuration of a circuit 16 included in the imaging device 10 will be described with reference to drawings.

In the present embodiment, it is assumed that the pixels 11 are arranged in n rows and m columns as in the first embodiment. The circuit configuration of the pixel 11 is the same as the circuit configuration illustrated in FIG. 5 described in Embodiment 2.

FIG. 17 illustrates the structure of the circuit 16 and the connection relation between the pixel 11, the circuit 16, and the circuit 17. The circuit 16 includes a transistor 50, a transistor 51, a transistor 52, a transistor 53, a transistor 54, a transistor 55, a transistor 56, a transistor 57, a transistor 58, a transistor 59, a transistor 60, a transistor 61, a transistor 62, a capacitor 63, a comparator 64, It has a comparator 65. Note that the circuit 16 includes m transistors 50 to 55 and m capacitors 63 each.

In FIG. 17, only the n-th row of the pixels 11 is shown.

Note that in FIG. 17, the transistors 50 to 55, the transistor 58, the transistor 59, and the transistor 62 are n-ch transistors, and the transistors 56, 57, 60, and 61 are p-ch transistors. The ch-type transistor may be replaced with a p-ch type, and some p-ch-type transistors may be replaced with an n-ch type.

In the circuit 16 in FIG. 17, one of the source and the drain of the transistor 50 [1] to [m] is electrically connected to the other of the source or the drain of the transistor 134 by a wiring 156 (VOUT [1] to [m]). Have been. The other of the sources or the drains of the transistors 50 [1] to [m] is one of the sources or the drains of the transistors 51 [1] to [m] and the other of the sources or the drains of the transistors 52 [1] to [m]. And one of the sources and drains of the transistors 53 [1] to [m]. The gates of the transistors 50 [1] to [m] are electrically connected to the wiring 70 (ABU).

The other of the sources and the drains of the transistors 51 [1] to [m] is electrically connected to one terminal of the capacitor 63 [1] to [m] and the wiring 71 (VSS). The gates of the transistors 51 [1] to [m] are electrically connected to the other of the sources or the drains of the transistors 52 [1] to [m] and the other terminals of the capacitors 63 [1] to [m]. Have been.

The gates of the transistors 52 [1] to [m] are electrically connected to the wiring 72 (ATC).

The gates of the transistors 53 [1] to [m] are electrically connected to the circuit 17 by wirings 73 (AOP [1] to [m]). The other of the sources or the drains of the transistors 53 [1] to [m] is one of the sources or the drains of the transistors 54 [1] to [m], the gates of the transistors 55 [1] to [m], and the transistor 55 [ 1] to [m].

The other of the sources and the drains of the transistors 54 [1] to [m] is electrically connected to the gates of the transistors 54 [1] to [m], one of the source and the drain of the transistor 56, and the non-inverting input terminal of the comparator 64. It is connected to the.

The other of the sources and the drains of the transistors 55 [1] to [m] is electrically connected to one of the source or the drain of the transistor 58 and the non-inverting input terminal of the comparator 65.

The other of the source and the drain of the transistor 56 is electrically connected to one of the source or the drain of the transistor 57, the one of the source or the drain of the transistor 60, and the one of the source or the drain of the transistor 61 by a wiring 76 (VDD2). ing. The gate of the transistor 56 is electrically connected to the gate of the transistor 57 and the output terminal of the comparator 64.

The other of the source and the drain of the transistor 57 is electrically connected to the other of the source and the drain of the transistor 61 and the one of the source and the drain of the transistor 62.

The other of the source and the drain of the transistor 58 is electrically connected to one of the source and the drain of the transistor 59 by a wiring 78 (VSS2). The gate of the transistor 58 is electrically connected to the gate of the transistor 59 and the output terminal of the comparator 65.

The other of the source and the drain of the transistor 59 is electrically connected to the other of the source and the drain of the transistor 60, the gate of the transistor 60, and the gate of the transistor 61.

The other of the source and the drain of the transistor 62 is electrically connected to the wiring 81 (VSS3). The gate of the transistor 62 is electrically connected to the wiring 82 (BIAS).

The inverting input terminal of the comparator 64 is electrically connected to the wiring 84 (Vref−). The inverting input terminal of the comparator 65 is electrically connected to the wiring 85 (Vref +).

Note that the potential “Vref−” of the wiring 84 (Vref−) and the potential “Vref +” of the wiring 85 (Vref +) can be set as appropriate.

Further, the wiring 71 (VSS) can be set to “L”, but can be operated by applying another potential.

FIG. 18 is a timing chart illustrating an example of the operation of the circuit 16. At the time T01, the wiring 165 (SEL [x]), the wiring 163 (AZ), the wiring 70 (ABU), and the wiring 72 (ATC) are set to “H”. Thus, the transistor 135, the transistor 133, the transistors 50 [1] to [m], and the transistors 52 [1] to [m] are turned on. Further, by setting the wiring 73 (AOP [1] to [m]) to “L”, the transistors 53 [1] to [m] are turned off. Note that the wiring 165 (SEL [x]) is the wiring 165 in an arbitrary row (x is a natural number equal to or less than n).

At this time, the current supplied to the wiring 156 (VOUT [1] to [m]) in each column corresponds to the imaging data of the reference frame, and the difference between the imaging data of the reference frame and the imaging data of the difference detection frame is different. The current value becomes "I0" at the time of zero. This current value I0 may be referred to as a reference current value.

The current values of the currents Ip [1] to Ip [m] flowing through the transistors 50 [1] to [m] are equal to the current value I0, and the currents flowing through the transistors 51 [1] to [m]. The current values of Ic [1] to Ic [m] are also equal to “I0”. In addition, the capacitors 63 [1] to [m] are charged with a potential corresponding to a gate voltage required for flowing “I0” to the transistors 51 [1] to [m].

At the time T02, the wiring 165 (SEL [x]), the wiring 163 (AZ), the wiring 70 (ABU), and the wiring 72 (ATC) are set to “L”, so that the transistors 135, 133, and 50 [1] To [m] and the transistors 52 [1] to [m] are turned off.

At the time T11, the wiring 135 (SEL [1]), the wiring 70 (ABU), and the wiring 73 (AOP [1]) are set to “H”, so that the transistor 135 included in the pixel 11 in the first row and the transistor 50 [1] to 50 [m] and the transistor 53 [1] are turned on. At this time, a current corresponding to the difference detected by the pixel 11 [1, 1] is supplied to the wiring 156 (VOUT [1]). Here, assuming that the difference in the pixel 11 [1, 1] is zero, the current value of the current supplied to the wiring 156 (VOUT [1]) is “I0”. Further, the current value of the current Ip [1] is equal to “I0”, and the current value of the current Ic [1] is also equal to “I0”.

At the time T12, the wiring 53 (AOP [2]) is set to “H”, whereby the transistor 53 [2] is turned on. Further, by setting the wiring 73 (AOP [1]) to “L”, the transistor 53 [1] is turned off. At this time, a current corresponding to the difference detected by the pixel 11 [1, 2] is supplied to the wiring 156 (VOUT [2]). Here, assuming that the difference in the pixel 11 [1, 2] is zero, the current value of the current supplied to the wiring 156 (VOUT [2]) is “I0”. The current value of the current Ip [2] is equal to “I0”, and the current value of the flowing current Ic [2] is also equal to “I0”.

At the time T13, the wiring 53 (AOP [2]) is set to “L”, whereby the transistor 53 [2] is turned off. At the time T14, the wiring 53 (AOP [m]) is set to "H", so that the transistor 53 [m] is turned on. At this time, a current corresponding to the difference detected by the pixel 11 [1, m] is supplied to the wiring 156 (VOUT [m]). Here, assuming that the difference in the pixel 11 [1, m] is zero, the current value of the current supplied to the wiring 156 (VOUT [m]) is “I0”. Further, the current value of the current Ip [m] is equal to “I0”, and the current value of the current Ic [m] is also equal to “I0”.

At the time T15, the wiring 135 (SEL [1]), the wiring 70 (ABU), and the wiring 73 (AOP [m]) are set to “L”, so that the transistor 135 included in the pixel 11 in the first row is 50 [1] to 50 [m] and the transistor 53 [m] are turned off. This is the end of the difference detection of the pixels 11 in the first row.

Next, at a time T21, the wiring 135 (SEL [2]), the wiring 70 (ABU), and the wiring 73 (AOP [1]) are set to “H”, so that the transistors 135 included in the pixels 11 in the second row. And the transistors 50 [1] to [m] and the transistor 53 [1] are turned on. At this time, a current corresponding to the difference detected by the pixel 11 [2, 1] is supplied to the wiring 156 (VOUT [1]). Here, assuming that the difference in the pixel 11 [2, 1] is zero, the current value of the current supplied to the wiring 156 (VOUT [1]) is “I0”. Further, the current value of the current Ip [1] is equal to “I0”, and the current value of the current Ic [1] is also equal to “I0”.

At a time T22, the wiring 73 (AOP [2]) is set to “H”, whereby the transistor 53 [2] is turned on. Further, by setting the wiring 73 (AOP [1]) to “L”, the transistor 53 [1] is turned off. At this time, a current corresponding to the difference detected by the pixel 11 [2, 2] is supplied to the wiring 156 (VOUT [2]). Here, assuming that the current value of the current supplied to the wiring 156 (VOUT [2]) is “I0−ΔI1”, the current value of the current Ip [2] is equal to “I0−ΔI1”, and the current Ic [ Since the current value of [2] is equal to “I0”, a current of the current value “ΔI1” flows through the transistor 53 [2] and the transistor 54 [2].

Note that the current value “I0−ΔI1” is smaller than the current value “I0”. This means that when the pixel 11 [2, 2] acquires the imaging data of the frame for detecting a difference, the illuminance of the light radiated to the photoelectric conversion element 120 indicates that the pixel 11 [2, 2] has the imaging data of the reference frame. This corresponds to a case where the illuminance is higher than the illuminance of light emitted to the photoelectric conversion element 120 at the time of acquisition.

Here, the current “I ⁻ ” is supplied by the operation of the comparator 64 and the transistor 56. Here, when the current “I ⁻ ” supplied to the transistor 54 [2] via the transistor 56 is smaller (greater) than “ΔI1”, the potential of the + terminal of the comparator 64 decreases (increases). The output of the comparator 64 decreases (increases). That is, the gate voltage of the transistor 56 decreases (increases). Since the transistor 56 is of the p-ch type, it is possible to supply more (less) current “I ⁻ ”.

Further, since the same potential as that of the gate of the transistor 56 is applied to the transistor 57, a current “n1 · I ⁻ ” obtained by multiplying the transistor 57 with respect to the transistor 56 by a ratio (n1) of W (channel width direction) / L (channel length direction). Flows through the transistor 57. Further, the signal 36 (TRIG) becomes “H” by the buffer including the transistor 62 and the transistor 57. Note that a bias voltage is applied to the wiring 82 (BIAS). The bias voltage can be set as appropriate.

At the time T23, the wiring 53 (AOP [2]) is set to “L”, whereby the transistor 53 [2] is turned off. At the time T24, the wiring 53 (AOP [m]) is set to "H", whereby the transistor 53 [m] is turned on. At this time, a current corresponding to the difference detected by the pixel 11 [2, m] is supplied to the wiring 156 (VOUT [m]). Here, assuming that the difference in the pixel 11 [2, m] is zero, the current value of the current supplied to the wiring 156 (VOUT [m]) is “I0”. Further, the current value of the current Ip [1] is equal to “I0”, and the current value of the current Ic [1] is also equal to “I0”.

At the time T25, the wiring 135 (SEL [2]), the wiring 70 (ABU), and the wiring 73 (AOP [m]) are set to “L”, so that the transistor 135 included in the pixel 11 in the second row and the transistor 50 [1] to 50 [m] and the transistor 53 [m] are turned off. This is the end of the difference detection of the pixels 11 in the second row.

Next, at a time T31, the wiring 135 (SEL [n]), the wiring 70 (ABU), and the wiring 73 (AOP [1]) are set to “H”, so that the transistor 135 included in the pixels 11 in the n-th row. And the transistors 50 [1] to [m] and the transistor 53 [1] are turned on. At this time, a current corresponding to the difference detected by the pixel 11 [n, 1] is supplied to the wiring 156 (VOUT [1]). Here, assuming that the difference in the pixel 11 [n, 1] is zero, the current value of the current supplied to the wiring 156 (VOUT [1]) is “I0”. Further, the current value of the current Ip [1] is equal to “I0”, and the current value of the current Ic [1] is also equal to “I0”.

At the time T32, the wiring 73 (AOP [2]) is set to “H”, whereby the transistor 53 [2] is turned on. Further, by setting the wiring 73 (AOP [1]) to “L”, the transistor 53 [1] is turned off. At this time, a current corresponding to the difference detected by the pixel 11 [n, 2] is supplied to the wiring 156 (VOUT [2]). Here, assuming that the current value of the current supplied to the wiring 156 (VOUT [2]) is “I0 + ΔI2”, the current value of the current Ip [2] is equal to “I0 + ΔI2”, and the current value of the current Ic [2] is Since the value is equal to “I0”, a current having a current value “ΔI2” flows through the transistor 53 [2] and the transistor 55 [2].

Note that the current value “I0 + ΔI2” is larger than the current value “I0”. This means that when the pixel 11 [2, 2] acquires the imaging data of the frame for detecting a difference, the illuminance of the light radiated to the photoelectric conversion element 120 indicates that the pixel 11 [2, 2] has the imaging data of the reference frame. This corresponds to a case where the illuminance is lower than the illuminance of the light emitted to the photoelectric conversion element 120 when acquiring.

Here, the current “I ⁺ ” is supplied by the operation of the comparator 65 and the transistor 58. Here, when the current “I ⁺ ” flowing from the transistor 55 [2] to the transistor 58 is smaller (greater) than “ΔI2”, the potential of the + terminal of the comparator 65 is increased (decreased), and the output of the comparator is Rise (decrease). That is, the gate voltage of the transistor 58 is increased (decreased), so that a larger (smaller) current “I ⁺ ” can be supplied.

Since the same potential as the gate of the transistor 58 is applied to the transistor 59, a current “n2 · I ⁺ ” obtained by multiplying the transistor 59 with respect to the transistor 58 by the W / L ratio (n2) flows through the transistor 59. The current flowing through the transistor 59 also flows through the transistor 60, and further, the current “n3 · n2 · I ⁺ ” obtained by multiplying the W / L ratio (n3) of the transistor 61 with respect to the transistor 60 flows through the transistor 61. Then, the signal 36 (TRIG) becomes “H” by the buffer including the transistor 62, the transistor 57, and the transistor 61.

At the time T33, the wiring 53 (AOP [2]) is set to “L”, whereby the transistor 53 [2] is turned off. At the time T34, the wiring 73 (AOP [m]) is set to “H”, whereby the transistor 53 [m] is turned on. At this time, a current corresponding to the difference detected by the pixel 11 [n, m] is supplied to the wiring 156 (VOUT [m]). Here, assuming that the difference in the pixel 11 [n, m] is zero, the current value of the current supplied to the wiring 156 (VOUT [m]) is “I0”. Further, the current value of the current Ip [m] is equal to “I0”, and the current value of the current Ic [m] is also equal to “I0”.

At the time T35, the wiring 165 (SEL [n]), the wiring 70 (ABU), and the wiring 73 (AOP [m]) are set to “L”, so that the transistor 135 included in the pixel 11 in the n-th row and the transistor 50 [1] to 50 [m] and the transistor 53 [m] are turned off. Thus, the difference detection of the pixels 11 in the n-th row is completed.

With the above structure, according to one embodiment of the present invention, a signal 36 (TRIG) for rewriting image data can be generated with a simple structure without requiring digital processing in detecting a difference. In addition, the wiring 73 (AOP) is separated into the wirings 73 (AOP [1] to [m]) and electrically connected to the transistors 53 [1] to [m], respectively. This makes it possible to specify the pixel 11 from which the difference has been detected.

Note that even when the pixel 11 has a configuration other than the configuration illustrated in FIG. 5, the circuit 16 having the configuration illustrated in FIG. 17 can be used. For the operation of the circuit 16 in the case where the pixel 11 has a structure other than that illustrated in FIG. 5, the timing chart illustrated in FIG. 18 can be referred to as appropriate.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, a specific structure example of an imaging device of one embodiment of the present invention will be described with reference to drawings.

FIG. 19A is an example of a cross-sectional view of an imaging device of one embodiment of the present invention, which illustrates an example of a specific connection mode of the photoelectric conversion element 120, the transistor 131, and the transistor 132 in the pixel 11 illustrated in FIG. ing. Note that the transistors 133 to 135 are not illustrated in FIG. The imaging device includes a layer 1100 provided with the transistors 131 to 135 and a layer 1200 provided with the photoelectric conversion element 120.

Note that, in the cross-sectional views described in this embodiment, each wiring, each electrode, and each conductor 91 are illustrated as individual elements, but when they are electrically connected, the same element is used. It may be provided as. In addition, a mode in which the gate, the source, or the drain of the transistor is connected to each wiring through the conductor 91 is an example, and each of the gate, the source, or the drain of the transistor may have a function as a wiring.

In addition, an insulating layer 92 and an insulating layer 93 which can function as a protective film, an interlayer insulating layer, or a planarization film are provided over each element. For example, as the insulating layer 92 and the insulating layer 93, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. Alternatively, an organic insulating film such as an acrylic resin or a polyimide resin may be used. It is preferable that the upper surfaces of the insulating layer 92, the insulating layer 93, and the like be subjected to a planarization treatment by a CMP (Chemical Mechanical Polishing) method or the like as necessary.

Note that in some cases, some of the wirings and the like illustrated in the drawing are not provided, and wirings and the like or transistors and the like not illustrated in the drawing are included in each layer. Further, a layer not illustrated in the drawings may be included in the stacked structure in some cases. In some cases, some of the layers illustrated in the drawings are not included.

Note that although FIG. 19A illustrates an example in which each transistor has a back gate, a structure without a back gate may be used as illustrated in FIG. 19B. Further, as illustrated in FIG. 19C, only part of the transistors, for example, the transistor 131 may have a back gate. In some cases, the back gate is electrically connected to a front gate of a transistor provided so as to face the back gate. Alternatively, a fixed potential different from that of the front gate may be supplied to the back gate. Note that the mode relating to the presence or absence of the back gate can be applied to other modes of the imaging device described in this embodiment.

Various types of elements can be used for the photoelectric conversion element 120 provided in the layer 1200. FIG. 19A illustrates an embodiment in which a selenium-based material is used for the photoelectric conversion layer 121. The photoelectric conversion element 120 using a selenium-based material has high external quantum efficiency for visible light. The photoelectric conversion element can be a high-sensitivity sensor in which the amount of electrons amplified by the amount of light incident due to the avalanche phenomenon is large. In addition, since the selenium-based material has a high light absorption coefficient, it has an advantage that the photoelectric conversion layer 121 can be easily thinned.

As the selenium-based material, amorphous selenium or crystalline selenium can be used. As an example, crystalline selenium can be obtained by forming amorphous selenium into a film and then performing heat treatment. Note that by making the crystal grain size of crystalline selenium smaller than the pixel pitch, it is possible to reduce variation in characteristics between pixels. In addition, crystalline selenium has a higher spectral sensitivity to visible light and a higher light absorption coefficient than amorphous selenium.

Further, the photoelectric conversion layer 121 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used. With CIS and CIGS, a photoelectric conversion element capable of utilizing an avalanche phenomenon can be formed as in the case of a single layer of selenium.

The photoelectric conversion element 120 using a selenium-based material can have a structure in which the photoelectric conversion layer 121 is provided between the electrode 126 formed using a metal material or the like and the light-transmitting conductive layer 122, for example. Further, CIS and CIGS are p-type semiconductors, and cadmium sulfide, zinc sulfide, or the like of an n-type semiconductor may be provided in contact therewith to form a junction.

In order to generate the avalanche phenomenon, it is preferable to apply a relatively high voltage (for example, 10 V or more) to the photoelectric conversion element. Since the OS transistor has a higher drain breakdown voltage than the Si transistor, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, by combining an OS transistor with a high drain withstand voltage and a photoelectric conversion element using a selenium-based material as a photoelectric conversion layer, an imaging device with high sensitivity and high reliability can be provided.

Note that although the photoelectric conversion layer 121 and the light-transmitting conductive layer 122 are not separated between circuits in FIG. 19A, they may be separated from each other as illustrated in FIG. It is preferable that a partition 127 made of an insulator be provided between pixels in a region where the electrode 126 is not provided so that a crack does not enter the photoelectric conversion layer 121 and the light-transmitting conductive layer 122. A structure without the partition wall 127 as shown in FIG. 19A illustrates a structure in which the wiring 95 and the conductor 91 are interposed between the light-transmitting conductive layer 122 and the wiring 94, but FIGS. 20C and 20D illustrate the structure. As described above, the light-transmitting conductive layer 122 and the wiring 94 may be in direct contact with each other.

Further, the electrode 126, the wiring 94, and the like may be a multilayer. For example, as illustrated in FIG. 21A, the electrode 126 can have two layers of a conductive layer 126a and a conductive layer 126b, and the wiring 94 can have two layers of a conductive layer 94a and a conductive layer 94b. In the structure of FIG. 21A, for example, the conductive layer 126a and the conductive layer 94a are formed by selecting a low-resistance metal or the like, and the conductive layer 126b is selected by a metal or the like having good contact characteristics with the photoelectric conversion layer 121. It is good to form. With such a structure, the electrical characteristics of the photoelectric conversion element can be improved. In addition, some metals may cause electrolytic corrosion by coming into contact with the light-transmitting conductive layer 122. Even when such a metal is used for the conductive layer 94a, electric corrosion can be prevented through the conductive layer 94b.

For the conductive layer 126a and the conductive layer 94a, for example, aluminum, titanium, or a stack in which aluminum is sandwiched between titanium can be used. For the conductive layer 126b and the conductive layer 94b, for example, molybdenum, tungsten, or the like can be used.

Further, a configuration in which the insulating layer 92 and the like are multilayered may be employed. For example, as illustrated in FIG. 21B, in the case where the insulating layer 92 includes an insulating layer 92a and an insulating layer 92b, and the etching rates and the like of the insulating layer 92a and the insulating layer 92b are different, the conductor 91 Will have. Similarly, when the interlayer insulating layer and other insulating layers used for the flattening film are multilayered, the conductor 91 similarly has a step. Although the example in which the insulating layer 92 has two layers is described here, the insulating layer 92 and the other insulating layers may have three or more layers.

Note that the partition wall 127 can be formed using an inorganic insulator, an insulating organic resin, or the like. Further, the partition wall 127 may be colored black or the like to block light from a transistor or the like and / or to determine the area of the light receiving portion per pixel.

Further, as the photoelectric conversion element 120, a pin diode element using an amorphous silicon film, a microcrystalline silicon film, or the like may be used.

For example, FIG. 22 illustrates an example in which a pin thin-film photodiode is used for the photoelectric conversion element 120. The photodiode has a structure in which a p-type semiconductor layer 125, an i-type semiconductor layer 124, and an n-type semiconductor layer 123 are sequentially stacked. It is preferable to use amorphous silicon for the i-type semiconductor layer 124. For the n-type semiconductor layer 123 and the p-type semiconductor layer 125, amorphous silicon, microcrystalline silicon, or the like containing a dopant imparting each conductivity type can be used. A photodiode using amorphous silicon as a photoelectric conversion layer has high sensitivity in the wavelength region of visible light and can easily detect weak visible light.

In the photoelectric conversion element 120 illustrated in FIG. 22, the p-type semiconductor layer 125 and the electrode 126 are electrically connected. The n-type semiconductor layer 123 is electrically connected to the wiring 94 via the conductor 91.

FIGS. 23A, 23B, 23C, 23D, and 23D show the structure of the photoelectric conversion element 120 having the form of a pin-type thin film photodiode and the connection form of the photoelectric conversion element 120 and the wiring. Examples shown in (E) and (F) may be used. Note that the configuration of the photoelectric conversion element 120 and the form of connection between the photoelectric conversion element 120 and the wiring are not limited thereto, and may be other forms.

FIG. 23A illustrates a structure in which a light-transmitting conductive layer 122 in contact with an n-type semiconductor layer 123 of a photoelectric conversion element 120 is provided. The light-transmitting conductive layer 122 functions as an electrode and can increase the output current of the photoelectric conversion element 120.

The light-transmitting conductive layer 122 includes, for example, indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, and fluorine. Tin oxide containing tin, tin oxide containing antimony, graphene, or the like can be used. Further, the light-transmitting conductive layer 122 is not limited to a single layer, and may be a stack of different films.

FIG. 23B illustrates a structure in which the n-type semiconductor layer 123 of the photoelectric conversion element 120 and the wiring 95 are directly connected.

FIG. 23C illustrates a structure in which the light-transmitting conductive layer 122 in contact with the n-type semiconductor layer 123 of the photoelectric conversion element 120 is provided, and the wiring 95 and the light-transmitting conductive layer 122 are electrically connected to each other. .

In FIG. 23D, an opening for exposing the n-type semiconductor layer 123 is provided in an insulating layer covering the photoelectric conversion element 120, and the light-transmitting conductive layer 122 covering the opening is electrically connected to the wiring 95. Configuration.

FIG. 23E illustrates a structure in which a conductor 91 penetrating the photoelectric conversion element 120 is provided. In this structure, the wiring 94 is electrically connected to the n-type semiconductor layer 123 through the conductor 91. Note that the drawing shows a form in which the wiring 94 and the electrode 126 are apparently electrically connected via the p-type semiconductor layer 125. However, since the p-type semiconductor layer 125 has a high electrical resistance in the lateral direction, if an appropriate space is provided between the wiring 94 and the electrode 126, the resistance between the two becomes extremely high. Therefore, the photoelectric conversion element 120 can have a diode characteristic without a short circuit between the anode and the cathode. Note that the number of the conductors 91 electrically connected to the n-type semiconductor layer 123 may be plural.

FIG. 23F illustrates a structure in which the light-transmitting conductive layer 122 which is in contact with the n-type semiconductor layer 123 is provided for the photoelectric conversion element 120 in FIG.

Note that the photoelectric conversion element 120 illustrated in FIGS. 23D, 23E, and 23F has an advantage that a wide light receiving area can be secured because a light receiving region and a wiring do not overlap.

Further, as shown in FIG. 24, a photodiode having the silicon substrate 100 as a photoelectric conversion layer can be used for the photoelectric conversion element 120.

The photoelectric conversion element 120 formed using the above-described selenium-based material, amorphous silicon, or the like can be manufactured using a general semiconductor manufacturing process such as a film formation process, a lithography process, or an etching process. Further, the selenium-based material has high resistance, and a structure in which the photoelectric conversion layer 121 is not separated between circuits as illustrated in FIG. Therefore, the imaging device of one embodiment of the present invention can have high yield and can be manufactured at low cost. On the other hand, in the case of forming a photodiode using the silicon substrate 100 as a photoelectric conversion layer, a highly difficult process such as a polishing process or a bonding process is required.

Further, the imaging device of one embodiment of the present invention may have a structure in which the silicon substrates 106 over which circuits are formed are stacked. For example, as illustrated in FIG. 25A, a structure in which a layer 1400 including the transistor 101 and the transistor 102 each including an active region in a silicon substrate 106 overlaps with a pixel circuit can be employed. Note that FIG. 25B corresponds to a cross-sectional view of the transistor in the channel width direction.

The circuit formed over the silicon substrate 106 can have a function of reading a signal output from the pixel circuit, a function of converting the signal, and the like; for example, a circuit illustrated in FIG. A configuration including a CMOS inverter can be adopted. The gate of the transistor 101 (n-ch type) and the gate of the transistor 102 (p-ch type) are electrically connected to each other. One of a source and a drain of one transistor is electrically connected to one of a source and a drain of the other transistor. The other of the source and the drain of both transistors is electrically connected to different wirings.

Further, the silicon substrate 100 and the silicon substrate 106 are not limited to a bulk silicon substrate, and a substrate made of germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used. it can.

Here, as shown in FIGS. 24 and 25A, insulation is provided between a region where a transistor including an oxide semiconductor is formed and a region where a Si device (Si transistor or Si photodiode) is formed. A layer 96 is provided.

Hydrogen in the insulating layer provided near the active region of the transistor 101 and the transistor 102 terminates a dangling bond of silicon. Therefore, the hydrogen has an effect of improving the reliability of the transistor 101 and the transistor 102. On the other hand, hydrogen in an insulating layer provided in the vicinity of an oxide semiconductor layer which is an active layer of the transistor 131 or the like is one of the factors which generate carriers in the oxide semiconductor layer. Therefore, the hydrogen may cause a reduction in reliability of the transistor 131 and the like in some cases. Therefore, in the case where one layer including a Si transistor and the other layer including an OS transistor are stacked, an insulating layer 96 which can have a function of preventing diffusion of hydrogen is preferably provided therebetween. By confining hydrogen in one layer with the insulating layer 96, the reliability of the transistor 101 and the transistor 102 can be improved. In addition, by suppressing diffusion of hydrogen from one layer to the other layer, reliability of the transistor 131 and the like can be improved.

Examples of the insulating layer 96 include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and yttria-stabilized zirconia (YSZ). Can be used.

Note that in the structure illustrated in FIG. 25A, a circuit (eg, a driver circuit) formed over the silicon substrate 106, the transistor 131, and the photoelectric conversion element 120 can be formed so as to overlap with each other. , The degree of integration of pixels can be increased. That is, the resolution of the imaging device can be increased. For example, it is suitable for use in an imaging device having 4K2K, 8K4K, or 16K8K pixels. Note that an 8K4K imaging device has about 33 million pixels, and thus can be referred to as 33M. Further, for example, the transistor 134 and the transistor 135 included in the pixel 11 are formed using Si transistors, and the transistor 131, the transistor 132, the transistor 133, and the photoelectric conversion element 120 are provided with a region where the transistor 134 and the transistor 135 overlap with each other. Can also. In this case, the transistors 131, 132, and 133 are formed using OS transistors.

The imaging device illustrated in FIG. 25A has a structure in which the silicon substrate 106 is not provided with a photoelectric conversion element. Therefore, an optical path to the photoelectric conversion element 120 can be secured without being affected by various transistors and wirings, and a pixel with a high aperture ratio can be formed.

Although FIGS. 25A and 25B illustrate a fin-type configuration of the Si transistor, the Si transistor may be of a planar type as shown in FIG. 26A. Alternatively, as illustrated in FIG. 26B, a transistor including a silicon thin film active layer 105 may be used. Further, the active layer 105 can be polycrystalline silicon or single crystal silicon of SOI (Silicon on Insulator).

The imaging device of one embodiment of the present invention can have a structure illustrated in FIG.

The imaging device illustrated in FIG. 27 is a modification example of the imaging device illustrated in FIG. 25A and illustrates an example in which a CMOS inverter includes OS transistors and Si transistors.

Here, the transistor 102 which is a Si transistor provided in the layer 1400 is a p-ch transistor and the transistor 101 which is an OS transistor provided in the layer 1100 is an n-ch transistor. By providing only the p-ch transistor on the silicon substrate 106, steps such as formation of a well and formation of an n-type impurity layer can be omitted.

Although the imaging device illustrated in FIG. 27 illustrates an example in which selenium or the like is used for the photoelectric conversion element 120, a configuration using a pin-type thin film photodiode may be used as in FIG.

In the imaging device illustrated in FIGS. 27A and 27B, the transistor 101 can be manufactured in the same process as the transistors 131 and 132 formed in the layer 1100. Therefore, the manufacturing process of the imaging device can be simplified.

In addition, as illustrated in FIG. 28, the imaging device of one embodiment of the present invention includes a structure including a photodiode formed over a silicon substrate 100 and a pixel formed using an OS transistor formed thereover, and a circuit formed thereover. A configuration may be adopted in which the bonded silicon substrate 106 is bonded. With such a configuration, the effective area of the photodiode formed on the silicon substrate 100 can be easily improved. In addition, a high-performance semiconductor device can be provided by highly integrating a circuit formed over the silicon substrate 106 using a miniaturized Si transistor.

FIG. 29A is a cross-sectional view of an example in which a color filter and the like are added to the imaging device. The cross-sectional view shows a part of a region having a pixel circuit for three pixels. An insulating layer 2500 is formed over the layer 1200 where the photoelectric conversion element 120 is formed. As the insulating layer 2500, a silicon oxide film with high light-transmitting property with respect to visible light can be used. Further, a structure in which a silicon nitride film is stacked as a passivation film may be employed. Further, a configuration in which a dielectric film such as hafnium oxide is stacked as the antireflection film may be adopted.

A light-blocking layer 2510 may be formed over the insulating layer 2500. The light-blocking layer 2510 can have a function of preventing color mixture of light passing through the upper color filter. The light-blocking layer 2510 can have a structure in which a metal layer of aluminum, tungsten, or the like, or a stack of the metal layer and a dielectric film which can function as an anti-reflection film can be provided.

An organic resin layer 2520 can be provided as a planarization film over the insulating layer 2500 and the light-blocking layer 2510. Further, a color filter 2530 (color filter 2530a, color filter 2530b, color filter 2530c) is formed for each pixel. For example, colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) are assigned to the color filters 2530a, 2530b, and 2530c. Thus, a color image can be obtained.

Over the color filter 2530, a light-transmitting insulating layer 2560 or the like can be provided.

Further, as shown in FIG. 29B, an optical conversion layer 2550 may be used instead of the color filter 2530. With such a configuration, an imaging device that can obtain images in various wavelength regions can be provided.

For example, if a filter that blocks light having a wavelength equal to or shorter than the wavelength of visible light is used for the optical conversion layer 2550, an infrared imaging device can be obtained. Further, when a filter that blocks light having a wavelength of near infrared rays or less is used for the optical conversion layer 2550, a far-infrared imaging device can be obtained. When a filter that blocks light having a wavelength equal to or longer than the wavelength of visible light is used for the optical conversion layer 2550, an ultraviolet imaging device can be obtained.

In addition, when a scintillator is used for the optical conversion layer 2550, an imaging device that can be used for an X-ray imaging device and obtains an image in which the intensity of radiation is visualized can be obtained. When radiation such as X-rays transmitted through a subject enters a scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a phenomenon called photoluminescence. Then, imaging data is obtained by detecting the light with the photoelectric conversion element 120. Further, the imaging device having the above configuration may be used for a radiation detector or the like.

The scintillator is made of a substance that emits visible light or ultraviolet light when irradiated with radiation such as X-rays or gamma rays, or a material containing the substance. For example, Gd ₂ O ₂ S: Tb, Gd ₂ O ₂ S: Pr, Gd ₂ O ₂ S: Eu, BaFCl: Eu, NaI, CsI, CaF ₂ , BaF ₂ , CeF ₃ , LiF, LiI, ZnO, etc. Materials and those obtained by dispersing them in resin or ceramics are known.

Note that in the photoelectric conversion element 120 using a selenium-based material, radiation such as X-rays can be directly converted into electric charge, so that a structure in which a scintillator is unnecessary can be employed.

A microlens array 2540 may be provided over the color filters 2530a, 2530b, and 2530c. Light that passes through the individual lenses of the microlens array 2540 passes through the color filter immediately below and irradiates the photoelectric conversion element 120. Note that a region other than the layer 1200 illustrated in FIGS. 29A, 29B, and 29C is referred to as a layer 1600.

The specific structure of the imaging device illustrated in FIG. 29C is as illustrated in FIG. 30 taking the imaging device illustrated in FIG. 19A as an example. FIG. 31 shows an example of the imaging apparatus shown in FIG.

The imaging device of one embodiment of the present invention may be combined with a diffraction grating 1500 as illustrated in FIGS. An image of the subject (diffraction image) via the diffraction grating 1500 is captured by the pixel, and an input image (image of the subject) can be formed from the captured image of the pixel by arithmetic processing. Further, by using the diffraction grating 1500 instead of the lens, the cost of the imaging device can be reduced.

The diffraction grating 1500 can be formed using a light-transmitting material. For example, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. Alternatively, an organic insulating film such as an acrylic resin or a polyimide resin may be used. Alternatively, a stack of the inorganic insulating film and the organic insulating film may be used.

Further, the diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. Further, it can be formed using a lithography step and an etching step. Further, it can be formed using nanoimprint lithography, laser scribe, or the like.

Note that an interval X may be provided between the diffraction grating 1500 and the microlens array 2540. The interval X can be 1 mm or less, preferably 100 μm or less. Note that the space may be a space or a light-transmitting material may be provided as a sealing layer or an adhesive layer. For example, an inert gas such as nitrogen or a rare gas can be sealed in the space. Alternatively, an acrylic resin, an epoxy resin, a polyimide resin, or the like may be provided at the interval. Alternatively, a liquid such as silicone oil may be provided. Note that even when the microlens array 2540 is not provided, an interval X may be provided between the color filter 2530 and the diffraction grating 1500.

Further, the imaging device of one embodiment of the present invention may be curved as illustrated in FIGS. 34A1 and 34B1. FIG. 34A1 shows a state in which the imaging device is curved in the direction of a two-dot chain line X1-X2 in FIG. FIG. 34 (A2) is a cross-sectional view of a portion indicated by a two-dot chain line X1-X2 in FIG. 34 (A1). FIG. 34 (A3) is a cross-sectional view of a portion indicated by a two-dot chain line Y1-Y2 in FIG. 34 (A1).

FIG. 34 (B1) shows a state in which the imaging device is curved in the direction of dashed-dotted line X3-X4 in FIG. 34 and also in the direction of dashed-dotted line Y3-Y4 in FIG. FIG. 34 (B2) is a cross-sectional view of a portion indicated by a two-dot chain line X3-X4 in FIG. 34 (B1). FIG. 34 (B3) is a cross-sectional view of a portion indicated by a two-dot chain line Y3-Y4 in FIG. 34 (B1).

Curving the imaging device can reduce field curvature and astigmatism. Therefore, optical design of a lens and the like used in combination with the imaging device can be facilitated. For example, since the number of lenses for correcting aberration can be reduced, the size and weight of a semiconductor device or the like using an imaging device can be easily reduced. Further, the quality of a captured image can be improved.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 6)
In the present embodiment, the structure of the display device 23 will be described in detail with reference to the drawings.

FIG. 35 is a circuit diagram illustrating a configuration example of the pixel 210 included in the display device 23. FIG. 35A illustrates an example of a pixel using a liquid crystal element as a display element, and FIG. 35B illustrates an example of a pixel using a light-emitting element as a display element.

A pixel 210 illustrated in FIG. 35A includes a transistor 211, a liquid crystal element 212, and a capacitor 213.

A wiring 215 is electrically connected to a gate of the transistor 211. A wiring 216 is electrically connected to one of a source and a drain of the transistor 211. In addition, one terminal of the liquid crystal element 212 and one terminal of the capacitor 213 are electrically connected to the other of the source and the drain of the transistor 211.

The transistor 211 can function as a switching element for controlling electrical connection between the liquid crystal element 212 and the wiring 216, and is turned on and off by a scan signal input from the wiring 215. Note that as the transistor 211, an OS transistor which can reduce off-state current is preferable.

The pixel 210 illustrated in FIG. 35B includes a transistor 221, a transistor 222, and a light-emitting element 223.

A wiring 215 is electrically connected to a gate of the transistor 221. The wiring 216 is electrically connected to one of a source and a drain of the transistor 221. The other of the source and the drain of the transistor 221 is electrically connected to the gate of the transistor 222. A wiring 217 is electrically connected to one of a source and a drain of the transistor 222. Further, one terminal of the light-emitting element 223 is electrically connected to the other of the source and the drain of the transistor 222.

The transistor 221 is a switching element that controls electrical connection between the gate of the transistor 222 and the wiring 216, and is turned on and off by a scan signal input from the wiring 215. Note that an OS transistor which can reduce off-state current is preferably used as the transistor 221.

In the circuit diagrams illustrated in FIGS. 35A and 35B, “OS” is added to a circuit symbol of the OS transistor in order to clearly indicate that the transistor is an OS transistor.

Note that the pixel 210 only needs to be able to hold image data in the second mode in which the imaging data 31 is not output. For this reason, the invention is not limited to the structure using a transistor with low off-state current. The pixel 210 may have a configuration including a memory capable of holding image data.

FIG. 36A illustrates a structure including a memory in the pixel 210. The pixel 210 can hold video data by including the memory 214. As a memory, a memory circuit in an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory) may be used. FIG. 36B illustrates an example of a circuit diagram in the case where an SRAM is applied to the memory 214.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 7)
In this embodiment, a transistor including an oxide semiconductor which can be used in one embodiment of the present invention will be described with reference to drawings. In the drawings of the present embodiment, some elements are enlarged, reduced, or omitted for clarity.

FIG. 37A is a top view of a transistor 401 of one embodiment of the present invention. A cross section in the direction of dashed-dotted line B1-B2 in FIG. 37A corresponds to FIG. A cross section in the direction of dashed-dotted line B3-B4 in FIG. 37A corresponds to FIG. Note that the direction of the dashed line B1-B2 may be referred to as a channel length direction, and the direction of the dashed line B3-B4 may be referred to as a channel width direction.

The transistor 401 includes a substrate 415, an insulating layer 420, an oxide semiconductor layer 430, a conductive layer 440, a conductive layer 450, an insulating layer 460, a conductive layer 470, an insulating layer 475, an insulating layer 480, Having.

The insulating layer 420 is in contact with the substrate 415, the oxide semiconductor layer 430 is in contact with the insulating layer 420, the conductive layers 440 and 450 are in contact with the insulating layer 420 and the oxide semiconductor layer 430, and the insulating layer 460 is The semiconductor layer 430, the conductive layer 440, and the conductive layer 450 are in contact with each other, the conductive layer 470 is in contact with the insulating layer 460, the insulating layer 475 is in contact with the insulating layer 420, the conductive layer 440, the conductive layer 450, and the conductive layer 470, and the insulating layer 480 is formed. Is in contact with the insulating layer 475.

Here, in the oxide semiconductor layer 430, a region overlapping with the conductive layer 440 is referred to as a region 531, a region overlapping with the conductive layer 450 is referred to as a region 532, and a region overlapping with the insulating layer 460 is referred to as a region 533.

Further, the conductive layers 440 and 450 are electrically connected to the oxide semiconductor layer 430.

The conductive layer 440 can function as a source or a drain, the conductive layer 450 can function as a source or a drain, the insulating layer 460 can function as a gate insulating layer, and the conductive layer 470 can function as a gate.

In addition, a region 531 illustrated in FIG. 37B can function as a source region or a drain region, the region 532 can function as a source region or a drain region, and the region 533 can function as a channel formation region.

Although the example in which the conductive layer 440 and the conductive layer 450 are formed as a single layer is illustrated, two or more layers may be stacked. Further, the example in which the conductive layer 470 is formed with two layers of the conductive layer 471 and the conductive layer 472 is illustrated; however, a single layer or a stack of three or more layers may be used. This structure can be applied to the other transistors described in this embodiment.

Note that a function as a planarization film may be added to the insulating layer 480 as necessary.

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 37C is a top view of the transistor 402. A cross section in the direction of dashed-dotted line C1-C2 in FIG. 37C corresponds to FIG. A cross section in the direction of dashed-dotted line C3-C4 in FIG. 37C corresponds to FIG. 39B. The direction of the dashed line C1-C2 may be referred to as a channel length direction, and the direction of the dashed line C3-C4 may be referred to as a channel width direction.

The transistor 402 is different from the transistor 401 in that an end portion of the insulating layer 460 does not coincide with an end portion of the conductive layer 470. In the structure of the transistor 402, since the conductive layers 440 and 450 are widely covered with the insulating layer 460, the electric resistance between the conductive layers 440 and 450 and the conductive layer 470 is high, and the gate leakage current is small. Has features.

Each of the transistors 401 and 402 has a top-gate structure including a region where the conductive layer 470 overlaps with the conductive layers 440 and 450. It is preferable that the width of the region in the channel length direction be 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. In this structure, since an offset region is not formed in the oxide semiconductor layer 430, a transistor with high on-state current is easily formed.

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 37E is a top view of the transistor 403. A cross section in the direction of dashed-dotted line D1-D2 in FIG. 37E corresponds to FIG. A cross section in the direction of dashed-dotted line D3-D4 in FIG. 37E corresponds to FIG. The direction of the dashed line D1-D2 may be referred to as a channel length direction, and the direction of the dashed line D3-D4 may be referred to as a channel width direction.

The insulating layer 420 of the transistor 403 is in contact with the substrate 415, the oxide semiconductor layer 430 is in contact with the insulating layer 420, the insulating layer 460 is in contact with the insulating layer 420 and the oxide semiconductor layer 430, the conductive layer 470 is in contact with the insulating layer 460, The insulating layer 475 is in contact with the insulating layer 420, the oxide semiconductor layer 430, and the conductive layer 470, the insulating layer 480 is in contact with the insulating layer 475, and the conductive layers 440 and 450 are in contact with the oxide semiconductor layer 430 and the insulating layer 480.

Openings are provided in the insulating layers 475 and 480, and the conductive layers 440 and 450 are electrically connected to the oxide semiconductor layer 430 through the openings.

Note that an insulating layer (a planarizing film) which is in contact with the conductive layer 440, the conductive layer 450, and the insulating layer 480 may be provided as necessary.

In the oxide semiconductor layer 430, a region which overlaps with the insulating layer 475 and is sandwiched between the region 531 and the region 533 is referred to as a region 534. A region that overlaps with the insulating layer 475 and is sandwiched between the region 532 and the region 533 is referred to as a region 535.

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 38A is a top view of the transistor 404. FIG. A cross section in the direction of dashed-dotted line E1-E2 in FIG. 38A corresponds to FIG. A cross section in the direction of dashed-dotted line E3-E4 in FIG. 38A corresponds to FIG. Note that the direction of the dashed line E1-E2 may be referred to as a channel length direction, and the direction of the dashed line E3-E4 may be referred to as a channel width direction.

The insulating layer 420 of the transistor 404 is in contact with the substrate 415, the oxide semiconductor layer 430 is in contact with the insulating layer 420, the conductive layers 440 and 450 are in contact with the insulating layer 420 and the oxide semiconductor layer 430, and the insulating layer 460 is an insulating layer. 420 and the oxide semiconductor layer 430; the conductive layer 470 is in contact with the insulating layer 460; the insulating layer 475 is in contact with the insulating layer 420, the oxide semiconductor layer 430, the conductive layer 440, the conductive layer 450, and the conductive layer 470; 480 is in contact with the insulating layer 475.

The transistor 404 is different from the transistor 403 in that the conductive layers 440 and 450 are in contact with each other so as to cover end portions of the oxide semiconductor layer 430.

The transistors 403 and 404 have a self-aligned structure in which the conductive layer 470 does not have a region where the conductive layer 440 and the conductive layer 450 overlap with each other. A transistor having a self-aligned structure has extremely small parasitic capacitance between a gate, a source, and a drain, and thus is suitable for high-speed operation.

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 38C is a top view of the transistor 405. FIG. A cross section in the direction of dashed-dotted line F1-F2 in FIG. 38C corresponds to FIG. A cross section in the direction of dashed-dotted line F3-F4 in FIG. 38C corresponds to FIG. Note that the direction of the dashed line F1-F2 may be referred to as a channel length direction, and the direction of the dashed line F3-F4 may be referred to as a channel width direction.

In the transistor 405, the conductive layer 440 is formed using two layers of a conductive layer 441 and a conductive layer 442, and the conductive layer 450 is formed using two layers of a conductive layer 451 and a conductive layer 452. The insulating layer 420 is in contact with the substrate 415, the oxide semiconductor layer 430 is in contact with the insulating layer 420, the conductive layers 441 and 451 are in contact with the oxide semiconductor layer 430, and the insulating layer 460 is an insulating layer 420 and an oxide semiconductor. The layers 430, 441, and 451 are in contact with each other, the conductive layer 470 is in contact with the insulating layer 460, the insulating layer 475 is in contact with the insulating layers 420, 441, 451, and 470, and the insulating layer 480 is insulated. The conductive layer 442 is in contact with the conductive layer 451 and the insulating layer 480, and the conductive layer 452 is in contact with the conductive layer 451 and the insulating layer 480.

Here, the conductive layers 441 and 451 are in contact with the top surface of the oxide semiconductor layer 430 and not with the side surfaces.

Note that an insulating layer which is in contact with the conductive layer 442, the conductive layer 452, and the insulating layer 480 may be provided as necessary.

Further, the conductive layers 441 and 451 are electrically connected to the oxide semiconductor layer 430. The conductive layer 442 is electrically connected to the conductive layer 441, and the conductive layer 452 is electrically connected to the conductive layer 451.

In the oxide semiconductor layer 430, a region overlapping with the conductive layer 441 becomes a region 531 which can function as one of a source region and a drain region, and a region overlapping with the conductive layer 451 functions as the other of the source region and the drain region. Region 532 that can have

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 38E is a top view of the transistor 406. A cross section in the direction of dashed-dotted line G1-G2 in FIG. 38E corresponds to FIG. A cross section in the direction of dashed-dotted line G3-G4 in FIG. 38E corresponds to FIG. Note that the direction of the dashed line G1-G2 may be referred to as a channel length direction, and the direction of the dashed line G3-G4 may be referred to as a channel width direction.

The transistor 406 is different from the transistor 403 in that a conductive layer 440 is formed using two layers of a conductive layer 441 and a conductive layer 442, and a conductive layer 450 is formed using two layers of a conductive layer 451 and a conductive layer 452.

In the structure of the transistor 405 and the transistor 406, the conductive layer 440 and the conductive layer 450 are not in contact with the insulating layer 420; therefore, oxygen in the insulating layer 420 is less likely to be taken by the conductive layer 440 and the conductive layer 450; Supply of oxygen from the 420 to the oxide semiconductor layer 430 can be facilitated.

Note that an impurity for forming oxygen vacancies and increasing conductivity may be added to the regions 534 and 535 in the transistors 403, 404, and 406. As an impurity which forms an oxygen vacancy in the oxide semiconductor layer, for example, phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, And at least one selected from carbon and carbon. As a method for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

When the above element is added to the oxide semiconductor layer as an impurity element, the bond between the metal element and oxygen in the oxide semiconductor layer is cut, so that oxygen vacancies are formed. The interaction between oxygen vacancies contained in the oxide semiconductor layer and hydrogen remaining in the oxide semiconductor layer or added later can increase the conductivity of the oxide semiconductor layer.

Note that when hydrogen is added to an oxide semiconductor in which an oxygen vacancy is formed by addition of an impurity element, hydrogen enters an oxygen vacancy site and forms a donor level in the vicinity of a conduction band. As a result, an oxide conductor can be formed. Here, the oxide semiconductor which is turned into a conductor is referred to as an oxide conductor. Note that the oxide conductor has a light-transmitting property like an oxide semiconductor.

The oxide conductor is a degenerate semiconductor, and it is assumed that the conduction band edge and the Fermi level match or substantially match. Therefore, contact between the oxide conductor layer and the conductive layer which can function as a source and a drain is ohmic contact, and the oxide conductor layer and the conductive layer which can function as a source and a drain. The contact resistance with the layer can be reduced.

In addition, in the transistors 401 to 406 in FIGS. 37 to 39, the example in which the oxide semiconductor layer 430 is a single layer is illustrated; however, the oxide semiconductor layer 430 may be a stacked layer. FIG. 40A is a top view of the oxide semiconductor layer 430, and FIGS. 40B and 40C are oxide semiconductor layers 430 having a two-layer structure of the oxide semiconductor layer 430a and the oxide semiconductor layer 430b. FIG. FIGS. 40D and 40E are cross-sectional views of the oxide semiconductor layer 430 having a three-layer structure of the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c.

Note that the oxide semiconductor layer 430a and the oxide semiconductor layer 430c can be referred to as insulating layers because no channel region is formed.

For the oxide semiconductor layers 430a, 430b, and 430c, oxide semiconductor layers having different compositions can be used.

The oxide semiconductor layer 430 of the transistors 401 to 406 can be replaced with the oxide semiconductor layer 430 illustrated in FIGS. 40B and 40C or FIGS. 40D and 40E.

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. FIGS. 41A, 41C, and 41E are top views of the transistors 407 to 412. FIGS. In addition, cross sections taken along the dashed-dotted lines H1-H2 through M1-M2 in FIGS. 41A, 41C, and 41E and FIGS. 42A, 42C, and 42E are shown in FIG. , (D), (F) and FIGS. 42 (B), (D), (F). FIGS. 43A and 41E show cross sections taken along dashed-dotted lines H3-H4 and J3-J4 to M3-M4 shown in FIGS. Equivalent to. A cross section in the direction of dashed-dotted line I3-I4 in FIG. 41C corresponds to FIG. Note that the dashed lines H1-H2 through M1-M2 may be referred to as channel length directions, and the dashed lines H3-H4 through M1-M2 may be referred to as channel widths.

In the transistor 407 and the transistor 408, the oxide semiconductor layer 430 has two layers (the oxide semiconductor layer 430a and the oxide semiconductor layer 430b) in the region 531 and the region 532, and the oxide semiconductor layer 430 has three layers in the region 533. A part of the oxide semiconductor layer (the oxide semiconductor layer 430 a, the oxide semiconductor layer 430 b, and the oxide semiconductor layer 430 c), and a part of the oxide semiconductor layer (the oxide semiconductor layer 430 and the conductive layer 450). It has a structure similar to that of the transistor 401 and the transistor 402 except that a semiconductor layer 430c) is interposed.

In the transistor 409, the transistor 410, and the transistor 412, the oxide semiconductor layer 430 has two layers (the oxide semiconductor layer 430a and the oxide semiconductor layer 430b) in the region 531, the region 532, the region 534, and the region 535; The transistor has the same structure as the transistor 403, the transistor 404, and the transistor 406 except that the oxide semiconductor layer 430 has three layers (an oxide semiconductor layer 430a, an oxide semiconductor layer 430b, and an oxide semiconductor layer 430c).

In the transistor 411, the region 531 and the region 532 each include two oxide semiconductor layers 430 (an oxide semiconductor layer 430a and an oxide semiconductor layer 430b), and the region 533 includes three oxide semiconductor layers 430 (an oxide semiconductor layer). Layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c), and part of the oxide semiconductor layer (the oxide semiconductor layer 430c) between the conductive layers 441 and 451 and the insulating layer 460. ) Has the same configuration as that of the transistor 405 except that the transistor 405 is interposed.

Further, the transistor of one embodiment of the present invention can be obtained with the use of the transistors in FIGS. 44A, B, C, D, E, and F, and FIGS. 45A, B, and C. , (D), (E), and (F) are cross-sectional views in the channel length direction of the transistors 401 to 412, and FIG. 39C are cross-sectional views in the channel width direction of the transistors 401 to 406 and FIG. A conductive layer 473 may be provided between the oxide semiconductor layer 430 and the substrate 415 as illustrated in a cross-sectional view of the transistors 407 to 412 in the channel width direction illustrated in FIG. With the use of the conductive layer 473 as a second gate (also referred to as a back gate), a channel formation region of the oxide semiconductor layer 430 is electrically surrounded by the conductive layer 470 and the conductive layer 473. Such a structure of a transistor is referred to as a surrounded channel (s-channel) structure. Thereby, the ON current can be increased. Further, the threshold voltage can be controlled. 44 (A), (B), (C), (D), (E), (F) and FIGS. 45 (A), (B), (C), (D), (E), In the cross-sectional view illustrated in FIG. 5F, the width of the conductive layer 473 may be shorter than that of the oxide semiconductor layer 430. Further, the width of the conductive layer 473 may be shorter than the width of the conductive layer 470.

In order to increase the on-state current, for example, the conductive layers 470 and 473 may have the same potential and be driven as a double-gate transistor. In order to control the threshold voltage, a constant potential different from that of the conductive layer 470 may be supplied to the conductive layer 473. In order to make the conductive layer 470 and the conductive layer 473 have the same potential, for example, as shown in FIGS. 39D and 43D, the conductive layer 470 and the conductive layer 473 are electrically connected to each other through a contact hole. Just connect.

The transistor in one embodiment of the present invention can have a structure illustrated in FIGS. 46A, 46B, and 46C. FIG. 46A is a top view. FIG. 46B is a cross-sectional view taken along dashed-dotted line N1-N2 in FIG. FIG. 46C is a cross-sectional view taken along dashed-dotted line N3-N4 in FIG. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

The insulating layer 420 of the transistor 413 is in contact with the substrate 415, the oxide semiconductor layer 430 (the oxide semiconductor layers 430a, 430b, and 430c) is in contact with the insulating layer 420, and the conductive layers 440 and 450 Is in contact with the oxide semiconductor layer 430b, the insulating layer 460 is in contact with the oxide semiconductor layer 430c, the conductive layer 470 is in contact with the insulating layer 460, and the insulating layer 480 is in contact with the insulating layer 420, the conductive layer 440, and the conductive layer 450. Note that the oxide semiconductor layer 430c, the insulating layer 460, and the conductive layer 470 are provided in the insulating layer 480 and provided in an opening reaching the oxide semiconductor layer 430b.

In the structure of the transistor 413, a region where the conductive layer 440 or the conductive layer 450 and the conductive layer 470 overlap with each other is smaller than that of the other transistors described above, so that parasitic capacitance can be reduced. Therefore, the transistor 413 is suitable as an element of a circuit requiring high-speed operation. Note that the top surface of the transistor 413 is preferably planarized by a CMP (Chemical Mechanical Polishing) method or the like as illustrated in FIGS. 46B and 46C, but a structure without planarization may be employed.

The conductive layers 440 and 450 in the transistor of one embodiment of the present invention have a width larger than the width (W _OS ) of the oxide semiconductor layer as illustrated in the top view of FIG. May be formed to have a long width (W _SD ), or may be formed to be short as shown in the top view of FIG. In particular, by setting W _OS ≧ W _SD (W _SD is equal to or less than W _OS ), a gate electric field is easily applied to the entire oxide semiconductor layer 430, so that electric characteristics of the transistor can be improved. Further, as illustrated in FIG. 47C, the conductive layers 440 and 450 may be formed only in a region overlapping with the oxide semiconductor layer 430.

Note that in FIGS. 47A, 47B, and 47C, only the oxide semiconductor layer 430, the conductive layer 440, and the conductive layer 450 are illustrated.

In a transistor including the oxide semiconductor layer 430a and the oxide semiconductor layer 430b and a transistor including the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c, By appropriately selecting a material of the layer or the three layers, current can flow through the oxide semiconductor layer 430b. When a current flows to the oxide semiconductor layer 430b, the oxide semiconductor layer 430b is not easily affected by interface scattering and a high on-state current can be obtained. Therefore, the on-state current may be improved by increasing the thickness of the oxide semiconductor layer 430b.

With the use of the transistor having the above structure, favorable electric characteristics can be given to a semiconductor device.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 8)
In this embodiment, components of the transistor described in Embodiment 6 are described in detail.

The type of the substrate 415 is not limited to a specific type. Examples of the substrate 415 include a semiconductor substrate (eg, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel still substrate, a substrate having a stainless steel foil, tungsten There is a substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of a glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of a flexible substrate, a laminated film, a base film, and the like include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, as an example, there is a synthetic resin such as acrylic. Alternatively, for example, a film made of polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, or the like is used. Alternatively, examples include polyamide, polyimide, aramid, epoxy, an inorganic vapor-deposited film, and paper. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with small variations in characteristics, size, shape, or the like, high current capability, and small size can be manufactured. . When a circuit is formed using such transistors, low power consumption of the circuit or high integration of the circuit can be achieved.

Alternatively, as the substrate 415, a silicon substrate over which a transistor is formed and a silicon substrate over which an insulating layer, a wiring, a conductor capable of functioning as a contact plug, or the like is formed can be used. Note that in the case where only a p-ch transistor is formed over a silicon substrate, a silicon substrate having an n ⁻ conductivity type is preferably used. Alternatively, an SOI substrate having an n ^- type or i-type silicon layer may be used. Further, it is preferable that the plane orientation of the surface on which the transistor is formed in the silicon substrate be the (110) plane. The mobility can be increased by forming a p-ch transistor on the (110) plane.

Alternatively, a flexible substrate may be used as the substrate 415, and a transistor may be directly formed over the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor. The peeling layer can be used to partially or entirely complete a semiconductor device thereon, separate it from a substrate, and transfer it to another substrate. In that case, the transistor can be transferred to a substrate having low heat resistance or a flexible substrate. Note that as the above-described peeling layer, for example, a structure in which an inorganic film of a tungsten film and a silicon oxide film is stacked, a structure in which an organic resin film such as polyimide is formed over a substrate, or the like can be used.

That is, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be provided over another substrate. Examples of a substrate to which a transistor is transferred include a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber, in addition to a substrate on which the above transistor can be formed). (Including silk, cotton, hemp), synthetic fibers (including nylon, polyurethane, and polyester) or recycled fibers (including acetate, cupra, rayon, and recycled polyester), a leather substrate, and a rubber substrate. With the use of such a substrate, formation of a transistor with favorable characteristics, formation of a transistor with low power consumption, manufacture of a device which is not easily broken, provision of heat resistance, reduction in weight, or reduction in thickness can be achieved.

The insulating layer 420 has a function of preventing diffusion of an impurity from an element included in the substrate 415 and a function of supplying oxygen to the oxide semiconductor layer 430. Therefore, the insulating layer 420 is preferably an insulating layer containing oxygen, and more preferably an insulating layer containing more oxygen than the stoichiometric composition. For example, a film in which the amount of released oxygen in terms of oxygen atoms is 1.0 × 10 ¹⁹ atoms / cm ³ or more by a thermal desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)). Note that the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C to 700 ° C, or 100 ° C to 500 ° C. In the case where the substrate 415 is a substrate over which another device is formed, the insulating layer 420 also has a function as an interlayer insulating layer. In that case, it is preferable to perform a planarization process by a CMP method or the like so that the surface becomes flat.

For example, the insulating layer 420 includes an oxide insulating layer such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. , Silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or another nitride insulating layer, or a mixed material thereof. Further, a stack of the above materials may be used.

Note that in this embodiment, the case where the oxide semiconductor layer 430 included in the transistor has a three-layer structure in which an oxide semiconductor layer 430a, an oxide semiconductor layer 430b, and an oxide semiconductor layer 430c are sequentially stacked from the insulating layer 420 side is described. The details will be mainly described.

Note that in the case where the oxide semiconductor layer 430 is a single layer, a layer corresponding to the oxide semiconductor layer 430b described in this embodiment may be used.

In the case where the oxide semiconductor layer 430 has two layers, a layer corresponding to the oxide semiconductor layer 430a and a layer corresponding to the oxide semiconductor layer 430b described in this embodiment are stacked in this order from the insulating layer 420 side. May be used. In this structure, the oxide semiconductor layer 430a and the oxide semiconductor layer 430b can be interchanged.

In the case where the number of the oxide semiconductor layers 430 is four or more, for example, a structure in which another oxide semiconductor layer is added to the three-layer oxide semiconductor layer 430 described in this embodiment is used. Can be.

As an example, an oxide semiconductor having higher electron affinity (energy from a vacuum level to the bottom of a conduction band) than the oxide semiconductor layers 430a and 430c is used for the oxide semiconductor layer 430b. The electron affinity can be obtained as a value obtained by subtracting the energy difference (energy gap) between the bottom of the conduction band and the top of the valence band from the energy difference (ionization potential) between the vacuum level and the top of the valence band.

The oxide semiconductor layer 430a and the oxide semiconductor layer 430c each include at least one metal element included in the oxide semiconductor layer 430b. For example, the energy of the lower end of the conduction band is 0.05 eV, 0. It is preferable that the oxide semiconductor be formed using an oxide semiconductor which is higher than any of 07 eV, 0.1 eV, and 0.15 eV and close to a vacuum level in a range of 2 eV, 1 eV, 0.5 eV, and 0.4 eV or lower.

In such a structure, when an electric field is applied to the conductive layer 470, a channel is formed in the oxide semiconductor layer 430b having the lowest energy at the bottom of the conduction band of the oxide semiconductor layer 430.

Further, the oxide semiconductor layer 430a includes one or more metal elements included in the oxide semiconductor layer 430b; thus, the oxide semiconductor layer 430a has higher oxidation resistance than an interface where the oxide semiconductor layer 430b is in contact with the insulating layer 420. At the interface between the semiconductor layer 430b and the oxide semiconductor layer 430a, an interface state is less likely to be formed. Since the interface state may form a channel, the threshold voltage of the transistor may be changed. Therefore, by providing the oxide semiconductor layer 430a, variation in electrical characteristics of the transistor, such as the threshold voltage, can be reduced. Further, the reliability of the transistor can be improved.

Further, the oxide semiconductor layer 430c includes one or more metal elements included in the oxide semiconductor layer 430b; thus, the oxide semiconductor layer 430c has an interface with the oxide semiconductor layer 430b which is in contact with the gate insulating layer (the insulating layer 460). In comparison, carrier scattering is less likely to occur at the interface between the oxide semiconductor layers 430b and 430c. Therefore, by providing the oxide semiconductor layer 430c, the field-effect mobility of the transistor can be increased.

The oxide semiconductor layer 430a and the oxide semiconductor layer 430c each include, for example, a material containing Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf at a higher atomic ratio than the oxide semiconductor layer 430b. Can be used. Specifically, the atomic ratio is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. Since the above element is strongly bonded to oxygen, it can have a function of suppressing generation of oxygen vacancies in the oxide semiconductor layer. That is, it can be said that the oxide semiconductor layers 430a and 430c are less likely to cause oxygen vacancies than the oxide semiconductor layer 430b.

An oxide semiconductor that can be used for the oxide semiconductor layers 430a, 430b, and 430c preferably contains at least In or Zn. Alternatively, it is preferable to include both In and Zn. Further, in order to reduce variation in electric characteristics of the transistor including the oxide semiconductor, it is preferable to include a stabilizer together with the oxide semiconductor.

Examples of the stabilizer include Ga, Sn, Hf, Al, and Zr. Other stabilizers include lanthanoids such as La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

For example, as an oxide semiconductor, indium oxide, tin oxide, gallium oxide, zinc oxide, In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide, Sn—Mg oxide, In -Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide , Sn—Al—Zn oxide, In—Hf—Zn oxide, In—La—Zn oxide, In—Ce—Zn oxide, In—Pr—Zn oxide, In—Nd—Zn oxide, In -Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er -Zn oxide, In-Tm-Zn oxide, In- b-Zn oxide, In-Lu-Zn oxide, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- A Zn oxide, an In-Sn-Hf-Zn oxide, or an In-Hf-Al-Zn oxide can be used.

Note that here, for example, an In—Ga—Zn oxide means an oxide containing In, Ga, and Zn as its main components. Further, a metal element other than In, Ga, and Zn may be contained. In this specification, a film including an In—Ga—Zn oxide is also referred to as an IGZO film.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0 and m is not an integer) may be used. Note that M represents one metal element or a plurality of metal elements selected from Ga, Y, Zr, La, Ce, or Nd. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0 and n is an integer) may be used.

Note that the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c each include at least indium, zinc, and a metal such as M (Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf). ), The oxide semiconductor layer 430a has In: M: Zn = x ₁ : y ₁ : z ₁ [atomic ratio], and the oxide semiconductor layer 430b has In: M: Assuming that Zn = x ₂ : y ₂ : z ₂ [atomic ratio] and the oxide semiconductor layer 430 c is In: M: Zn = x ₃ : y ₃ : z ₃ [atomic ratio], y ₁ / x ₁ and Preferably, y ₃ / x ₃ is greater than y ₂ / x ₂ . y ₁ / x ₁ and y ₃ / x ₃ are 1.5 times or more, preferably 2 times or more, more preferably 3 times or more than y ₂ / x ₂ . At this time, when y ₂ is greater than or equal to x ₂ in the oxide semiconductor layer 430b, electric characteristics of the transistor can be stabilized. Note that when y ₂ is three times or more than x ₂ , the field-effect mobility of the transistor is reduced; therefore, y ₂ is preferably less than three times x ₂ .

In the case where Zn and O in the oxide semiconductor layer 430a and the oxide semiconductor layer 430c are excluded, the atomic ratio of In and M is preferably such that In is less than 50 atomic%, M is higher than 50 atomic%, and more preferably, In is less than 50 atomic%. Less than 25 atomic% and M is higher than 75 atomic%. In addition, the atomic ratio of In and M excluding Zn and O in the oxide semiconductor layer 430b is preferably such that In is higher than 25 atomic%, M is lower than 75 atomic%, further preferably In is higher than 34 atomic%, and M is higher than 34 atomic%. Is less than 66 atomic%.

In addition, the oxide semiconductor layer 430b preferably has a higher indium content than the oxide semiconductor layers 430a and 430c. In an oxide semiconductor, the s orbital of a heavy metal mainly contributes to carrier conduction, and by increasing the content of In, more s orbitals overlap. Therefore, an oxide having a composition in which In is larger than M is In Has a higher mobility than an oxide having a composition equal to or less than that of M. Therefore, by using an oxide containing a large amount of indium for the oxide semiconductor layer 430b, a transistor with high field-effect mobility can be realized.

The thickness of the oxide semiconductor layer 430a is 3 nm to 100 nm, preferably 5 nm to 50 nm, more preferably 5 nm to 25 nm. The thickness of the oxide semiconductor layer 430b is 3 nm to 200 nm, preferably 5 nm to 150 nm, more preferably 10 nm to 100 nm. The thickness of the oxide semiconductor layer 430c is 1 nm to 50 nm, preferably 2 nm to 30 nm, more preferably 3 nm to 15 nm. Further, it is preferable that the oxide semiconductor layer 430b be thicker than the oxide semiconductor layer 430c.

Note that in order to impart stable electric characteristics to a transistor including the oxide semiconductor layer as a channel, the impurity concentration in the oxide semiconductor layer is reduced and the oxide semiconductor layer is made intrinsic or substantially intrinsic. It is valid. Here, “substantially intrinsic” means that the carrier density of the oxide semiconductor layer is less than 1 × 10 ¹⁵ / cm ^3, less than 1 × 10 ¹³ / cm ³ , and 8 × 10 ¹¹ / cm ^3. Less than 1 × 10 ⁸ / cm ³ and 1 × 10 ⁻⁹ / cm ³ or more.

In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main components become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase carrier density. Further, silicon contributes to formation of impurity levels in the oxide semiconductor layer. The impurity level serves as a trap, which may deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentration in the oxide semiconductor layers 430a, 430b, and 430c and at the interfaces between the layers.

In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, the silicon concentration estimated by SIMS (Secondary Ion Mass Spectrometry) analysis is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm 3. Control is performed so as to have a region of less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . In addition, the hydrogen concentration is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, and still more preferably 5 × 10 ¹⁸ atoms / cm ^3. Control is performed so as to have an area of not more than cm ³ . In addition, for example, the nitrogen concentration is lower than 5 × 10 ¹⁹ atoms / cm ³ , preferably lower than or equal to 5 × 10 ¹⁸ atoms / cm ^{3 at} a certain depth of the oxide semiconductor layer or a certain region of the oxide semiconductor layer. And more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, further preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer may be reduced. In order not to lower the crystallinity of the oxide semiconductor layer, for example, the silicon concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and more preferably 1 × 10 ¹⁸ atoms / cm 3. Control is performed so as to have an area smaller than ³ . Further, the carbon concentration is controlled so as to have a region where the concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

In addition, the off-state current of a transistor including the highly purified oxide semiconductor layer for a channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-state current per channel width of the transistor can be reduced to several yA / μm to several zA / μm. It becomes possible.

Note that an insulating layer containing silicon is often used as a gate insulating layer of the transistor; therefore, a region serving as a channel of the oxide semiconductor layer is in contact with the gate insulating layer as in the transistor of one embodiment of the present invention for the above reason. It can be said that a non-structure is preferable. In the case where a channel is formed at the interface between the gate insulating layer and the oxide semiconductor layer, carrier scattering occurs at the interface, so that the field-effect mobility of the transistor may be reduced. From such a viewpoint, it can be said that a region of the oxide semiconductor layer which serves as a channel is preferably separated from the gate insulating layer.

Therefore, when the oxide semiconductor layer 430 has a stacked structure of the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c, a channel can be formed in the oxide semiconductor layer 430b, and high electric field effect can be obtained. A transistor having mobility and stable electric characteristics can be formed.

In the band structure of the oxide semiconductor layers 430a, 430b, and 430c, the energy at the bottom of the conduction band changes continuously. This is also understood from the fact that the compositions of the oxide semiconductor layers 430a, 430b, and 430c are close to each other, so that oxygen easily diffuses into each other. Therefore, although the oxide semiconductor layers 430a, 430b, and 430c are stacks of layers with different compositions, they can be said to be continuous in physical properties. Are represented by dotted lines.

The oxide semiconductor layer 430 having a main component in common is formed by a continuous junction (here, in particular, a U-shaped well structure in which the energy at the bottom of the conduction band changes continuously between the layers, instead of simply stacking the layers). (U Shape Well)). That is, the stacked structure is formed so that there is no impurity that forms a defect level such as a trap center or a recombination center at the interface between the layers. If impurities are mixed between layers of the stacked oxide semiconductor layers, continuity of the energy band is lost and carriers disappear at the interface by trapping or recombination.

For example, In: Ga: Zn = 1: 3: 2, 1: 3: 3, 1: 3: 4, 1: 3: 6, and 1: 4: 5 in the oxide semiconductor layers 430a and 430c. , 1: 6: 4 or 1: 9: 6 (atomic ratio) or the like can be used. In addition, the oxide semiconductor layer 430b has an In-Ga-layer such as In: Ga: Zn = 1: 1: 1, 2: 1: 3, 5: 5: 6, or 3: 1: 2 (atomic ratio). Zn oxide or the like can be used. Note that the atomic ratios of the oxide semiconductor layers 430a, 430b, and 430c each include an error of ± 40% of the above atomic ratio as an error.

The oxide semiconductor layer 430b in the oxide semiconductor layer 430 serves as a well, and a channel is formed in the oxide semiconductor layer 430b. Note that the oxide semiconductor layer 430 can be called a U-shaped well because the energy at the bottom of the conduction band changes continuously. A channel formed with such a structure can also be called a buried channel.

Further, a trap level due to an impurity or a defect can be formed in the vicinity of the interface between the oxide semiconductor layers 430a and 430c and an insulating layer such as a silicon oxide film. With the oxide semiconductor layer 430a and the oxide semiconductor layer 430c, the oxide semiconductor layer 430b can be separated from the trap level.

Note that when the difference between the energy at the bottom of the conduction band of the oxide semiconductor layer 430a and the bottom of the conduction band of the oxide semiconductor layer 430c and the energy at the bottom of the conduction band of the oxide semiconductor layer 430b is small, the electrons in the oxide semiconductor layer 430b have the energy difference. May exceed the trap level. When electrons are captured by the trap levels, negative charges are generated at the interface of the insulating layer, so that the threshold voltage of the transistor shifts in the positive direction.

The oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c preferably include a crystal part. In particular, by using c-axis oriented crystals, a transistor can have stable electric characteristics. In addition, a crystal oriented along the c-axis is resistant to distortion, and can improve the reliability of a semiconductor device using a flexible substrate.

The conductive layer 440 serving as one of the source and the drain and the conductive layer 450 serving as the other of the source and the drain include, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, Alternatively, a single layer or a stacked layer of a material selected from alloys of the metal materials can be used. Typically, it is more preferable to use W, which has a high melting point, particularly because Ti is easily bonded to oxygen, and the subsequent process temperature can be relatively high. Alternatively, a stack of a low-resistance alloy such as Cu or Cu-Mn and the above material may be used. Note that in the transistors 405, 406, 411, and 412, for example, W can be used for the conductive layers 441 and 451, and a stacked film of Ti and Al can be used for the conductive layers 442 and 452.

The above materials have a property of extracting oxygen from the oxide semiconductor layer. Therefore, oxygen in the oxide semiconductor layer is released in part of the oxide semiconductor layer in contact with the above material, so that oxygen vacancies are formed. When the hydrogen slightly contained in the film is combined with the oxygen vacancy, the region becomes significantly n-type. Therefore, the n-type region can function as a source or a drain of the transistor.

In the case where W is used for the conductive layers 440 and 450, nitrogen may be doped. By doping with nitrogen, the property of extracting oxygen can be appropriately weakened, and the n-type region can be prevented from expanding to the channel region. Further, the conductive layer 440 and the conductive layer 450 are stacked with an n-type semiconductor layer, and the n-type region is prevented from expanding to a channel region also by contacting the n-type semiconductor layer and the oxide semiconductor layer. be able to. As the n-type semiconductor layer, an In—Ga—Zn oxide to which nitrogen is added, zinc oxide, indium oxide, tin oxide, indium tin oxide, or the like can be used.

The insulating layer 460 serving as a gate insulating layer includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating layer containing at least one of hafnium oxide and tantalum oxide can be used. The insulating layer 460 may be a stack of any of the above materials. Note that the insulating layer 460 may contain La, N, Zr, or the like as an impurity.

Further, an example of a stacked structure of the insulating layer 460 is described. The insulating layer 460 includes, for example, oxygen, nitrogen, silicon, hafnium, or the like. Specifically, it is preferable to include hafnium oxide and silicon oxide or silicon oxynitride.

Hafnium oxide and aluminum oxide have higher dielectric constants than silicon oxide and silicon oxynitride. Therefore, the thickness of the insulating layer 460 can be increased as compared with the case where silicon oxide is used, so that a leak current due to a tunnel current can be reduced. That is, a transistor with small off-state current can be realized. Furthermore, hafnium oxide having a crystalline structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, hafnium oxide having a crystal structure is preferably used. Examples of the crystal structure include a monoclinic system and a cubic system. Note that one embodiment of the present invention is not limited thereto.

Further, it is preferable that the insulating layer 420 and the insulating layer 460 which are in contact with the oxide semiconductor layer 430 be a film which releases less nitrogen oxide. In the case where the insulating layer which emits a large amount of nitrogen oxide is in contact with the oxide semiconductor, the level density due to the nitrogen oxide may increase. The level density due to the nitrogen oxide may be formed in an energy gap of the oxide semiconductor in some cases. For the insulating layer 420 and the insulating layer 460, for example, an oxide insulating layer such as a silicon oxynitride film or an aluminum oxynitride film which releases less nitrogen oxide can be used.

Note that a silicon oxynitride film with a small amount of released nitrogen oxide is a film in which the amount of released ammonia is larger than the amount of released nitrogen oxide in the TDS method, and typically, the amount of released ammonia is 1 × 10 ¹⁸ Pcs / cm ³ or more and 5 × 10 ¹⁹ pcs / cm ³ or less. Note that the release amount of ammonia is a release amount by heat treatment in which the surface temperature of the film is 50 ° C or higher and 650 ° C or lower, preferably 50 ° C or higher and 550 ° C or lower.

With the use of the above oxide insulating layers as the insulating layers 420 and 460, a shift in threshold voltage of the transistor can be reduced and variation in electrical characteristics of the transistor can be reduced.

For the conductive layer 470 acting as a gate, for example, a conductive layer of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, W, or the like is used. Can be. Further, an alloy of the above material or a conductive nitride of the above material may be used. Further, a stack of a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials may be used. Typically, a stack of tungsten, a stack of tungsten and titanium nitride, a stack of tungsten and tantalum nitride, or the like can be used. Alternatively, a low-resistance alloy such as Cu or Cu-Mn or a stack of the above material and an alloy such as Cu or Cu-Mn may be used. In this embodiment, the conductive layer 470 is formed using tantalum nitride for the conductive layer 471 and tungsten for the conductive layer 472.

As the insulating layer 475, a silicon nitride film containing hydrogen, an aluminum nitride film, or the like can be used. In the transistor 403, the transistor 404, the transistor 406, the transistor 409, the transistor 410, and the transistor 412 described in Embodiment 6, the oxide semiconductor layer 430 and the insulating layer 475 are partially in contact with each other; With the use of the insulating layer, part of the oxide semiconductor layer 430 can be made n-type. Further, the nitride insulating layer also has a function as a blocking film for moisture and the like, so that the reliability of the transistor can be improved.

Further, as the insulating layer 475, an aluminum oxide film can be used. In particular, in the transistors 401, 402, 405, 407, 408, and 411 described in Embodiment 6, an aluminum oxide film is preferably used for the insulating layer 475. The aluminum oxide film has a high effect of blocking both oxygen and impurities such as hydrogen and moisture and oxygen. Therefore, the aluminum oxide film prevents impurities such as hydrogen and moisture from entering the oxide semiconductor layer 430, prevents oxygen from being released from the oxide semiconductor layer, and prevents the impurity from the insulating layer 420 during and after the process of manufacturing the transistor. It is suitable for use as a protective film having an effect of preventing unnecessary release of oxygen. Further, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer.

Further, the insulating layer 480 is preferably formed over the insulating layer 475. The insulating layer contains at least one of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating layer can be used. Further, the insulating layer may be a stack of any of the above materials.

Here, like the insulating layer 420, the insulating layer 480 preferably contains more oxygen than the stoichiometric composition. Oxygen released from the insulating layer 480 can be diffused into the channel formation region of the oxide semiconductor layer 430 through the insulating layer 460; therefore, oxygen can be compensated for oxygen vacancies formed in the channel formation region. . Therefore, stable electric characteristics of the transistor can be obtained.

For high integration of a semiconductor device, miniaturization of a transistor is indispensable. On the other hand, it is known that electrical characteristics of a transistor are deteriorated by miniaturization of the transistor. Particularly, when a channel width is reduced, an on-state current is reduced.

In the transistors 407 to 412 of one embodiment of the present invention, the oxide semiconductor layer 430c is formed so as to cover the oxide semiconductor layer 430b where a channel is formed, so that the channel formation layer does not contact with the gate insulating layer. Has become. Therefore, scattering of carriers generated at the interface between the channel formation layer and the gate insulating layer can be suppressed, and on-state current of the transistor can be increased.

In the transistor of one embodiment of the present invention, the gate (the conductive layer 470) is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 430 as described above. On the other hand, in addition to the gate electric field from the vertical direction, a gate electric field from the side direction is applied. That is, a gate electric field is applied to the entire channel forming layer, and the effective channel width is increased, so that the on-current can be further increased.

In the case of a transistor having two or three oxide semiconductor layers 430 in one embodiment of the present invention, an interface state is formed by forming the oxide semiconductor layer 430b where a channel is formed over the oxide semiconductor layer 430a. It has the effect of making it difficult to do. In the case of a transistor having three layers of the oxide semiconductor layer 430 in one embodiment of the present invention, the oxide semiconductor layer 430b is a layer located in the middle of the three-layer structure, so that the influence of impurity contamination from above and below can be eliminated. And so on. Therefore, in addition to the improvement of the on-state current of the transistor described above, the threshold voltage can be stabilized and the S value (sub-threshold value) can be reduced. Therefore, the current when the gate voltage VG is 0 V can be reduced, and the power consumption can be reduced. Further, since the threshold voltage of the transistor is stabilized, long-term reliability of the semiconductor device can be improved. In addition, the transistor of one embodiment of the present invention can be said to be suitable for formation of a highly integrated semiconductor device because deterioration of electric characteristics due to miniaturization is suppressed.

Note that various films such as a metal film, a semiconductor film, and an inorganic insulating film described in this embodiment can be typically formed by a sputtering method or a plasma CVD (Chemical Vapor Deposition) method; For example, it may be formed by a thermal CVD method. Examples of the thermal CVD method include an MOCVD method and an ALD (Atomic Layer Deposition) method.

The thermal CVD method has an advantage that defects are not generated due to plasma damage because the film formation method does not use plasma.

In the thermal CVD method, a raw material gas and an oxidizing agent are simultaneously sent into a chamber, and the inside of the chamber is set at atmospheric pressure or reduced pressure, and the film is formed by reacting near the substrate or on the substrate and depositing on the substrate. Is also good.

In the ALD method, a film is formed by setting the inside of the chamber to atmospheric pressure or reduced pressure, introducing and reacting a source gas for the reaction into the chamber, and repeating this. An inert gas (eg, argon or nitrogen) may be introduced as a carrier gas together with the source gas. For example, two or more types of source gases may be sequentially supplied to the chamber. At this time, after reacting the first source gas, an inert gas is introduced and a second source gas is introduced so that a plurality of types of source gases are not mixed. Alternatively, instead of introducing an inert gas, the second source gas may be introduced after discharging the first source gas by evacuation. The first source gas adsorbs and reacts on the surface of the substrate to form a first layer, and a second source gas introduced later adsorbs and reacts, and the second layer becomes the first layer. A thin film is formed by being laminated thereon. By repeating the gas introduction sequence a plurality of times until a desired thickness is obtained, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repetitions of gas introduction, precise film thickness adjustment is possible, which is suitable for manufacturing a fine FET.

A thermal CVD method such as an MOCVD method or an ALD method can form various films such as a metal film, a semiconductor film, and an inorganic insulating film disclosed in the embodiments described above. For example, In-Ga-Zn in the case of forming an -O membrane, trimethylindium _{(in (CH 3) 3)} , trimethyl gallium _{(Ga (CH 3) 3)} , and dimethyl zinc (Zn _{(CH 3) 2)} can be used. Not limited to these combinations, triethylgallium (Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethyl gallium, and diethyl zinc (Zn (C ₂ H ₅ ) ₂ ) is used instead of dimethyl zinc. You can also.

For example, when a hafnium oxide film is formed by a film formation apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide, tetrakisdimethylamidohafnium (TDMAH, Hf [N (CH ₃ ) ₂ ] ₄ ) ) Or hafnium amide such as tetrakis (ethylmethylamide) hafnium, and two kinds of gases, ozone (O ₃ ), are used as oxidizing agents.

For example, when an aluminum oxide film is formed by a film forming apparatus using ALD, a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor (such as trimethyl aluminum (TMA, Al (CH ₃ ) ₃ )) is used. And two kinds of gases of H ₂ O are used as oxidizing agents. Other materials include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

For example, in the case where a silicon oxide film is formed by a film formation apparatus using ALD, hexachlorodisilane is adsorbed on a surface on which a film is to be formed, and radicals of an oxidizing gas (O ₂ , nitrous oxide) are supplied to adsorb. React with things.

For example, when a tungsten film is formed by a film forming apparatus using ALD, an WF ₆ gas and a B ₂ H ₆ gas are sequentially introduced to form an initial tungsten film, and thereafter, a WF ₆ gas and a H ₂ gas Are sequentially introduced to form a tungsten film. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, when an oxide semiconductor layer, for example, an In—Ga—Zn—O film is formed by a film formation apparatus using ALD, an In (CH ₃ ) ₃ gas and an O ₃ gas are sequentially introduced to introduce an In— An O layer is formed, and then, a Ga (CH ₃ ) ₃ gas and an O ₃ gas are sequentially introduced to form a GaO layer, and thereafter, a Zn (CH ₃ ) ₂ gas and an O ₃ gas are sequentially introduced to form a ZnO layer. To form The order of these layers is not limited to this example. A mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, and a Ga—Zn—O layer may be formed using these gases. Note that, instead of the O ₃ gas, an H ₂ O gas obtained by bubbling with an inert gas such as Ar may be used, but an O ₃ gas containing no H is preferably used.

Note that a facing target sputtering apparatus can be used for forming the oxide semiconductor layer. The film formation method using the facing target sputtering apparatus can also be referred to as VDSP (vapor deposition SP).

When the oxide semiconductor layer is formed using a facing target sputtering apparatus, plasma damage at the time of forming the oxide semiconductor layer can be reduced. Therefore, oxygen vacancies in the film can be reduced. In addition, by using a facing target sputtering apparatus, film formation can be performed at low pressure; therefore, the impurity concentration (eg, hydrogen, a rare gas (eg, argon), or water) in the formed oxide semiconductor layer can be reduced. Can be done.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 9)
The structure of an oxide semiconductor layer that can be used in one embodiment of the present invention is described below.

In this specification, “parallel” refers to a state where two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case where the angle is −5 ° or more and 5 ° or less is also included. Further, “substantially parallel” refers to a state in which two straight lines are arranged at an angle of −30 ° or more and 30 ° or less. “Vertical” means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, a case where the angle is 85 ° or more and 95 ° or less is also included. The term “substantially perpendicular” refers to a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

In this specification, when the crystal is a trigonal or rhombohedral, it is represented as a hexagonal system.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like OS). : Amorphous-like oxide semiconductor) and an amorphous oxide semiconductor.

From another viewpoint, an oxide semiconductor is classified into an amorphous oxide semiconductor and another crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

Amorphous structures are generally isotropic and have no heterogeneous structure, are metastable and have no fixed atom arrangement, have a flexible bond angle, have short-range order but have long-range order It is said that there is no such thing.

That is, a stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. Further, an oxide semiconductor that is not isotropic (eg, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. On the other hand, the a-like OS is not isotropic, but has an unstable structure having voids (also referred to as voids). In terms of being unstable, the a-like OS is physically close to an amorphous oxide semiconductor.

First, the CAAC-OS will be described.

The CAAC-OS is a kind of an oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD) will be described. For example, when structural analysis is performed on an CAAC-OS having an InGaZnO ₄ crystal classified into the space group R-3m by an out-of-plane method, a diffraction angle (2θ) is obtained as illustrated in FIG. A peak appears around 31 °. Since this peak is attributed to the (009) plane of the crystal of InGaZnO ₄ , in the CAAC-OS, the crystal has c-axis orientation and the c-axis forms a CAAC-OS film (formation surface). Or a surface substantially perpendicular to the upper surface. In addition, a peak may appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. The peak near 2θ of 36 ° originates from the crystal structure classified into the space group Fd-3m. Therefore, it is preferable that the CAAC-OS do not show the peak.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays enter from a direction parallel to the formation surface, a peak appears when 2θ is around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. Even when 2θ is fixed to around 56 ° and the analysis (φ scan) is performed while rotating the sample around the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when φ scan is performed on single crystal InGaZnO ₄ with 2θ fixed at around 56 °, six peaks belonging to a crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD confirms that the orientation of the a-axis and the b-axis of the CAAC-OS is irregular.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a surface on which the CAAC-OS is formed, a diffraction pattern (restricted field) illustrated in FIG. Electron diffraction pattern) may appear. This diffraction pattern includes spots originating from the (009) plane of the InGaZnO ₄ crystal. Therefore, by electron diffraction, it is found that the pellets included in the CAAC-OS have c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the upper surface. On the other hand, FIG. 48E shows a diffraction pattern obtained when an electron beam having a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. FIG. 48E shows a ring-like diffraction pattern. Therefore, even by electron diffraction using an electron beam with a probe diameter of 300 nm, it is found that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation. Note that the first ring in FIG. 48E is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO ₄ crystal. The second ring in FIG. 48E is considered to be derived from the (110) plane and the like.

In addition, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of a CAAC-OS is observed with a transmission electron microscope (TEM), a plurality of pellets can be confirmed. Can be. On the other hand, even in the case of a high-resolution TEM image, a boundary between pellets, that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, in the CAAC-OS, a reduction in electron mobility due to crystal grain boundaries does not easily occur.

FIG. 49A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction (Spherical Aberration Corrector) function was used. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed by, for example, an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 49A shows a pellet in which metal atoms are arranged in a layered manner. It can be seen that one pellet has a size of 1 nm or more and 3 nm or more. Therefore, the pellet can also be called a nanocrystal (nc). Further, the CAAC-OS can be referred to as an oxide semiconductor having CAN (C-Axis Aligned nanocrystals). The pellet reflects unevenness of a surface or an upper surface of the CAAC-OS and is parallel to the surface or the upper surface of the CAAC-OS.

FIGS. 49B and 49C show Cs-corrected high-resolution TEM images of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. FIGS. 49D and 49E are images obtained by performing image processing on FIGS. 49B and 49C, respectively. Hereinafter, an image processing method will be described. First, an FFT image is obtained by performing Fast Fourier Transform (FFT) processing on FIG. 49B. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, an image processed image is obtained by performing an inverse fast Fourier transform (IFFT) on the masked FFT image. The image thus obtained is called an FFT filtering image. The FFT filtering image is an image obtained by extracting a periodic component from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

In FIG. 49 (D), broken portions of the lattice arrangement are indicated by broken lines. A region surrounded by a broken line is one pellet. The portion shown by the broken line is the connection between the pellets. Since the broken line is hexagonal, it can be seen that the pellet is hexagonal. The shape of the pellet is not limited to a regular hexagon, but is often a non-regular hexagon.

In FIG. 49E, a portion where the direction of the lattice arrangement changes between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform is indicated by a dotted line, and the change in the direction of the lattice arrangement is shown. This is indicated by a broken line. Even near the dotted line, a clear crystal grain boundary cannot be confirmed. Distorted hexagons, pentagons and / or heptagons can be formed by connecting surrounding grid points around grid points near the dotted line. That is, it is understood that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to a non-dense atomic arrangement in the a-b plane direction or a change in the bond length between atoms caused by substitution with a metal element. Conceivable.

As described above, the CAAC-OS has a c-axis orientation and has a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction and have a strain. Therefore, the CAAC-OS can be referred to as CAA crystal (c-axis-aligned ab-plane-anchored crystal).

The CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of the oxide semiconductor might be reduced due to entry of impurities, generation of defects, or the like, the CAAC-OS can be regarded as an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

Note that the impurity is an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, deprives the oxide semiconductor of oxygen and thereby disturbs an atomic arrangement of the oxide semiconductor and decreases crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have large atomic radii (or molecular radii), so that the atomic arrangement of the oxide semiconductor is disturbed and the crystallinity is reduced.

Next, the nc-OS will be described.

A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by an out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.

Further, for example, when an nc-OS having InGaZnO ₄ crystal is sliced and an electron beam with a probe diameter of 50 nm is incident on a region with a thickness of 34 nm in parallel to a formation surface, FIG. A ring-like diffraction pattern (nano-beam electron diffraction pattern) as shown is observed. FIG. 50B shows a diffraction pattern (a nanobeam electron diffraction pattern) obtained when an electron beam having a probe diameter of 1 nm is incident on the same sample. From FIG. 50B, a plurality of spots are observed in the ring-shaped region. Therefore, the order of the nc-OS is not confirmed when an electron beam having a probe diameter of 50 nm is incident, but the order is confirmed when an electron beam having a probe diameter of 1 nm is incident.

When an electron beam having a probe diameter of 1 nm is incident on a region having a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. In some cases. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a range where the thickness is less than 10 nm. Note that there are regions where regular electron diffraction patterns are not observed because the crystals are oriented in various directions.

FIG. 50D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. The nc-OS has a region in which a crystal part can be confirmed in a high-resolution TEM image, such as a portion indicated by an auxiliary line, and a region in which a crystal part cannot be clearly observed. The crystal part included in the nc-OS has a size of from 1 nm to 10 nm, particularly from 1 nm to 3 nm. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm may be referred to as a microcrystalline oxide semiconductor. In the nc-OS, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly observed in some cases. Note that a nanocrystal may have the same origin as a pellet in the CAAC-OS. Therefore, the crystal part of the nc-OS is hereinafter sometimes referred to as a pellet.

As described above, the nc-OS has a periodic atomic arrangement in a minute region (for example, a region with a thickness of 1 nm to 10 nm, in particular, a region with a size of 1 nm to 3 nm). In the nc-OS, there is no regularity in crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

Note that since the crystal orientation between the pellets (nanocrystals) does not have a regularity, the nc-OS is replaced with an oxide semiconductor having RANC (Random Aligned Nanocrystals) or an oxide semiconductor having NANC (Non-Aligned Nanocrystals). It can also be called a semiconductor.

The nc-OS is an oxide semiconductor having higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than the a-like OS and the amorphous oxide semiconductor. However, nc-OS has no regularity in crystal orientation between different pellets. Thus, the nc-OS has a higher density of defect states than the CAAC-OS.

The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.

FIG. 51 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 51A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 51B is a high-resolution cross-sectional TEM image of the a-like OS after electron (e ⁻ ) irradiation of 4.3 × 10 ⁸ e ⁻ / nm ² . FIGS. 51A and 51B show that a stripe-like bright region extending in the vertical direction is observed in the a-like OS from the start of electron irradiation. Further, it can be seen that the shape of the bright region changes after the electron irradiation. The bright region is assumed to be a void or a low-density region.

The a-like OS has an unstable structure because it has porosity. In the following, a structure change due to electron irradiation is shown in order to show that the a-like OS has a more unstable structure than the CAAC-OS and the nc-OS.

An a-like OS, an nc-OS, and a CAAC-OS are prepared as samples. Each sample is an In-Ga-Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is obtained. According to the high-resolution cross-sectional TEM image, each sample has a crystal part.

Note that the unit lattice of the crystal of InGaZnO ₄ has a structure in which three layers of In—O and six layers of Ga—Zn—O are provided, and a total of nine layers are stacked in the c-axis direction. Are known. The distance between these adjacent layers is about the same as the lattice plane distance (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as a crystal part of InGaZnO ₄ . Note that the lattice fringes correspond to the a-b plane of the InGaZnO ₄ crystal.

FIG. 52 is an example in which the average size of the crystal parts (22 to 30 places) of each sample was investigated. Note that the length of the above-described lattice fringes is the size of the crystal part. FIG. 52 shows that the crystal part size of the a-like OS increases in accordance with the cumulative irradiation amount of electrons for obtaining a TEM image and the like. As shown in FIG. 52, the crystal part (also referred to as an initial nucleus) having a size of about 1.2 nm in the early stage of observation by the TEM has a cumulative irradiation amount of electrons (e ⁻ ) of 4.2 × 10 ⁸ e ⁻ / nm. ^In No. ² , it can be seen that it has grown to a size of about 1.9 nm. On the other hand, in the case of the nc-OS and the CAAC-OS, the size of the crystal part does not change when the cumulative irradiation amount of electrons from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. FIG. 52 shows that the sizes of the crystal parts of the nc-OS and the CAAC-OS are about 1.3 nm and about 1.8 nm, respectively, regardless of the cumulative electron irradiation dose. The electron beam irradiation and TEM observation were performed using a Hitachi transmission electron microscope H-9000NAR. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 ⁵ e ⁻ / (nm ² · s), and a diameter of the irradiation region of 230 nm.

As described above, in the a-like OS, a crystal part may be grown by electron irradiation in some cases. On the other hand, in the nc-OS and the CAAC-OS, growth of a crystal part due to electron irradiation is hardly observed. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

Further, due to the presence of voids, the a-like OS has a structure with lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal having the same composition. The density of the nc-OS and the density of the CAAC-OS are greater than or equal to 92.3% and less than 100% of the density of a single crystal having the same composition. It is difficult to form an oxide semiconductor having a density of less than 78% of the density of the single crystal.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, In: Ga: Zn = 1 : 1: 1 in the oxide semiconductor which satisfies the atomic ratio of the density of a-like OS is less than 5.0 g / cm ³ or more 5.9 g / cm ³ . For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are 5.9 g / cm ³ or more and 6.3 g / cm ^3. cm ³ .

Note that in the case where single crystals having the same composition do not exist, the density corresponding to a single crystal having a desired composition can be estimated by combining single crystals having different compositions in an arbitrary ratio. The density corresponding to a single crystal having a desired composition may be estimated using a weighted average with respect to a ratio of combining single crystals having different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

As described above, oxide semiconductors have various structures and each have various characteristics. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

Next, the carrier density of an oxide semiconductor is described below.

As a factor affecting the carrier density of the oxide semiconductor, an oxygen vacancy (Vo) in the oxide semiconductor, an impurity in the oxide semiconductor, or the like can be given.

When the number of oxygen vacancies in the oxide semiconductor is increased, the density of defect states is increased when hydrogen is bonded to the oxygen vacancies (this state is also referred to as VoH). Alternatively, when the amount of impurities in the oxide semiconductor is increased, the density of defect states is increased due to the impurities. Therefore, by controlling the density of defect states in the oxide semiconductor, the carrier density of the oxide semiconductor can be controlled.

Here, a transistor using an oxide semiconductor for a channel region is considered.

In the case where the purpose is to suppress a negative shift of the threshold voltage of the transistor or to reduce the off-state current of the transistor, it is preferable to reduce the carrier density of the oxide semiconductor. In the case where the carrier density of the oxide semiconductor is reduced, the impurity concentration in the oxide semiconductor may be reduced and the density of defect states may be reduced. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. The carrier density of the highly purified intrinsic oxide semiconductor is less than 8 × 10 ¹⁵ cm ⁻³ , preferably less than 1 × 10 ¹¹ cm ⁻³ , more preferably less than 1 × 10 ¹⁰ cm ⁻³ , and 1 × 10 5 ^What is necessary is just to be ^-9 cm- ³ or more.

On the other hand, in the case where the on-state current of the transistor is improved or the field-effect mobility of the transistor is improved, it is preferable to increase the carrier density of the oxide semiconductor. In the case where the carrier density of the oxide semiconductor is increased, the impurity concentration of the oxide semiconductor may be slightly increased, or the density of defect states of the oxide semiconductor may be slightly increased. Alternatively, the band gap of the oxide semiconductor may be reduced. For example, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher density of defect states can be regarded as substantially intrinsic in a range where the on / off ratio of the Id-Vg characteristics of the transistor can be obtained. In addition, an oxide semiconductor having a high electron affinity and accordingly a small band gap and thus an increased density of thermally excited electrons (carriers) can be considered substantially intrinsic. Note that in the case where an oxide semiconductor with higher electron affinity is used, the threshold voltage of the transistor is lower.

The above oxide semiconductor with an increased carrier density is slightly n-type. Therefore, an oxide semiconductor with an increased carrier density may be referred to as “Slightly-n”.

The carrier density of a substantially intrinsic oxide semiconductor is preferably 1 × 10 ⁵ cm ⁻³ or more and less than 1 × 10 ¹⁸ cm ^−3, more preferably 1 × 10 ⁷ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less. It is more preferably 1 × 10 ⁹ cm ⁻³ or more and 5 × 10 ¹⁶ cm ⁻³ or less, further preferably 1 × 10 ¹⁰ cm ⁻³ or more and 1 × 10 ¹⁶ cm ⁻³ or less, and more preferably 1 × 10 ¹¹ cm ⁻³ or more. It is more preferably 1 × 10 ¹⁵ cm ⁻³ or less.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 10)
<Configuration of CAC>
Hereinafter, a structure of a Cloud Aligned Complementary (OS) -OS that can be used in one embodiment of the present invention will be described.

The CAC is a structure of a material in which an element included in an oxide semiconductor is unevenly distributed in a size of, for example, 0.5 nm or more and 10 nm or less, preferably, 1 nm or more and 2 nm or less. Note that in the following, one or more metal elements are unevenly distributed in an oxide semiconductor, and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or a size in the vicinity thereof. The state mixed by is also referred to as a mosaic shape or a patch shape.

For example, CAC-IGZO in an In-Ga-Zn oxide (hereinafter, also referred to as IGZO) refers to indium oxide (hereinafter, InO _X1 (where X1 is a real number greater than 0)) or indium zinc oxide. (Hereinafter, In _X2 Zn _Y2 O _Z2 (X2, Y2, and Z2 are real numbers larger than 0)) and gallium oxide (hereinafter, GaO _X3 (X3 is a real number larger than 0)). ), or gallium zinc oxide _{(hereinafter, Ga X4 Zn Y4 O Z4 (} X4, Y4, and Z4 is greater real than 0) and.) and the like, the material becomes mosaic by separate into, mosaic InO _X1 or In _X2 Zn _Y2 O _Z2 is uniformly distributed in the film (hereinafter, also referred to as a cloud shape).

That is, CAC-IGZO is a composite oxide semiconductor having a structure in which a region containing GaO _X3 as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are mixed. Note that in this specification, for example, it is assumed that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the In concentration is higher than that of the region No. 2.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. Representative examples are _represented by InGaO 3 _(ZnO) m1 (m1 is a natural number), or _{In (1 + x0) Ga (} 1-x0) O 3 (ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number) Crystalline compounds may be mentioned.

The above crystalline compound has a single crystal structure, a polycrystal structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without being oriented in the ab plane.

CAC, on the other hand, relates to the material composition. CAC refers to a region that is observed as a nanoparticle mainly containing Ga as a part and a nanoparticle mainly containing In as a part in a material configuration containing In, Ga, Zn, and O. Observed regions refer to a configuration in which each of the regions is randomly dispersed in a mosaic shape. Thus, in CAC, the crystal structure is a secondary element.

Note that CAC does not include a stacked structure of two or more films having different compositions. For example, a structure including two layers of a film mainly containing In and a film mainly containing Ga is not included.

Note that a clear boundary may not be observed between a region where GaO _X3 is a main component and a region where GaO _X3 is a main component and In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component.

<Analysis of CAC-IGZO>
Next, results of measurement of an oxide semiconductor formed over a substrate using various measurement methods will be described.

構成 Configuration of sample and preparation method 作 製
Hereinafter, nine samples according to one embodiment of the present invention will be described. Each sample is manufactured under different conditions for a substrate temperature and an oxygen gas flow ratio when an oxide semiconductor is formed. Note that the sample has a structure including a substrate and an oxide semiconductor over the substrate.

A method for manufacturing each sample will be described.

First, a glass substrate is used as a substrate. Subsequently, an In-Ga-Zn oxide with a thickness of 100 nm is formed as an oxide semiconductor over a glass substrate with a sputtering device. The deposition conditions are such that the pressure in the chamber is 0.6 Pa, and an oxide target (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) is used as a target. In addition, 2500 W of AC power is supplied to the oxide target provided in the sputtering apparatus.

Note that as a condition for forming an oxide film, the substrate temperature was set to a temperature at which heating was not performed intentionally (hereinafter, also referred to as RT), 130 ° C, or 170 ° C. Further, nine samples are manufactured by setting the flow ratio of oxygen gas to a mixed gas of Ar and oxygen (hereinafter, also referred to as oxygen gas flow ratio) to 10%, 30%, or 100%.

<< Analysis by X-ray diffraction >>
In this section, results of X-ray diffraction (XRD) measurement performed on nine samples will be described. Note that D8 ADVANCE manufactured by Bruker was used as the XRD apparatus. The condition is that the scan range is 15 deg. In the θ / 2θ scan by the out-of-plane method. To 50 deg. , The step width is 0.02 deg. The scanning speed is 3.0 deg. / Min.

FIG. 58 shows the result of measuring an XRD spectrum using the out-of-plane method. In FIG. 58, the upper part shows the measurement results of a sample whose substrate temperature is 170 ° C. during the film formation, the middle part shows the measurement results of the sample whose substrate temperature is 130 ° C. during the film formation, and the lower part shows the measurement result of the film formation Substrate temperature condition is R. T. 2 shows the measurement results of the sample. The left column shows the measurement results for a sample having an oxygen gas flow ratio condition of 10%, the middle column shows the measurement results for a sample having an oxygen gas flow ratio condition of 30%, and the right column shows the oxygen gas flow ratio. The measurement results of a sample in which the ratio condition is 100% are shown.

In the XRD spectrum shown in FIG. 58, the peak intensity near 2θ = 31 ° increases by increasing the substrate temperature during film formation or increasing the ratio of the oxygen gas flow rate during film formation. Note that the peak near 2θ = 31 ° is a crystalline IGZO compound (also referred to as CAAC (c-axis aligned crystalline) -IGZO) which is oriented along the c-axis with respect to a direction substantially perpendicular to the formation surface or the upper surface. It is known to come from.

Further, in the XRD spectrum shown in FIG. 58, a clearer peak did not appear as the substrate temperature during film formation was lower or the oxygen gas flow ratio was smaller. Therefore, it can be seen that the sample in which the substrate temperature at the time of film formation is low or the oxygen gas flow ratio is small has no orientation in the a-b plane direction and the c-axis direction of the measurement region.

≫Analysis by electron microscope≫
In this item, the substrate temperature R.D. T. And a sample prepared at an oxygen gas flow rate ratio of 10% were observed and analyzed by HAADF (High-Angle Annular Dark Field) -STEM (Scanning Transmission Electron Microscope), and the results of analysis (hereinafter, HAADF-EM obtained by HAADF-ST) were described. The image is also called a TEM image.)

A result of image analysis of a plane image (hereinafter, also referred to as a plane TEM image) and a cross-sectional image (hereinafter, also referred to as a cross-sectional TEM image) obtained by the HAADF-STEM will be described. The TEM image was observed using a spherical aberration correction function. The HAADF-STEM image was taken by irradiating an electron beam with an acceleration voltage of 200 kV and a beam diameter of about 0.1 nmφ using an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 59A shows the substrate temperature R.D. T. FIG. 4 is a planar TEM image of a sample manufactured at an oxygen gas flow rate ratio of 10%. FIG. 59B shows the substrate temperature R.D. T. 3 is a cross-sectional TEM image of a sample manufactured at a flow rate of 10% and oxygen gas.

≫Analysis of electron diffraction pattern≫
In this item, the substrate temperature R.D. T. The result obtained by irradiating an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam) to a sample manufactured at a flow rate ratio of oxygen gas of 10% to obtain an electron beam diffraction pattern will be described.

As shown in FIG. T. , And an electron beam diffraction pattern indicated by black point a1, black point a2, black point a3, black point a4, and black point a5 in a planar TEM image of a sample manufactured at an oxygen gas flow rate ratio of 10%. The observation of the electron beam diffraction pattern is performed while moving at a constant speed from the position of 0 seconds to the position of 35 seconds while irradiating the electron beam. FIG. 59 (C) shows the result of black point a1, FIG. 59 (D) shows the result of black point a3, FIG. 59 (E) shows the result of black point a3, FIG. 59 (F) shows the result of black point a4, and FIG. It is shown in FIG.

From FIG. 59C, FIG. 59D, FIG. 59E, FIG. 59F, and FIG. 59G, a region with high luminance can be observed in a circular shape (in a ring shape). Further, a plurality of spots can be observed in the ring-shaped area.

In addition, as shown in FIG. T. , And an electron beam diffraction pattern indicated by black point b1, black point b2, black point b3, black point b4, and black point b5 in a cross-sectional TEM image of a sample manufactured at an oxygen gas flow rate ratio of 10%. FIG. 59 (H) shows the result of black point b1, FIG. 59 (I) shows the result of black point b3, FIG. 59 (J) shows the result of black point b3, FIG. 59 (K) shows the result of black point b4, and FIG. It is shown in FIG.

59 (H), 59 (I), 59 (J), 59 (K), and 59 (L), a region having a high luminance can be observed in a ring shape. Further, a plurality of spots can be observed in the ring-shaped area.

Here, for example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS having an InGaZnO ₄ crystal in parallel to a sample surface, a spot caused by the (009) plane of the InGaZnO ₄ crystal is included. A diffraction pattern is seen. That is, the CAAC-OS has c-axis orientation and the c-axis is oriented substantially perpendicular to the formation surface or the upper surface. On the other hand, when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicular to the sample surface, a ring-shaped diffraction pattern is confirmed. That is, in the CAAC-OS, the a-axis and the b-axis have no orientation.

In addition, when an electron diffraction using an electron beam having a large probe diameter (for example, 50 nm or more) is performed on an oxide semiconductor having nanocrystals (nanocrystalline oxide semiconductor, hereinafter referred to as nc-OS), a halo pattern is obtained. A strong diffraction pattern is observed. When nanobeam electron diffraction using an electron beam with a small probe diameter (for example, less than 50 nm) is performed on the nc-OS, a bright point (spot) is observed. In addition, when nanobeam electron diffraction is performed on the nc-OS, a high-luminance region may be observed in a circular shape (in a ring shape). Further, a plurality of bright spots may be observed in a ring-shaped area.

Substrate temperature during film formation T. The electron beam diffraction pattern of the sample prepared at a flow rate of 10% and an oxygen gas has a ring-shaped region with high brightness and a plurality of bright spots in the ring region. Therefore, the substrate temperature R.D. T. And the sample produced at an oxygen gas flow rate ratio of 10% has an electron diffraction pattern of nc-OS, and has no orientation in the plane direction and the cross-sectional direction.

As described above, an oxide semiconductor having a low substrate temperature at the time of film formation or a low oxygen gas flow ratio has a property distinctly different from an oxide semiconductor film having an amorphous structure and an oxide semiconductor film having a single crystal structure. Can be estimated.

≪Elemental analysis≫
In this item, by using EDX (Energy Dispersive X-ray spectroscopy), an EDX mapping is acquired and evaluated to obtain a substrate temperature R.D. T. And the results of elemental analysis of a sample prepared at an oxygen gas flow rate ratio of 10% will be described. In the EDX measurement, an energy dispersive X-ray analyzer JED-2300T manufactured by JEOL Ltd. is used as an element analyzer. Note that a Si drift detector is used to detect X-rays emitted from the sample.

In the EDX measurement, each point in the analysis target region of the sample is irradiated with an electron beam, the energy of the characteristic X-rays generated by the sample and the number of times of generation are measured, and an EDX spectrum corresponding to each point is obtained. In this embodiment mode, the peaks of the EDX spectrum at each point are represented by the electronic transition of an In atom to an L shell, the electronic transition of a Ga atom to a K shell, the electronic transition of a Zn atom to a K shell, and the K shell of an O atom. And the ratio of each atom at each point is calculated. By performing this for the analysis target region of the sample, it is possible to obtain an EDX mapping showing the distribution of the ratio of each atom.

FIG. 60 shows the substrate temperature R.D. T. And EDX mapping in a cross section of a sample manufactured at an oxygen gas flow ratio of 10%. FIG. 60A shows EDX mapping of Ga atoms (the ratio of Ga atoms to all atoms is in the range of 1.18 to 18.64 [atomic%]). FIG. 60B is an EDX mapping of In atoms (the ratio of In atoms to all atoms is in the range of 9.28 to 33.74 [atomic%]). FIG. 60C is an EDX mapping of Zn atoms (the ratio of Zn atoms to all atoms is in the range of 6.69 to 24.99 [atomic%]). FIGS. 60A, 60B and 60C show the substrate temperature R.D. T. And the cross section of the sample manufactured at an oxygen gas flow rate ratio of 10% shows the same range of regions. In the EDX mapping, the proportion of elements is shown in a light and dark manner so that, in a range, the larger the number of measured elements, the brighter and the smaller the number of measured elements, the darker. The magnification of the EDX mapping shown in FIG. 60 is 7.2 million times.

In the EDX mapping shown in FIGS. 60 (A), 60 (B), and 60 (C), a relatively bright and dark distribution is observed in the image, and the substrate temperature R.D. T. And a sample prepared with an oxygen gas flow ratio of 10%, it can be confirmed that each atom has a distribution. Here, attention is paid to a range surrounded by a solid line and a range surrounded by a broken line shown in FIGS. 60 (A), 60 (B), and 60 (C).

In FIG. 60A, a range surrounded by a solid line includes many relatively dark regions, and a range surrounded by a broken line includes many relatively bright regions. In FIG. 60B, a range surrounded by a solid line includes many relatively bright regions, and a range surrounded by a broken line includes many relatively dark regions.

That is, the range surrounded by the solid line is a region where the number of In atoms is relatively large, and the range surrounded by the broken line is a region where the number of In atoms is relatively small. Here, in FIG. 60C, in the range surrounded by the solid line, the right side is a relatively bright area, and the left side is a relatively dark area. Therefore, a range surrounded by a solid line is a region in which In _X2 Zn _Y2 O _Z2 , InO _X1 , or the like is a main component.

The range surrounded by the solid line is a region where the number of Ga atoms is relatively small, and the range surrounded by the broken line is a region where the number of Ga atoms is relatively large. In FIG. 60C, the upper left area is a relatively bright area and the lower right area is a relatively dark area in a range surrounded by a broken line. Therefore, a range surrounded by a broken line is a region in which GaO _X3 , Ga _X4 Zn _Y4 O _Z4 , or the like is a main component.

Further, from FIGS. 60A, 60B, and 60C, the distribution of In atoms is relatively more uniform than that of Ga atoms, and InO _X1 is a main component. The regions appear to be connected to each other through a region in which In _X2 Zn _Y2 O _Z2 is a main component. As described above, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is formed to spread in a cloud shape.

As described above, an In—Ga—Zn oxide having a structure in which a region containing GaO _X3 as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are unevenly distributed and mixed. Can be referred to as CAC-IGZO.

Further, the crystal structure in CAC has an nc structure. The nc structure of CAC has, in an electron diffraction image, several or more bright spots (spots) besides a single crystal, a polycrystal, or a bright spot (spot) caused by IGZO including the CAAC structure. Alternatively, the crystal structure is defined such that a region having high brightness appears in a ring shape in addition to several or more bright spots (spots).

According to FIGS. 60A, 60B, and 60C, the size of the region where GaO _X3 is a main component and the region where In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component are shown. Is observed from 0.5 nm to 10 nm, or from 1 nm to 3 nm. Preferably, in the EDX mapping, the diameter of a region in which each metal element is a main component is greater than or equal to 1 nm and less than or equal to 2 nm.

As described above, CAC-IGZO has a different structure from an IGZO compound in which metal elements are uniformly distributed, and has different properties from an IGZO compound. In other words, CAC-IGZO is phase-separated into a region containing GaO _X3 or the like as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component. Has a mosaic structure. Therefore, when CAC-IGZO is used for a semiconductor element, a property caused by GaO _X3 or the like and a property caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act complementarily to each other, resulting in a high on-current. (I _on ) and high field-effect mobility (μ).

A semiconductor element using CAC-IGZO has high reliability. Therefore, CAC-IGZO is most suitable for various semiconductor devices including a display.

This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification or another example.

(Embodiment 11)
In this embodiment, an example of a package and a module containing an image sensor chip will be described. The structure of the imaging device of one embodiment of the present invention can be used for the image sensor chip.

FIG. 53A is an external perspective view of an upper surface side of a package containing an image sensor chip. The package includes a package substrate 810 for fixing the image sensor chip 850, a cover glass 820, an adhesive 830 for bonding the two, and the like.

FIG. 53B is an external perspective view of the lower surface side of the package. The lower surface of the package has a BGA (Ball grid array) configuration in which solder balls are used as bumps 840. In addition, not limited to BGA, LGA (Land Grid Array) or PGA (Pin Grid Array) may be used.

FIG. 53 (C) is a perspective view of the package with a cover glass 820 and a part of the adhesive 830 omitted, and FIG. 53 (D) is a cross-sectional view of the package. An electrode pad 860 is formed on the package substrate 810, and the electrode pad 860 and the bump 840 are electrically connected through a through hole 880 and a land 885. The electrode pad 860 is electrically connected to an electrode of the image sensor chip 850 by a wire 870.

FIG. 54A is an external perspective view of the upper side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 811 for fixing the image sensor chip 851, a lens cover 821, a lens 835, and the like. Further, an IC chip 890 having a function such as a driving circuit and a signal conversion circuit of an imaging device is provided between the package substrate 811 and the image sensor chip 851, and has a configuration as a SiP (System in package). I have.

FIG. 54B is an external perspective view of the lower surface side of the camera module. The lower surface and four side surfaces of the package substrate 811 have a QFN (Quad flat no-lead package) configuration in which mounting lands 841 are provided. Note that this configuration is an example, and a QFP (Quad flat package) or the above-described BGA may be used.

FIG. 54C is a perspective view of the module with a part of the lens cover 821 and the lens 835 omitted, and FIG. 54D is a cross-sectional view of the camera module. A part of the land 841 is used as an electrode pad 861, and the electrode pad 861 is electrically connected to electrodes of the image sensor chip 851 and the IC chip 890 by wires 871.

By mounting the image sensor chip in a package having the above-described form, mounting becomes easy, and the image sensor chip can be incorporated in various semiconductor devices and electronic devices.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 12)
In the present embodiment, a case will be described in which the imaging device 10 described in Embodiment 1 is used as a monitoring device.

FIG. 55 is a block diagram illustrating a configuration example of a monitoring device according to the present embodiment. The monitoring device has a camera 600, a storage device 24, and a display device 23. The camera 600 includes the imaging device 10 which is an imaging device of one embodiment of the present invention. The camera 600, the storage device 24, and the display device 23 are each functionally connected. The image captured by the camera 600 is recorded in the storage device 24 and displayed on the display device 23.

The camera 600 outputs the image data captured by the image capturing device 10 to the storage device 24 and the display device 23 only when a difference between the reference frame and the difference detection frame is detected. For this reason, the frequency of outputting the imaging data to the storage device 24 and the display device 23 can be reduced as compared with the case where the difference detection is not performed, so that the power consumption in the storage device 24 and the display device 23 can be reduced. In addition, the storage capacity of the storage device 24 can be saved, and not only can imaging be performed for a longer time, but also required data can be easily searched from stored data.

In addition, in the imaging device 10, a process of consuming an enormous amount of power such as A / D conversion may be performed only when acquiring imaging data to be output to the storage device 24 and the display device 23. Therefore, power consumption can be reduced as compared with a case where difference detection is not performed or a case where difference detection is performed using data after A / D conversion.

The monitoring device according to the present embodiment can output image data to the storage device 24 and the display device 23 only when, for example, detecting an event that easily causes a traffic accident. FIG. 56 shows an image displayed on the display device 23 when the camera 600 is installed above the T-junction. On the T-shaped road, it is assumed that the accident occurrence rate of a car turning right is high and the accident occurrence rate of a car going straight is low. In this case, when the difference between the reference frame and the difference detection frame described above in the first embodiment is detected near the T-shaped road with a high accident occurrence rate, new imaging data is acquired and output to an external device. By setting the area 41, when a vehicle passes near a T-shaped road, image data can be output to the storage device 24 and the display device 23. On the other hand, even when the vehicle passes through a straight line area such as the area 43 where the accident occurrence rate is low, the image data is not output to the storage device 24 and the display device 23. That is, it is possible to store the image data in the storage device 24 and update the image displayed on the display device 23 only when the vehicle has passed a place where the accident occurrence rate is high. Thereby, power consumption and storage capacity of the storage device 24 can be reduced. Further, when an accident occurs in the area 41, an image at the time of occurrence of the accident can be easily searched.

When the reference frame is not updated, it is considered that a difference is detected even if the vehicle does not pass through the area 41, for example, even if the brightness changes with time, and the image data is stored in the storage device 24 and the display device 23. It may be output. For example, when the reference frame is photographed at midnight, if it becomes bright in the morning, it is considered that a difference has been detected in all frames regardless of whether or not a vehicle passes through the area 41. In addition, for example, when the traffic volume at midnight is small, the reference frame may not be rewritten until it becomes bright in the morning. Therefore, by periodically rewriting the reference frame, the imaging data can be output to the storage device 24 and the display device 23 only when the vehicle passes through the area 41. Thereby, power consumption and storage capacity of the storage device 24 can be reduced. Further, when an accident occurs in the area 41, an image at the time of occurrence of the accident can be easily searched.

Note that the monitoring device according to the present embodiment can be applied to various uses such as a security camera for capturing an image of an illegal intruder.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 13)
In this embodiment, an example of an electronic device to which the imaging device of one embodiment of the present invention can be applied will be described.

As an electronic device to which the imaging device of one embodiment of the present invention can be applied, a display device such as a television and a monitor, a lighting device, a desktop or notebook personal computer, a word processor, and a recording medium such as a DVD (Digital Versatile Disc) are provided. Image reproducing device for reproducing the recorded still image or moving image, portable CD player, radio, tape recorder, headphone stereo, stereo, navigation system, table clock, wall clock, cordless telephone handset, transceiver, mobile phone, car phone, portable type Large game machines such as game machines, tablet terminals, pachinko machines, calculators, portable information terminals, electronic notebooks, electronic book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, microwave ovens, etc. high frequency Heating equipment, electric rice cooker, electric washing machine, vacuum cleaner, water heater, electric fan, hair dryer, air conditioner, humidifier, air conditioner such as dehumidifier, dishwasher, dish dryer, clothes dryer, futon dryer Appliances, electric refrigerators, electric freezers, electric freezers, DNA storage freezers, flashlights, tools such as chainsaws, smoke detectors, medical equipment such as dialysis machines, facsimile machines, printers, multifunction printers, automatic teller machines ( ATM), vending machines and the like. Further, industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, and power storage devices for leveling and smart grid power. In addition, moving objects driven by electric motors using electric power are also included in the category of electronic devices. Examples of the moving body include an electric vehicle (EV), a hybrid vehicle (HEV) having both an internal combustion engine and an electric motor, a plug-in hybrid vehicle (PHEV), a tracked vehicle having these tire wheels changed to an endless track, an electric assist. Motorized bicycles including bicycles, motorcycles, electric wheelchairs, golf carts, small or large vessels, submarines, helicopters, aircraft, rockets, satellites, space and planetary probes, spacecrafts, and the like.

FIG. 57A illustrates a monitoring device including a housing 961, a lens 962, a supporting portion 963, and the like. An imaging device of one embodiment of the present invention can be provided at a position where the lens 962 is a focal point. As the monitoring device, the monitoring device described in Embodiment 12 can be used.

FIG. 57B illustrates a video camera, which includes a housing 941, a housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation keys 944 and the lens 945 are provided on the housing 941, and the display portion 943 is provided on the housing 942. The housing 941 and the housing 942 are connected by a connection portion 946, and the angle between the housing 941 and the housing 942 can be changed by the connection portion 946. The image on the display portion 943 may be switched according to the angle between the housing 941 and the housing 942 in the connection portion 946. An imaging device of one embodiment of the present invention can be provided at a position where the lens 945 is a focal point.

FIG. 57C illustrates a mobile phone, which includes a display portion 952, a microphone 957, a speaker 954, a camera 959, an input / output terminal 956, operation buttons 955, and the like in a housing 951. The imaging device of one embodiment of the present invention can be used for the camera 959.

FIG. 57D illustrates a digital camera, which includes a housing 921, a shutter button 922, a microphone 923, a light-emitting portion 927, a lens 925, and the like. An imaging device of one embodiment of the present invention can be provided at a position where the lens 925 is a focal point.

FIG. 57E illustrates a portable game machine including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, a camera 909, and the like. Note that the portable game machine illustrated in FIG. 57A includes two display portions 903 and 904; however, the number of display portions included in the portable game machine is not limited to this. The imaging device of one embodiment of the present invention can be used for the camera 909.

FIG. 57F illustrates a wristwatch-type information terminal, which includes a housing 931, a display portion 932, a wristband 933, a camera 939, and the like. The display unit 932 may be a touch panel. The imaging device of one embodiment of the present invention can be used for the camera 939.

Note that there is no particular limitation on the electronic devices described above as long as the imaging device of one embodiment of the present invention is provided.

This embodiment can be combined with any of the other embodiments in this specification as appropriate.

REFERENCE SIGNS LIST 10 imaging device 11 pixel 12 pixel array 13 circuit 14 circuit 15 circuit 16 circuit 17 circuit 18 circuit 19 circuit 21 circuit 22 circuit 23 display device 24 storage device 25 circuit 31 imaging data 32 row address 33 column address 34 clock signal 35 clock signal 36 Signal 37 Row address 38 Column address 39 Signal 41 Area 42 Coordinate 43 Area 50 Transistor 51 Transistor 52 Transistor 53 Transistor 54 Transistor 55 Transistor 56 Transistor 57 Transistor 58 Transistor 59 Transistor 60 Transistor 61 Transistor 62 Transistor 63 Capacitance element 64 Comparator 65 Comparator 70 Wiring 71 wiring 72 wiring 73 wiring 76 wiring 78 wiring 81 wiring 82 wiring 84 wiring 85 wiring 91 conductor 92 insulation Layer 92a insulating layer 92b insulating layer 93 insulating layer 94 wiring 94a conductive layer 94b conductive layer 95 wiring 96 insulating layer 100 silicon substrate 101 transistor 102 transistor 105 active layer 106 silicon substrate 120 photoelectric conversion element 121 photoelectric conversion layer 122 translucent conductive layer 123 semiconductor layer 124 semiconductor layer 125 semiconductor layer 126 electrode 126a conductive layer 126b conductive layer 127 partition 131 transistor 132 transistor 133 transistor 134 transistor 135 transistor 141 capacitor element 142 capacitor element 151 wiring 152 wiring 153 wiring 154 wiring 155 wiring 156 wiring 161 wiring 162 Wiring 163 Wiring 165 Wiring 201 Imaging operation 202 Data holding operation 203 Reading operation 210 Pixel 211 Transistor 212 Liquid crystal element 213 Capacitance Child 214 memory 215 wiring 216 wiring 217 wiring 221 transistor 222 transistor 223 light emitting element 401 transistor 402 transistor 403 transistor 404 transistor 405 transistor 406 transistor 407 transistor 408 transistor 409 transistor 410 transistor 411 transistor 412 transistor 413 transistor 415 substrate 420 insulating layer 430 oxide Semiconductor layer 430a oxide semiconductor layer 430b oxide semiconductor layer 430c oxide semiconductor layer 440 conductive layer 441 conductive layer 442 conductive layer 450 conductive layer 451 conductive layer 452 conductive layer 460 insulating layer 470 conductive layer 471 conductive layer 472 conductive layer 473 conductive layer 475 insulating layer 480 insulating layer 531 region 532 region 533 region 534 region 53 Area 600 Camera 810 Package substrate 811 Package substrate 820 Cover glass 821 Lens cover 830 Adhesive 835 Lens 840 Bump 841 Land 850 Image sensor chip 851 Image sensor chip 860 Electrode pad 861 Electrode pad 870 Wire 871 Wire 880 Through hole 885 Land 890 IC chip 901 housing 902 housing 903 display unit 904 display unit 905 microphone 906 speaker 907 operation keys 908 stylus 909 camera 921 housing 922 shutter button 923 microphone 925 lens 927 light emitting unit 931 housing 932 display unit 933 wristband 939 camera 941 housing 942 housing 943 display unit 944 operation keys 945 lens 946 connection unit 951 housing 952 display unit 954 speaker 955 button 956 input / output terminal 957 microphone 959 camera 961 housing 962 lens 963 support portion 1100 layer 1200 layer 1400 layer 1500 diffraction grating 1600 layer 2500 insulating layer 2510 light shielding layer 2520 organic resin layer 2530 color filter 2530a color filter 2530b color filter 2530c color Filter 2540 Micro lens array 2550 Optical conversion layer 2560 Insulating layer

Claims (11)

A pixel, a first circuit, a second circuit, a third circuit, a fourth circuit, a fifth circuit, a sixth circuit, and a seventh circuit,
The pixels are arranged in a matrix to form a pixel array,
The first circuit has a function of selecting a row of the pixel array,
The second circuit has a function of selecting a column of the pixel array,
The third circuit has a function of calculating a difference between image data of a first frame and image data of a second frame of a pixel selected by the first circuit and the second circuit. And
The fourth circuit has a function of outputting a row address of a pixel subjected to the difference calculation,
The fifth circuit has a function of outputting a column address of a pixel subjected to the difference calculation,
The sixth circuit has a function of storing a row address and a column address that define a designated area of the pixel array,
The seventh circuit includes: a coordinate included in an area defined by a row address and a column address stored in the sixth circuit; and coordinates including a row address and a column address of a pixel whose difference is detected. An imaging apparatus characterized by having a function of comparing. In claim 1,
When the coordinates composed of the row address and the column address of the pixel for which the difference has been detected are included in the area stored in the sixth circuit, image data of a third frame is acquired, and the image data is acquired. An imaging device having a function of outputting to an external device. In claim 2,
Two row addresses and two column addresses of the specified pixel array are stored in the sixth circuit to form four coordinates,
When the coordinates composed of the row address and the column address of the pixel from which the difference has been detected are included in the rectangle enclosed by the four coordinates stored in the sixth circuit, the third frame An image pickup apparatus having a function of acquiring image pickup data and outputting the image pickup data to the external device. In any one of claims 1 to 3,
The pixel has a transistor and a photoelectric conversion element,
In the transistor, the active layer includes an oxide semiconductor,
An imaging device, wherein the oxide semiconductor includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). In claim 4,
The imaging device, wherein the photoelectric conversion element includes selenium or a compound containing selenium in a photoelectric conversion layer. In a first step, acquiring imaging data of a first frame,
In the second step, outputting the imaging data of the first frame to an external device,
In the third step, it is determined whether to return to the first step,
If the process does not return to the first step, after obtaining the image data of the second frame, in the fourth step, after obtaining the image data of the third frame, the second frame is obtained. The difference between the image data of the third frame and the image data of the third frame is calculated for each pixel, and the row address and column address of the pixel subjected to the difference calculation are calculated.
If no difference is detected, the process returns to the fourth step,
If a difference is detected in the fourth step, in a fifth step, it is determined whether or not to output imaging data to the external device,
When the imaging data is not output to the external device, the process returns to the fourth step,
When outputting the imaging data to the external device, in a sixth step, acquisition of imaging data of a fourth frame is performed;
The method according to claim 7, further comprising returning to the fourth step after outputting the imaging data of the fourth frame to the external device in the seventh step. In claim 6,
When no difference is detected by the difference calculation in the fourth step and / or
When it is determined in the fifth step that the imaging data is not output to the external device,
An operation method of the imaging apparatus, wherein the method returns to the fourth step after acquiring the imaging data of the second frame. In claim 6 or 7,
Designate an area of a pixel array formed by arranging a plurality of the pixels,
Acquiring the imaging data of the fourth frame by the sixth step when the coordinates formed by the row address and the column address of the pixel from which the difference is detected are included in the pixel array area; An operation method of the imaging apparatus, wherein the imaging data is output to the external device in the step (7). In claim 8,
Designating four coordinates by designating two row addresses and two column addresses of the pixel array,
An operation method of an imaging device, wherein an inside of a rectangle surrounded by the four coordinates is a region of the pixel array. In any one of claims 6 to 9,
The operation method of an imaging device, wherein the external device is a display device and / or a storage device.   An electronic apparatus, comprising: the imaging device according to claim 1; and a display device.