JP2020109995A - Electronic apparatus - Google Patents

Abstract

To provide an imaging apparatus that can reduce power consumption.SOLUTION: In an imaging apparatus 10, pixels 11 are arranged in matrix to form a pixel array 12. The imaging apparatus selects a row and a column of the pixel array with first and second circuits 13, 14, 17, and performs difference calculation between imaging data of a first frame and image data of a second frame of a selected pixel with a third circuit 16, and outputs a row address and a column address of the pixel for which the difference calculation is performed or a pixel for which difference calculation is performed immediately before the pixel with fourth and fifth circuits 18, 19. The imaging apparatus stores a row address and a column address defining a designated region of the pixel array in a sixth circuit 21, and compares the coordinates included in the stores region with the coordinates of the pixel in which the difference is detected with a seventh circuit 22. When the coordinates of the pixel in which the difference is detected are included in the region stored by the sixth circuit 21, the imaging apparatus acquires imaging data of a third frame and outputs the imaging data to external apparatuses, such as a display device and a storage device.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to an imaging device, an operation method thereof, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, as technical fields of one embodiment of the present invention disclosed in this specification, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, a storage device,
The driving method thereof or the manufacturing method thereof can be cited as an example.

A display device has been proposed in which a transistor having a small leak current is used as a pixel transistor to reduce the frequency of rewriting image data (for example, Patent Document 1). When rewriting the image data, the image data of the difference detection frame and the image data of the reference frame are compared by digital processing by the difference processing, and it is determined whether or not the image data needs to be rewritten based on the digital processing result. .. By reducing the frequency of rewriting image data, the power consumption of the display device is reduced.

U.S. Patent Application Publication No. 2011/0090204

In order to further reduce the power consumption of the image pickup apparatus, it is desirable to further reduce the frequency of rewriting image pickup data. Further, this makes it possible to save the storage capacity when the imaged data is stored in the storage device.

An object of one embodiment of the present invention is to provide a novel imaging device, a novel imaging device operating method, a novel electronic device, and the like.

Alternatively, it is an object of one embodiment of the present invention to provide an imaging device or the like having a novel structure that can reduce power consumption. Alternatively, it is an object of one embodiment of the present invention to provide an imaging device or the like having a novel structure in which it is possible to determine whether or not to rewrite imaging data while holding the imaging data written in a pixel. Alternatively, it is an object of one embodiment of the present invention to provide an imaging device or the like having a novel structure in which the storage capacity of a storage device for storing imaging data can be saved.

Another object of one embodiment of the present invention is to provide a novel method for operating an imaging device and the like that can reduce power consumption. Another object of one embodiment of the present invention is to provide a novel method for operating an imaging device in which it is possible to determine the necessity of rewriting imaging data while holding the imaging data written in pixels. .. Another object of one embodiment of the present invention is to provide a novel method for operating an imaging device in which the storage capacity of a storage device for storing imaging data can be saved.

Note that the problem of one embodiment of the present invention is not limited to the problems listed above. The issues listed above are
It does not prevent the existence of other issues. The other issues are the ones not mentioned in this item, which will be described below. Problems that are not mentioned in this item can be derived from the description such as the specification or the drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention is to solve at least one of the above description and/or other problems.

One embodiment of the present invention is a pixel, a first circuit, a second circuit, a third circuit, a fourth circuit, a fifth circuit, a sixth circuit, and a seventh circuit. And an image pickup apparatus including. The pixels are arranged in a matrix to form a pixel array, the first circuit has a function of selecting a row of the pixel array, the second circuit has a function of selecting a column of the pixel array, and a third circuit The circuit of 2 has a function of calculating a difference between the image data of the first frame and the image data of the second frame of the pixel selected by the first circuit and the second circuit. Further, the fourth circuit has a function of outputting a row address of a pixel which is a target of difference calculation, and the fifth circuit has a function of outputting a column address of a pixel which is a target of difference calculation. Further, the sixth circuit has a function of storing a row address and a column address which define a specified region of the pixel array, and a seventh circuit uses the row address and the column address stored in the sixth circuit. Coordinates included in the defined area,
It is characterized by having a function of comparing with a coordinate composed of a row address and a column address of a pixel for which a difference is detected.

In addition, in the imaging device of one embodiment of the present invention, when the coordinates including the row address and the column address of the pixel in which the difference is detected are included in the region stored in the sixth circuit, It may have a function of acquiring image pickup data and outputting the image pickup data to an external device.

Further, in the imaging device of one embodiment of the present invention, two row addresses and two column addresses of a specified pixel array are stored in the sixth circuit to form four coordinates, and a row of pixels in which a difference is detected. When the coordinate composed of the address and the column address is included in the inside of the quadrangle surrounded by the four coordinates stored in the sixth circuit, the image data of the third frame is acquired, and the image data is acquired. It may have a function of outputting to an external device.

Further, in the imaging device of one embodiment of the present invention, the pixel may include a transistor and a photoelectric conversion element. In the transistor, the active layer has an oxide semiconductor, and the oxide semiconductor is I
n, Zn, M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or H
f) and may be included.

The photoelectric conversion element may have selenium or a compound containing selenium in the photoelectric conversion layer.

A method for operating the imaging device is also one embodiment of the present invention. In the operation method, in the first step, the image data of the first frame is acquired, in the second step, the image data of the first frame is output to an external device, and in the third step, the image data of the first frame is output. If it does not return to the first step, it is determined whether or not to return to the first step, and after acquiring the imaging data of the second frame, the imaging data of the third frame is acquired in the fourth step. Of the second frame and the third frame, the difference calculation between the image data of the second frame and the image data of the third frame is performed for each pixel, and the row address and the column address of the pixel subjected to the difference calculation are further calculated. To calculate. When the difference is not detected, the procedure returns to the fourth step, and when the difference is detected in the fourth step, in the fifth step, it is determined whether or not the imaging data is output to the external device, When the imaging data is not output to the external device, the process returns to the fourth step. When the imaging data is output to the external device, the imaging data of the fourth frame is acquired in the sixth step, and the seventh step is performed. In, after outputting the image data of the fourth frame to the external device, the process returns to the fourth step.

In addition, according to the operation method of the imaging device of one embodiment of the present invention, it is determined that the imaging data is not output to the external device when the difference is not detected by the difference calculation in the fourth step and/or the fifth step. In that case, the imaging data of the second frame may be acquired, and then the process may return to the fourth step.

Further, according to an operation method of an imaging device of one embodiment of the present invention, a region of a pixel array formed by arranging a plurality of pixels is designated, and a coordinate including a row address and a column address of a pixel in which a difference is detected is determined. When the image data is included in the area of the pixel array, the image data of the fourth frame may be acquired in the sixth step, and the image data may be output to an external device in the seventh step.

Further, according to an operation method of an imaging device of one embodiment of the present invention, four coordinates are specified by specifying two row addresses and two column addresses of a pixel array, and an inside of a rectangle surrounded by the four coordinates is specified. It may be a region of the pixel array.

The external device may be a display device and/or a storage device.

An electronic device including the imaging device of one embodiment of the present invention and the display device is also one embodiment of the present invention.

One embodiment of the present invention can provide a novel imaging device, a method for operating the novel imaging device, a novel electronic device, and the like.

Alternatively, according to one embodiment of the present invention, it is possible to provide an imaging device or the like having a novel structure that can reduce power consumption. Alternatively, according to one embodiment of the present invention, an imaging device or the like having a novel structure can be provided in which it is possible to determine whether or not to rewrite imaging data in a state where imaging data written in a pixel is held. Alternatively, according to one embodiment of the present invention, an imaging device or the like having a novel structure in which the storage capacity of a storage device for storing imaging data can be saved can be provided.

Alternatively, one embodiment of the present invention can provide a novel method for operating an imaging device and the like that can reduce power consumption. Alternatively, according to one embodiment of the present invention, a novel method for operating an imaging device and the like, which can determine whether or not imaging data written in a pixel is held, can be provided. Alternatively, one embodiment of the present invention can provide a novel method for operating an imaging device in which the storage capacity of a storage device for storing imaging data can be saved.

Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above are
It does not prevent the existence of other effects. The other effects are the effects which are not mentioned in this item, which will be described below. The effects not mentioned in this item can be derived from the description in the specification or the drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and/or other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

The block diagram of an imaging device. The block diagram of an imaging device. 6 is a flowchart illustrating an operation of the imaging device. The figure explaining the output determination to the external device of imaging data. FIG. 6 illustrates a pixel circuit of an imaging device. 7 is a timing chart illustrating an imaging operation. 7 is a timing chart illustrating an imaging operation. FIG. 6 illustrates a pixel circuit of an imaging device. FIG. 6 illustrates a pixel circuit of an imaging device. FIG. 6 illustrates a pixel circuit of an imaging device. FIG. 6 illustrates a pixel circuit of an imaging device. FIG. 6 illustrates a pixel circuit of an imaging device. FIG. 6 illustrates a pixel circuit of an imaging device. The figure explaining operation of a rolling shutter system and a global shutter system. FIG. 6 illustrates a pixel circuit of an imaging device. FIG. 6 illustrates a pixel circuit of an imaging device. FIG. 6 illustrates a difference detection circuit of an imaging device. 6 is a timing chart illustrating a difference detection operation of the image pickup apparatus. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. 3A and 3B are a cross-sectional view and a circuit diagram illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a cross-sectional view illustrating a structure of an imaging device. FIG. 6 illustrates a curved imaging device. FIG. 6 illustrates a pixel circuit of a display device. FIG. 6 illustrates a pixel circuit of a display device. 3A and 3B are a top view and a cross-sectional view illustrating a transistor. 3A and 3B are a top view and a cross-sectional view illustrating a transistor. 6A to 6C each illustrate a cross section of a transistor in a channel width direction. 3A and 3B are a top view and a cross-sectional view illustrating an oxide semiconductor layer. 3A and 3B are a top view and a cross-sectional view illustrating a transistor. 3A and 3B are a top view and a cross-sectional view illustrating a transistor. 6A to 6C each illustrate a cross section of a transistor in a channel width direction. 6A to 6C each illustrate a cross section of a transistor in a channel length direction. 6A to 6C each illustrate a cross section of a transistor in a channel length direction. 3A and 3B are a top view and a cross-sectional view illustrating a transistor. FIG. 6 is a top view illustrating a transistor. 6A to 6C each illustrate a structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD, and a selected area electron diffraction pattern of the CAAC-OS. A cross-sectional TEM image of the CAAC-OS, a planar TEM image, and an image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 10 is a diagram showing a change in a crystal part of an In—Ga—Zn oxide by electron irradiation. 3A and 3B are a perspective view and a cross-sectional view of a package including an imaging device. 3A and 3B are a perspective view and a cross-sectional view of a package including an imaging device. The figure explaining the structure of a monitoring apparatus. The figure explaining the use of a monitoring device. 7A to 7C each illustrate an electronic device. The figure explaining the measurement result of the XRD spectrum of a sample. 6A and 6B each illustrate a TEM image of a sample and an electron diffraction pattern. The figure explaining EDX mapping of a sample.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously modified without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structure of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and repeated description thereof may be omitted. In addition, hatching of the same elements forming the drawings may be appropriately omitted or changed between different drawings.

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to that scale. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, a signal due to noise, a variation in voltage or current, or a signal due to a timing shift,
It is possible to include variations in voltage or current.

In addition, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, the channel region, and the source. Can be done.

Here, since the source and the drain are changed depending on the structure of the transistor, operating conditions, and the like, it is difficult to determine which is the source or the drain. For this reason,"
The terms “source” and “drain” can be interchanged with each other depending on the case or circumstances.

It should be noted that the ordinal numbers “first”, “second”, and “third” used in this specification are added to avoid confusion among constituent elements, and are not limited numerically. To do.

Further, in this specification and the like, when it is explicitly described that X and Y are connected, a case where X and Y are electrically connected and a case where X and Y function The case where they are connected to each other and the case where X and Y are directly connected are disclosed in this specification and the like.
Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text,
Other than the connection relation shown in the figure or the text, it shall be described in the figure or the text.

Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive layers, layers, etc.).

As an example of the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display, etc.) that enables an electrical connection between X and Y is given. Elements, light-emitting elements, loads, etc.) are not connected between X and Y, and elements that enable electrical connection between X and Y (for example, switches, transistors, capacitive elements, inductors) , Resistor element, diode, display element, light emitting element, load, etc.) and X and Y are connected.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display, etc.) that enables the X and Y to be electrically connected. Element, light emitting element, load, etc.) may be connected between X and Y. The switch has a function of controlling on/off. That is, the switch is in a conducting state (on state) or a non-conducting state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

Examples of the case where X and Y are functionally connected include a circuit (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.)) that enables functional connection between X and Y, and signal conversion. Circuits (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (step-up circuit, step-down circuit, etc.), level shifter circuit for changing signal potential level, etc.)
, Voltage source, current source, switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc. ) Can be connected more than once between X and Y. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. To do. Note that X and Y
When and are functionally connected, when X and Y are directly connected, and when X and Y are connected.
It includes cases where and are electrically connected.

In addition, when it is explicitly described that X and Y are electrically connected, when X and Y are electrically connected (that is, when X and Y are separately connected, Element or another circuit is sandwiched and connected) and X and Y are functionally connected (that is, another circuit is sandwiched between X and Y and functionally connected) And a case where X and Y are directly connected (that is, a case where another element or another circuit is connected between X and Y without being sandwiched). It is assumed to be disclosed in a written document. That is, when explicitly described as being electrically connected, the same content as the case where only explicitly described as being connected is disclosed in this specification and the like. It has been done.

Note that, for example, the source (or the first terminal or the like) of the transistor is electrically connected to X via Z1 (or not), and the drain of the transistor (or the second terminal or the like) is connected.
Is electrically connected to Y via Z2 (or not), or the source of the transistor (or the first terminal or the like) is directly connected to a part of Z1, and Another part is directly connected to X, the drain (or the second terminal or the like) of the transistor is directly connected to part of Z2, and another part of Z2 is directly connected to Y. If so, it can be expressed as follows.

For example, “X and Y, the source (or the first terminal or the like) of the transistor, and the drain (or the second terminal or the like) are electrically connected to each other, and X, the source of the transistor (or the first terminal, or the like). Terminal), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.” Or “the source of the transistor (or the first terminal or the like) is electrically connected to X, the drain of the transistor (or the second terminal or the like) is electrically connected to Y, and X, the source of the transistor (or the like). Alternatively, the first terminal or the like), the drain of the transistor (or the second terminal, or the like), and Y are electrically connected in this order”. Or, "X is the source (
Alternatively, it is electrically connected to Y via a first terminal or the like) and a drain (or a second terminal or the like), and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.). 2 terminals), and Y are provided in this connection order.” The source (or the first terminal or the like) of the transistor and the drain (or the second terminal or the like) are separated from each other by defining the order of connection in the circuit structure using the expression method similar to these examples. Apart from this, the technical scope can be determined.

Alternatively, as another expression method, for example, “the source of the transistor (or the first terminal or the like) is electrically connected to X via at least the first connection path, and the first connection path is The second connection path does not have a second connection path, and the second connection path is provided between the source (or the first terminal or the like) of the transistor and the drain (or the second terminal or the like) of the transistor through the transistor. The first connection path is a path via Z1, and the drain (or the second terminal or the like) of the transistor is at least via a third connection path.
It is electrically connected to Y, the third connection path does not have the second connection path, and the third connection path is a path via Z2. Can be expressed as Or,
The source of the transistor (or the first terminal or the like) is electrically connected to X via at least the first connection path via Z1, and the first connection path has a second connection path. The second connection path has a connection path via a transistor, and the drain (or the second terminal or the like) of the transistor is connected to Y via Z2 by at least the third connection path. It is electrically connected and the third connection path does not have the second connection path. Can be expressed as Or “the source of the transistor (or the first terminal, etc.) is electrically connected to X via Z1 by at least a first electrical path,
The first electrical path does not have a second electrical path, and the second electrical path is
An electrical path from a source of a transistor (or a first terminal or the like) to a drain of a transistor (or a second terminal or the like), where the drain of the transistor (or the second terminal or the like) is at least a third electrical Is electrically connected to Y through a path Z2, the third electrical path does not have a fourth electrical path, and the fourth electrical path is a drain of a transistor. (Or second terminal, etc.) to source of transistor (or first
Electrical terminals). Can be expressed as By defining the connection path in the circuit configuration using the expression method similar to these examples, the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor can be distinguished from each other. , The technical scope can be determined.

Note that these expression methods are examples and are not limited to these expression methods. Where X
, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive layers,
Layers, etc.).

In addition, even when independent components are illustrated as electrically connected to each other in the circuit diagram, when one component also has the functions of a plurality of components. There is also. For example, when a part of the wiring has a function as an electrode, one conductive layer has a function of the wiring,
It also has the functions of both components of the function of the electrode. Therefore, the term “electrically connect” in this specification includes in its category such a case where one conductive layer also has functions of a plurality of components.

Note that in this specification, terms such as “above” and “below” are used for convenience in order to describe the positional relationship between components with reference to the drawings. Further, the positional relationship between the components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the words and phrases described in the specification, but can be paraphrased appropriately according to the situation.

Note that the layout of the circuit blocks in the block diagrams in the drawings is for specifying the positional relationship for the sake of explanation, and even if it is shown that different functions are realized by different circuit blocks, the same circuit blocks are actually used. In some cases, they are provided so that different functions can be realized inside. Further, the function of each circuit block in the drawings is to identify the function for the purpose of explanation, and even if it is shown as one circuit block, in the actual circuit block, the processing performed by one circuit block is performed by a plurality of circuit blocks. In some cases, it may be provided to do so.

Note that the term “film” and the term “layer” can be interchanged with each other depending on the case or circumstances. For example, it may be possible to change the term "conductive layer" to the term "conductive film". Alternatively, for example, it may be possible to change the term “insulating film” to the term “insulating layer”.

(Embodiment 1)
A structure of an imaging device of one embodiment of the present invention will be described with reference to the drawings.

In this specification and the like, an imaging device refers to all devices having an imaging function. Alternatively, a circuit having an imaging function or an entire system including the circuit is referred to as an imaging device.

In this specification and the like, a display device generally means a device having a display function. The display device has a plurality of pixels, a circuit for driving the pixels, and the like. Further, the display device may include a control circuit, a power supply circuit, a signal generation circuit, and the like.

FIG. 1 is a block diagram illustrating a structure of an imaging device of one embodiment of the present invention. The imaging device 10 includes a pixel 11, a circuit 13, a circuit 14, a circuit 15, a circuit 16, a circuit 17, a circuit 18, a circuit 19, a circuit 21, and a circuit 22. The pixels 11 are arranged in a matrix and are arranged in n rows and m columns (n, m
Is a natural number).

Further, external devices such as the display device 23 and the storage device 24 can be provided outside the imaging device 10. As the storage device 24, a hard disk, a magnetic disk, a magneto-optical disk (M
Any non-volatile memory such as O (Magneto-Optical disk) or flash memory can be used.

The circuit 13 can function as a row driver that selects a row of the pixel array 12. The circuit 14 can function as a first column driver that selects a column of the pixel array 12. The circuit 15 can have a function as an A/D conversion circuit.

The circuit 16 can have a function of performing data processing on imaging data which is analog data output from each pixel 11. The circuit 17 can have a function as a second column driver that selects the pixel 11 in the column for which the data processing is performed by the circuit 16.

The circuit 18 can have a function of calculating the row address of the pixel 11 of the row selected by the circuit 13. The circuit 19 can have a function of calculating a column address of the pixel 11 in the column selected by the circuit 17. The circuit 21 can have a function of storing a row address and a column address which define a specified region of the pixel array 12. The circuit 22 is based on the signal output from the circuit 16, the row address output from the circuit 18 and the column address output from the circuit 19, and the row address and the column address stored in the circuit 21.
It is possible to have a function of determining whether or not to output the imaging data to an external device.

Here, the area of the pixel array 12 means a set of coordinates of the pixels 11. Further, the coordinates are a set of numerical values indicating in which row and in which column the pixels of the pixel array 12 are arranged, and are defined by the row address and the column address. For example, pixel 11[1,1] is 1
The pixels 11 arranged in the first row and the first column are shown. The pixel 11[n,m] indicates the pixel 11 arranged in the n-th row and the m-th column.

Various circuits such as a decoder and a shift register are used for the circuit 13, the circuit 14, and the circuit 17.

The circuit 14 and the circuit 17 may have the same circuit configuration or different circuit configurations. Further, as shown in FIG. 2, the circuit 14 and the circuit 17 may be commonly used as a circuit 25.

Next, the operation of the imaging device 10 shown in FIG. 1 will be described using the flowchart shown in FIG. The imaging device 10 can operate in the first mode or the second mode.

First, imaging in the first mode is performed (S1). In this mode, the imaging data 31 is acquired from all the pixels 11. The acquired image data 31 is converted into digital data by the circuit 15 and then output to an external device (S2).

That is, the first mode is an imaging mode in which imaging data is acquired and output to an external device.

Next, it is determined whether to switch to the second mode (S3). When the preset switching condition is not satisfied, S1 to S3 are performed again. The switching condition may be, for example, the elapse of a designated time, or the input of a signal for switching to the second mode.

When the switching condition is satisfied, the image pickup data of the reference frame and the image pickup data of the difference detection frame are obtained in the second mode. In this mode, one pixel 11 is selected by selecting a row of the pixel array 12 by the circuit 13 and selecting a column of the pixel array 12 by the circuit 17. Then, after the image data of the reference frame is acquired by the selected pixel 11 and output to the circuit 16, the image data of the difference detection frame is acquired by the selected pixel 11 and output to the circuit 16.
Then, difference calculation is performed between the image data of the reference frame and the image data of the difference detection frame (S4). The circuit 16 also produces a signal 36. The signal 36 is made active when a difference is detected, and made inactive when no difference is detected. The difference data representing the result of the difference calculation can be stored in the pixel 11.

That is, the second mode is a difference detection mode in which the difference between the image data of the reference frame and the image data of the difference detection frame is detected.

Here, making the signal 36 active means outputting a signal of “H” (also referred to as a high-potential signal), for example. Conversely, deactivating the signal 36 means outputting a signal of "L" (also referred to as a low potential signal), for example. The logic of signal 36 may be reversed.

In this specification, “L” can be set to the ground potential, for example.

As a method of calculating a difference by the circuit 16, a method of determining the presence or absence of a difference based on a difference between a current value resulting from the imaging data of the reference frame output from the pixel 11 and a current value resulting from the imaging data of the difference detection frame Etc. can be used. If there is a difference between the current values, it is determined that there is a difference, and if there is no difference, it is determined that there is no difference. The specific circuit configuration and operation of the circuit 16 for realizing the method will be described later.

Further, the circuit 18 calculates the row address 32 and the circuit 19 calculates the column address 33, which form the coordinates of the pixel 11 for which the difference is calculated. Then, the row address 32 and the column address 33 are output to the circuit 22 as an address signal. By supplying the clock signal 34 to the circuits 13 and 18, the selection of the row of the pixel array 12 by the circuit 13 and the calculation of the row address 32 by the circuit 18 can be performed in synchronization. Further, by supplying the clock signal 35 to the circuits 17 and 19, the column selection of the pixel array 12 by the circuit 17 and the calculation of the column address 33 by the circuit 19 can be performed in synchronization.

Note that in one embodiment of the present invention, the row address 32 is calculated by the circuit 18 and the column address 33 is calculated by the circuit 19 for all the pixels 11 for which the difference calculation is performed regardless of the presence or absence of the difference. Only the row address 32 and the column address 33 of the detected pixel 11 may be calculated.

When no difference is detected and the signal 36 becomes inactive, the process returns to S4, the image pickup data of the difference detection frame is acquired again, and the difference calculation is performed between the reference frame and the difference detection frame. ..

In the second mode, for example, the pixel 11 in the first row and the first column is selected, the difference calculation is performed, and then the first row 2
The pixel 11 in the column is selected to calculate the difference, and the pixels 11 in the first row and the m-th column are sequentially selected to calculate the difference. For the pixels 11 on the second and subsequent rows, the difference calculation is sequentially performed from the pixel 11 on the first column to the pixel 11 on the m-th column in the same procedure as the pixel 11 on the first row. After the difference calculation is performed on the pixel 11 in the nth row and the mth column, the difference calculation is sequentially performed again from the pixel 11 in the 1st row and 1st column to the pixel 11 in the nth row and mth column. In any one of the pixels 11, the signal 36 becomes active when a difference is detected between the image data of the reference frame and the image data of the difference detection frame.

Note that the imaging data of the reference frame can be held in the circuit 16. Therefore, when the difference is not detected in the difference calculation and the operation in the second mode is performed again, the acquisition of the image data of the reference frame may or may not be performed. When acquiring the imaged data of the reference frame, it is possible to perform highly accurate difference calculation even if the held imaged data changes due to the passage of time or the like. When the imaged data of the reference frame is not acquired, the power consumption can be reduced and the operation can be speeded up.

When the difference is detected and the signal 36 becomes active, the circuit 22 determines whether to output the imaging data to the external device (S5). Hereinafter, an example of the operation in S5 will be described in detail.

Prior to operating the imaging device 10, the circuit 21 is provided with a region 41 (see FIG. 4) in the pixel array 12.
The row address 37 and the column address 38 defining the reference) are stored. The row address 37 and the column address 38 may be stored in the circuit 21 during the operation of the imaging device 10.

When a difference is detected between the image data of the reference frame and the image data of the difference detection frame in the area 41, the image data is newly acquired in the first mode and output to the external device. A plurality of row addresses 37 and column addresses 38 can be designated to define the area. For example, the area enclosed by connecting the coordinates designated by the respective addresses can be the area 41. Further, for example, the coordinates designated by each address may be connected by a straight line or a line segment, and the straight line or the line segment may be set as the region 41. Further, for example, the coordinates themselves designated by each address can be set as the area 41.

Then, when the difference is detected by S4 and the signal 36 becomes active, the coordinates of the region 41 and the pixel in which the difference is detected (the difference calculation was performed by the circuit 16 immediately before the signal 36 becomes active) The circuit 22 compares the coordinates 42 composed of the row address 32 and the column address 33 of 11 with each other. The area 41 and the coordinates 42 are not shown in FIG. Then, the circuit 22 generates the signal 39, and when the coordinate 42 is included in the region 41, the signal 39 is activated because it is determined that the output condition of the imaging data to the external device is satisfied. If the coordinates 42 are not included in the area 41, the signal 39 is deactivated because it is determined that the output condition of the imaging data to the external device is not satisfied.

Here, the fact that the coordinate 42 is included in the area 41 means that the coordinate 42 coincides with one of the coordinates included in the area 41. Further, if the coordinate 42 is not included in the area 41, it means that the coordinate
2 means that none of the coordinates of the area 41 match.

In addition, making the signal 39 active means outputting a signal of, for example, “H” like the signal 36. On the contrary, deactivating the signal 39 means outputting a signal of "L", for example. The logic of signal 39 may be reversed.

Note that the imaging device 10 may have a structure without the circuit 21. in this case,
The row address 37 and the column address 38 are directly supplied to the circuit 22.

Next, a specific example of the above-mentioned determination of the output of the imaged data to the external device will be described with reference to FIG.

In the pixel array 12, the coordinates of the upper left pixel 11 are [1, 1], and the coordinates of the lower right pixel 11 are [n, m]. Then, "xmin" and "xmax" are set as the row address 37,
“Ymin” and “ymax” are stored in the circuit 21 as column addresses 38, respectively. Here, 1≦xmin≦xmax≦n (xmin is 1 or more and xmax or less, xma
x is xmin or more and n or less), and 1≦ymin≦ymax≦m (ymin is 1 or more and ymax or less, ymax is ymin or more and m or less). Further, xmin, xmax, ymin and ymax are natural numbers.

In this case, the area 41 has coordinates [xmin, ymin], [xmi, as shown in FIG.
It may be an area inside a quadrangle surrounded by four points of [n, ymax], [xmax, ymin] and [xmax, ymax]. When the coordinate 42 is [x1, y1] (x1 is a natural number of xmin or more and xmax or less, y1 is a natural number of ymin or more and ymax or less), the signal 42 can be activated because the coordinate 42 is included in the region 41. .. Further, for example, the coordinate 42 is [x2, y2] (x2 is a natural number of xmax or more and n or less, y2 is ym).
If a natural number from in to ymax), the signal 39 can be made inactive because the coordinate 42 is not included in the region 41. Further, for example, the coordinates 42 are [x, y] (x and y are natural numbers), x is xmin or less, x is xmax or more, y is ymin or less, and y is ymax.
When any one of the above conditions is satisfied, the signal 39 can be made inactive because the coordinate 42 is not included in the region 41.

Note that the region 41 has coordinates [xmin, ymin], [xmin, ymax], [xmax
, Ymin] and [xmax, ymax] can be an area outside the quadrangle. In this case, for example, when the coordinate 42 is [x2, y2] or [x, y], it is determined that the coordinate 42 is included in the region 41 and the signal 39 is activated.
x1, y1], the coordinate 42 is not included in the region 41 and can be made inactive.

Although the region 41 is described as a quadrangle in FIG. 4, the region 41 can have various shapes. For example, three row addresses 37 and three column addresses 38 are stored in the circuit 21, three coordinates are designated, and the inside or outside of the triangle formed by connecting each coordinate with a straight line can be used as the region 41. .. Further, the area 41 is set to the row address 37 and the column address 3
It can also be inside or outside the circle defined by 8. The area 41 can also be inside or outside the polygon defined by the row address 37 and the column address 38.

The coordinates on the boundary line between the inside and the outside of the area 41 can be included inside or outside the area 41.

Although the case where the area 41 is a surface has been described above, the area 41 may be a line or a point. When the area 41 is a line, for example, two row addresses 37 and two column addresses 38 are stored in the circuit 21, two coordinates are designated, each coordinate is connected by a straight line or a line segment, and the coordinate 42 is the straight line. It is also possible to activate the signal 39 when it is located on or above the line segment, and deactivate the signal 39 when the straight line or the line segment does not pass through the coordinate 42. When the straight line or the line segment does not pass through the coordinate 42, the signal 39 is activated and the coordinate 42
It is also possible to deactivate the signal 39 when is on the straight line or on the line segment.

When the area 41 is used as a point, for example, one or a plurality of row addresses 37 and one or a plurality of column addresses 38 are stored in the circuit 21 to specify one or more coordinates, and the coordinates 42 specify the coordinates (the area 41 ), the signal 39 can be made active, and if it is different from the designated coordinate (area 41), it can be made inactive. Further, the row address 37 and the column address 38 are stored in the circuit 21 to specify coordinates, and the coordinates 42 specify the specified coordinates (area 41
Signal 39, the signal 39 can be made active, and if it is the same as the designated coordinate (region 41), it can be made inactive.

Further, one or a plurality of row addresses 37 and/or column addresses 38 are stored in the circuit 21, and when the coordinate 42 includes one or both of the row address 37 and the column address 38, the signal 39 is activated, and the row address 37 and Signal 39 may be deactivated if neither column address 38 is included. Further, one or a plurality of row addresses 37 and/or column addresses 38 are stored in the circuit 21, and when the coordinate 42 does not include both the row address 37 and the column address 38, the signal 39 is activated and the row address 37 or the column address 38 is stored. If one or both of the addresses 38 are included, the signal 39 may be inactive.

Further, all of the row address and the column address stored in the circuit 21 may be used for defining the region 41, or a part thereof may be used for defining the region 41. Area 4
1 is used to define the area 41 by supplying a signal to the circuit 21, for example.
The row address 37 and/or the column address 38 used to define the address can be specified from among the row address and/or the column address stored in the circuit 21.

The methods of defining the area 41 described above can be used in combination as appropriate.

If the signal 39 becomes inactive in S5, the process returns to S4 and the image data of the reference frame and the image data of the difference detection frame are acquired again in the second mode. And calculate the difference. As described above, when the image data of the reference frame is held in the circuit 16 or the like, the acquisition of the image data of the reference frame may be omitted.

When the signal 39 becomes active, the mode is switched to the first mode and the imaging data 31 is acquired in the same procedure as S1 (S6). Then, the imaging data 31 is output to the external device in the same procedure as S2 (S7).

After execution of S7, the process returns to S4, switches to the second mode, acquires the image pickup data of the difference detection frame again, and calculates the difference between the reference frame and the difference detection frame. It should be noted that, after execution of S7, it may be determined whether to return to S4 to perform the operation in the second mode or return to S6 to continue the imaging in the first mode. Further, it may be determined whether to return to S1. Similar to S3, the determination condition may be, for example, the elapse of a designated time or the input of a signal for switching to the second mode. The above is the operation of the imaging device which is one embodiment of the present invention.

As described above, in the image pickup apparatus 10 shown in FIG. 1, in the second mode, processing such as A/D conversion that consumes a huge amount of power is not performed. Further, it is only necessary to perform the minimum processing for generating the signal 36 having a function of transmitting to the other circuits whether or not the difference is detected. Therefore, it is possible to reduce power consumption as compared with the case of a configuration in which the difference between the reference frame and the difference detection frame is detected with A/D conversion or the like.

Even when the difference is detected in the second mode, the output determination of the image data to the external device is performed, and the image data 31 is imaged in the first mode only when the output condition is satisfied. Output to external device. Therefore, if the difference is detected, the imaging data 3 is unconditionally detected.
The output frequency of the imaging data 31 can be reduced as compared with the case of imaging 1 and outputting it to an external device. Thereby, for example, when the display device 23 is connected to the imaging device 10 as an external device,
The frequency of rewriting the image data in the display device 23 can be reduced. In the period when the image data is not rewritten, the operation of the circuit of the display device 23 can be stopped particularly by configuring the display device 23 to have the structure described in Embodiment 6, so that power consumption can be reduced. Further, for example, when the storage device 24 is connected to the imaging device 10 as an external device, the amount of data stored can be reduced. As a result, the storage capacity of the storage device 24 can be saved, and not only imaging for a longer time can be performed, but also necessary data can be easily retrieved from the stored data.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, the pixel 11 included in the imaging device 10 and an example of operation are described with reference to drawings.

FIG. 5 is a circuit diagram of the pixel 11. The pixel 11 includes the photoelectric conversion element 120 and the transistor 1
31 includes a transistor 132, a transistor 133, a transistor 134, a transistor 135, a capacitor 141, and a capacitor 142. Note that in FIG. 5, all the transistors 131 to 135 are n-ch types.

In the pixel 11 of FIG. 5, one terminal of the photoelectric conversion element 120 is electrically connected to one of a source and a drain of the transistor 131. The other of the source and the drain of the transistor 131 is electrically connected to one of the source and the drain of the transistor 132 and one terminal of the capacitor 141. Further, one of a source and a drain of the transistor 133 is electrically connected to the other terminal of the capacitor 141, one terminal of the capacitor 142, and the gate of the transistor 134. Also, the transistor 13
One of the source and the drain of 4 is electrically connected to one of the source and the drain of the transistor 135.

The other terminal of the photoelectric conversion element 120 is electrically connected to the wiring 151 (VPD). The other of the source and the drain of the transistor 132 is connected to the wiring 152 (VR).
Is electrically connected to. The other of the source and the drain of the transistor 133 is electrically connected to the wiring 153 (VAZ). The other terminal of the capacitor 142 is electrically connected to the wiring 154 (VSS). The other of the source and the drain of the transistor 135 is electrically connected to the wiring 155 (VPI). The other of the source and the drain of the transistor 134 is electrically connected to the wiring 156 (VOUT). The gate of the transistor 131 is electrically connected to the wiring 161 (TX). The gate of the transistor 132 is electrically connected to the wiring 162 (RES). The gate of the transistor 133 is electrically connected to the wiring 163 (AZ). The gate of the transistor 135 is electrically connected to the wiring 165 (SEL).

Here, the wiring 151 (VPD), the wiring 152 (VR), the wiring 153 (VAZ), and the wiring 15
4 (VSS) and the wiring 155 (VPI) can function as power supply lines. In addition, the wiring 161 (TX), the wiring 162 (RES), the wiring 163 (AZ), and the wiring 165.
(SEL) can function as a signal line.

In the above structure, the other of the source and the drain of the transistor 131, the transistor 1
A node to which one of the source and the drain of 32 and one terminal of the capacitor 141 is connected is FD1. In addition, a node to which one of the source and the drain of the transistor 133, the gate of the transistor 134, the other terminal of the capacitor 141, and one terminal of the capacitor 142 is connected is FD2.

In the pixel 11, the photoelectric conversion element 120 is a light receiving element and can have a function of generating a current according to light incident on the pixel 11. The transistor 131 is the photoelectric conversion element 12
It can have a function of controlling charge accumulation or discharge to the node FD1 by 0. The transistor 132 can have a function of resetting the potential of the node FD1. The transistor 133 can have a function of resetting the potential of the node FD2. The transistor 134 can have a function as an amplification transistor which outputs a signal according to the potential of the node FD2. The transistor 135 can have a function as a selection transistor which controls selection of the pixel 11 at the time of reading. In addition, the wiring 156 (
VOUT) can have a function of outputting imaging data acquired by the pixel 11 as a signal.

The operation of the pixel 11 in the first mode will be described in detail with reference to the timing chart shown in FIG. The timing chart shown in FIG. 6 shows the wiring 161 (TX) and the wiring 162.
(RES), wiring 163 (AZ), wiring 165 (SEL), node FD1 and node F
The potential of D2 is shown. Note that the operation of turning on or off each transistor is performed by supplying a potential which turns on or off the transistor to a wiring connected to the gate of each transistor.

Note that the wiring 151 (VPD) is “L”, the wiring 152 (VR) is “H”, and the wiring 153 (VA
Z) is “H”, the wiring 154 (VSS) is “L”, and the wiring 155 (VPI) is “H”. However, other potentials can be applied to the wiring to operate.

At time T1, the wiring 161 (TX), the wiring 162 (RES), and the wiring 163 (AZ
) Is set to "H", the transistors 131, 132, and 133 are turned on. Further, the transistor 135 is turned off by setting the wiring 165 (SEL) to “L”. Accordingly, the potential of the node FD1 is set to the potential "VR" of the wiring 152 (VR), and the potential of the node FD2 is set to the potential "VAZ" of the wiring 153 (VAZ).

At the time T2, the wiring 162 (RES) and the wiring 163 (AZ) are set to "L", whereby the transistors 132 and 133 are turned off. As a result, the potential of the node FD1 drops.

Here, assuming that the potential decrease of the node FD1 is “ΔV1”, the potential of the node FD1 is “VR−”.
ΔV1”. Also, the capacitance of the capacitor 141 (capacitance value “C1”) and the combined capacitance of the capacitor 142 (capacitance value “C2”) and the gate capacitance of the transistor 134 (capacitance value “Cg”). The coupling also lowers the potential of the node FD2.
If V2”, then “ΔV2=ΔV1·C1/(C1+C2+Cg)=ΔV1·α”, and the potential of the node FD2 becomes “VAZ−ΔV2”. Note that “α=C1/(C1+C2+).
Cg)”.

Note that in order to make “ΔV1” and “ΔV2” as equal as possible, it is preferable that the capacitance value of the capacitor 141 be larger than the sum of the capacitance value of the capacitor element 142 and the gate capacitance value of the transistor 134.

The higher the illuminance of the light with which the photoelectric conversion element 120 is irradiated, the more the potential of the node FD1 decreases. Therefore, the potential of the node FD2 also drops significantly.

At the time T3, the wiring 161 (TX) is set to “L”, whereby the transistor 131 is turned off. As a result, the potentials of the nodes FD1 and FD2 are held.

At the time T4, the wiring 165 (SEL) is set to “H”, whereby the transistor 135
To turn on. Accordingly, the wiring 156 (VOUT) is connected to the wiring 156 (VOUT) depending on the potential of the node FD2.
A signal corresponding to the imaged data is output. Note that the lower the potential of the node FD2, the wiring 1
The potential of the signal output from 56 (VOUT) becomes low. That is, the photoelectric conversion element 120
The higher the illuminance of the light with which the wiring 156 is irradiated, the lower the potential of the wiring 156 (VOUT).

At the time T5, the wiring 165 (SEL) is set to “L”, whereby the transistor 135
To turn off. The above is the operation of the pixel 11 in the first mode.

Next, the operation in the second mode will be described with reference to FIG.

Times T01 to T06 correspond to a period in which the imaging data of the reference frame is acquired and output. At time T01, the wiring 161 (TX), the wiring 162 (RES), and the wiring 16
By setting 3(AZ) to "H", the transistor 131, the transistor 132, and the transistor 133 are turned on. Further, the transistor 135 is turned off by setting the wiring 165 (SEL) to “L”. Accordingly, the potential of the node FD1 is set to the wiring 152 (V
R) is reset to the potential “VR”, and the potential of the node FD2 is reset to the potential “VAZ” of the wiring 153 (VAZ).

At Time T02, the wiring 162 (RES) is set to “L”, so that the transistor 1
Turn off 32. As a result, the potential of the node FD1 drops. Further, at time T03, the wiring 161 (TX) is set to “L”, whereby the transistor 131 is turned off. As a result, the potential of the node FD1 is held. The interval from time T02 to time T03 is T.

When the potential decrease of the node FD1 from time T02 to time T03 is “ΔV1”, the potential of the node FD1 becomes “VR−ΔV1”. The higher the illuminance of the light with which the photoelectric conversion element 120 is irradiated, the more the potential of the node FD1 decreases. Note that the potential of the node FD2 does not change.

Then, at Time T04, the wiring 163 (AZ) is set to “L”, whereby the transistor 133 is turned off. As described above, the imaging data of the reference frame is acquired.

By setting the wiring 165 (SEL) to “H” at time T05, the transistor 13
Turn 5 on. Accordingly, a signal corresponding to imaging data is output to the wiring 156 (VOUT) according to the potential of the node FD2.

At the time T06, the wiring 165 (SEL) is set to “L”, so that the transistor 13
Turn off 5. The above is the acquisition and output operation of the imaging data of the reference frame.

Times T11 to T15 correspond to a period in which the difference data is acquired by acquiring and outputting the image data of the difference detection frame when there is no difference between the image data of the reference frame and the image data of the difference detection frame. To do. This is from time T12 to time T13 described later.
This corresponds to the case where the illuminance of the light applied to the photoelectric conversion element 120 is equal to the illuminance of the light applied from time T02 to time T03.

At Time T11, the wiring 161 (TX) and the wiring 162 (RES) are set to “H”, whereby the transistors 131 and 132 are turned on. As a result, the potential of the node FD1 changes from "VR-ΔV1" to "VR". That is, the potential rises by "ΔV1", which is the potential decrease from time T02 to time T03. In addition, the potential of the node FD2 also rises. Here, if the potential rise of the node FD2 is “ΔV2”, then “ΔV2=ΔV1
.Alpha.", that is, the potential of the node FD2 changes from "VAZ" to "VAZ+.DELTA.V2".

At time T12, the wiring 162 (RES) is set to “L”, so that the transistor 1
Turn off 32. As a result, the potential of the node FD1 drops, and the potential of the node FD2 also drops.

By setting the wiring 161 (TX) to “L” at time T13, the transistor 131
To turn off. As a result, the potentials of the nodes FD1 and FD2 are held.

Here, assuming that the interval from time T12 to time T13 is T, light having the same illuminance as that from time T02 to time T03 is applied to the photoelectric conversion element 120, so that the potential drop of the node FD1 occurs at time T.
It is equal to the potential decrease “ΔV1” from 02 to time T03. That is, from time T12 to time T1
The potential decrease of the node FD1 at 3 is equal to the potential increase of the node FD1 at time T11. Further, the potential decrease of the node FD2 is equal to the potential increase “ΔV2” at the time T11. Therefore, the potential of the node FD2 becomes "VAZ". That is, it is equal to the potential of the wiring 153 (VAZ).

At time T14, the wiring 165 (SEL) is set to “H”, whereby the transistor 1
Turn on 35. Accordingly, the wiring 156 (VOUT) is supplied depending on the potential of the node FD2.
A signal corresponding to the imaged data is output to. Note that the potential of the signal is equal to the potential of the signal from time T05 to time T06.

At time T15, the wiring 165 (SEL) is set to “L”, so that the transistor 13
Turn off 5. The above is the operation of acquiring and outputting the imaged data of the difference detection frame when there is no difference between the reference frame and the difference detection frame.

Times T21 to T25 correspond to a period in which the difference data is acquired by acquiring and outputting the image data of the difference detection frame when there is a difference between the image data of the reference frame and the image data of the difference detection frame. To do. This is from time T22 to time T23 described later.
This corresponds to the case where the illuminance of the light applied to the photoelectric conversion element 120 is higher than the illuminance of the light applied from time T12 to time T13.

The operations of the transistor 131, the transistor 132, the transistor 133, and the transistor 135 at times T21 to T25 are similar to the operations of the transistors at times T11 to T15.

At time T21, the potential of the node FD1 becomes “VR”. That is, the potential rises by "ΔV1", which is the potential decrease from time T12 to time T13. On the other hand, the potential of the node FD2 also increases by “ΔV2”, which is the potential decrease from time T12 to time T13. That is, the potential of the node FD2 becomes “VAZ+ΔV2”.

At time T22, the potential of the node FD1 drops, and the potential of the node FD2 also drops.

At time T23, the potentials of the nodes FD1 and FD2 are held. Time T22
The illuminance of the light with which the photoelectric conversion element 120 is irradiated is T
Since the illuminance of light with which the photoelectric conversion element 120 is irradiated from 12 to time T13 is higher, the potential decrease “ΔV1′” of the node FD1 is larger than the potential decrease “ΔV1” from time T12 to time T13 (ΔV1′>ΔV1). In addition, the potential drop of the node FD2 “ΔV2′=ΔV1′·
α” is also larger than the decrease amount “ΔV2” from time T12 to time T13 (ΔV2′>ΔV2)
.. Therefore, the potential “VAZ+ΔV2-ΔV2′” of the node FD2 is equal to the wiring 153 (VA
Z) potential lower than "VAZ".

At time T24, a signal corresponding to imaging data is output to the wiring 156 (VOUT) in accordance with the potential of the node FD2. Note that the potential of the signal output from the wiring 156 (VOUT) is lower as the illuminance of light with which the photoelectric conversion element 120 is irradiated is higher from Time T22 to Time T23; therefore, the potential of the output signal is from Time T14 to Time T15. It becomes lower than the potential of the output signal.

From time T31 to time T35, as in the case of time T11 to time T15, when there is no difference between the image data of the reference frame and the image data of the difference detection frame, the image data of the difference detection frame is acquired and output. , Which corresponds to the period for acquiring the difference data.

The operations of the transistor 131, the transistor 132, the transistor 133, and the transistor 135 from time T31 to time T35 are similar to the operation of each transistor from time T11 to time T15.

From time T31 to time T32, the potential of the node FD1 becomes “VR”. That is,
The potential rises by "ΔV1'", which is the potential drop from time T22 to time T23. on the other hand,
The potential of the node FD2 also increases by “ΔV2′”, which is the decrease in potential from time T22 to time T23. That is, the potential of the node FD2 becomes “V2+ΔV2”.

Assuming that the interval from time T32 to time T33 is T, light having the same illuminance as that from time T12 to time T13 is applied to the photoelectric conversion element 120. It is equal to ΔV1″. In addition, the potential drop of the node FD2 also occurs at time T
It is equal to the potential decrease “ΔV2” from 12 to time T13. Therefore, the potential of the node FD2 becomes "VAZ". That is, it is equal to the potential of the wiring 153 (VAZ).

Times T41 to T45 correspond to a period during which difference data is acquired by acquiring and outputting the image data of the difference detection frame when there is a difference between the image data of the reference frame and the image data of the difference detection frame. To do. This is from time T42 to time T43 described later.
This corresponds to the case where the illuminance of the light applied to the photoelectric conversion element 120 is lower than the illuminance of the light applied from time T32 to time T33.

The operations of the transistor 131, the transistor 132, the transistor 133, and the transistor 135 at times T41 to T45 are similar to the operations of the transistors at times T31 to T35.

At time T41, the potential of the node FD1 becomes “VR”. That is, the potential rises by "ΔV1", which is the potential decrease from time T32 to time T33. On the other hand, the potential of the node FD2 also increases by the amount of decrease in potential “ΔV2” from time T32 to time T33. That is, the potential of the node FD2 becomes “VAZ+ΔV2”.

At time T42, the potential of the node FD1 drops, and the potential of the node FD2 also drops.

At time T43, the potentials of the nodes FD1 and FD2 are held. Time T42
The illuminance of light with which the photoelectric conversion element 120 is irradiated is T
Since it is lower than the illuminance of light with which the photoelectric conversion element 120 is irradiated from 32 to time T33, the potential decrease “ΔV1”” of the node FD1 is equal to the potential decrease “ΔV1” from time T32 to time T33.
It is smaller (ΔV1″<ΔV1). In addition, the potential drop of the node FD2 "ΔV2"=ΔV
1″·α” is also smaller than the decrease “ΔV2” from time T32 to time T33 (ΔV2″)
<ΔV2). Therefore, the potential “VAZ+ΔV2−ΔV2″” of the node FD2 is higher than the potential “VAZ” of the wiring 153 (VAZ).

At time T44, a signal corresponding to imaging data is output to the wiring 156 (VOUT) in accordance with the potential of the node FD2. Note that the potential of the signal output from the wiring 156 (VOUT) is higher as the illuminance of light with which the photoelectric conversion element 120 is irradiated is lower from Time T42 to Time T43; therefore, the potential of the output signal is from Time T34 to Time T35. It becomes higher than the potential of the output signal.

The example of the operation of the pixel 11 in the second mode has been described above.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 3)
In the present embodiment, a modified example of the pixel 11 included in the imaging device 10 will be described with reference to the drawings.

The pixel 11 included in the imaging device 10 of one embodiment of the present invention is not limited to the structure illustrated in FIG. The configuration shown in FIG. 8 can also be used. FIG. 8 illustrates a structure in which all the transistors 131 to 135 illustrated in FIG. 5 are p-ch types. By reversing the magnitude relationship of the potentials as necessary, the operation in the first mode can be referred to FIG. 6, and the operation in the second mode can be referred to FIG. Note that some of the transistors 131 to 135 may be replaced with p-ch transistors. Alternatively, a CMOS configuration may be used.

Further, although the transistor 135 is arranged between the transistor 134 and the wiring 155 (VPI) in FIG. 5, the transistor 134 is connected to the transistor 135 and the wiring 1 as shown in FIG.
It may be arranged between 55 (VPI).

The pixel 11 included in the imaging device 10 of one embodiment of the present invention may have the structure illustrated in FIG. FIG. 10 is a configuration in which the connection direction of the photoelectric conversion element 120 in the pixel 11 is opposite to that in FIG. In this case, the wiring 151 (VPD) is "H" and the wiring 152 (VR) is "L". 6 can be referred to for the operation in the first mode and FIG. 7 can be referred to for the operation in the second mode. In this case, the higher the illuminance of the light with which the photoelectric conversion element 120 is irradiated, the higher the illuminance of the node FD1 and the node. The potential of FD2 becomes high. Therefore, in the circuit configuration of FIG. 10, the higher the illuminance of the light with which the photoelectric conversion element 120 is irradiated, the wiring 156 (VOUT).
The electric potential of the output signal output from is large.

In addition, FIG. 11A illustrates a structure in which the transistor 132 is removed from the pixel 11 illustrated in FIG. In this case, the wiring 151 (VPD) can be changed to "L" and "H". The reset operation of the node FD1 can be performed by setting the wiring 151 (VPD) to “H”. When the wiring 151 (VPD) is set to “H” during the predetermined period, the photoelectric conversion element 120
Is forward biased. Therefore, the node FD1 can be set to the potential "VPD" of the wiring 151 (VPD).

In addition, when the imaging data is acquired, the wiring 151 (VPD) is set to “L”. Wiring 15
By setting 1 (VPD) to "L", a reverse bias is applied to the photoelectric conversion element 120, so that charge can be discharged from the node FD1 to the wiring 151 (VPD) depending on the illuminance of light. In this case, the higher the illuminance of the light with which the photoelectric conversion element 120 is irradiated, the lower the potential of the node FD1 and thus the lower the potential of the node FD2. Therefore, in the circuit configuration of FIG. 11A, as the illuminance of the light with which the photoelectric conversion element 120 is irradiated is higher, the wiring 156 (V
The potential of the output signal output from (OUT) becomes low.

In addition, as another mode of the pixel 11 included in the imaging device 10 of one embodiment of the present invention, FIG.
A structure without the transistor 131 as in B) may be used. Alternatively, a structure without the capacitor 142 may be used as shown in FIG.

In addition, in FIG. 11, a part of the wiring is omitted.

Further, in FIG. 5, the wirings that give the same potential are shown as different wirings, but the wirings may be the same. For example, like the pixel 11 illustrated in FIG. 12A, the wiring 152 (VR) for applying “H”, the wiring 153 (VAZ), and the wiring 155 (VPI) may be the same wiring. Alternatively, as in the pixel 11 illustrated in FIG. 12B, the wiring 151 (V which applies “L”)
PD) and the wiring 154 (VSS) may be the same wiring.

FIG. 13A illustrates transistors 131 to 135 in the pixel 11 in FIG.
Is a transistor in which an active layer or an active region is formed using an oxide semiconductor (hereinafter referred to as an OS transistor).

Unless otherwise specified, the off-state current in this specification refers to a drain current of a transistor in an off state (also referred to as a non-conduction state or a cutoff state). Unless otherwise specified, the off state is a state in which the voltage “Vgs” between the gate and the source is lower than the threshold voltage “Vth” in the n-channel type transistor, and the voltage between the gate and the source in the p-channel type transistor is lower than the threshold voltage “Vth”. A voltage "Vgs" between them is higher than a threshold voltage "Vth". For example, the off-state current of an n-channel transistor may be a drain current when the voltage “Vgs” between the gate and the source is lower than the threshold voltage “Vth”.

The off-state current of a transistor may depend on "Vgs". Therefore, the off-state current of a transistor is "I" or less means that the off-state current of a transistor is "I" or less".
It may mean that there is a value of “Vgs”. The off-state current of a transistor is a predetermined “V”.
It may refer to an off-state in gs", an off-state in "Vgs" within a predetermined range, or an off-state in "Vgs" at which a sufficiently reduced off-state current is obtained.

As an example, when the threshold voltage “Vth” is 0.5V, the drain current when “Vgs” is 0.5V is 1×10 ⁻⁹ A, and the drain current when “Vgs” is 0.1V is 1V.
× ^{10 -13} is A, "Vgs" is the drain current at -0.5 V 1 × ^{10 -19}
Assume an n-channel transistor with A and a drain current of 1×10 ⁻²² A at “Vgs” of −0.8V. The drain current of the transistor is “Vgs
Since "" is -0.5 V or "Vgs" is in the range of -0.5 V to -0.8 V, it is 1×10 ⁻¹⁹ A or less, and thus the off-state current of the transistor is 1×10 ⁻¹⁹ A.
The following may be the case. Since there is "Vgs" in which the drain current of the transistor is 1×10 ⁻²² A or lower, the off-state current of the transistor is 1×10 ⁻²² A or lower in some cases.

In this specification, the off-state current of a transistor having a channel width W may be represented by a current value flowing around the channel width W. Further, it may be represented by a current value flowing around a predetermined channel width (for example, 1 μm). In the latter case, the unit of off-current may be represented by a unit having a dimension of current/length (for example, A/μm).

The off-state current of a transistor may depend on temperature. In the present specification, off-state current may represent off-state current at room temperature, 60° C., 85° C., 95° C., or 125° C., unless otherwise specified. Alternatively, at a temperature at which reliability of a semiconductor device or the like including the transistor is guaranteed or at a temperature at which the semiconductor device or the like including the transistor is used (for example, any one temperature of 5 °C to 35 °C). Off current may be expressed. The off-state current of a transistor is "I" or less means that the temperature is room temperature, 60°C, 85°C, 95°C, 125°C
A transistor at a temperature at which reliability of a semiconductor device including the transistor is guaranteed or at a temperature at which a semiconductor device including the transistor is used (eg, any one temperature of 5° C. to 35° C.) In some cases, there is a value of "Vgs" at which the off-state current of "Is" is less than or equal to "I".

The off-state current of a transistor may depend on the voltage "Vds" between the drain and the source. In the present specification, unless otherwise specified, the off-state current is "Vds" of 0.1 V, 0.
8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V
, Or off current at 20V. Alternatively, it may represent “Vds” with which reliability of a semiconductor device or the like including the transistor is guaranteed or off-state current at “Vds” used in the semiconductor device or the like including the transistor. The off-state current of the transistor is "I" or less means that "Vds" is 0.1V, 0.8V, 1V.
, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V,
The Vds that guarantees the reliability of the semiconductor device including the transistor, or the "Vds" used in the semiconductor device including the transistor, in which the off-state current of the transistor is "I" or less. It may indicate that a value exists.

In this specification, the term “leakage current” may be used in the same meaning as off-state current.

In this specification, the off-state current may refer to a current flowing between the source and the drain when the transistor is in an off state, for example.

When the OS transistor is used for the pixel 11, the dynamic range of imaging can be expanded. In the circuit configuration shown in FIG. 5, when the illuminance of light incident on the photoelectric conversion element 120 is high, the potential of the node FD1 becomes small, and therefore the potential of the node FD2 also becomes small. Since the OS transistor has an extremely low off-state current, even when the potential of the node FD2 (the gate potential of the transistor 134) is extremely low, a current according to the gate potential can be accurately output. Therefore, the range of illuminance that can be detected, that is, the dynamic range can be expanded.

In addition, the low off-state current characteristics of the transistor can significantly extend the period in which electric charge can be held in the nodes FD1 and FD2. Therefore, it is possible to apply the global shutter method in which the imaging data is simultaneously acquired in all pixels without complicating the circuit configuration and the operating method.

Generally, in an imaging device in which pixels are arranged in a matrix, a rolling shutter method, which is a driving method for performing an imaging operation 201, a data holding operation 202, and a reading operation 203 for each row, is used as illustrated in FIG. To be When the rolling shutter method is used, the simultaneity of image pickup is lost, so that the image is distorted when the subject moves.

Therefore, according to one embodiment of the present invention, it is preferable to use a global shutter method in which the imaging operation 201 is simultaneously performed in all rows and the reading operation 203 is sequentially performed in each row, as illustrated in FIG. By using the global shutter method, it is possible to ensure the simultaneity of image pickup in each pixel of the image pickup apparatus, and it is possible to easily obtain an image with small distortion even when the subject moves.

Further, the OS transistor is a transistor whose active layer or region is formed of silicon (
Since the temperature dependence of the electric characteristic fluctuation is smaller than that of Si transistor), it can be used in an extremely wide temperature range. Therefore, the imaging device and the semiconductor device having the OS transistor are suitable for mounting on an automobile, an aircraft, a spacecraft, or the like.

In addition, a transistor connected to either the node FD1 or the node FD2 is required to have low noise. A transistor including a two-layer oxide semiconductor layer or a three-layer oxide semiconductor layer to be described later has a buried channel and has extremely strong noise resistance. Therefore, an image with less noise can be obtained by using the transistor.

In particular, with the structure shown in FIG. 13A, a pixel can be formed using a photoelectric conversion element including silicon and an OS transistor. With this configuration,
Since it is not necessary to form the Si transistor in the pixel, it becomes easy to increase the effective area of the photoelectric conversion element. Therefore, the imaging sensitivity can be improved.

In addition to the pixel 11, peripheral circuits such as the circuit 13, the circuit 14, the circuit 15, the circuit 16, the circuit 17, the circuit 18, the circuit 19, the circuit 21, and the circuit 22 may be formed using OS transistors. The configuration in which the peripheral circuit is formed by only the OS transistors is effective in reducing the cost of the image pickup device because the step of forming the Si transistors is unnecessary. Further, the configuration in which the peripheral circuit is formed only of the OS transistor and the p-type Si transistor does not require the step of forming the n-type Si transistor, and is therefore effective in reducing the cost of the imaging device. Further, since the peripheral circuit can be a CMOS circuit, it is effective for reducing the power consumption of the peripheral circuit, that is, for reducing the power consumption of the imaging device.

Further, FIG. 13B shows a modification example of the circuit diagram of the pixel 11 which is a modification of FIG. 13A. In the pixel 11 illustrated in FIG. 13B, the transistor 134 and the transistor 135 are
It is configured to be a Si transistor.

The Si transistor has a characteristic of having a field effect mobility superior to that of the OS transistor. Therefore, the value of current flowing through the transistor functioning as an amplification transistor or a selection transistor can be increased. For example, in FIG. 13B, the node FD2
The amount of current flowing through the transistor 134 and the transistor 135 can be increased in accordance with the charge stored in the transistor.

In the circuit diagrams shown in FIGS. 13A and 13B, “OS” is added to the circuit symbol of the OS transistor in order to clearly indicate that it is an OS transistor.

The transistor used for the pixel 11 may have a structure in which a back gate is provided for the transistor 131, the transistor 132, and the transistor 133 as illustrated in FIG. 15A or 15B. FIG. 15A shows a structure in which a constant potential is applied to the back gate, and the threshold voltage can be controlled. Further, FIG. 15B shows a structure in which the same potential as that of the front gate is applied to the back gate, so that the on-state current can be increased. In addition,
As illustrated in FIG. 15C or 15D, the transistors 131 to 1
A configuration in which a back gate is provided at 35 may be used.

Further, as shown in FIG. 15E, a transistor in one pixel may have a structure in which the same potential as the front gate is applied to the back gate, or a structure in which a constant potential is applied to the back gate as needed. It may be a combined configuration. Furthermore, a configuration in which a back gate is not provided may be arbitrarily combined as needed. Note that the constant potential is applied to the back gates, for example, as shown in FIG. 15F, the same potential can be applied to all the back gates.

Note that in FIG. 15, a part of the wiring is omitted.

Since the OS transistor has a lower on-current than the Si transistor, it is particularly preferable to provide the OS transistor with a back gate. For example, as illustrated in FIG. 13A, in the case where OS transistors are used for the transistors 131 to 135, it is preferable to provide a back gate to the transistors 131 to 135. In the case where OS transistors are used for the transistors 131 to 133, for example, as illustrated in FIG. 13B, a back gate is preferably provided for the transistors 131 to 133.

Further, the pixel 11 may have a mode in which the transistor 132, the transistor 133, the transistor 134, and the transistor 135 are shared by a plurality of pixels as illustrated in FIG. 16. Note that although FIG. 16 illustrates a structure in which the plurality of pixels in the vertical direction share the transistor 132, the transistor 133, the transistor 134, and the transistor 135, the plurality of pixels in the horizontal direction or the plurality of pixels in the horizontal and vertical directions form the transistor 132 and the transistor 133. , The transistor 134 and the transistor 135 may be shared. With such a structure, the number of transistors included in one pixel can be reduced.

Note that although FIG. 16 illustrates a mode in which the transistor 132, the transistor 133, the transistor 134, and the transistor 135 are shared by four pixels, two pixels, three pixels, or five pixels are shown.
It may be a form shared by more than one pixel.

With the above structure, an imaging device having a highly integrated pixel array can be formed. Further, it is possible to provide an image pickup apparatus capable of obtaining high quality image pickup data.

The configurations shown in FIGS. 5, 8 to 13, 15 and 16 can be arbitrarily combined.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, an example of the structure of the circuit 16 included in the imaging device 10 will be described with reference to the drawings.

In the present embodiment, it is assumed that the pixels 11 are arranged in n rows and m columns as in the first embodiment. Further, the circuit configuration of the pixel 11 is similar to the circuit configuration shown in FIG. 5 described in the second embodiment.

FIG. 17 shows the configuration of the circuit 16 and the connection relationship between the pixel 11, the circuit 16, and the circuit 17. The circuit 16 includes a transistor 50, a transistor 51, a transistor 52, a transistor 53, a transistor 54, a transistor 55, a transistor 56, a transistor 57, a transistor 58, a transistor 59, a transistor 60, a transistor 61, a transistor 62, a capacitor 63, a comparator 64, and It has a comparator 65. Note that the circuit 16 includes m transistors each including the transistors 50 to 55 and the capacitor 63.

Further, in FIG. 17, the pixel 11 is shown only in the n-th row.

Note that in FIG. 17, the transistors 50 to 55, the transistor 58, the transistor 59, and the transistor 62 are n-ch type transistors, the transistor 56, the transistor 57,
Although the transistors 60 and 61 are p-ch type transistors, some n-ch type transistors may be replaced with p-ch type transistors, and some p-ch type transistors may be replaced with n-ch type transistors.

In the circuit 16 in FIG. 17, one of a source and a drain of the transistors 50[1] to [m] is electrically connected to the other of a source and a drain of the transistor 134 by a wiring 156 (VOUT[1] to [m]). Has been done. In addition, the transistors 50[1] to [[
The other of the sources or drains of m] is one of the sources or drains of the transistors 51[1] to [m], one of the sources or drains of the transistors 52[1] to [m] and the transistors 53[1] to [m]. ], and is electrically connected to one of a source and a drain. Further, the gates of the transistors 50[1] to [m] are electrically connected to the wiring 70 (ABU).

The other of the source and the drain of the transistors 51[1] to [m] is connected to the capacitor 6
3[1] to [m], and is electrically connected to the wiring 71 (VSS).
The gates of the transistors 51[1] to [m] are connected to the transistors 52[1] to [m].
] And the other terminal of the capacitive element 63[1] to [m].

The gates of the transistors 52[1] to 52[m] are electrically connected to the wiring 72 (ATC).

The gates of the transistors 53[1] to [m] are connected to the wiring 73 (AOP[1] to [m].
]) is electrically connected to the circuit 17. In addition, the transistors 53[1] to 53[1]
The other of the source and the drain of m] is one of the source and the drain of the transistors 54[1] to [m], the gate of the transistors 55[1] to [m], and the transistor 55.
It is electrically connected to either the source or the drain of [1] to [m].

The other of the sources and drains of the transistors 54[1] to [m] is electrically connected to the gates of the transistors 54[1] to [m], one of the sources and drains of the transistors 56, and the non-inverting input terminal of the comparator 64. It is connected to the.

The other of the sources and drains of the transistors 55[1] to [m] is electrically connected to one of the source and the drain of the transistor 58 and the non-inverting input terminal of the comparator 65.

The other of the source and the drain of the transistor 56 is electrically connected to one of the source and the drain of the transistor 57, one of the source and the drain of the transistor 60, and one of the source and the drain of the transistor 61 by a wiring 76 (VDD2). ing. The gate of the transistor 56 is electrically connected to the gate of the transistor 57 and the output terminal of the comparator 64.

The other of the source and the drain of the transistor 57 is electrically connected to the other of the source and the drain of the transistor 61 and one of the source and the drain of the transistor 62.

The other of the source and the drain of the transistor 58 is electrically connected to one of the source and the drain of the transistor 59 by a wiring 78 (VSS2). The gate of the transistor 58 is electrically connected to the gate of the transistor 59 and the output terminal of the comparator 65.

The other of the source and the drain of the transistor 59 is electrically connected to the other of the source and the drain of the transistor 60, the gate of the transistor 60, and the gate of the transistor 61.

The other of the source and the drain of the transistor 62 is electrically connected to the wiring 81 (VSS3). The gate of the transistor 62 is electrically connected to the wiring 82 (BIAS).

The inverting input terminal of the comparator 64 is electrically connected to the wiring 84 (Vref−). The inverting input terminal of the comparator 65 is electrically connected to the wiring 85 (Vref+).

Note that the potential “Vref−” of the wiring 84 (Vref−) and the potential “Vref+” of the wiring 85 (Vref+) can be set as appropriate.

Further, the wiring 71 (VSS) can be set to “L”, but it can be operated by applying another potential.

FIG. 18 is a timing chart showing an example of the operation of the circuit 16. At time T01, the wiring 165 (SEL[x]), the wiring 163 (AZ), the wiring 70 (ABU), and the wiring 7
2 (ATC) is set to "H". As a result, the transistors 135, 133,
The transistors 50[1] to [m] and the transistors 52[1] to [m] are turned on. Further, the wirings 73 (AOP[1] to [m]) are set to "L", whereby the transistors 53[1] to [m] are turned off. Note that the wiring 165 (SEL[x]) is the wiring 165 in an arbitrary row (x is a natural number of n or less).

At this time, the current supplied to the wiring 156 (VOUT[1] to [m]) of each column corresponds to the image data of the reference frame, and there is a difference between the image data of the reference frame and the image data of the difference detection frame. The current value at zero is "I0". The current value I0 may be referred to as a reference current value.

The current values Ip[1] to Ip[m] flowing through the transistors 50[1] to [m] are equal to the current value I0, and the current values flowing through the transistors 51[1] to [m]. The current values of Ic[1] to current Ic[m] are also equal to "I0". In addition, the capacitive element 63 [
1] to [m] are charged with a potential corresponding to the gate voltage required to flow “I0” through the transistors 51[1] to [m].

At time T02, the wiring 165 (SEL[x]), the wiring 163 (AZ), and the wiring 70 (A
BU) and the wiring 72 (ATC) are set to “L”, whereby the transistor 135, the transistor 133, the transistors 50[1] to [m], and the transistors 52[1] to [m] are turned off.

At time T11, the wiring 165 (SEL[1]), the wiring 70 (ABU), and the wiring 73.
By setting (AOP[1]) to "H", the transistor 135 included in the pixel 11 in the first row, the transistors 50[1] to [m], and the transistor 53[1] are turned on. At this time, a current corresponding to the difference detected by the pixel 11[1,1] is supplied to the wiring 156(
VOUT[1]). Here, if the difference in the pixel 11[1,1] is zero, the current value of the current supplied to the wiring 156 (VOUT[1]) is “I0”. Also,
The current value of the current Ip[1] is equal to “I0”, and the current value of the current Ic[1] is also equal to “I0”.

At Time T12, the wiring 73 (AOP[2]) is set to “H”, whereby the transistor 53[2] is turned on. Further, the wiring 73 (AOP[1]) is set to “L”, whereby the transistor 53[1] is turned off. At this time, a current corresponding to the difference detected by the pixel 11[1,2] is supplied to the wiring 156 (VOUT[2]). Here, the pixel 11 [
If the difference between 1, 2] is zero, the current value of the current supplied to the wiring 156 (VOUT[2]) is “I0”. Further, the current value of the current Ip[2] is equal to “I0”, and the current value of the flowing current Ic[2] is also equal to “I0”.

At Time T13, the wiring 73 (AOP[2]) is set to “L” to turn off the transistor 53[2]. Further, at time T14, the wiring 73 (AOP[m]) is set to "
By setting to H″, the transistor 53[m] is turned on. At this time, the pixel 11[1,
The current corresponding to the difference detected by [m] is supplied to the wiring 156 (VOUT[m]). Here, if the difference between the pixels 11[1,m] is zero, the wiring 156 (VOUT[m
]) has a current value of “I0”. Further, the current value of the current Ip[m] is “I
The current value of the current Ic[m] is also equal to 0".

At time T15, the wiring 165 (SEL[1]), the wiring 70 (ABU), and the wiring 73.
By setting (AOP[m]) to "L", the transistor 135 included in the pixel 11 in the first row, the transistors 50[1] to [m], and the transistor 53[m] are turned off. This is the end of the difference detection of the pixels 11 in the first row.

Next, at time T21, the wiring 165 (SEL[2]), the wiring 70 (ABU), and the wiring 73 (AOP[1]) are set to “H”, whereby the transistor 135 included in the pixel 11 in the second row. Then, the transistors 50[1] to [m] and the transistor 53[1] are turned on. At this time, a current corresponding to the difference detected by the pixel 11[2,1] is applied to the wiring 1
56 (VOUT[1]). Here, assuming that the difference between the pixels 11[2,1] is zero, the current value of the current supplied to the wiring 156 (VOUT[1]) is “I0”.
The current value of the current Ip[1] is equal to “I0”, and the current value of the current Ic[1] is also “I0”.
be equivalent to.

At Time T22, the wiring 73 (AOP[2]) is set to “H”, whereby the transistor 53[2] is turned on. Further, the wiring 73 (AOP[1]) is set to “L”, whereby the transistor 53[1] is turned off. At this time, a current corresponding to the difference detected by the pixel 11[2,2] is supplied to the wiring 156 (VOUT[2]). Here, the wiring 156
If the current value of the current supplied to (VOUT[2]) is “I0−ΔI1”, the current Ip[
2] is equal to “I0−ΔI1”, and the current value of the current Ic[2] is equal to “I0”. Therefore, the current value of “2” is obtained via the transistor 53[2] and the transistor 54[2]. ΔI
A current of 1" will flow.

The current value “I0−ΔI1” is smaller than the current value “I0”. This is pixel 11[2
2] when the pixel 11[2, 2] acquires the image data of the reference frame, the illuminance of light applied to the photoelectric conversion element 120 when the image data of the difference detection frame is acquired by the photoelectric conversion element 120. It corresponds to the case where the illuminance is higher than that of the light radiated to the.

Here, the current “I ⁻ ”is supplied by the functions of the comparator 64 and the transistor 56. Here, the current “I” supplied to the transistor 54[2] through the transistor 56.
^{When −} ” is less (more) than “ΔI1”, the potential of the + terminal of the comparator 64 decreases (increases), and the output of the comparator 64 decreases (increases). That is, the gate voltage of the transistor 56 decreases. Since the transistor 56 is a p-ch type, it is possible to supply a larger (smaller) current “I ⁻ ”.

Further, since the same potential as the gate of the transistor 56 is applied to the transistor 57, W (channel width direction)/L (channel length direction) of the transistor 57 with respect to the transistor 56.
A current “n1·I ⁻ ”multiplied by the ratio (n1) flows through the transistor 57. In addition, the signal 36 (TRIG) changes to "H" by the buffer including the transistor 62 and the transistor 57.
Becomes A bias voltage is applied to the wiring 82 (BIAS). The bias voltage can be set appropriately.

At Time T23, the wiring 73 (AOP[2]) is set to "L", whereby the transistor 53[2] is turned off. In addition, at time T24, the wiring 73 (AOP[m]) is set to "
By setting it to H″, the transistor 53[m] is turned on. At this time, the pixel 11[2]
The current corresponding to the difference detected by [m] is supplied to the wiring 156 (VOUT[m]). Here, assuming that the difference between the pixels 11[2, m] is zero, the wiring 156 (VOUT[m
]) has a current value of “I0”. The current value of the current Ip[1] is "I
0", and the current value of the current Ic[1] is also equal to "I0".

At time T25, the wiring 165 (SEL[2]), the wiring 70 (ABU), and the wiring 73.
By setting (AOP[m]) to "L", the transistor 135 included in the pixel 11 in the second row, the transistors 50[1] to [m], and the transistor 53[m] are turned off. This is the end of the difference detection for the pixels 11 in the second row.

Next, at time T31, the wiring 165 (SEL[n]), the wiring 70 (ABU), and the wiring 73 (AOP[1]) are set to “H”, whereby the transistor 135 included in the pixel 11 in the nth row. Then, the transistors 50[1] to [m] and the transistor 53[1] are turned on. At this time, a current corresponding to the difference detected by the pixel 11[n, 1] is applied to the wiring 1
56 (VOUT[1]). Here, when the difference in the pixel 11[n, 1] is zero, the current value of the current supplied to the wiring 156 (VOUT[1]) is “I0”.
The current value of the current Ip[1] is equal to “I0”, and the current value of the current Ic[1] is also “I0”.
be equivalent to.

At Time T32, the wiring 73 (AOP[2]) is set to “H”, whereby the transistor 53[2] is turned on. Further, the wiring 73 (AOP[1]) is set to “L”, whereby the transistor 53[1] is turned off. At this time, a current corresponding to the difference detected by the pixel 11[n, 2] is supplied to the wiring 156 (VOUT[2]). Here, the wiring 156
If the current value of the current supplied to (VOUT[2]) is “I0+ΔI2”, the current Ip[
2] is equal to “I0+ΔI2” and the current value of the current Ic[2] is equal to “I0”. Therefore, the current value “ΔI” is obtained via the transistor 53[2] and the transistor 55[2].
A 2" current will flow.

The current value “I0+ΔI2” is larger than the current value “I0”. This is pixel 11[2
2] when the pixel 11[2, 2] acquires the image data of the reference frame, the illuminance of light applied to the photoelectric conversion element 120 when the image data of the difference detection frame is acquired by the photoelectric conversion element 120. It corresponds to the case where the illuminance of the light irradiating to is lower than.

Here, the current “I ⁺ ”is supplied by the functions of the comparator 65 and the transistor 58. Here, the current “I ⁺ ” flowing from the transistor 55[2] into the transistor 58 is “
If it is smaller (more) than ΔI2″, the potential of the + terminal of the comparator 65 rises (falls), and the output of the comparator rises (falls). That is, the gate voltage of the transistor 58 rises (falls), It becomes possible to supply more (less) current "I ⁺ ".

Since the same potential as the gate of the transistor 58 is applied to the transistor 59, a current “n2·I ⁺ ”, which is the W/L ratio (n2) of the transistor 59 to the transistor 58, flows through the transistor 59. The current flowing through the transistor 59 also flows through the transistor 60,
Further, the current “n” multiplied by the W/L ratio (n3) of the transistor 61 with respect to the transistor 60
3·n2·I ⁺ ″ flows into the transistor 61. Then, the signal 36 (TRIG) is generated by the buffer including the transistor 62, the transistor 57, and the transistor 61.
Becomes "H".

At Time T33, the wiring 73 (AOP[2]) is set to “L”, whereby the transistor 53[2] is turned off. In addition, at time T34, the wiring 73 (AOP[m]) is set to "
By setting it to H″, the transistor 53[m] is turned on. At this time, the pixel 11[n,
The current corresponding to the difference detected by [m] is supplied to the wiring 156 (VOUT[m]). Here, assuming that the difference in the pixel 11[n,m] is zero, the wiring 156 (VOUT[m
]) has a current value of “I0”. Further, the current value of the current Ip[m] is “I
The current value of the current Ic[m] is also equal to 0".

At Time T35, the wiring 165 (SEL[n]), the wiring 70 (ABU), and the wiring 73.
By setting (AOP[m]) to "L", the transistor 135 included in the pixel 11 in the nth row, the transistors 50[1] to [m], and the transistor 53[m] are turned off. This is the end of the difference detection for the pixels 11 in the nth row.

With the above structure, one embodiment of the present invention can generate the signal 36 (TRIG) for rewriting image data with a simple structure without requiring digital processing in the difference detection.
Further, the wiring 73 (AOP) is separated into the wiring 73 (AOP [1] to [m]) and electrically connected to the transistors 53 [1] to [m], respectively, so that difference detection for each pixel can be performed. This makes it possible to specify the pixel 11 in which the difference is detected.

Even when the pixel 11 has a configuration other than that shown in FIG. 5, the circuit 16 having the configuration shown in FIG. 17 can be used. Further, the circuit 16 in the case where the pixel 11 has a configuration other than that shown in FIG.
The operation can be referred to the timing chart shown in FIG. 18 as appropriate.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, a specific structural example of the imaging device of one embodiment of the present invention will be described with reference to the drawings.

19A is an example of a cross-sectional view of the imaging device of one embodiment of the present invention, which includes the pixel 11 shown in FIG.
1 shows an example of a specific connection mode of the photoelectric conversion element 120, the transistor 131, and the transistor 132 in FIG. Note that the transistors 133 to 135 are not illustrated in FIG. The imaging device includes a layer 1100 including the transistors 131 to 135 and a layer 1200 including the photoelectric conversion element 120.

Note that in the cross-sectional views described in this embodiment, each wiring, each electrode, and each conductor 91 is illustrated as an individual element; however, when they are electrically connected, the same element is used. It may be provided as. In addition, a mode in which the gate, the source, or the drain of the transistor is connected to each wiring through the conductor 91 is an example.
In some cases, each of the source and the drain has a function as a wiring.

Further, an insulating layer 92 and an insulating layer 93 which can function as a protective film, an interlayer insulating layer, or a planarizing film are provided over each element. For example, as the insulating layer 92, the insulating layer 93, and the like, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. Alternatively, an organic insulating film such as an acrylic resin or a polyimide resin may be used. The upper surfaces of the insulating layer 92, the insulating layer 93, etc. may be CMP (Chemical Mechanical) as necessary.
It is preferable to perform the flattening treatment by an al polishing method or the like.

In some cases, some of the wirings and the like shown in the drawings may not be provided, or wirings and transistors not shown in the drawings may be included in each layer. In addition, a layer not shown in the drawings may be included in the layered structure. In addition, some of the layers illustrated in the drawings may not be included.

Note that although each transistor has a back gate in FIG. 19A, the transistor may have no back gate as illustrated in FIG. 19B. Also,
As shown in FIG. 19C, only some of the transistors, for example, the transistor 131 may have a back gate. The back gate may be electrically connected to the front gates of the transistors provided to face each other. Alternatively, a fixed potential different from that of the front gate may be supplied to the back gate. Note that the form regarding the presence or absence of the back gate can be applied to the forms of other imaging devices described in the present embodiment.

As the photoelectric conversion element 120 provided in the layer 1200, various types of elements can be used. In FIG. 19A, a mode in which a selenium-based material is used for the photoelectric conversion layer 121 is illustrated. The photoelectric conversion element 120 using a selenium-based material has characteristics of high external quantum efficiency with respect to visible light. The photoelectric conversion element can be a highly sensitive sensor in which the amplification of electrons with respect to the amount of light incident due to the avalanche phenomenon is large. Further, since the selenium-based material has a high light absorption coefficient, it has an advantage that the photoelectric conversion layer 121 can be easily thinned.

Amorphous selenium or crystalline selenium can be used as the selenium-based material. Crystalline selenium can be obtained, for example, by heat treatment after forming amorphous selenium into a film. In addition,
By making the crystal grain size of crystalline selenium smaller than the pixel pitch, it is possible to reduce the characteristic variation between pixels. Further, crystalline selenium has characteristics such as higher spectral sensitivity to visible light and a higher light absorption coefficient than amorphous selenium.

Further, the photoelectric conversion layer 121 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, it may be a layer containing a compound of copper, indium, gallium, and selenium (CIGS). With CIS and CIGS, it is possible to form a photoelectric conversion element that can utilize the avalanche phenomenon as in the case of a single layer of selenium.

The photoelectric conversion element 120 using a selenium-based material is, for example, an electrode 1 formed of a metal material or the like.
The photoelectric conversion layer 121 may be provided between the transparent conductive layer 122 and the transparent conductive layer 122.
Further, CIS and CIGS are p-type semiconductors, and n-type semiconductors such as cadmium sulfide and zinc sulfide may be provided in contact with each other in order to form a junction.

In order to generate the avalanche phenomenon, a relatively high voltage (for example, 10
V or more) is preferably applied. Since the OS transistor has a higher drain breakdown voltage than the Si transistor, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, by combining an OS transistor having a high drain breakdown voltage and a photoelectric conversion element including a selenium-based material as a photoelectric conversion layer, an imaging device with high sensitivity and high reliability can be obtained.

Note that although the photoelectric conversion layer 121 and the light-transmitting conductive layer 122 are not separated between the circuits in FIG. 19A, they may be separated between the circuits as illustrated in FIG.
In addition, it is preferable that a partition wall 127 is provided between the pixels in a region where the electrode 126 is not provided with an insulator so that a crack is not formed in the photoelectric conversion layer 121 and the light-transmitting conductive layer 122. The partition 127 may not be provided as shown in FIG. In addition, FIG.
20C illustrates a structure in which the wiring 95 and the conductor 91 are provided between the light-transmitting conductive layer 122 and the wiring 94, as shown in FIGS. Layer 122 and wiring 94
May be in direct contact with each other.

Further, the electrode 126, the wiring 94, and the like may be multi-layered. For example, as illustrated in FIG. 21A, the electrode 126 can be a double layer of a conductive layer 126a and a conductive layer 126b, and the wiring 94 can be a double layer of a conductive layer 94a and a conductive layer 94b. In the configuration of FIG. 21(A),
For example, the conductive layer 126a and the conductive layer 94a may be formed by selecting a metal or the like having low resistance, and the conductive layer 126b may be formed by selecting a metal or the like having good contact characteristics with the photoelectric conversion layer 121.
With such a structure, the electrical characteristics of the photoelectric conversion element can be improved. Further, some metals may cause electrolytic corrosion by coming into contact with the translucent conductive layer 122. Even when such a metal is used for the conductive layer 94a, electrolytic corrosion can be prevented by interposing the conductive layer 94b.

For the conductive layer 126a and the conductive layer 94a, for example, aluminum, titanium, or a stack in which aluminum is sandwiched by titanium can be used. For the conductive layer 126b and the conductive layer 94b, molybdenum, tungsten, or the like can be used, for example.

Further, the insulating layer 92 and the like may have a multi-layer structure. For example, as shown in FIG. 21B, the insulating layer 92 has an insulating layer 92a and an insulating layer 92b, and the insulating layer 92a and the insulating layer 9 are
If the etching rate is different from that of 2b, the conductor 91 has a step. Similarly, when the interlayer insulating layer and other insulating layers used for the flattening film are multilayer, the conductor 91 also has a step. Although the example in which the insulating layer 92 has two layers is shown here, the insulating layer 92 and the other insulating layers may have three or more layers.

Note that the partition wall 127 can be formed using an inorganic insulator, an insulating organic resin, or the like. In addition, the partition wall 127 may be colored in black or the like in order to shield the transistor or the like from light and/or to determine the area of the light receiving portion per pixel.

Further, for the photoelectric conversion element 120, a pi using an amorphous silicon film, a microcrystalline silicon film, or the like is used.
An n-type diode element or the like may be used.

For example, FIG. 22 shows an example in which a pin type thin film photodiode is used as the photoelectric conversion element 120. The photodiode includes a p-type semiconductor layer 125, an i-type semiconductor layer 124, and an n-type semiconductor layer 124.
The semiconductor layers 123 of the mold have a configuration in which they are sequentially stacked. Amorphous silicon is preferably used for the i-type semiconductor layer 124. For the n-type semiconductor layer 123 and the p-type semiconductor layer 125, amorphous silicon or microcrystalline silicon containing a dopant imparting each conductivity type can be used. A photodiode including amorphous silicon as a photoelectric conversion layer has high sensitivity in a visible light wavelength region and easily detects weak visible light.

In the photoelectric conversion element 120 shown in FIG. 22, the p-type semiconductor layer 125 and the electrode 126 are electrically connected. The n-type semiconductor layer 123 is electrically connected to the wiring 94 via the conductor 91.

23A, 23B, 23C, and 23D show the structure of the photoelectric conversion element 120 in the form of a pin-type thin film photodiode and the connection mode of the photoelectric conversion element 120 and wiring.
), (E), and (F). Note that the configuration of the photoelectric conversion element 120 and the connection mode of the photoelectric conversion element 120 and the wiring are not limited to these and may be another mode.

FIG. 23A shows the light-transmitting conductive layer 12 in contact with the n-type semiconductor layer 123 of the photoelectric conversion element 120.
2 is provided. The transparent conductive layer 122 acts as an electrode and can increase the output current of the photoelectric conversion element 120.

For the light-transmitting conductive layer 122, for example, indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, or fluorine is used. Tin oxide containing, tin oxide containing antimony, graphene, or the like can be used. The transparent conductive layer 122 is not limited to a single layer and may be a stack of different films.

FIG. 23B shows a structure in which the n-type semiconductor layer 123 of the photoelectric conversion element 120 and the wiring 95 are directly connected.

FIG. 23C shows the light-transmitting conductive layer 12 in contact with the n-type semiconductor layer 123 of the photoelectric conversion element 120.
2 is provided, and the wiring 95 and the transparent conductive layer 122 are electrically connected.

In FIG. 23D, an opening where the n-type semiconductor layer 123 is exposed is provided in an insulating layer that covers the photoelectric conversion element 120, and the light-transmitting conductive layer 122 that covers the opening is electrically connected to the wiring 95. It is a configured structure.

FIG. 23E illustrates a structure in which the conductor 91 which penetrates the photoelectric conversion element 120 is provided. In this structure, the wiring 94 is electrically connected to the n-type semiconductor layer 123 via the conductor 91. Note that, in the drawing, the wiring 94 and the electrode 126 are shown to be electrically connected to each other through the p-type semiconductor layer 125. However, the electric resistance in the lateral direction of the p-type semiconductor layer 125 is high, and therefore, if an appropriate interval is provided between the wiring 94 and the electrode 126, the resistance between them becomes extremely high. Therefore, the photoelectric conversion element 120 can have diode characteristics without short-circuiting the anode and the cathode. Note that a plurality of conductors 91 may be electrically connected to the n-type semiconductor layer 123.

FIG. 23F illustrates a structure in which the photoelectric conversion element 120 in FIG. 23E is provided with a light-transmitting conductive layer 122 which is in contact with the n-type semiconductor layer 123.

The photoelectric conversion element 120 shown in FIGS. 23D, 23E, and 23F has an advantage that a wide light receiving area can be secured because the light receiving region and the wiring and the like do not overlap with each other.

Further, as the photoelectric conversion element 120, as shown in FIG. 24, a photodiode having a silicon substrate 100 as a photoelectric conversion layer can be used.

The photoelectric conversion element 120 formed using the above-described selenium-based material, amorphous silicon, or the like can be manufactured using a general semiconductor manufacturing process such as a film forming process, a lithography process, or an etching process. Further, the selenium-based material has high resistance, and the photoelectric conversion layer 121 can have a structure in which it is not separated between circuits as illustrated in FIG. Therefore, the imaging device of one embodiment of the present invention has high yield and can be manufactured at low cost. On the other hand, when forming a photodiode using the silicon substrate 100 as a photoelectric conversion layer, highly difficult steps such as a polishing step and a bonding step are required.

Further, the imaging device of one embodiment of the present invention may have a structure in which silicon substrates 106 each having a circuit are stacked. For example, as illustrated in FIG. 25A, the layer 1400 including the transistor 101 and the transistor 102 each having an active region in the silicon substrate 106 can overlap with the pixel circuit. Note that FIG. 25B corresponds to a cross-sectional view of the transistor in the channel width direction.

The circuit formed on the silicon substrate 106 can have a function of reading a signal output from the pixel circuit and a function of performing a process of converting the signal, for example, as shown in a circuit diagram in FIG. It can be configured to include a CMOS inverter. Transistor 101 (
The gate of the n-ch type) and the gate of the transistor 102 (p-ch type) are electrically connected to each other. In addition, one of a source and a drain of one transistor is electrically connected to one of a source and a drain of the other transistor. Further, the other of the source and the drain of both transistors is electrically connected to another wiring.

Further, the silicon substrate 100 and the silicon substrate 106 are not limited to bulk silicon substrates,
It is also possible to use a substrate made of germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor.

Here, as shown in FIGS. 24 and 25A, insulation is provided between a region where a transistor including an oxide semiconductor is formed and a region where a Si device (Si transistor or Si photodiode) is formed. A layer 96 is provided.

Hydrogen in the insulating layer provided in the vicinity of the active regions of the transistors 101 and 102 terminates a dangling bond of silicon. Therefore, the hydrogen is
01 and the transistor 102 have an effect of improving reliability. On the other hand, transistor 1
Hydrogen in the insulating layer such as 31 provided in the vicinity of the oxide semiconductor layer which is an active layer is one of the factors which generate carriers in the oxide semiconductor layer. Therefore, the hydrogen is
In some cases, it may cause a decrease in reliability such as 1. Therefore, when one layer having a Si transistor and the other layer having an OS transistor are stacked, an insulating layer 96 which can have a function of preventing diffusion of hydrogen is preferably provided between them. Insulation layer 9
6, by confining hydrogen in one layer, the transistor 101 and the transistor 1
02 reliability can be improved. In addition, since the diffusion of hydrogen from one layer to the other layer is suppressed, the reliability of the transistor 131 or the like can be improved.

Examples of the insulating layer 96 include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and yttria-stabilized zirconia (YSZ: Ytria-Stabili).
zed Zirconia) or the like can be used.

Note that in the structure illustrated in FIG. 25A, a circuit (eg, a driver circuit) formed over the silicon substrate 106, the transistor 131, and the photoelectric conversion element 120 can be formed to overlap with each other. The degree of integration of pixels can be increased. That is, the resolution of the imaging device can be increased. For example, it is suitable to be used for an image pickup device having a pixel number of 4K2K, 8K4K, or 16K8K. Since the 8K4K image pickup device has about 33 million pixels, it can be called 33M. In addition, for example, the transistor 13 included in the pixel 11
4 and the transistor 135 may be formed of Si transistors, and a region in which the transistor 131, the transistor 132, the transistor 133, and the photoelectric conversion element 120 overlap with the transistor 134 and the transistor 135 may be included. in this case,
The transistors 131, 132, and 133 are OS transistors.

The imaging device illustrated in FIG. 25A has a structure in which the silicon substrate 106 is not provided with a photoelectric conversion element. Therefore, the photoelectric conversion element 1 is not affected by various transistors and wirings.
An optical path for 20 can be secured, and a pixel with a high aperture ratio can be formed.

25A and 25B, the Si transistor exemplifies a fin-type structure, but may be a planar type as shown in FIG. Alternatively, as illustrated in FIG. 26B, the transistor may include a silicon thin film active layer 105. Also,
The active layer 105 is made of polycrystalline silicon or SOI (Silicon on Insulator).
) Single crystal silicon.

The imaging device of one embodiment of the present invention can have a structure illustrated in FIG. 27.

The image pickup device shown in FIG. 27 is a modification of the image pickup device shown in FIG. 25A, and illustrates an example in which a CMOS inverter is formed using an OS transistor and a Si transistor.

Here, the transistor 102 which is a Si transistor provided in the layer 1400 is a p-ch type and the transistor 101 which is an OS transistor provided in the layer 1100 is an n-ch type. By providing only the p-ch type transistor on the silicon substrate 106, steps such as well formation and n type impurity layer formation can be omitted.

Although the image pickup apparatus shown in FIG. 27 shows an example in which selenium or the like is used for the photoelectric conversion element 120,
A configuration using a pin type thin film photodiode may be used as in the case of FIG.

In the imaging device illustrated in FIG. 27, the transistor 101 can be manufactured in the same step as the transistor 131 and the transistor 132 which are formed in the layer 1100. Therefore, the manufacturing process of the imaging device can be simplified.

In addition, as shown in FIG. 28, the imaging device of one embodiment of the present invention has a structure including a pixel formed of a photodiode formed over the silicon substrate 100 and an OS transistor formed over the photodiode, and a circuit formed therein. It may be configured to be bonded to the silicon substrate 106 that has been formed.
With such a configuration, it becomes easy to increase the effective area of the photodiode formed on the silicon substrate 100. Further, a high-performance semiconductor device can be provided by highly integrating a circuit formed on the silicon substrate 106 with a miniaturized Si transistor.

FIG. 29A is a cross-sectional view of an example of a mode in which a color filter or the like is added to the imaging device. The cross-sectional view shows a part of a region having a pixel circuit for three pixels. Photoelectric conversion element 120
An insulating layer 2500 is formed on the layer 1200 in which the insulating layer 2500 is formed. For the insulating layer 2500, a silicon oxide film or the like having a high light-transmitting property with respect to visible light can be used. Alternatively, a silicon nitride film may be stacked as the passivation film. Further, as the antireflection film, a dielectric film of hafnium oxide or the like may be laminated.

A light-blocking layer 2510 may be formed over the insulating layer 2500. The light-blocking layer 2510 can have a function of preventing color mixture of light passing through the upper color filter. The light-blocking layer 2510 can have a structure in which a metal layer of aluminum, tungsten, or the like or a dielectric film that can function as an antireflection film is stacked with the metal layer.

An organic resin layer 2520 can be provided as a planarization film over the insulating layer 2500 and the light-blocking layer 2510. In addition, a color filter 2530 (color filter 25
30a, a color filter 2530b, and a color filter 2530c) are formed. For example, the color filter 2530a, the color filter 2530b, and the color filter 2530
A color image can be obtained by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to c.

An insulating layer 2560 having a light-transmitting property or the like can be provided over the color filter 2530.

Further, as shown in FIG. 29B, instead of the color filter 2530, the optical conversion layer 255 is used.
You may use 0. With such a configuration, it is possible to provide an imaging device that can obtain images in various wavelength regions.

For example, an infrared imaging device can be obtained by using a filter that blocks light having a wavelength of visible light or less in the optical conversion layer 2550. Further, if a filter that blocks light having a wavelength of near infrared rays or less is used for the optical conversion layer 2550, a far infrared imaging device can be obtained. Also, the optical conversion layer 2550
An ultraviolet imaging device can be obtained by using a filter that blocks light having a wavelength of visible light or more.

Further, if a scintillator is used for the optical conversion layer 2550, it can be used as an imaging device used for an X-ray imaging device or the like to obtain an image in which the intensity of radiation is visualized. When radiation such as X-rays that have passed through a subject is incident on a scintillator, it is converted into light (fluorescence) such as visible light and ultraviolet light by a phenomenon called photoluminescence. Then, the light is converted into the photoelectric conversion element 120.
The imaging data is acquired by detecting with. Moreover, you may use the imaging device of the said structure for a radiation detector etc.

The scintillator is made of a substance that absorbs energy of the radiation such as X-rays and gamma rays to emit visible light or ultraviolet light, or a material containing the substance. For example, Gd ₂ O
₂ S:Tb, Gd ₂ O ₂ S:Pr, Gd ₂ O ₂ S:Eu, BaFCl:Eu, NaI, C
Materials such as sI, CaF ₂ , BaF ₂ , CeF ₃ , LiF, LiI, and ZnO, and those obtained by dispersing them in a resin or ceramics are known.

In addition, in the photoelectric conversion element 120 using a selenium-based material, radiation such as X-rays can be directly converted into electric charges, so that a scintillator can be omitted.

Color filter 2530a, color filter 2530b, and color filter 2530c
A microlens array 2540 may be provided above. Micro lens array 2540
The light passing through the individual lenses of the device passes through the color filter immediately below and is applied to the photoelectric conversion element 120. Note that a region other than the layer 1200 illustrated in FIGS. 29A, 29B, and 29C is a layer 1600.

The specific configuration of the imaging device illustrated in FIG. 29C is as illustrated in FIG. 30 when the imaging device illustrated in FIG. 19A is taken as an example. Further, when the image pickup apparatus shown in FIG. 24 is taken as an example, it becomes as shown in FIG.

In addition, as shown in FIGS. 32 and 33, the imaging device of one embodiment of the present invention has a diffraction grating 1500.
May be combined with. An image of a subject (diffraction image) that has passed through the diffraction grating 1500 can be captured in a pixel, and an input image (image of the subject) can be configured by arithmetic processing from a captured image in the pixel. Further, the cost of the image pickup device can be reduced by using the diffraction grating 1500 instead of the lens.

The diffraction grating 1500 can be formed using a light-transmitting material. For example, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. Alternatively, an organic insulating film such as an acrylic resin or a polyimide resin may be used. Alternatively, it may be a laminate of the above-mentioned inorganic insulating film and organic insulating film.

The diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. Alternatively, it can be formed using a lithography process and an etching process. It can also be formed using nanoimprint lithography, laser scribing, or the like.

A space X may be provided between the diffraction grating 1500 and the microlens array 2540. The interval X can be 1 mm or less, preferably 100 μm or less. Note that the space may be a space, or a light-transmitting material may be provided as a sealing layer or an adhesive layer. For example, an inert gas such as nitrogen or a rare gas can be contained in the space. Alternatively, an acrylic resin, an epoxy resin, a polyimide resin, or the like may be provided at the interval. Alternatively, a liquid such as silicone oil may be provided. Even when the microlens array 2540 is not provided, the space X may be provided between the color filter 2530 and the diffraction grating 1500.

In addition, the imaging device of one embodiment of the present invention may be curved as illustrated in FIGS. 34A1 and 34B1. FIG. 34(A1) shows a state in which the imaging device is curved in the direction of the chain double-dashed line X1-X2 in the figure. FIG. 34(A2) is a chain double-dashed line X in FIG. 34(A1).
It is sectional drawing of the site|part shown by 1-X2. 34A3 is a cross-sectional view of a portion indicated by dashed-two dotted line Y1-Y2 in FIG. 34A1.

FIG. 34(B1) shows a state in which the imaging device is curved in the direction of the alternate long and two short dashes line X3-X4 in the same figure and is also curved in the direction of the alternate long and two short dashes line Y3-Y4 in the same figure. FIG. 34(B2) is a cross-sectional view of a portion indicated by alternate long and two short dashes line X3-X4 in FIG. 34(B1). FIG. 34(B3) shows
FIG. 35 is a cross-sectional view of a portion indicated by alternate long and two short dashes line Y3-Y4 in FIG. 34(B1).

By curving the imaging device, field curvature and astigmatism can be reduced. Therefore, the optical design of a lens or the like used in combination with the imaging device can be facilitated. For example,
Since the number of lenses for aberration correction can be reduced, it is possible to easily reduce the size and weight of a semiconductor device or the like using an image pickup device. Moreover, the quality of the captured image can be improved.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 6)
In this embodiment, the configuration of the display device 23 will be described in detail with reference to the drawings.

FIG. 35 is a circuit diagram showing a configuration example of the pixel 210 included in the display device 23. FIG. 35(A)
Is an example of a pixel using a liquid crystal element as a display element, and FIG. 35B is an example of a pixel using a light emitting element as a display element.

A pixel 210 illustrated in FIG. 35A includes a transistor 211, a liquid crystal element 212, and a capacitor 213.

A wiring 215 is electrically connected to the gate of the transistor 211. A wiring 216 is electrically connected to one of a source and a drain of the transistor 211. Further, the liquid crystal element 212 and one terminal of the capacitor 213 are electrically connected to the other of the source and the drain of the transistor 211.

The transistor 211 can function as a switching element which controls electrical connection between the liquid crystal element 212 and the wiring 216, and is turned on/off by a scan signal input from the wiring 215. Note that the transistor 211 is preferably an OS transistor which can reduce off-state current.

A pixel 210 illustrated in FIG. 35B includes a transistor 221, a transistor 222, and a light emitting element 223.

A wiring 215 is electrically connected to the gate of the transistor 221. A wiring 216 is electrically connected to one of a source and a drain of the transistor 221. The gate of the transistor 222 is electrically connected to the other of the source and the drain of the transistor 221. A wiring 217 is electrically connected to one of a source and a drain of the transistor 222. Further, one terminal of the light emitting element 223 is electrically connected to the other of the source and the drain of the transistor 222.

The transistor 221 is a switching element that controls electrical connection between the gate of the transistor 222 and the wiring 216, and is turned on/off by a scan signal input from the wiring 215. Note that the transistor 221 is preferably an OS transistor which can reduce off-state current.

In the circuit diagrams shown in FIGS. 35A and 35B, “OS” is added to the circuit symbol of the OS transistor in order to clearly indicate that it is an OS transistor.

Note that the pixel 210 only needs to be able to hold the image data in the second mode in which the imaging data 31 is not output. Therefore, the structure is not limited to the case where a transistor with low off-state current is used. The pixel 210 may have a configuration including a memory capable of holding image data.

A structure having a memory in the pixel 210 is shown in FIG. The pixel 210 can hold video data by including the memory 214. As the memory, SRA
M (Static Random Access Memory) and DRAM (Dyna)
Mic Random Access Memory) or the like may be applied. FIG. 36B shows an example of a circuit diagram in the case where SRAM is applied to the memory 214.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 7)
In this embodiment, a transistor including an oxide semiconductor, which can be used in one embodiment of the present invention, will be described with reference to drawings. Note that in the drawings of this embodiment, some of the elements are enlarged, reduced, or omitted for clarity.

FIG. 37A is a top view of the transistor 401 of one embodiment of the present invention. In addition, in FIG.
37B corresponds to a cross section in the direction of dashed-dotted line B1-B2 in FIG. In addition, FIG. 37(A)
The cross section in the direction of dashed-dotted line B3-B4 shown in FIG. The alternate long and short dash line B1-
The B2 direction may be referred to as the channel length direction, and the alternate long and short dash line B3-B4 direction may be referred to as the channel width direction.

The transistor 401 includes a substrate 415, an insulating layer 420, an oxide semiconductor layer 430, a conductive layer 440, a conductive layer 450, an insulating layer 460, a conductive layer 470, an insulating layer 475, and an insulating layer 480. Have.

The insulating layer 420 is in contact with the substrate 415, the oxide semiconductor layer 430 is in contact with the insulating layer 420, and the conductive layers 440 and 450 are in contact with the insulating layer 420 and the oxide semiconductor layer 430.
60 is in contact with the insulating layer 420, the oxide semiconductor layer 430, the conductive layer 440, and the conductive layer 450,
The conductive layer 470 is in contact with the insulating layer 460, the insulating layer 475 is in contact with the insulating layer 420, the conductive layer 440, the conductive layer 450, and the conductive layer 470, and the insulating layer 480 is in contact with the insulating layer 475.

Here, in the oxide semiconductor layer 430, a region overlapping with the conductive layer 440 is a region 531, a region overlapping with the conductive layer 450 is a region 532, and a region overlapping with the insulating layer 460 is a region 533.

The conductive layers 440 and 450 are electrically connected to the oxide semiconductor layer 430.

The conductive layer 440 can function as a source or a drain, the conductive layer 450 can function as a source or a drain, the insulating layer 460 can function as a gate insulating layer, and the conductive layer 470 can function as a gate.

A region 531 illustrated in FIG. 37B is one of the source region and the drain region, which is the region 53.
2 is a source region or a drain region, and the region 533 can function as a channel formation region.

Further, although the conductive layer 440 and the conductive layer 450 are illustrated as an example of being formed as a single layer, they may be a stack of two or more layers. Furthermore, although the conductive layer 470 is illustrated as an example formed of two layers of the conductive layer 471 and the conductive layer 472, it may be a single layer or a stacked layer of three or more layers. The structure can be applied to the other transistors described in this embodiment.

Note that a function as a planarization film may be added to the insulating layer 480 as needed.

In addition, the transistor of one embodiment of the present invention may have the structure illustrated in FIGS. 37C and 37D. FIG. 37C is a top view of the transistor 402. A cross section in the direction of dashed-dotted line C1-C2 in FIG. 37C corresponds to FIG. 37D. A cross section in the direction of dashed-dotted line C3-C4 in FIG. 37C corresponds to FIG. 39B. In addition, the dashed-dotted line C1-C2 direction may be called a channel length direction, and the dashed-dotted line C3-C4 direction may be called a channel width direction.

In the transistor 402, the end portion of the insulating layer 460 and the end portion of the conductive layer 470 do not match,
Different from the transistor 401. In the structure of the transistor 402, the conductive layer 440 and the conductive layer 450 are widely covered with the insulating layer 460; therefore, the electrical resistance between the conductive layer 440 and the conductive layer 450 and the conductive layer 470 is high and the gate leakage current is small. It has features.

The transistors 401 and 402 each have a top-gate structure including a region where the conductive layer 470 overlaps with the conductive layers 440 and 450. The width of the region in the channel length direction is preferably 3 nm or more and less than 300 nm in order to reduce the parasitic capacitance. In this structure, since the offset region is not formed in the oxide semiconductor layer 430, a transistor with high on-state current can be easily formed.

In addition, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. 37E and 37F. FIG. 37E is a top view of the transistor 403. A cross section in the direction of dashed-dotted line D1-D2 in FIG. 37E corresponds to FIG. A cross section in the direction of dashed-dotted line D3-D4 in FIG. 37E corresponds to FIG. In addition, the dashed-dotted line D1-D2 direction may be called a channel length direction, and the dashed-dotted line D3-D4 direction may be called a channel width direction.

The insulating layer 420 of the transistor 403 is in contact with the substrate 415, the oxide semiconductor layer 430 is in contact with the insulating layer 420, the insulating layer 460 is in contact with the insulating layer 420 and the oxide semiconductor layer 430, and the conductive layer 470 is in contact with the insulating layer 460. The insulating layer 475 is in contact with the insulating layer 420, the oxide semiconductor layer 430, and the conductive layer 470, the insulating layer 480 is in contact with the insulating layer 475, and the conductive layer 440 and the conductive layer 450 are in contact with the oxide semiconductor layer 430 and the insulating layer 480.

Openings are provided in the insulating layer 475 and the insulating layer 480, and the conductive layer 440 is provided through the openings.
The conductive layer 450 is electrically connected to the oxide semiconductor layer 430.

Note that an insulating layer (planarizing film) in contact with the conductive layer 440, the conductive layer 450, and the insulating layer 480 may be included as needed.

In the oxide semiconductor layer 430, the insulating layer 475 overlaps with the regions 531 and 533.
The region sandwiched between is the region 534. In addition, the region 532 and the region 5 overlap with the insulating layer 475.
A region sandwiched by 33 is a region 535.

In addition, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. 38A and 38B. FIG. 38A is a top view of the transistor 404. A cross section in the direction of dashed-dotted line E1-E2 in FIG. 38A corresponds to FIG. 38B. A cross section in the direction of dashed-dotted line E3-E4 in FIG. 38A corresponds to FIG. In addition, the dashed-dotted line E1-E2 direction may be called a channel length direction, and the dashed-dotted line E3-E4 direction may be called a channel width direction.

The insulating layer 420 of the transistor 404 is in contact with the substrate 415, the oxide semiconductor layer 430 is in contact with the insulating layer 420, and the conductive layers 440 and 450 are the insulating layer 420 and the oxide semiconductor layer 4.
30, the insulating layer 460 is in contact with the insulating layer 420 and the oxide semiconductor layer 430, and the conductive layer 4 is
70 is in contact with the insulating layer 460, the insulating layer 475 is in contact with the insulating layer 420, the oxide semiconductor layer 430, the conductive layer 440, the conductive layer 450, and the conductive layer 470, and the insulating layer 480 is in contact with the insulating layer 475.

The transistor 404 is different from the transistor 403 in that the conductive layers 440 and 450 are in contact with each other so as to cover the end portion of the oxide semiconductor layer 430.

The transistors 403 and 404 have a self-aligned structure in which the conductive layer 470 does not have a region where the conductive layers 440 and 450 overlap. The self-aligned transistor has extremely small parasitic capacitance between the gate and the source and drain, and is suitable for high-speed operation.

In addition, the transistor of one embodiment of the present invention may have the structure illustrated in FIGS. 38C and 38D. FIG. 38C is a top view of the transistor 405. A cross section in the direction of dashed-dotted line F1-F2 in FIG. 38C corresponds to FIG. A cross section in the direction of dashed-dotted line F3-F4 in FIG. 38C corresponds to FIG. 39A. In addition, the dashed-dotted line F1-F2 direction may be called a channel length direction, and the dashed-dotted line F3-F4 direction may be called a channel width direction.

In the transistor 405, the conductive layer 440 is formed of two layers of a conductive layer 441 and a conductive layer 442,
The conductive layer 450 is formed of two layers, a conductive layer 451 and a conductive layer 452. In addition, the insulating layer 42
0 is in contact with the substrate 415, the oxide semiconductor layer 430 is in contact with the insulating layer 420, the conductive layers 441 and 451 are in contact with the oxide semiconductor layer 430, and the insulating layer 460 is the insulating layer 420, the oxide semiconductor layer 430, and the conductive layer. The layer 441 and the conductive layer 451 are in contact, the conductive layer 470 is in contact with the insulating layer 460, the insulating layer 475 is in contact with the insulating layer 420, the conductive layer 441, the conductive layer 451, and the conductive layer 470, and the insulating layer 480 is in contact with the insulating layer 475. , The conductive layer 442 is the conductive layer 441 and the insulating layer 4.
80, the conductive layer 452 is in contact with the conductive layer 451 and the insulating layer 480.

Here, the conductive layers 441 and 451 are in contact with the top surface of the oxide semiconductor layer 430 and are not in contact with the side surfaces thereof.

Note that an insulating layer in contact with the conductive layer 442, the conductive layer 452, and the insulating layer 480 may be included as needed.

In addition, the conductive layers 441 and 451 are electrically connected to the oxide semiconductor layer 430. The conductive layer 442 is electrically connected to the conductive layer 441, and the conductive layer 452 is electrically connected to the conductive layer 451.

In the oxide semiconductor layer 430, a region overlapping with the conductive layer 441 serves as a region 531 which can function as one of a source region and a drain region, and a region overlapping with the conductive layer 451 serves as the other of the source region and the drain region. Area 53 which can have
It becomes 2.

The transistor of one embodiment of the present invention may have any of the structures illustrated in FIGS. 38E and 38F. FIG. 38E is a top view of the transistor 406. A cross section in the direction of dashed-dotted line G1-G2 in FIG. 38E corresponds to FIG. A cross section in the direction of dashed-dotted line G3-G4 in FIG. 38E corresponds to FIG. 39A. In addition, the dashed-dotted line G1-G2 direction may be called a channel length direction, and the dashed-dotted line G3-G4 direction may be called a channel width direction.

The transistor 406 is different from the transistor 403 in that the conductive layer 440 is formed of two layers of a conductive layer 441 and a conductive layer 442, and the conductive layer 450 is formed of two layers of a conductive layer 451 and a conductive layer 452.

In the structure of the transistor 405 and the transistor 406, the conductive layer 440 and the conductive layer 4 are included.
Since 50 is not in contact with the insulating layer 420, oxygen in the insulating layer 420 is less likely to be taken by the conductive layers 440 and 450, and oxygen can be easily supplied from the insulating layer 420 into the oxide semiconductor layer 430. Can be

Note that an impurity for forming oxygen vacancies and increasing conductivity may be added to the regions 534 and 535 in the transistors 403, 404, and 406. Examples of impurities that form oxygen vacancies in the oxide semiconductor layer include phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and And one or more selected from carbon and carbon can be used. As a method for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

When the above element is added to the oxide semiconductor layer as an impurity element, the bond between the metal element and oxygen in the oxide semiconductor layer is broken and oxygen vacancies are formed. The conductivity of the oxide semiconductor layer can be increased by the interaction between oxygen vacancies contained in the oxide semiconductor layer and hydrogen left in the oxide semiconductor layer or added later.

Note that when hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed by addition of an impurity element,
Hydrogen enters the oxygen vacancy site and a donor level is formed near the conduction band. As a result, an oxide conductor can be formed. Here, the oxide semiconductor which is made to be a conductor is referred to as an oxide conductor. Note that the oxide conductor has a light-transmitting property like an oxide semiconductor.

The oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level match or substantially match. Therefore, the contact between the oxide conductor layer and the conductive layer which can have a function as a source and a drain is an ohmic contact, and the oxide conductor layer and a conductive layer which can have a function as a source and a drain. The contact resistance with the layer can be reduced.

Although the oxide semiconductor layer 430 is a single layer in the transistors 401 to 406 in FIGS. 37 to 39, the oxide semiconductor layer 430 may be a stacked layer. 40A is a top view of the oxide semiconductor layer 430, and FIGS. 40B and 40C are
FIG. 4 is a cross-sectional view of an oxide semiconductor layer 430 having a two-layer structure of an oxide semiconductor layer 430a and an oxide semiconductor layer 430b. 40D and 40E are cross-sectional views of the oxide semiconductor layer 430 having a three-layer structure of the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c.

Note that the oxide semiconductor layer 430a and the oxide semiconductor layer 430c do not form a channel region and thus can be referred to as insulating layers.

For the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c, oxide semiconductor layers having different compositions, or the like can be used.

The oxide semiconductor layer 430 of the transistors 401 to 406 is shown in FIG.
It can be replaced with the oxide semiconductor layer 430 shown in (C) or FIGS. 40D and 40E.

In addition, the transistor of one embodiment of the present invention may have any of the structures illustrated in FIGS.
41(A), (C), (E) and FIGS. 42(A), (C), (E) show the transistor 40.
7 is a top view of transistors 7 to 412. FIG. 41B is a cross-sectional view taken along dashed-dotted line H1-H2 direction to M1-M2 direction in FIGS. 41A, 41C, and 42E, 42A, 42C, and 42E. , (D), (F) and FIGS. 42(B), (D), (F). In addition, alternate long and short dash lines H3-H4 shown in FIGS. 41(A) and (E) and FIGS. 42(A), (C), and (E)
A cross section in the directions J3-J4 to M3-M4 corresponds to FIG. Further, FIG.
A cross section in the direction of dashed-dotted line I3-I4 shown in (C) corresponds to FIG. Note that the dashed-dotted line H1-H2 direction to M1-M2 direction is the channel length direction, and the dashed-dotted line H3-H4 direction to M1.
The -M2 direction may be referred to as the channel width direction.

In the transistor 407 and the transistor 408, the oxide semiconductor layer 430 has two layers (the oxide semiconductor layer 430a and the oxide semiconductor layer 430b) in the regions 531 and 532, and the oxide semiconductor layer 430 has three layers (in the region 533). The oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c), and between the conductive layers 440 and 450 and the insulating layer 460, part of the oxide semiconductor layer (oxide). Semiconductor layer 430c
) Is included, the transistor 401 and the transistor 402 have the same configuration.

In the transistor 409, the transistor 410, and the transistor 412, in the region 531, the region 532, the region 534, and the region 535, the oxide semiconductor layer 430 has two layers (the oxide semiconductor layer 430a and the oxide semiconductor layer 430b), and in the region 533. The oxide semiconductor layer 430 has three layers (the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 4).
30c), and has the same configuration as the transistor 403, the transistor 404, and the transistor 406.

In the transistor 411, the oxide semiconductor layer 430 has two layers (the oxide semiconductor layer 430a and the oxide semiconductor layer 430b) in the regions 531 and 532, and the transistor 411 has three layers (the oxide semiconductor layer 430 in the region 533). The layer 430a, the oxide semiconductor layer 430b, the oxide semiconductor layer 430c), the conductive layer 441 and the conductive layer 451, and the insulating layer 4
60 has the same configuration as the transistor 405 except that a part of the oxide semiconductor layer (the oxide semiconductor layer 430c) is interposed between the transistor 60 and the transistor 60.

In addition, a transistor of one embodiment of the present invention has a structure shown in FIGS.
), (F) and FIGS. 45(A), (B), (C), (D), (E), and (F), the cross-sectional views in the channel length direction of the transistors 401 to 412, and FIG. C)
4A to 4C and cross-sectional views in the channel width direction of the transistors 401 to 406 illustrated in FIGS.
A conductive layer 473 may be provided between the oxide semiconductor layer 430 and the substrate 415 as in a cross-sectional view in the channel width direction of the transistors 407 to 412 illustrated in FIG.
By using the conductive layer 473 as a second gate (also referred to as a back gate), the channel formation region of the oxide semiconductor layer 430 is electrically surrounded by the conductive layers 470 and 473. The structure of such a transistor is described as a rounded channel (s-
channel) structure. As a result, the on-current can be increased. Also,
The threshold voltage can be controlled. 44(A), (B), (C), (D)
45(A), (E), (F) and FIGS. 45A, 45B, 45C, 45D, 45E, and 45F, the width of the conductive layer 473 is set to be the oxide semiconductor layer. It may be shorter than 430. Further, the width of the conductive layer 473 may be shorter than the width of the conductive layer 470.

To increase the on-state current, for example, the conductive layer 470 and the conductive layer 473 may be set to the same potential and driven as a double gate transistor. Further, in order to control the threshold voltage, a constant potential different from that of the conductive layer 470 may be supplied to the conductive layer 473. Conductive layer 470 and conductive layer 4
To make 73 the same potential, for example, as shown in FIGS. 39D and 43D, the conductive layer 470 and the conductive layer 473 may be electrically connected to each other through a contact hole.

In addition, the transistor of one embodiment of the present invention can have a structure illustrated in FIGS. 46A, 46B, and 46C. FIG. 46A is a top view. 46B is a cross-sectional view taken along dashed-dotted line N1-N2 in FIG. In addition, FIG. 46C is the same as FIG.
It is sectional drawing corresponding to the dashed-dotted line N3-N4 shown in FIG. Note that in the top view of FIG.
Some elements are omitted for clarity.

The insulating layer 420 of the transistor 413 is in contact with the substrate 415, and the oxide semiconductor layer 430 (the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c) is the insulating layer 4
20, the conductive layers 440 and 450 are in contact with the oxide semiconductor layer 430b, the insulating layer 460 is in contact with the oxide semiconductor layer 430c, the conductive layer 470 is in contact with the insulating layer 460, and the insulating layer 4
80 contacts the insulating layer 420, the conductive layer 440, and the conductive layer 450. Note that the oxide semiconductor layer 430c, the insulating layer 460, and the conductive layer 470 are provided in the insulating layer 480 and are provided in openings which reach the oxide semiconductor layer 430b.

In the structure of the transistor 413, the conductive layer 440 or the conductive layer 450 and the conductive layer 470 do not overlap with each other in a small region as compared with the structures of the other transistors described above, so that parasitic capacitance can be reduced. Therefore, the transistor 413 is suitable as an element of a circuit which needs high speed operation. Note that the top surface of the transistor 413 is shown in FIGS.
As shown in, CMP (Chemical Mechanical Polishing)
Although it is preferable to planarize by using a method or the like, it is also possible to adopt a configuration in which it is not planarized.

In addition, the conductive layers 440 and 450 in the transistor of one embodiment of the present invention are shown in FIG.
The width (W _SD ) of the conductive layer 440 and the conductive layer 450 may be longer than the width (W _OS ) of the oxide semiconductor layer as in the top view illustrated in FIG. It may be formed short as in the top view shown in FIG. In particular, when W _OS ≧W _SD (W _SD is less than or equal to W _OS ), a gate electric field is easily applied to the entire oxide semiconductor layer 430, so that electric characteristics of the transistor can be improved. Further, as shown in FIG. 47C, the conductive layers 440 and 450 may be formed only in a region overlapping with the oxide semiconductor layer 430.

Note that in FIGS. 47A, 47B, and 47C, only the oxide semiconductor layer 430, the conductive layer 440, and the conductive layer 450 are illustrated.

Further, a transistor including the oxide semiconductor layer 430a and the oxide semiconductor layer 430b, and the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c.
In the transistor including, by appropriately selecting a two-layer material or a three-layer material forming the oxide semiconductor layer 430, current can be supplied to the oxide semiconductor layer 430b. Since a current flows through the oxide semiconductor layer 430b, it is less susceptible to interface scattering and a high on-state current can be obtained. Therefore, increasing the thickness of the oxide semiconductor layer 430b might improve the on-state current.

By using the transistor having the above structure, favorable electric characteristics can be given to the semiconductor device.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 8)
In this embodiment, the components of the transistor described in Embodiment 6 will be described in detail.

The type of the substrate 415 is not limited to a particular type. Examples of the substrate 415 include a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a stainless steel substrate.
There is a substrate having a foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, paper including a fibrous material, a base film, or the like. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of the flexible substrate, the laminated film, the base film and the like include the following. For example, polyethylene terephthalate (PET)
), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, as an example, there is a synthetic resin such as acrylic resin. Alternatively, as an example, there is a film formed of polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, or the like. Or, as an example, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film,
Or there is paper etc. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with small variation in characteristics, size, shape, high current capability, or small size can be manufactured. .. When a circuit is formed using such transistors, low power consumption of the circuit or high integration of the circuit can be achieved.

As the substrate 415, a silicon substrate over which a transistor is formed and an insulating layer, a wiring, a conductor that can function as a contact plug, or the like formed over the silicon substrate can be used. When only p-ch type transistors are formed on the silicon substrate, it is preferable to use a silicon substrate having an n ⁻ type conductivity type.
Alternatively, it may be an SOI substrate having an n ⁻ type or i type silicon layer. Further, the plane direction of the surface of the silicon substrate on which the transistor is formed is preferably (110) plane. The mobility can be increased by forming a p-ch type transistor on the (110) plane.

Alternatively, a flexible substrate may be used as the substrate 415, and the transistor may be directly formed over the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the transistor. The peeling layer can be used for separating a semiconductor device over a part or the whole of the semiconductor layer, separating it from the substrate, and transferring the semiconductor device to another substrate. At that time, the transistor can be transferred to a substrate having poor heat resistance or a flexible substrate. Note that, for the above-described release layer, for example, a structure having a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or the like can be used.

That is, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate and the transistor may be arranged on another substrate. As an example of a substrate on which a transistor is transferred, in addition to a substrate on which the above transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber) (Including silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (acetate, cupra, rayon, recycled polyester, etc.), leather substrate, or rubber substrate. By using these substrates, formation of a transistor with excellent characteristics, formation of a transistor with low power consumption, manufacture of a device that is not easily broken, heat resistance imparted, weight reduction, or thickness reduction can be achieved.

The insulating layer 420 has a role of preventing diffusion of impurities from an element included in the substrate 415 and a role of supplying oxygen to the oxide semiconductor layer 430. Therefore, the insulating layer 420 is preferably an insulating layer containing oxygen, and more preferably an insulating layer containing oxygen at a higher stoichiometric composition. For example, thermal desorption gas analysis (TDS (Therm
al Desorption Spectroscopy)), the amount of released oxygen in terms of oxygen atoms is 1.0×10 ¹⁹ atoms/cm ³ or more. The surface temperature of the film during the TDS analysis is 100° C. or higher and 700° C. or lower, or 100° C.
The range of not less than 500° C. is preferable. When the substrate 415 is a substrate on which another device is formed, the insulating layer 420 also has a function as an interlayer insulating layer. In that case, it is preferable to perform a flattening treatment by a CMP method or the like so that the surface becomes flat.

For example, the insulating layer 420 includes an oxide insulating layer such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. , A nitride insulating layer such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide, or a mixed material thereof can be used. Alternatively, a stack of the above materials may be used.

Note that in this embodiment, the case where the oxide semiconductor layer 430 included in the transistor has a three-layer structure in which the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c are sequentially stacked from the insulating layer 420 side is described. The details will be mainly described.

Note that when the oxide semiconductor layer 430 is a single layer, the oxide semiconductor layer 43 described in this embodiment is used.
A layer corresponding to 0b may be used.

In the case where the oxide semiconductor layer 430 has two layers, the oxide semiconductor layer 43 described in this embodiment.
0a and a layer corresponding to the oxide semiconductor layer 430b may be stacked in this order from the insulating layer 420 side. In this structure, the oxide semiconductor layer 430a and the oxide semiconductor layer 430b can be replaced with each other.

In the case where the number of the oxide semiconductor layers 430 is four or more, another oxide semiconductor layer is added to the oxide semiconductor layer 430 having a three-layer structure described in this embodiment, for example. You can

For example, the oxide semiconductor layer 430b is formed using an oxide semiconductor whose electron affinity (energy from the vacuum level to the bottom of the conduction band) is higher than that of the oxide semiconductor layers 430a and 430c. The electron affinity can be obtained as a value obtained by subtracting the energy difference (energy gap) between the bottom of the conduction band and the top of the valence band from the energy difference (ionization potential) between the vacuum level and the top of the valence band.

The oxide semiconductor layer 430a and the oxide semiconductor layer 430c include one or more kinds of metal elements included in the oxide semiconductor layer 430b, and for example, the energy at the bottom of the conduction band is the oxide semiconductor layer 43.
It is closer to the vacuum level in the range of 0.05 eV, 0.07 eV, 0.1 eV, 0.15 eV or more than 0 b, and 2 eV, 1 eV, 0.5 eV, 0.4 eV or less. It is preferably formed using an oxide semiconductor.

In such a structure, when an electric field is applied to the conductive layer 470, a channel is formed in the oxide semiconductor layer 430b of the oxide semiconductor layer 430, which has the lowest energy at the bottom of the conduction band.

In addition, since the oxide semiconductor layer 430a includes one or more metal elements included in the oxide semiconductor layer 430b, the oxide semiconductor layer 430a is more likely to be oxidized than the interface when the oxide semiconductor layer 430b and the insulating layer 420 are in contact with each other. An interface state is less likely to be formed at the interface between the object semiconductor layer 430b and the oxide semiconductor layer 430a. Since the interface state may form a channel, the threshold voltage of the transistor may change. Therefore, by providing the oxide semiconductor layer 430a, variation in electrical characteristics such as the threshold voltage of the transistor can be reduced.
In addition, reliability of the transistor can be improved.

In addition, since the oxide semiconductor layer 430c includes one or more metal elements that form the oxide semiconductor layer 430b, an interface when the oxide semiconductor layer 430b is in contact with the gate insulating layer (insulating layer 460) is formed. In comparison, carrier scattering is less likely to occur at the interface between the oxide semiconductor layer 430b and the oxide semiconductor layer 430c. Therefore, by providing the oxide semiconductor layer 430c, the field-effect mobility of the transistor can be increased.

The oxide semiconductor layer 430a and the oxide semiconductor layer 430c include, for example, Al, Ti, and Ga.
, Ge, Y, Zr, Sn, La, Ce, or Hf with a higher atomic ratio than the oxide semiconductor layer 430b can be used. Specifically, the atomic ratio is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. Since the above element is strongly bonded to oxygen, it can have a function of suppressing generation of oxygen vacancies in the oxide semiconductor layer. That is, the oxide semiconductor layer 430a and the oxide semiconductor layer 430c are the same as the oxide semiconductor layer 43.
It can be said that oxygen deficiency is less likely to occur than 0b.

In addition, the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430.
The oxide semiconductor that can be used as c preferably contains at least In or Zn. Alternatively, it preferably contains both In and Zn. In addition, in order to reduce variation in electric characteristics of a transistor including the oxide semiconductor, it is preferable to include a stabilizer together with the oxide semiconductor.

Examples of the stabilizer include Ga, Sn, Hf, Al, Zr and the like. Other stabilizers include lanthanoids such as La, Ce, Pr, Nd, Sm, Eu and G.
There are d, Tb, Dy, Ho, Er, Tm, Yb, Lu and the like.

For example, as an oxide semiconductor, indium oxide, tin oxide, gallium oxide, zinc oxide, I
n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg
Oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-
Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxidation. Thing, In
-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-
Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxidation. Thing, In
-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn-
Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I
n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn
Oxides can be used.

Note that here, for example, an In-Ga-Zn oxide means an oxide containing In, Ga, and Zn as main components. Further, a metal element other than In, Ga and Zn may be contained. In addition, in this specification, a film formed of an In—Ga—Zn oxide is also referred to as an IGZO film.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m>0, and m is not an integer) may be used. In addition, M represents one metal element or a plurality of metal elements selected from Ga, Y, Zr, La, Ce, or Nd. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n>0, and n is an integer) may be used.

Note that the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c are
At least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La
, Ce, or a metal such as Hf), the oxide semiconductor layer 4 is an In-M-Zn oxide.
30a is In:M:Zn=x ₁ :y ₁ :z ₁ [atomic ratio], and the oxide semiconductor layer 430b is I.
_{n: M: Zn = x 2} : y 2: z 2 [ atomic ratio], the oxide semiconductor layer 430c In: M: Z
_{n = x 3: y 3:} z 3 When atomic _ratio], y ₁ / _x 1 and _y 3 / _{x 3} is _y 2 / _{x 2}
It is preferably larger than 1 than y ₁ / _{x 1} and _y 3 / _{x 3} is _{y 2} / _x 2.
It is 5 times or more, preferably 2 times or more, more preferably 3 times or more. At this time, when y ₂ is greater than or equal to x ₂ in the oxide semiconductor layer 430b, electrical characteristics of the transistor can be stable. However, when y ₂ is 3 times or more as large as x ₂ , field effect mobility of the transistor is lowered, so that y ₂ is preferably less than 3 times as large as x ₂ .

When Zn and O in the oxide semiconductor layer 430a and the oxide semiconductor layer 430c are excluded, the atomic ratio of In and M is preferably In of less than 50 atomic %.
M is higher than 50 atomic%, more preferably In is less than 25 atomic%, M
Is higher than 75 atomic %. The atomic ratio of In and M excluding Zn and O in the oxide semiconductor layer 430b is preferably In higher than 25 atomic% and M.
Is less than 75 atomic %, more preferably In is higher than 34 atomic %, and M is less than 66 atomic %.

The oxide semiconductor layer 430b is the oxide semiconductor layer 430a and the oxide semiconductor layer 430.
The content of indium may be higher than that of c. In an oxide semiconductor, the s orbital of a heavy metal mainly contributes to carrier conduction, and by increasing the In content, more s orbitals are overlapped. Therefore, an oxide having a composition of In larger than M is In Has a higher mobility than an oxide having a composition equal to or smaller than M. Therefore, by using an oxide with a high content of indium for the oxide semiconductor layer 430b, a transistor with high field-effect mobility can be realized.

The thickness of the oxide semiconductor layer 430a is 3 nm or more and 100 nm or less, preferably 5 nm or more 5
The thickness is 0 nm or less, and more preferably 5 nm or more and 25 nm or less. In addition, the oxide semiconductor layer 4
The thickness of 30b is 3 nm or more and 200 nm or less, preferably 5 nm or more and 150 nm or less, and more preferably 10 nm or more and 100 nm or less. The thickness of the oxide semiconductor layer 430c is 1 nm to 50 nm inclusive, preferably 2 nm to 30 nm inclusive, more preferably 3 nm to 15 nm inclusive. The oxide semiconductor layer 430b is the oxide semiconductor layer 43.
Thicker than 0c is preferable.

Note that in order to impart stable electric characteristics to a transistor including an oxide semiconductor layer as a channel, it is necessary to reduce the concentration of impurities in the oxide semiconductor layer and make the oxide semiconductor layer intrinsic or substantially intrinsic. It is valid. Here, “substantially intrinsic” means that the carrier density of the oxide semiconductor layer is less than 1×10 ¹⁵ /cm ^3, less than 1×10 ¹³ /cm ³ , and 8×
Less than 10 ¹¹ /cm ³ , or less than 1×10 ⁸ /cm ³ and 1×1
And it is at 0 ^-9 / cm ³ or more.

In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal element other than the main component become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity level serves as a trap and may deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the concentration of impurities in the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c, and at the interfaces between them.

In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, SIMS (Secondary)
The region where the silicon concentration estimated by y Ion Mass Spectrometry) is less than 1×10 ¹⁹ atoms/cm ³ , preferably less than 5×10 ¹⁸ atoms/cm ³ , and more preferably less than 1×10 ¹⁸ atoms/cm ^3. Control to have. Further, the hydrogen concentration is 2×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ^1.
It is controlled so as to have a region of ⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, and further preferably 5×10 ¹⁸ atoms/cm ³ or less.
The nitrogen concentration is, for example, less than 5×10 ¹⁹ atoms/cm ³ , preferably 5×10 ^{18 at} a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer.
Atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, and further preferably 5×10 ¹⁷ atoms/cm ³ or less.

Further, when silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer may be deteriorated. In order not to reduce the crystallinity of the oxide semiconductor layer, for example, the silicon concentration is set to 1×1.
It is controlled to have a region of less than 0 ¹⁹ atoms/cm ³ , preferably less than 5×10 ¹⁸ atoms/cm ³ , and more preferably less than 1×10 ¹⁸ atoms/cm ³ .
The carbon concentration is less than 1×10 ¹⁹ atoms/cm ³ , preferably 5×10 ¹⁸ atoms.
It is controlled to have a region of less than ms/cm ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ .

Further, the off-state current of the transistor including the highly purified oxide semiconductor layer in the channel formation region is extremely low. For example, if the voltage between the source and drain is 0.1V, 5
When it is set to V or about 10 V, the off current per channel width of the transistor can be reduced to several yA/μm to several zA/μm.

Note that an insulating layer containing silicon is often used as a gate insulating layer of a transistor; therefore, a region of the oxide semiconductor layer, which serves as a channel, is in contact with the gate insulating layer like the transistor of one embodiment of the present invention. It can be said that the structure which does not include is preferable. In the case where a channel is formed at the interface between the gate insulating layer and the oxide semiconductor layer, carrier scattering may occur at the interface, which leads to low field-effect mobility of the transistor. From this point of view, it can be said that it is preferable to separate the region of the oxide semiconductor layer, which serves as a channel, from the gate insulating layer.

Therefore, the oxide semiconductor layer 430 is replaced with the oxide semiconductor layer 430a and the oxide semiconductor layer 430b.
With the stacked-layer structure of the oxide semiconductor layer 430c, a channel can be formed in the oxide semiconductor layer 430b, so that a transistor having high field-effect mobility and stable electric characteristics can be formed.

In the band structure of the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c, the energy at the bottom of the conduction band continuously changes. This is the oxide semiconductor layer 4
It can also be understood from the fact that the compositions of the oxide semiconductor layer 430b, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c are similar to each other, whereby oxygen easily diffuses into each other. Therefore, the oxide semiconductor layer 430a
Although the oxide semiconductor layer 430b and the oxide semiconductor layer 430c are stacked bodies each having a different composition, it can be said that the oxide semiconductor layer 430b and the oxide semiconductor layer 430c are physically continuous, and in the drawings, each interface of the stacked body is represented by a dotted line. There is.

The oxide semiconductor layer 430 stacked with the main component in common is not a simple stack of the layers but a continuous junction (here, a U-shaped well structure in which the energy at the bottom of the conduction band continuously changes between the layers). (U Shape Well)) is formed. That is, the laminated structure is formed so that impurities that form a defect level such as a trap center and a recombination center do not exist at the interface of each layer. If impurities are mixed between the layers of the stacked oxide semiconductor layers, the continuity of energy bands is lost and carriers disappear at the interface due to trapping or recombination.

For example, In:Ga:Zn= for the oxide semiconductor layers 430a and 430c.
1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1:
An In—Ga—Zn oxide such as 9:6 (atomic ratio) can be used. In the oxide semiconductor layer 430b, In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, or 3:1:2 (atomic ratio), such as In-Ga-. Zn oxide or the like can be used.
Note that the oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430 are included.
Each of the atomic ratios of c includes a variation of ±40% of the above atomic ratio as an error.

The oxide semiconductor layer 430b in the oxide semiconductor layer 430 serves as a well and a channel is formed in the oxide semiconductor layer 430b. Note that since the energy at the bottom of the conduction band of the oxide semiconductor layer 430 is continuously changed, it can be referred to as a U-shaped well. In addition, the channel formed with such a configuration can also be referred to as a buried channel.

Further, a trap level due to impurities or defects can be formed in the vicinity of the interface between the oxide semiconductor layers 430a and 430c and an insulating layer such as a silicon oxide film. Since the oxide semiconductor layer 430a and the oxide semiconductor layer 430c are provided, the oxide semiconductor layer 43
It is possible to separate 0b from the trap level.

However, when the difference between the energy at the bottom of the conduction band of the oxide semiconductor layers 430a and 430c and the energy at the bottom of the conduction band of the oxide semiconductor layers 430b is small, the electrons in the oxide semiconductor layer 430b have the energy difference. And reach the trap level. Since the electrons are trapped by the trap level, a negative charge is generated at the interface of the insulating layer, and the threshold voltage of the transistor shifts in the positive direction.

The oxide semiconductor layer 430a, the oxide semiconductor layer 430b, and the oxide semiconductor layer 430c include
It is preferable that a crystal part is included. In particular, the use of crystals oriented in the c-axis makes it possible to impart stable electric characteristics to the transistor. Also, the crystals oriented to the c-axis are strong against distortion,
The reliability of a semiconductor device using a flexible substrate can be improved.

The conductive layer 440 acting as one of the source and the drain and the conductive layer 450 acting as the other of the source and the drain include, for example, Al, Cr, Cu, Ta, Ti, Mo,
A single layer or a stacked layer of a material selected from W, Ni, Mn, Nd, Sc, and an alloy of the metal material can be used. Typically, it is more preferable to use W, which has a high melting point, because Ti is particularly likely to bond with oxygen, and the subsequent process temperature can be relatively high. Alternatively, a stack of a low-resistance alloy such as Cu or Cu-Mn and the above material may be used. Note that the transistor 405, the transistor 406, the transistor 411, and the transistor 412.
In this case, for example, W can be used for the conductive layers 441 and 451 and a laminated film of Ti and Al can be used for the conductive layers 442 and 452.

The above material has a property of extracting oxygen from the oxide semiconductor layer. Therefore, oxygen in the oxide semiconductor layer is released in part of the region of the oxide semiconductor layer which is in contact with the above material and oxygen vacancies are formed. Due to the combination of the hydrogen deficiency contained in the film and the oxygen deficiency, the region is remarkably made n-type. Therefore, the n-type region can serve as a source or a drain of the transistor.

When W is used for the conductive layers 440 and 450, nitrogen may be doped. By doping nitrogen, the property of extracting oxygen can be appropriately weakened, and the n-type region can be prevented from expanding to the channel region. In addition, the conductive layer 440 and the conductive layer 450 are stacked with an n-type semiconductor layer and the n-type semiconductor layer and the oxide semiconductor layer are in contact with each other to prevent the n-type region from expanding to the channel region. be able to. As the n-type semiconductor layer, nitrogen-added In-Ga-Zn oxide, zinc oxide,
Indium oxide, tin oxide, indium tin oxide, or the like can be used.

The insulating layer 460 which functions as a gate insulating layer includes aluminum oxide, magnesium oxide,
Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide,
An insulating layer containing one or more of hafnium oxide and tantalum oxide can be used. Also,
The insulating layer 460 may be a stack of any of the above materials. Note that La, N, and Zr are formed on the insulating layer 460.
Etc. may be included as impurities.

In addition, an example of a stacked structure of the insulating layer 460 is described. The insulating layer 460 includes, for example, oxygen, nitrogen, silicon, hafnium, or the like. Specifically, it is preferable to contain hafnium oxide and silicon oxide or silicon oxynitride.

Hafnium oxide and aluminum oxide have higher relative permittivity than silicon oxide and silicon oxynitride. Therefore, compared with the case where silicon oxide is used, the thickness of the insulating layer 460 can be increased, so that the leakage current due to the tunnel current can be reduced. That is, a transistor with low off-state current can be realized. Further, hafnium oxide having a crystalline structure has a higher relative dielectric constant than hafnium oxide having an amorphous structure. Therefore, it is preferable to use hafnium oxide having a crystal structure in order to obtain a transistor with a low off-state current. Examples of the crystal structure include monoclinic system and cubic system. However, one embodiment of the present invention is not limited to these.

For the insulating layer 420 and the insulating layer 460 which are in contact with the oxide semiconductor layer 430, it is preferable to use a film from which the amount of released nitrogen oxide is small. When the insulating layer that releases a large amount of nitrogen oxide is in contact with the oxide semiconductor, the level density due to the nitrogen oxide might be high. The level density due to the nitrogen oxide may be formed in the energy gap of the oxide semiconductor in some cases. For the insulating layer 420 and the insulating layer 460, for example, an oxide insulating layer such as a silicon oxynitride film or an aluminum oxynitride film that releases less nitrogen oxide can be used.

Note that a silicon oxynitride film with a small amount of released nitrogen oxide is a film with a larger amount of released ammonia than the amount of released nitrogen oxide in the TDS method.
It is not less than ×10 ¹⁸ pieces/cm ^{3 and not} more than 5×10 ¹⁹ pieces/cm ³ . Note that the amount of released ammonia is an amount released by heat treatment at a surface temperature of the film of 50° C. to 650° C., preferably 50° C. to 550° C.

By using the above oxide insulating layer as the insulating layers 420 and 460, shift of the threshold voltage of the transistor can be reduced and variation in electric characteristics of the transistor can be reduced.

The conductive layer 470 acting as a gate is formed of, for example, Al, Ti, Cr, Co, Ni, Cu.
, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W can be used. Alternatively, an alloy of the above materials or a conductive nitride of the above materials may be used. Also,
It may be a stack of a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials. Typically, tungsten, a stack of tungsten and titanium nitride, a stack of tungsten and tantalum nitride, or the like can be used. In addition, low resistance Cu or C
An alloy such as u-Mn or a stack of the above material and an alloy such as Cu or Cu-Mn may be used. In this embodiment, the conductive layer 470 is formed using tantalum nitride for the conductive layer 471 and tungsten for the conductive layer 472.

As the insulating layer 475, a silicon nitride film containing hydrogen, an aluminum nitride film, or the like can be used. In the transistor 403, the transistor 404, the transistor 406, the transistor 409, the transistor 410, and the transistor 412 described in Embodiment 6, the oxide semiconductor layer 430 and the insulating layer 475 are partly in contact with each other; therefore, the insulating layer 475 contains hydrogen. By using the insulating layer, part of the oxide semiconductor layer 430 can be made n-type. In addition, the nitride insulating layer also has a function as a blocking film against moisture and the like, so that reliability of the transistor can be improved.

Alternatively, an aluminum oxide film can be used as the insulating layer 475. In particular, in the transistor 401, the transistor 402, the transistor 405, the transistor 407, the transistor 408, and the transistor 411 described in Embodiment 6, it is preferable to use an aluminum oxide film for the insulating layer 475. The aluminum oxide film has a high blocking effect of not permeating both the impurities such as hydrogen and water and oxygen. Therefore, the aluminum oxide film is used for preventing impurities such as hydrogen and moisture from entering the oxide semiconductor layer 430, preventing oxygen from being released from the oxide semiconductor layer, and insulating layer 4 during and after the manufacturing process of the transistor.
It is suitable for use as a protective film having an effect of preventing unnecessary release of oxygen from 20. Further, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer.

Further, the insulating layer 480 is preferably formed over the insulating layer 475. The insulating layer contains one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating layer can be used. Further, the insulating layer may be a stack of any of the above materials.

Here, like the insulating layer 420, the insulating layer 480 preferably contains more oxygen than the stoichiometric composition. Since oxygen released from the insulating layer 480 can be diffused into the channel formation region of the oxide semiconductor layer 430 through the insulating layer 460, oxygen vacancies formed in the channel formation region can be supplemented with oxygen. .. Therefore, stable electrical characteristics of the transistor can be obtained.

The miniaturization of transistors is essential for high integration of semiconductor devices. On the other hand, it is known that miniaturization of a transistor deteriorates electrical characteristics of the transistor. Especially, when the channel width is reduced, the on-current is reduced.

In each of the transistors 407 to 412 of one embodiment of the present invention, the oxide semiconductor layer 430c is formed so as to cover the oxide semiconductor layer 430b in which a channel is formed, and the channel formation layer and the gate insulating layer are not in contact with each other. Has become. Therefore, scattering of carriers generated at the interface between the channel formation layer and the gate insulating layer can be suppressed and the on-state current of the transistor can be increased.

In the transistor of one embodiment of the present invention, the gate (the conductive layer 470) is formed so as to electrically surround the oxide semiconductor layer 430 in the channel width direction as described above; On the other hand, in addition to the gate electric field from the vertical direction, the gate electric field from the side surface direction is applied. That is, the gate electric field is applied to the channel forming layer as a whole, and the effective channel width is expanded, so that the on-current can be further increased.

In addition, in the transistor in which the oxide semiconductor layer 430 has two or three layers in one embodiment of the present invention, the interface state is formed by forming the oxide semiconductor layer 430b in which a channel is formed over the oxide semiconductor layer 430a. It has the effect of making it difficult to do. In the transistor including the three-layer oxide semiconductor layer 430 in one embodiment of the present invention, the effect of mixing impurities from above and below can be eliminated by forming the oxide semiconductor layer 430b in the middle of the three-layer structure. And so on. Therefore, in addition to improving the on-state current of the transistor described above, it is possible to stabilize the threshold voltage and reduce the S value (subthreshold value). Therefore, the current when the gate voltage VG is 0 V can be reduced, and the power consumption can be reduced. Further, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. Further, the transistor of one embodiment of the present invention can be said to be suitable for formation of a highly integrated semiconductor device because deterioration of electrical characteristics due to miniaturization can be suppressed.

Note that various films such as a metal film, a semiconductor film, and an inorganic insulating film described in this embodiment are typically formed by a sputtering method or a plasma CVD (Chemical Vapor Deposition).
Ion) method, but may be formed by another method, for example, a thermal CVD method. Examples of the thermal CVD method include MOCVD method and ALD (Atomic Layer).
Deposition) method.

Since the thermal CVD method is a film forming method that does not use plasma, it has an advantage that defects are not generated due to plasma damage.

Further, in the thermal CVD method, a raw material gas and an oxidant are simultaneously sent into a chamber, the inside of the chamber is kept at atmospheric pressure or under reduced pressure, and the reaction is performed in the vicinity of the substrate or on the substrate to deposit the film on the substrate. Good.

In the ALD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, a source gas for reaction is introduced into the chamber and reacted, and this is repeated to form a film. Inert gas (
Argon or nitrogen) may be introduced as a carrier gas. For example, two or more kinds of source gases may be sequentially supplied to the chamber. At that time, an inert gas is introduced and a second source gas is introduced after the reaction of the first source gas so that a plurality of types of source gases are not mixed. Alternatively, instead of introducing the inert gas, the second raw material gas may be introduced after exhausting the first raw material gas by evacuation. The first source gas is adsorbed/reacted on the surface of the substrate to form a first layer, and the second source gas introduced later is adsorbed/reacted, so that the second layer is the first layer. A thin film is formed by laminating on top. By repeating the gas introduction sequence a plurality of times until the desired thickness is achieved, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction is repeated, it is possible to precisely adjust the film thickness, which is suitable for producing a fine FET.

The thermal CVD method such as the MOCVD method and the ALD method can form various films such as the metal film, the semiconductor film, and the inorganic insulating film disclosed in the above-described embodiments. For example, In-Ga
In the case of forming the -zn-O film, trimethylindium _{(In (CH 3) 3)} , trimethyl gallium _{(Ga (CH 3) 3)} , and dimethyl zinc (Zn _{(CH 3) 2)} be used it can. Not limited to these combinations, triethylgallium (Ga(C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (Zn(C ₂ H ₅ ) ₂ ) can be used instead of dimethylzinc. You can also

For example, when forming a hafnium oxide film by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide, tetrakisdimethylamide hafnium (TDMAH, Hf[N(CH ₃ ) ₂ ] ₄ ) ) Or tetrakis(ethylmethylamide) hafnium and other hafnium amides) source gas and ozone (oxidizer)
Two types of gas, O ₃ ) are used.

For example, when forming an aluminum oxide film by a film forming apparatus using ALD, a liquid containing a solvent and an aluminum precursor (trimethylaluminum (TMA, Al(CH ₃ ) ₃
), Etc.) and the raw material gas by vaporizing, using two types of gases H _{2 O} as the oxidizing agent. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), and the like.

For example, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film formation surface, and radicals of an oxidizing gas (O ₂ , nitrous oxide) are supplied to adsorb the hexachlorodisilane. React with things.

For example, in the case of forming a tungsten film by a film forming apparatus using ALD, WF ₆ gas and B ₂ H ₆ gas are sequentially introduced to form an initial tungsten film, and then WF ₆ gas and H 2
_Two gases are sequentially introduced to form a tungsten film. _{Incidentally,} SiH ₄ instead of B 2 _{H 6} gas
Gas may be used.

For example, an oxide semiconductor layer such as In-Ga-Zn-O is formed by a deposition apparatus using ALD.
When forming a film, In(CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced to form an In—O layer, and then Ga(CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced. To form a GaO layer, and then Zn(CH ₃ ) ₂ gas and O ₃ gas are sequentially introduced to form a ZnO layer. The order of these layers is not limited to this example. Using these gases, an In-Ga-O layer or In-Zn
A mixed compound layer such as an —O layer or a Ga—Zn—O layer may be formed. Incidentally, instead of the O ₃ gas may be used the H _{2 O} gas obtained by bubbling with an inert gas such as Ar, but better to use an O ₃ gas containing no H are preferred.

Note that a facing target sputtering apparatus can be used for forming the oxide semiconductor layer. The film formation method using the facing target type sputtering apparatus is performed by VDSP (vap
or position position SP).

By forming an oxide semiconductor layer using a facing target type sputtering apparatus,
Plasma damage at the time of forming the oxide semiconductor layer can be reduced. Therefore, oxygen vacancies in the film can be reduced. In addition, since film formation can be performed at low pressure by using a facing target sputtering apparatus, the concentration of impurities in the formed oxide semiconductor layer (eg, hydrogen, rare gas (argon, etc.), water, etc.) can be reduced. Can be made.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 9)
The structure of an oxide semiconductor layer that can be used in one embodiment of the present invention is described below.

In the present specification, “parallel” means a state in which two straight lines are arranged at an angle of −10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30° or more and 30° or less. In addition, “vertical” means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.

Oxide semiconductors are classified into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned) is used.
crystalline oxide semiconductor, polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor)
uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l)
ike oxide semiconductor) and an amorphous oxide semiconductor.

From another viewpoint, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. As the crystalline oxide semiconductor, a single crystal oxide semiconductor, CAAC-
OS, polycrystalline oxide semiconductor, nc-OS, and the like.

Amorphous structure is generally isotropic and does not have a heterogeneous structure, metastable state in which the arrangement of atoms is not fixed, bond angle is flexible, short-range order but long-range order It is said that they do not have

That is, a stable oxide semiconductor is completely amorphous.
) It cannot be called an oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (eg, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. On the other hand, a-li
The ke OS is not isotropic but has an unstable structure having a void (also referred to as a void).
The a-like OS is physically similar to an amorphous oxide semiconductor in that it is unstable.

First, the CAAC-OS will be described.

The CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when the CAAC-OS including InGaZnO ₄ crystals classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) is obtained as illustrated in FIG. Shows a peak near 31°. Since this peak is assigned to the (009) plane of the InGaZnO ₄ crystal, in the CAAC-OS, the crystal has c-axis orientation and the c-axis is a plane which forms a film of the CAAC-OS (formation target). It is also confirmed that it is oriented in a direction substantially perpendicular to the upper surface). Note that 2θ is 31°
In addition to the peak in the vicinity, a peak may appear near 2θ of 36°. The peak near 2θ of 36° is due to the crystal structure classified into the space group Fd-3m. Therefore, CAAC
-OS preferably does not exhibit the peak.

On the other hand, with respect to the CAAC-OS, X-rays are made incident on the CAAC-OS in a direction parallel to the formation surface.
When structural analysis is performed by the ne method, a peak appears at 2θ of around 56°. This peak is I
It is assigned to the (110) plane of the crystal of nGaZnO ₄ . Then, even if 2θ is fixed to around 56° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), it is clear as shown in FIG. No peak appears. On the other hand, single crystal InGaZ
When 2θ is fixed to 56° in the vicinity of nO ₄ and a φ scan is performed, as shown in FIG. 48C, six peaks attributed to a crystal plane equivalent to the (110) plane are observed. Therefore, X
From the structural analysis using RD, it can be confirmed that the CAAC-OS has irregular a-axis and b-axis orientations.

Next, the CAAC-OS analyzed by electron diffraction will be described. For example, InGaZ
When an electron beam with a probe diameter of 300 nm is incident on the CAAC-OS having nO ₄ crystals in parallel to the surface where the CAAC-OS is formed, a diffraction pattern (selected area electron diffraction) shown in FIG. (Also referred to as a pattern) may appear. In this diffraction pattern, In
A spot due to the (009) plane of the GaZnO ₄ crystal is included. Therefore, electron diffraction also shows that the pellets included in the CAAC-OS have c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 48E shows a diffraction pattern of the same sample when an electron beam having a probe diameter of 300 nm was made incident perpendicular to the sample surface.
Shown in. From FIG. 48E, a ring-shaped diffraction pattern is confirmed. Therefore, it is found that the a-axis and the b-axis of the pellet included in the CAAC-OS do not have orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 48E is considered to be derived from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. The second ring in FIG. 48E is considered to be derived from the (110) plane and the like.

In addition, a transmission electron microscope (TEM) is used.
A plurality of pellets can be confirmed by observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of the CAAC-OS with a microscope. On the other hand, even in a high-resolution TEM image, a boundary between pellets, that is, a grain boundary (also referred to as a grain boundary) may not be clearly confirmed in some cases. Therefore, CAAC
It can be said that -OS is unlikely to cause a decrease in electron mobility due to the grain boundaries.

FIG. 49A shows a high resolution T of the cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface.
An EM image is shown. For observation of high resolution TEM images, spherical aberration correction (Spherical Ab
The error correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high resolution TEM image is
For example, it can be observed with an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

From FIG. 49A, a pellet which is a region where metal atoms are arranged in layers can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be called a nanocrystal (nc). In addition, the CAAC-OS is replaced by the CANC (C-Axis Aligned Nan).
The oxide semiconductor can also be referred to as an oxide semiconductor. Pellets are CAAC
-OS reflects unevenness on the formation surface or the top surface, and is parallel to the formation surface or the top surface of the CAAC-OS.

Further, in FIGS. 49B and 49C, CAAC observed from a direction substantially perpendicular to the sample surface.
-Shows a Cs-corrected high resolution TEM image of the OS plane. 49D and 49E,
49(B) and FIG. 49(C) are image-processed images, respectively. The method of image processing will be described below. First, the fast Fourier transform (FFT: Fast) of FIG.
An FFT image is acquired by performing a Fourier Transform. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT:
Inverse Fast Fourier Transform) processing is performed to obtain the image-processed image. The image thus obtained is called an FFT filtered image. The FFT filtered image is an image obtained by extracting the periodic component from the Cs-corrected high resolution TEM image, and shows a lattice arrangement.

In FIG. 49(D), the places where the lattice arrangement is disturbed are indicated by broken lines. The area surrounded by the broken line
It is one pellet. And the part shown by the broken line is the connecting portion between the pellets. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. The shape of the pellet is not limited to the regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 49E, a dotted line indicates a portion where the orientation of the lattice arrangement is changed between the area where the lattice arrangement is aligned and another area where the lattice arrangement is aligned. It is indicated by a broken line. Even in the vicinity of the dotted line, no clear grain boundary can be confirmed. By connecting surrounding grid points around a grid point near the dotted line, a distorted hexagon, pentagon, and/or heptagon can be formed. That is, it is understood that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS has a non-dense atomic arrangement in the ab plane direction,
It is considered that strain can be tolerated because the bond distance between atoms changes due to the substitution with the metal element.

As described above, the CAAC-OS has a c-axis orientation and has a strained crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction. Therefore, CA
AC-OS, CAA crystal (c-axis-aligned a-b-pl.
It can also be referred to as an an-anchored crystal).

CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated due to entry of impurities, generation of defects, or the like, the CAAC-OS includes impurities and defects (
It can also be said to be an oxide semiconductor with little oxygen deficiency.

Note that the impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon which has a stronger bonding force with oxygen than a metal element forming the oxide semiconductor deprives the oxide semiconductor of oxygen, which disturbs the atomic arrangement of the oxide semiconductor and reduces crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or a molecular radius), which disturbs the atomic arrangement of the oxide semiconductor and causes deterioration of crystallinity.

Next, the nc-OS will be described.

A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by the out-of-plane method, no peak showing orientation is observed. That is, the nc-OS crystal has no orientation.

In addition, for example, nc-OS having a crystal of InGaZnO ₄ is thinned to have a thickness of 34 nm.
When an electron beam with a probe diameter of 50 nm is made incident on the region of FIG.
A ring-shaped diffraction pattern (nano-beam electron diffraction pattern) as shown in (A) is observed. A diffraction pattern (nano-beam electron diffraction pattern) when an electron beam with a probe diameter of 1 nm is incident on the same sample is shown in FIG. From FIG. 50B, a plurality of spots are observed in the ring-shaped region. Therefore, in the nc-OS, ordering is not confirmed when an electron beam having a probe diameter of 50 nm is incident, but ordering is confirmed when an electron beam having a probe diameter of 1 nm is incident.

Further, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm,
As shown in FIG. 50C, an electron diffraction pattern in which spots are arranged in a substantially regular hexagon may be observed. Therefore, it is found that the nc-OS has a highly ordered region, that is, a crystal in the thickness range of less than 10 nm. In addition, since the crystals are oriented in various directions, there are regions where a regular electron diffraction pattern is not observed.

FIG. 50D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. In the high-resolution TEM image, the nc-OS has a region where crystal parts can be confirmed, such as a portion indicated by an auxiliary line, and a region where clear crystal parts cannot be confirmed. The crystal part included in the nc-OS has a size of 1 nm to 10 nm, in particular, a size of 1 nm to 3 nm in many cases. The size of the crystal part is 1
An oxide semiconductor having a size of greater than 0 nm and less than or equal to 100 nm is a microcrystalline oxide semiconductor (micro
It may be referred to as a crystalline oxide semiconductor). In the nc-OS, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed in some cases. Note that nanocrystals may have the same origin as pellets in CAAC-OS. Therefore, the crystal part of nc-OS may be called a pellet below.

As described above, the nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, in particular, a region of 1 nm to 3 nm). Further, in the nc-OS, no regularity is found in the crystal orientation between different pellets. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.

Since the crystal orientation between the pellets (nanocrystals) has no regularity, nc-OS is
It can also be referred to as an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide semiconductor having NANC (Non-Aligned nanocrystals).

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. for that reason,
The defect level density of the nc-OS is lower than that of the a-like OS or the amorphous oxide semiconductor. However, in the nc-OS, no regularity is found in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.

FIG. 51 shows a high-resolution cross-sectional TEM image of a-like OS. Here, FIG. 51A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. Figure 51 (B
) Is a high-resolution cross-sectional TEM image of a-like OS after irradiation with electrons (e ⁻ ) at 4.3×10 ⁸ e ⁻ /nm ² . From FIG. 51(A) and FIG. 51(B), the a-like OS
It can be seen that a striped bright region extending in the longitudinal direction is observed from the start of electron irradiation. Also, it is found that the shape of the bright region changes after the electron irradiation. The bright region is presumed to be a void or a low density region.

The a-like OS has an unstable structure because it has a void. In the following, a-like
Since the OS has a more unstable structure than the CAAC-OS and the nc-OS, a structure change due to electron irradiation is shown.

As samples, a-like OS, nc-OS and CAAC-OS are prepared. All the samples are In-Ga-Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. From the high-resolution cross-sectional TEM image, each sample has a crystal part.

Note that the unit cell of the InGaZnO ₄ crystal has three In—O layers and also has a Ga—Zn—
It is known that a total of 9 layers having 6 O layers are layered in the c-axis direction. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as the d value) of the (009) plane, and the value is determined to be 0.29 nm from the crystal structure analysis. Therefore, in the following, the portion where the lattice fringe spacing is 0.28 nm or more and 0.30 nm or less is referred to as InGaZn.
It was regarded as a crystal part of O ₄ . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 52 is an example in which the average size of the crystal parts (22 to 30 points) of each sample was investigated. The length of the above-mentioned lattice fringes is the size of the crystal part. From FIG. 52, a-like
It can be seen that the crystal part of the OS becomes larger according to the cumulative irradiation amount of electrons related to the acquisition of the TEM image. As shown in FIG. 52, the crystal part (also referred to as an initial nucleus), which had a size of about 1.2 nm in the initial observation with TEM, had an accumulated irradiation dose of electrons (e ⁻ ) of 4.2×10 ⁸ e ^−.
It can be seen that the film has grown to a size of about 1.9 nm at /nm ² . On the other hand, nc
-OS and CAAC-OS have a cumulative electron irradiation amount of 4.2×10 ⁸ from the start of electron irradiation.
It can be seen that there is no change in the size of the crystal part in the range up to e ⁻ /nm ² . From FIG. 52, the size of the crystal part of the nc-OS and the CAAC-OS is
It can be seen that they are about 1.3 nm and about 1.8 nm, respectively. For electron beam irradiation and TEM observation, a Hitachi Transmission Electron Microscope H-9000NAR was used. The electron beam irradiation conditions were such that the acceleration voltage was 300 kV, the current density was 6.7×10 ⁵ e ⁻ /(nm ² ·s), and the diameter of the irradiation region was 230 nm.

As described above, in the a-like OS, crystal growth may be observed by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, almost no crystal part growth due to electron irradiation is observed. That is, the a-like OS is
It can be seen that the structure is unstable.

Further, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal having the same composition. Also, the density of nc-OS and CAAC
The density of -OS is 92.3% or more and less than 100% of the density of a single crystal having the same composition. It is difficult to form an oxide semiconductor having a single crystal density of less than 78%.

For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g/cm ³ . Therefore, for example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of a-like OS is 5.0 g/cm ³ or more and less than 5.9 g/cm ^3. .. In addition, for example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio],
nc-OS Density Density and CAAC-OS of 5.9 g / cm ³ or more 6.3 g / cm ³
Is less than.

When single crystals having the same composition do not exist, the density corresponding to the single crystal having the desired composition can be estimated by combining the single crystals having different compositions at an arbitrary ratio. The density corresponding to a single crystal having a desired composition is relative to the ratio of combining single crystals having different compositions,
It may be estimated using a weighted average. However, it is preferable to estimate the density by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and have various characteristics. Note that the oxide semiconductor is, for example, an amorphous oxide semiconductor, a-like OS, nc-OS,
A stacked film including two or more kinds of CAAC-OS may be used.

Next, the carrier density of the oxide semiconductor will be described below.

Factors that affect the carrier density of an oxide semiconductor include oxygen vacancies in the oxide semiconductor (
Vo), impurities in the oxide semiconductor, or the like.

When the number of oxygen vacancies in the oxide semiconductor is large, the density of defect states is high when hydrogen is bonded to the oxygen vacancies (this state is also referred to as VoH). Alternatively, when the amount of impurities in the oxide semiconductor is large, the density of defect states is high due to the impurities. Therefore, the carrier density of the oxide semiconductor can be controlled by controlling the density of defect states in the oxide semiconductor.

Here, consider a transistor including an oxide semiconductor in a channel region.

For the purpose of suppressing the negative shift of the threshold voltage of the transistor or reducing the off-state current of the transistor, it is preferable to lower the carrier density of the oxide semiconductor. In the case of reducing the carrier density of the oxide semiconductor, the concentration of impurities in the oxide semiconductor may be lowered and the density of defect states may be lowered. In this specification and the like, low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. The carrier density of a high-purity intrinsic oxide semiconductor is less than 8×10 ¹⁵ cm ⁻³ , preferably 1×10 ¹¹
less than cm ⁻³ , more preferably less than 1×10 ¹⁰ cm ⁻³ , and 1×10 ⁻⁹ cm ^−.
It may be ³ or more.

On the other hand, when the purpose is to improve the on-current of the transistor or the field-effect mobility of the transistor, it is preferable to increase the carrier density of the oxide semiconductor. In the case of increasing the carrier density of the oxide semiconductor, the impurity concentration of the oxide semiconductor may be slightly increased or the defect level density of the oxide semiconductor may be slightly increased. Alternatively, the band gap of the oxide semiconductor may be smaller. For example, the transistor Id-Vg
An oxide semiconductor in which the impurity concentration is slightly higher or the defect level density is slightly higher in a range where the on/off ratio of characteristics can be taken can be regarded as substantially intrinsic. Further, an oxide semiconductor in which the electron affinity is high and the band gap is reduced accordingly, and as a result, the density of thermally excited electrons (carriers) is increased can be regarded as substantially intrinsic. Note that when an oxide semiconductor having a higher electron affinity is used, the threshold voltage of the transistor becomes lower.

The above oxide semiconductor with an increased carrier density is slightly n-type. Therefore, the oxide semiconductor with an increased carrier density may be referred to as “Slightly-n”.

The carrier density of the substantially intrinsic oxide semiconductor is 1×10 ⁵ cm ⁻³ or more and 1×10 ¹⁸ c.
It is preferably less than m ^−3, more preferably 1×10 ⁷ cm ⁻³ or more and 1×10 ¹⁷ cm ⁻³ or less, still more preferably 1×10 ⁹ cm ⁻³ or more and 5×10 ¹⁶ cm ⁻³ or less, 1×10 3. ¹⁰
cm ⁻³ or more and 1×10 ¹⁶ cm ⁻³ or less are more preferable, and 1×10 ¹¹ cm ⁻³ or more 1.
×10 ¹⁵ cm ⁻³ or less is more preferable.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 10)
<CAC configuration>
Hereinafter, a CAC (Cloud Aligned) that can be used in one embodiment of the present invention will be described.
Complementary) The configuration of the OS will be described.

CAC is, for example, a structure of a material in which an element included in an oxide semiconductor is unevenly distributed at a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or a size in the vicinity thereof. Note that in the following, in the oxide semiconductor, one or more metal elements are unevenly distributed and the region containing the metal element is 0.5 nm to 10 nm inclusive, preferably 1 nm to 2 nm inclusive.
A state of being mixed in a size of not more than nm or in the vicinity thereof is also called a mosaic shape or a patch shape.

For example, CAC-IGZ in In-Ga-Zn oxide (hereinafter also referred to as IGZO).
O is indium oxide (hereinafter, InO _X1 (X1 is a real number larger than 0).)
Or indium zinc oxide (hereinafter, In _X2 Zn _Y2 O _Z2 (X2, Y2, and Z
2 is a real number larger than 0). ) And gallium oxide (hereinafter GaO _X3 (X3 is 0
Greater than the real number). ), or gallium zinc oxide (hereinafter, Ga _X4 Zn _Y4 O
Let _Z4 (X4, Y4, and Z4 are real numbers greater than 0). ) And the like, the material is separated into a mosaic shape, and the mosaic InO _X1 or In _X2 Zn _Y2 O _Z2
Is a structure uniformly distributed in the film (hereinafter, also referred to as a cloud shape).

That is, CAC-IGZO has a region containing GaO _X3 as a main component and In _X2 Zn _Y2 O _Z.
2 or a region containing InO _X1 as a main component is a mixed oxide semiconductor having a mixed structure. In the present specification, for example, the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the region of No. 2.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number), or In _{(
1 + x0) Ga (1-} x0) O 3 (ZnO) m0 (-1 ≦ x0 ≦ 1, m0 can be mentioned crystalline compound represented by any number).

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. In addition,
The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals has c-axis orientation and is connected without being oriented in the ab plane.

On the other hand, CAC relates to material composition. CAC is, in a material structure containing In, Ga, Zn, and O, a partly observed region in the form of nanoparticles containing Ga as a main component, and a part of In.
A region in which nanoparticles are contained as a main component and are observed in the form of nanoparticles is randomly dispersed in a mosaic pattern. Therefore, in CAC, the crystal structure is a secondary factor.

Note that CAC does not include a laminated structure of two or more kinds of films having different compositions. For example, a structure having two layers of a film containing In as a main component and a film containing Ga as a main component is not included.

Note that a clear boundary may not be observed between the region containing GaO _X3 as a main component and the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component.

<Analysis of CAC-IGZO>
Next, the results of measuring the oxide semiconductor formed on the substrate by using various measuring methods will be described.

≪Sample structure and preparation method≫
Hereinafter, nine samples according to one embodiment of the present invention will be described. Each sample is manufactured under the condition that the substrate temperature and the oxygen gas flow rate ratio when forming the oxide semiconductor are different. Note that the sample has a structure including a substrate and an oxide semiconductor over the substrate.

The method for producing each sample will be described.

First, a glass substrate is used as the substrate. Then, a 100-nm-thick In-Ga-Zn oxide is formed as an oxide semiconductor on a glass substrate using a sputtering device. The film forming conditions were such that the pressure in the chamber was 0.6 Pa, and the target was an oxide target (
In:Ga:Zn=4:2:4.1 [atomic ratio]) is used. Also, 2500 W of AC power is supplied to the oxide target installed in the sputtering apparatus.

As a condition for forming the oxide film, the substrate temperature is set to a temperature at which heating is not intentionally performed (hereinafter,
R. T. Also called. ), 130° C., or 170° C. Further, nine samples are prepared by setting the flow rate ratio of oxygen gas to the mixed gas of Ar and oxygen (hereinafter, also referred to as oxygen gas flow rate ratio) to 10%, 30%, or 100%.

<<Analysis by X-ray diffraction>>
In this item, X-ray diffraction (XRD: X-ray diffratio) was applied to nine samples.
n) The result of the measurement will be described. As an XRD device, D manufactured by Bruker
8 ADVANCE was used. Further, the condition is θ/2 by the Out-of-plane method.
In the θ scan, the scanning range is 15 deg. To 50 deg. , Step width 0.02de
g. , The scanning speed is 3.0 deg. /Min.

FIG. 58 shows the result of measurement of the XRD spectrum using the Out-of-plane method.
58, the upper part shows the measurement result of the sample whose substrate temperature condition at the time of film formation is 170° C., the middle part shows the measurement result of the sample whose substrate temperature condition at the time of film formation is 130° C., the lower part shows the time of film formation. The substrate temperature condition of R. T. The measurement results of the sample are shown. Further, the left column shows the measurement results of the sample having the oxygen gas flow rate ratio of 10%, and the center column shows the oxygen gas flow rate ratio of 3%.
The measurement result for the 0% sample and the measurement result for the sample with the oxygen gas flow rate ratio of 100% are shown in the right column.

In the XRD spectrum shown in FIG. 58, the peak intensity near 2θ=31° is increased by increasing the substrate temperature during film formation or increasing the ratio of the oxygen gas flow rate ratio during film formation. Note that the peak near 2θ=31° is a crystalline IGZO compound (CAAC (c-axis aligned crystal) oriented in the c-axis with respect to the direction substantially perpendicular to the formation surface or the upper surface.
ine)-also referred to as IGZO. ) Is known to be derived from.

In the XRD spectrum shown in FIG. 58, a clearer peak did not appear as the substrate temperature during film formation was lower or the oxygen gas flow rate ratio was smaller. Therefore, it can be seen that the samples having a low substrate temperature during film formation or a small oxygen gas flow rate ratio do not show orientation in the ab plane direction and the c-axis direction of the measurement region.

<<Analysis by electron microscope>>
In this item, the substrate temperature R. T. , And a sample prepared at an oxygen gas flow rate ratio of 10%, HAADF (High-Angle Annular Dark Field)-ST
EM (Scanning Transmission Electron Micros)
The result of observation and analysis by the following (hereinafter, HAADF-S will be described.
The image acquired by TEM is also called a TEM image. ).

The results of image analysis of a planar image (hereinafter, also referred to as a planar TEM image) and a sectional image (hereinafter, also referred to as a sectional TEM image) acquired by HAADF-STEM will be described.
The TEM image was observed using the spherical aberration correction function. The HAADF-STEM image was photographed by using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. and irradiating an electron beam with an acceleration voltage of 200 kV and a beam diameter of about 0.1 nmφ.

FIG. 59A shows the substrate temperature R.V. T. And a plane TEM image of a sample manufactured at an oxygen gas flow rate ratio of 10%. FIG. 59B shows the substrate temperature R.V. T. And a cross-sectional TEM image of a sample manufactured at an oxygen gas flow rate ratio of 10%.

<<Analysis of electron diffraction pattern>>
In this item, the substrate temperature R. T. , And the sample prepared at an oxygen gas flow rate ratio of 10% are irradiated with an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam), and a result of acquiring an electron beam diffraction pattern will be described.

As shown in FIG. 59A, the substrate temperature R. T. , And in a plane TEM image of a sample manufactured at an oxygen gas flow rate ratio of 10%, electron beam diffraction patterns indicated by black dots a1, black dots a2, black dots a3, black dots a4, and black dots a5 are observed. The electron beam diffraction pattern is observed while irradiating the electron beam while moving from the position of 0 seconds to the position of 35 seconds at a constant speed. The result of black dot a1 is shown in FIG. 59(C), the result of black dot a2 is shown in FIG. 59(D), and the result of black dot a3 is shown in FIG.
E), the result of black dot a4 is shown in FIG. 59(F), and the result of black dot a5 is shown in FIG. 59(G).

From FIG. 59(C), FIG. 59(D), FIG. 59(E), FIG. 59(F), and FIG. 59(G),
Regions with high brightness can be observed like a circle (in a ring). Moreover, a plurality of spots can be observed in the ring-shaped region.

In addition, as shown in FIG. 59B, the substrate temperature R. T. , And an electron diffraction pattern shown by black dots b1, black dots b2, black dots b3, black dots b4, and black dots b5 in a cross-sectional TEM image of a sample manufactured at an oxygen gas flow rate ratio of 10%. The result of black point b1 is shown in FIG. 59(H), the result of black point b2 is shown in FIG. 59(I), the result of black point b3 is shown in FIG. 59(J), and the result of black point b4 is shown in FIG.
K) and the result of black dot b5 are shown in FIG. 59(L).

From FIG. 59(H), FIG. 59(I), FIG. 59(J), FIG. 59(K), and FIG. 59(L),
A ring-shaped area of high brightness can be observed. Moreover, a plurality of spots can be observed in the ring-shaped region.

Here, for example, to CAAC-OS having a crystal InGaZnO _4, the probe diameter parallel to the sample surface is caused to enter the electron beam 300 nm, of InGaZnO ₄ of crystals (009
) A diffraction pattern containing a spot due to the surface is seen. That is, it is found that the CAAC-OS has c-axis orientation and the c-axis faces a direction substantially perpendicular to the formation surface or the top surface. On the other hand, when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface, a ring-shaped diffraction pattern is confirmed. That is, the CAAC-OS has the a-axis and the b-axis.
It can be seen that the axis has no orientation.

In addition, an oxide semiconductor having nanocrystals (nano crystalline oxide)
semiductor. Hereinafter referred to as nc-OS. ), a large probe diameter (
When electron beam diffraction using an electron beam of, for example, 50 nm or more) is performed, a diffraction pattern such as a halo pattern is observed. In addition, when the nc-OS is subjected to nanobeam electron diffraction using an electron beam with a small probe diameter (for example, less than 50 nm), bright spots (spots) are observed. In addition, when nanobeam electron diffraction is performed on the nc-OS, a region with high luminance may be observed like a circle (in a ring shape). Furthermore, a plurality of bright spots may be observed in the ring-shaped region.

Substrate temperature R. T. , And the electron beam diffraction pattern of the sample manufactured at an oxygen gas flow rate ratio of 10% have a ring-shaped region of high brightness and a plurality of bright points in the ring region. Therefore,
Substrate temperature R. T. , And the sample produced with the oxygen gas flow rate ratio of 10% have an electron beam diffraction pattern of nc-OS and have no orientation in the plane direction and the cross-sectional direction.

From the above, the oxide semiconductor having a low substrate temperature during film formation or a small oxygen gas flow rate ratio,
It can be inferred that the oxide semiconductor film having an amorphous structure and the oxide semiconductor film having a single crystal structure have clearly different properties.

<< Elemental analysis >>
In this item, energy dispersive X-ray spectroscopy (EDX: Energy Dispersive) is used.
e X-ray spectroscopy), the EDX mapping is acquired and evaluated to determine the substrate temperature R. T. , And the results of elemental analysis of the sample prepared at an oxygen gas flow rate ratio of 10% will be described. For the EDX measurement, an energy dispersive X-ray analyzer JED-2300T manufactured by JEOL Ltd. is used as an elemental analyzer. A Si drift detector is used to detect the X-rays emitted from the sample.

In the EDX measurement, each point in the analysis target region of the sample is irradiated with an electron beam, the energy of the characteristic X-ray of the sample generated thereby and the number of times of generation are measured, and the EDX spectrum corresponding to each point is obtained. In the present embodiment, the peaks of the EDX spectrum at each point are represented by the electronic transition of the In atom to the L shell, the Ga atom to the K shell, the Zn atom to the K shell, and the O atom to the K shell. Then, the ratio of each atom at each point is calculated. By performing this for the analysis target region of the sample, EDX mapping showing the distribution of the ratio of each atom can be obtained.

In FIG. 60, the substrate temperature R. T. , And EDX mapping in the cross section of the sample produced with the oxygen gas flow rate ratio of 10%. FIG. 60A shows EDX mapping of Ga atom (
The ratio of Ga atoms to all atoms is 1.18 to 18.64 [atomic %]. ). FIG. 60B is EDX mapping of In atoms (the ratio of In atoms to all atoms is in the range of 9.28 to 33.74 [atomic %]). Fig. 60 (
C) is EDX mapping of Zn atoms (the ratio of Zn atoms to all atoms is 6.69 to 2).
The range is 4.99 [atomic %]. ). Further, FIG. 60(A) and FIG. 60(B
), and FIG. 60C show the substrate temperature R. T. , And the cross-section of the sample manufactured with the oxygen gas flow rate ratio of 10%, the region of the same range is shown. EDX mapping is
In the range, the more measurement elements there are, the brighter it becomes, and the fewer measurement elements, the darker it becomes,
The ratio of elements is shown in light and dark. The EDX mapping magnification shown in FIG. 60 is 7.2 million times.

In the EDX mapping shown in FIGS. 60(A), 60(B), and 60(C), a relative brightness distribution is seen in the image, and the substrate temperature R. T. , And oxygen gas flow rate ratio 10%
It can be confirmed that each atom exists in a distribution in the sample prepared in. Here, attention is paid to the range surrounded by the solid line and the range surrounded by the broken line shown in FIGS. 60A, 60B, and 60C.

In FIG. 60A, the range surrounded by the solid line includes many relatively dark regions, and the range surrounded by the broken line includes many relatively bright regions. Further, in FIG. 60B, the range surrounded by the solid line includes many relatively bright regions, and the range surrounded by the broken line includes many relatively dark regions.

That is, the range surrounded by the solid line is a region having a relatively large amount of In atoms, and the range surrounded by a broken line is a region having a relatively small amount of In atoms. Here, in FIG. 60C, in a range surrounded by a solid line,
The right side is a relatively bright area and the left side is a relatively dark area. Therefore, the range surrounded by the solid line is a region whose main component is In _X2 Zn _Y2 O _Z2 or InO _X1 .

The range surrounded by the solid line is a region where the Ga atoms are relatively small, and the range surrounded by the broken line is a region where the Ga atoms are relatively large. In FIG. 60C, the upper left region is a relatively bright region and the lower right region is a relatively dark region in the range surrounded by the broken line. Therefore, the range surrounded by a broken line is a region whose main component is GaO _X3 , Ga _X4 Zn _Y4 O _Z4 , or the like.

From FIGS. 60A, 60B, and 60C, the distribution of In atoms is Ga.
The region in which InO _X1 is the main component, which is relatively uniformly distributed as compared with the atoms, is In _X2
It seems that they are formed so as to be connected to each other through the region where Zn _Y2 O _Z2 is the main component. As described above, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is formed to spread in a cloud shape.

As described above, a region containing GaO _X3 as a main component, In _X2 Zn _Y2 O _Z2 , or InO
_The In-Ga-Zn oxide having a structure in which the region where _X1 is a main component is unevenly distributed and mixed can be referred to as CAC-IGZO.

The crystal structure of CAC has an nc structure. In the electron diffraction image, the nc structure of CAC has several or more bright spots (spots) in addition to the bright spots (spots) caused by IGZO containing a single crystal, a polycrystal, or a CAAC structure. Alternatively, the crystal structure is defined as a ring-shaped region of high brightness in addition to several bright spots.

From FIGS. 60A, 60B, and 60C, the size of a region containing GaO _X3 as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component Is observed at 0.5 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less. In the EDX mapping, the diameter of the region containing each metal element as a main component is preferably 1 nm or more and 2 nm or less.

From the above, CAC-IGZO has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, CAC-IGZO is GaO
_A region having _X3 or the like as a main component and a region having In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are phase-separated from each other, and a region having each element as a main component has a mosaic structure. .. Therefore, when CAC-IGZO is used for a semiconductor element, a property due to GaO _X3 or the like and a property due to In _X2 Zn _Y2 O _Z2 or InO _X1 act in a complementary manner so that a high on-state current is obtained. (I _on ) and high field effect mobility (μ) can be realized.

Further, a semiconductor element using CAC-IGZO has high reliability. Therefore, CAC-IGZ
O is most suitable for various semiconductor devices such as displays.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments or other examples described in this specification.

(Embodiment 11)
In this embodiment mode, an example of a package and a module each accommodating an image sensor chip will be described. The structure of the imaging device of one embodiment of the present invention can be used for the image sensor chip.

FIG. 53A is an external perspective view of the upper surface side of the package containing the image sensor chip. The package has a package substrate 810 for fixing the image sensor chip 850, a cover glass 820, an adhesive 830 for bonding the both, and the like.

FIG. 53B is an external perspective view of the lower surface side of the package. On the bottom of the package,
It has a BGA (Ball grid array) configuration in which solder balls are used as the bumps 840. Not only BGA but also LGA (Land grid array) and PGA (P
in Grid Array) or the like.

53C is a perspective view of the package in which the cover glass 820 and the adhesive 830 are partially omitted, and FIG. 53D is a cross-sectional view of the package. Electrode pads 860 are formed on the package substrate 810, and the electrode pads 860 and the bumps 840 are electrically connected through the through holes 880 and the lands 885. Electrode pad 860
Are electrically connected to the electrodes of the image sensor chip 850 by wires 870.

Also, FIG. 54A is an external perspective view of the upper surface side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 811, which fixes an image sensor chip 851, a lens cover 821, and a lens 835.
And so on. Further, an IC chip 890 having a function such as a driving circuit and a signal conversion circuit of an imaging device is provided between the package substrate 811 and the image sensor chip 851, and has a structure as a SiP (System in package). There is.

FIG. 54B is an external perspective view of the lower surface side of the camera module. Package board 8
Mounting lands 841 are provided on the lower surface and four side surfaces of the QFN (Quad f).
lat no-lead package). In addition, the said structure is an example and QFP(Quad flat package), the above-mentioned BGA, etc. may be used.

54C is a perspective view of the module without the lens cover 821 and the lens 835, and FIG. 54D is a cross-sectional view of the camera module. Land 8
Part of 41 is used as an electrode pad 861, and the electrode pad 861 is electrically connected to the electrodes of the image sensor chip 851 and the IC chip 890 by a wire 871.

By mounting the image sensor chip in the package having the above-described form, mounting becomes easy, and the image sensor chip can be incorporated in various semiconductor devices and electronic devices.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 12)
In the present embodiment, a case will be described in which the imaging device 10 described in the first embodiment is used as a monitoring device.

FIG. 55 is a block diagram showing a configuration example of the monitoring device according to the present embodiment. The monitoring device has a camera 600, a storage device 24, and a display device 23. The camera 600 includes the imaging device 10 which is an imaging device according to one embodiment of the present invention. Camera 600, storage device 24 and display device 2
3 are functionally connected to each other. The image captured by the camera 600 is recorded in the storage device 24 and displayed on the display device 23.

The camera 600 outputs the imaging data captured by the imaging device 10 to the storage device 24 and the display device 23 only when the difference between the reference frame and the difference detection frame is detected. Therefore, the frequency of outputting the imaged data to the storage device 24 and the display device 23 can be reduced as compared with the case where the difference detection is not performed, and thus the power consumption of the storage device 24 and the display device 23 can be reduced. In addition, the storage capacity of the storage device 24 can be saved,
Not only will it be possible to capture images for a longer time, but it will also be possible to easily retrieve the necessary data from the stored data.

Further, in the image pickup device 10, a huge power consumption process such as A/D conversion may be performed only when the image pickup data to be output to the storage device 24 and the display device 23 is acquired.
Therefore, power consumption can be reduced as compared with the case where the difference detection is not performed or the difference detection is performed using the data after A/D conversion.

The monitoring device according to the present embodiment can output the imaging data to the storage device 24 and the display device 23, for example, only when an event in which a traffic accident is likely to occur is detected. FIG. 56 shows T
An image displayed on the display device 23 when the camera 600 is installed above the path is shown. At the T-shaped road, it is assumed that the accident rate of the vehicle turning right is high and the accident rate of the vehicle going straight is low. In this case, when the difference between the reference frame and the difference detection frame described above in the first embodiment is detected in the vicinity of the T-junction where the accident rate is high, new imaging data is acquired and output to an external device. By setting the area 41, when the vehicle passes near the T-shaped road, the imaging data is stored in the storage device 2.
4 and the display device 23. On the other hand, even if the vehicle passes through a straight line area having a low accident rate, such as the area 43, the imaging data is not output to the storage device 24 and the display device 23. That is, it is possible to store the imaging data in the storage device 24 and update the image displayed on the display device 23 only when the vehicle passes through a place where the accident rate is high. As a result, the power consumption and the storage capacity of the storage device 24 can be reduced. Further, when an accident occurs in the area 41, the image at the time of the accident can be easily searched.

If the reference frame is not updated, it is considered that the difference is detected even if the vehicle does not pass through the area 41, for example, the brightness changes with the passage of time, and the imaging data is stored in the storage device 24 and the display device 23. It may be output. For example, when the reference frame is photographed at midnight, if it becomes bright in the morning, it is considered that the difference is detected in all the frames regardless of whether or not there is a vehicle passing through the area 41. Further, for example, when the traffic volume is low at midnight, the reference frame may not be rewritten until it becomes bright in the morning. Therefore, by periodically rewriting the reference frame, it is possible to output the imaging data to the storage device 24 and the display device 23 only when the vehicle passes through the area 41. As a result, the power consumption and the storage capacity of the storage device 24 can be reduced. Further, when an accident occurs in the area 41, the image at the time of the accident can be easily searched.

The monitoring device according to the present embodiment may be, for example, a security camera that images an illegal intruder,
It can be applied to various purposes.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 13)
In this embodiment, examples of electronic devices to which the imaging device of one embodiment of the present invention can be applied are described.

As an electronic device to which the imaging device according to one embodiment of the present invention can be applied, a display device such as a television or a monitor, a lighting device, a desktop or notebook personal computer, a word processor, or a recording medium such as a DVD (Digital Versatile Disc) is stored. Image reproducing device for reproducing still images or moving images, portable CD player, radio, tape recorder, headphone stereo, stereo, navigation system, table clock, wall clock, cordless telephone handset, transceiver, mobile phone, car phone, portable type game machine,
High frequency heating devices such as tablet type terminals, large game machines such as pachinko machines, calculators, portable information terminals, electronic organizers, electronic book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, microwave ovens, etc. , Electric rice cooker, electric washing machine, electric vacuum cleaner, water heater, fan, hair dryer, air conditioner, humidifier, dehumidifier and other air conditioning equipment, dishwasher, tableware dryer, clothes dryer, futon dryer, Electric refrigerators, electric freezers, electric freezers, DNA storage freezers, flashlights, tools such as chainsaws, smoke detectors, medical equipment such as dialysis machines, facsimiles, printers, printer multifunction machines, automatic teller machines (ATM). ,
Examples include vending machines. In addition, guide lights, traffic lights, belt conveyors, elevators,
Examples include industrial equipment such as escalator, industrial robot, power storage system, power leveling and power storage device for smart grid. In addition, a moving body or the like that is driven by an electric motor using electric power is also included in the category of electronic devices. Examples of the moving body include an electric vehicle (EV), a hybrid vehicle (HEV) having both an internal combustion engine and an electric motor, a plug-in hybrid vehicle (PHEV), a tracked vehicle in which these tire wheels are changed to an endless track, and an electric assist. Examples thereof include motorized bicycles including bicycles, motorcycles, electric wheelchairs, golf carts, small or large vessels, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spacecraft.

FIG. 57A illustrates a monitoring device, which includes a housing 961, a lens 962, a supporting portion 963, and the like.
The imaging device of one embodiment of the present invention can be provided at a position where the lens 962 is a focal point. As the monitoring device, the monitoring device described in Embodiment 12 can be used.

FIG. 57B illustrates a video camera, which includes a housing 941, a housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation keys 944 and the lens 945 are provided in the housing 941, and the display portion 943 is provided in the housing 942. Then, the housing 941 and the housing 942 are connected to each other by the connection portion 946, and the housing 941 and the housing 94 are connected to each other.
The angle between the two can be changed by the connecting portion 946. The image on the display unit 943
The connection portion 946 may be switched according to the angle between the housing 941 and the housing 942. The imaging device of one embodiment of the present invention can be provided at a position which is a focus of the lens 945.

FIG. 57C illustrates a mobile phone, which includes a housing 951 including a display portion 952, a microphone 957, a speaker 954, a camera 959, an input/output terminal 956, operation buttons 955, and the like. For the camera 959, the imaging device of one embodiment of the present invention can be used.

FIG. 57D illustrates a digital camera, which includes a housing 921, a shutter button 922, and a microphone 9.
23, a light emitting unit 927, a lens 925, and the like. The imaging device of one embodiment of the present invention can be provided at a position which is a focus of the lens 925.

FIG. 57E illustrates a portable game machine including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, a camera 909, and the like. The portable game machine illustrated in FIG. 57A has two display portions 903.
However, the number of display portions included in the portable game machine is not limited to this. The imaging device of one embodiment of the present invention can be used for the camera 909.

FIG. 57F shows a wristwatch type information terminal, which includes a housing 931, a display portion 932, and a wristband 9.
33, a camera 939 and the like. The display portion 932 may be a touch panel. For the camera 939, the imaging device of one embodiment of the present invention can be used.

Note that the electronic device described above is not particularly limited as long as the imaging device of one embodiment of the present invention is included.

This embodiment can be combined with any of the other embodiments in this specification as appropriate.

10 image pickup device 11 pixel 12 pixel array 13 circuit 14 circuit 15 circuit 16 circuit 17 circuit 18 circuit 19 circuit 21 circuit 22 circuit 23 display device 24 storage device 25 circuit 31 image pickup data 32 row address 33 column address 34 clock signal 35 clock signal 36 Signal 37 Row address 38 Column address 39 Signal 41 Region 42 Coordinates 43 Region 50 Transistor 51 Transistor 52 Transistor 53 Transistor 54 Transistor 55 Transistor 56 Transistor 57 Transistor 58 Transistor 59 Transistor 60 Transistor 61 Transistor 62 Transistor 63 Capacitive element 64 Comparator 65 Comparator 70 Wiring 71 wiring 72 wiring 73 wiring 76 wiring 78 wiring 81 wiring 82 wiring 84 wiring 85 wiring 91 conductor 92 insulating layer 92a insulating layer 92b insulating layer 93 insulating layer 94 wiring 94a conductive layer 94b conductive layer 95 wiring 96 insulating layer 100 silicon substrate 101 Transistor 102 Transistor 105 Active layer 106 Silicon substrate 120 Photoelectric conversion element 121 Photoelectric conversion layer 122 Translucent conductive layer 123 Semiconductor layer 124 Semiconductor layer 125 Semiconductor layer 126 Electrode 126a Conductive layer 126b Conductive layer 127 Partition wall 131 Transistor 132 Transistor 133 Transistor 134 Transistor 135 transistor 141 capacitance element 142 capacitance element 151 wiring 152 wiring 153 wiring 154 wiring 155 wiring 156 wiring 161 wiring 162 wiring 163 wiring 165 wiring 201 imaging operation 202 data holding operation 203 reading operation 210 pixel 211 transistor 212 liquid crystal element 213 capacitive element 214 memory 215 wiring 216 wiring 217 wiring 221 transistor 222 transistor 223 light emitting element 401 transistor 402 transistor 403 transistor 404 transistor 405 transistor 406 transistor 407 transistor 408 transistor 409 transistor 410 transistor 411 transistor 412 transistor 413 transistor 415 substrate 420 insulating layer 430 oxide semiconductor layer 430a Oxide semiconductor layer 430b Oxide semiconductor layer 430c Oxide semiconductor layer 440 Conductive layer 441 Conductive layer 442 Conductive layer 450 conductive layer 451 conductive layer 452 conductive layer 460 insulating layer 470 conductive layer 471 conductive layer 472 conductive layer 473 conductive layer 475 insulating layer 480 insulating layer 531 region 532 region 533 region 534 region 535 region 600 camera 810 package substrate 811 package substrate 820 cover Glass 821 Lens cover 830 Adhesive 835 Lens 840 Bump 841 Land 850 Image sensor chip 851 Image sensor chip 860 Electrode pad 861 Electrode pad 870 Wire 871 Wire 880 Through hole 885 Land 890 IC chip 901 Housing 902 Housing 903 Display 904 Display 905 microphone 906 speaker 907 operation key 908 stylus 909 camera 921 housing 922 shutter button 923 microphone 925 lens 927 light emitting unit 931 housing 932 display unit 933 wristband 939 camera 941 housing 942 housing 943 display unit 944 operation key 945 lens 946 Connection portion 951 Housing 952 Display portion 954 Speaker 955 Button 956 Input/output terminal 957 Microphone 959 Camera 961 Housing 962 Lens 963 Support portion 1100 layer 1200 layer 1400 layer 1500 Diffraction grating 1600 layer 2500 Insulating layer 2510 Light shielding layer 2520 Organic resin layer 2530 color filter 2530a color filter 2530b color filter 2530c color filter 2540 microlens array 2550 optical conversion layer 2560 insulating layer

Claims (3)

A lens, a pixel array having a plurality of pixels, and first to fifth circuits,
Each of the plurality of pixels has a photoelectric conversion element,
The photoelectric conversion element is arranged so as to have an overlap with the lens in a front view,
The first circuit has a function of calculating a difference between the image data of the first frame and the image data of the second frame of the selected pixel,
The second circuit has a function of outputting a row address of a pixel which is a target of the difference calculation,
The third circuit has a function of outputting a column address of a pixel which is a target of the difference calculation,
The fourth circuit has a function of storing a row address and a column address which define a designated area of the pixel array,
The fifth circuit has coordinates included in an area defined by the row address and the column address stored in the fourth circuit, and coordinates composed of the row address and the column address of the pixel in which the difference is detected. An electronic device having a function of comparing. A lens, a pixel array having a plurality of pixels, and first to fifth circuits,
Each of the plurality of pixels has a photoelectric conversion element,
Light incident through the lens is incident on the photoelectric conversion element,
The first circuit has a function of calculating a difference between the image data of the first frame and the image data of the second frame of the selected pixel,
The second circuit has a function of outputting a row address of a pixel which is a target of the difference calculation,
The third circuit has a function of outputting a column address of a pixel which is a target of the difference calculation,
The fourth circuit has a function of storing a row address and a column address which define a designated area of the pixel array,
The fifth circuit has coordinates included in an area defined by the row address and the column address stored in the fourth circuit, and coordinates composed of the row address and the column address of the pixel in which the difference is detected. An electronic device having a function of comparing. In claim 1 or 2,
Each of the plurality of pixels has a transistor electrically connected to the photoelectric conversion element,
An electronic device in which the transistor includes an oxide semiconductor in a channel formation region.