JP6670523B2 - Synchronous rectifier driving device and synchronous rectifier driving method - Google Patents

Description

  The present invention relates to a synchronous rectifier driving device and a synchronous rectifier driving method for driving a synchronous rectifier that is provided on a secondary side of a flyback type switching power supply and rectifies a transformer secondary winding voltage.

  A technique has been proposed in which a MOSFET (hereinafter, referred to as a synchronous rectification MOS) provided as a synchronous rectifying element on the secondary side of a flyback type switching power supply device is driven based on a drain voltage (for example, see Patent Document 1). ). In Patent Document 1, the drain voltage of the synchronous rectification MOS is compared with a first reference voltage, and when the drain voltage becomes equal to or lower than the first reference voltage, the gate of the synchronous rectification MOS is driven via a transconductance amplifier. The drain voltage and the second reference voltage are compared by a comparator, and when the drain voltage becomes equal to or higher than the second reference voltage, the output of the transconductance amplifier is pulled down to 0 by a switch to turn off the synchronous rectification MOS. I have.

US Patent No. 8067973

  However, the operation of the flyback type switching power supply device includes an operation in a current discontinuous state as shown in FIG. 13A, an operation in a current critical state as shown in FIG. There is an operation in a continuous current state as shown in c). In the related art, it is possible to secure a good operation in a current critical state, but there is a problem that it is difficult to secure good controllability in a discontinuous current state or a continuous current state.

  In a current discontinuous state in which there is a zero current period while the primary main switch is off, after the release of the magnetic flux energy stored in the transformer is completed, the magnetic flux energy is stored in the transformer again by turning on the main switch. There is a delay before it is started. It is known that in the delay time, a ringing occurs due to the formation of a series resonance circuit of the inductance component of the transformer and a parasitic capacitance such as a primary side main switch, a snubber circuit, and a secondary side rectifier circuit. If the drain voltage of the synchronous rectification MOS becomes lower than or equal to the first reference voltage due to the ringing, the synchronous rectification MOS may operate despite the timing at which the synchronous rectification control is not necessary. It is difficult to secure the property.

  In a continuous current state in which a current flows continuously while the primary main switch is off, the primary main switch starts operating before the release of magnetic flux energy stored in the transformer is completed. Therefore, it is necessary to stop the gate of the synchronous rectification MOSFET before the operation of the primary side main switch starts, but in the related art, the synchronous rectification MOS keeps operating until the drain voltage becomes equal to or higher than the second reference voltage. I do. As a result, an abnormal state occurs in which the primary-side main switch and the synchronous rectification MOS are simultaneously turned on, which may cause a problem such as a decrease in efficiency or a breakage of a circuit. Therefore, it is difficult to ensure good controllability. It is.

  An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a synchronous rectifying element driving device and a synchronous rectifying element driving method capable of achieving a good synchronous rectifying operation regardless of the operation state of a switching power supply. It is in.

A synchronous rectifying element driving device of the present invention is a synchronous rectifying element driving device for driving a synchronous rectifying element for rectifying a voltage of a secondary winding of a transformer in a switching power supply device, based on a voltage across the synchronous rectifying element. A first detector for detecting an on-timing of the synchronous rectifier, a second detector for detecting a reference timing of a voltage change of the secondary winding, and a reference timing detected by the second detector in advance. A control unit for turning on the synchronous rectifying element at the on-time detected by the first detection unit on condition that the time is within a set determination period.
Further, in the synchronous rectifier driving device of the present invention, the second detector may detect, as the reference timing, a timing at which the secondary winding reverses its polarity to a rectifiable voltage polarity.
Further, in the synchronous rectifier driving device of the present invention, the first detector detects the on-timing by comparing a voltage across the synchronous rectifier with a turn-on reference voltage,
The second detector may detect the reference timing by comparing a voltage between both ends of the synchronous rectifier with a first reference voltage different from the turn-on reference voltage.
Further, in the synchronous rectifying element driving device of the present invention, the synchronous rectifying element driving device further includes a voltage dividing unit that divides an output voltage of the switching power supply device to generate a resistance voltage dividing signal, wherein the second detecting unit includes both ends of the synchronous rectifying element. The reference timing may be detected by comparing a voltage with the resistance divided signal.
Further, in the synchronous rectifying element driving device of the present invention, the synchronous rectifying element driving device further includes a series circuit including a capacitor and a resistor connected to both ends of the synchronous rectifying element, and the second detection unit includes the capacitor and the resistor in the series circuit. The reference timing may be detected by comparing a voltage at a connection point with the second reference voltage .
Also, the synchronous rectification device driving apparatus of the present invention is a synchronous rectifier driving device for driving a synchronous rectifier device for rectifying the voltage of the secondary winding of the transformer in the switching power supply device, the voltage across the synchronous rectifier And a turn-on reference voltage to detect an on-timing of the synchronous rectifier element, and compare a voltage between both ends of the synchronous rectifier element with a turn-off reference voltage to detect an off-timing of the synchronous rectifier element. A second detection unit for detecting a reference timing of a voltage change of the secondary winding; a period from the on-timing to the off-timing detected by the first detection unit as a synchronous rectification period; Maximum on-time generator that generates a maximum on-time limit signal that limits the on-period of the rectifier to a period shorter than the synchronous rectification period one cycle before. A beam generation unit, it on condition the is within the second preset determination period from the reference timing detected by the detecting unit, the synchronous rectification element in the ON timing detected by said first detection unit A control unit for turning on and turning off the synchronous rectifying element based on the maximum on-time limit signal or the off-timing.
Also, a synchronous rectifying element driving method of the present invention is a synchronous rectifying element driving method for driving a synchronous rectifying element for rectifying a voltage of a secondary winding of a transformer in a switching power supply device, wherein the first detecting unit detects the synchronous rectifying element. Control for detecting the on-timing of the synchronous rectifying element based on the voltage between both ends of the rectifying element, detecting the reference timing of the voltage fluctuation of the secondary winding by the second detector, and controlling the driving of the synchronous rectifying element; The unit may turn on the synchronous rectifying element at the ON timing detected by the first detection unit , on condition that it is within a predetermined determination period from the reference timing detected by the second detection unit. Features .
Also, synchronous rectifier driving method of the present invention is a synchronous rectifier driving device for driving a synchronous rectifier device for rectifying the voltage of the secondary winding of the transformer in the switching power supply apparatus, by the first detecting unit, wherein The on-timing of the synchronous rectifier is detected by comparing the voltage across the synchronous rectifier with the turn-on reference voltage, and the off-timing of the synchronous rectifier is compared by comparing the voltage across the synchronous rectifier with the turn-off reference. And a second detecting unit detects a reference timing of a voltage change of the secondary winding, and a maximum on-time generating unit detects a period from the on-timing to the off-timing detected by the first detecting unit. Is a synchronous rectification period, and the maximum ON period for limiting the ON period of the synchronous rectification element to a period shorter than the synchronous rectification period one cycle before. Generates Im restriction signal, the controller for controlling the driving of the synchronous rectification element, it on condition the second detection portion is within preset determination period from the reference timing of detecting the first detection The synchronous rectifying element is turned on at the on-timing detected by the unit , and the synchronous rectifying element is turned off based on the maximum on-time limit signal or the off-timing.

According to the present invention, it is possible to prevent the synchronous rectifier from malfunctioning due to ringing after the completion of the release of the magnetic flux energy accumulated in the transformer, and it is possible to prevent a current having a zero current period while the primary-side switching element Q1 is off. There is an effect that a good synchronous rectification operation can be realized even in a discontinuous state.
Further, the operation of the synchronous rectifying element can be reliably stopped before the operation of the primary-side switching element starts, so that the current is continuously flowing while the primary-side switching element is off. Thus, a good synchronous rectification operation can be realized.

FIG. 1 is a circuit configuration diagram illustrating a circuit configuration of a switching power supply device including a synchronous rectification element driving device according to a first embodiment of the present invention. FIG. 2 is a circuit configuration diagram illustrating a circuit configuration of the synchronous rectification element driving device illustrated in FIG. 1. FIG. 3 is a circuit configuration diagram illustrating a circuit configuration of a pulse generator illustrated in FIG. 2. FIG. 4 is a circuit configuration diagram illustrating a circuit configuration of a maximum on-time generation circuit illustrated in FIG. 3. FIG. 4 is an operation waveform diagram of the maximum on-time generation circuit shown in FIG. 3. FIG. 3 is an operation waveform diagram of the synchronous rectification element driving device shown in FIG. 2 when current is discontinuous. FIG. 3 is an operation waveform diagram of the synchronous rectifying element driving device shown in FIG. 2 when a current is continuous. FIG. 3 is an operation waveform diagram at the time of a critical operation of the synchronous rectification element driving device shown in FIG. 2. FIG. 4 is a circuit configuration diagram showing a circuit configuration of a second embodiment of the synchronous rectification element driving device according to the present invention. FIG. 9 is a circuit configuration diagram illustrating a circuit configuration of a third embodiment of the synchronous rectification element driving device according to the present invention. FIG. 10 is an operation waveform diagram of the synchronous rectification element driving device shown in FIG. 9 when current is discontinuous. FIG. 9 is a circuit configuration diagram illustrating a circuit configuration of a fourth embodiment of the synchronous rectification element driving device according to the present invention. FIG. 3 is an operation waveform diagram of the switching power supply device.

  Next, embodiments of the present invention will be specifically described with reference to the drawings. In each of the embodiments, the same components are denoted by the same reference numerals, and description thereof will not be repeated.

(First Embodiment)
The switching power supply device 1 provided with the synchronous rectifier driving device 10 of the first embodiment is an isolated flyback converter. Referring to FIG. 1, a rectifier circuit DB, smoothing capacitors C1 and C2, and a transformer T A switching element Q1, a controller 2, a synchronous rectifying element Q2, an error amplifier (E / A) 3, a light emitting diode PC1 and a light receiving transistor PC2 forming a photocoupler, and a resistor R1.

  A commercial AC power supply AC is connected to the AC input terminals ACin1 and ACin2 of the rectifier circuit DB having a diode bridge configuration, and the AC voltage input from the commercial AC power supply AC is full-wave rectified and output from the rectifier circuit DB. A smoothing capacitor C1 is connected between the rectified output positive terminal and the rectified output negative terminal of the rectifier circuit DB. Thus, a DC power supply obtained by rectifying and smoothing the commercial AC power supply AC by the rectifier circuit DB and the smoothing capacitor C1 is obtained.

  The primary winding Np of the transformer T, the switching element Q1, and the resistor R1 are connected in series between the rectified output positive terminal and the rectified output negative terminal of the rectifier circuit DB. In this embodiment, the switching element Q1 is formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the source terminal is connected to the rectified output negative terminal of the rectifier circuit DB via the resistor R1, and the drain terminal is connected to the primary winding. They are connected to the rectification output positive terminals of the rectification circuit DB via Np. Further, the gate terminal of the switching element Q1 is connected to the gate control terminal G of the controller 2, and the switching element Q1 is on / off controlled by the controller 2.

  By the on / off control of the switching element Q1, the DC power rectified and smoothed by the rectifier circuit DB and the smoothing capacitor C1 is intermittently applied to the primary winding Np.

  In the transformer T, magnetic energy is stored when the switching element Q1 is on, and the magnetic energy stored when the switching element Q1 is off is discharged as electric power from the secondary winding Ns.

  A smoothing capacitor C2 and a synchronous rectifier Q2 are connected in series between both terminals of the secondary winding Ns, and the power discharged from the secondary winding of the transformer T is supplied to the smoothing capacitor C2 and the synchronous rectifier Q2. And the voltage between the terminals of the smoothing capacitor C2 is output from the output terminal as the output voltage Vo. In the present embodiment, the synchronous rectifier Q2 is formed of an N-type MOSFET, and has a source terminal connected to the negative terminal of the smoothing capacitor C2 and a drain terminal connected to one end of the secondary winding Ns. The symbol D1 shown in FIG. 1 is a parasitic diode of the switching element Q1.

  An error amplifier 3 is connected in series between the positive terminal and the negative terminal of the smoothing capacitor C2. The error amplifier 3 controls the current flowing through the light emitting diode PC1 of the photocoupler according to the difference between the output voltage Vo and the steady voltage. The FB terminal of the controller 2 is connected to a ground terminal via a light receiving transistor PC2 of a photocoupler. As a result, a feedback signal corresponding to the output voltage is transmitted from the light emitting diode PC1 on the secondary side to the light receiving transistor PC2 on the primary side, and is input to the FB terminal of the controller 2. The controller 2 controls the duty ratio of the gate signal of the switching element Q1 based on the feedback signal input to the FB terminal, and controls the amount of power supplied to the secondary side.

The synchronous rectifier driving device 10 turns on the synchronous rectifier Q2 only during a period in which the secondary current _iNs flows from the source terminal to the drain terminal of the synchronous rectifier Q2 to reduce conduction loss.

  Referring to FIG. 2, the synchronous rectifier driving device 10 includes a first comparator CP1, a second comparator CP2, a pulse generator 11, and a driving circuit 12.

  The first comparator CP1 is a hysteresis comparator, in which an offset voltage Vref1 as a turn-on threshold and an offset voltage Vref2 as a turn-off threshold are set. In the first comparator CP1, the drain terminal of the synchronous rectifier Q2 is connected to the inverting input terminal, and the source terminal of the synchronous rectifier Q2 is connected to the non-inverting input terminal via the offset voltage Vref1 or the offset voltage Vref2. A drive timing notification signal Sig_A for notifying the drive timing of the rectifier element Q2 is output.

The first comparator CP1 is the offset voltage Vref1, detects the conduction of the parasitic diode D1 of the synchronous rectifier Q2 due to a decrease in the drain voltage _{V Q2} of synchronous rectifier Q2, switching the drive timing notification signal Sig_A to a high level. The first comparator CP1 is the offset voltage Vref2, detects a decrease in the secondary current _{i Ns,} switch the drive timing notification signal Sig_A to a low level.

  The second comparator CP2 detects the timing at which the voltage across the secondary winding Ns of the transformer T is inverted, and notifies the timing at which the voltage across the secondary winding Ns is inverted to a rectifiable voltage polarity as a reference timing. Output as the reference timing notification signal Sig_B. In the second comparator CP2, the connection point between the secondary winding Ns of the transformer T and the positive terminal of the smoothing capacitor C2 is connected to the non-inverting input terminal, and the connection between the secondary winding Ns of the transformer T and the drain terminal of the synchronous rectification element Q2 is connected. Points are connected to the inverting input terminals, respectively.

  The pulse generator 11 generates a PWM signal that controls the on-period of the synchronous rectifier Q2 with a pulse width based on the drive timing notification signal Sig_A and the reference timing notification signal Sig_B.

The drive circuit 12 drives the synchronous rectifier Q2 based on the PWM signal generated by the pulse generator 11. Drive signal of the synchronous rectifying element Q2 may be a rectangular pulse signal may be a linear signal corresponding to the drain voltage V _Q2 of synchronous rectifier Q2.

  Referring to FIG. 3, the pulse generator 11 includes a one-shot pulse generation circuit OS1, an inversion circuit NOT1, a NAND circuit NAND1, an OR circuit OR1, an RS flip-flop FF1, FF2, and a maximum on-time generation circuit. 13 is provided. The pulse generator 11 receives the input of the reference timing notification signal Sig_B output from the second comparator CP2 through the input terminal of the one-shot pulse generation circuit OS1, and outputs the input from the first comparator CP1 through the input terminal of the inversion circuit NOT1. The input of the drive timing notification signal Sig_A is received. Then, the pulse generator 11 outputs a PWM signal for controlling the synchronous rectifier element Q2 from the output terminal Q of the flip-flop FF2.

  The one-shot pulse generation circuit OS1 is a circuit that outputs a pulse signal that is at a low level for a predetermined period when a rising edge of the reference timing notification signal Sig_B is detected. The output terminal is connected to one input terminal of the NAND circuit NAND1. It is connected. The output terminal of the inverter NOT1 is connected to the other input terminal of the NAND circuit NAND1.

  The output terminal of the NAND circuit NAND1 is connected to the set terminal S of the flip-flop FF1 and the set terminal S of the flip-flop FF2. Therefore, the PWM signal output from the output terminal Q of the flip-flop FF2 and the on-period signal Sig_on output from the output terminal Q of the flip-flop FF2 are determined based on the condition that the one-shot pulse generation circuit OS1 is outputting a pulse signal. It rises at the same timing as the rise of the drive timing notification signal Sig_A.

  The output terminal of the inverting circuit NOT1 is connected to the reset terminal R of the flip-flop FF1. Therefore, the on-period signal Sig_on output from the output terminal Q of the flip-flop FF1 falls at the same timing as the fall of the drive timing notification signal Sig_A.

  The input terminal of the maximum on-time generation circuit 13 is connected to the output terminal Q of the flip-flop FF1, and the output terminal of the maximum on-time generation circuit 13 is connected to one input terminal of the OR circuit OR1. The output terminal of the inverting circuit NOT1 is connected to the other input terminal of the OR circuit OR1, and the output terminal of the OR circuit OR1 is connected to the reset terminal R of the flip-flop FF2. Therefore, the PWM signal output from the output terminal Q of the flip-flop FF2 is earlier than the falling of the drive timing notification signal Sig_A or the rising of the maximum on-time limit signal MOTG output from the maximum on-time generation circuit 13. Fall at the same timing as the one.

  The configuration and operation of the maximum on-time generation circuit 13 will be described in detail with reference to FIGS.

  As shown in FIG. 4, the maximum on-time generating circuit 13 includes a D-type flip-flop FF3, AND circuits AND1, AND2, RS-type flip-flops FF4, FF5, inverting circuits NOT2, NOT3, and a constant current circuit. CC1, CC2, CC3, CC4, charge switches Q3, Q5, discharge switches Q4, Q6, capacitors C3, C4, comparators CP3, CP4, an OR circuit OR2, and a one-shot pulse generation circuit OS2. I have.

The waveforms shown in FIG. 5 are, from the top, an on-period signal Sig_on, an input waveform to the data input terminal D of the flip-flop FF3, an output waveform from the output terminal Q of the flip-flop FF3, an output waveform of the AND circuit AND1, and an AND circuit AND2. , The output waveform from the inverted output terminal Qb of the flip-flop FF4, the output waveform from the inverted output terminal Qb of the flip-flop FF5, the drive waveform of the charge switch Q3, the drive waveform of the discharge switch Q4, and the drive waveform of the charge switch Q5 Drive waveform of discharge switch Q6, voltage waveform of capacitor C3, voltage waveform of capacitor C4, output waveform of comparator CP3,
The output waveform of the comparator CP4, the output waveform of the OR circuit OR2, and the output waveform of the one-shot pulse generation circuit OS2 are shown.

  The ON period signal Sig_on is input to the inverted clock input terminal CLK of the flip-flop FF3 and is also input to one input terminal of each of the AND circuits AND1 and AND2. Note that the ON period signal Sig_on signal is a flip-flop different from the flip-flop FF2 that generates the PWM signal for synchronous rectification so as not to be affected by the maximum on-time limit signal MOTG output from the maximum on-time generation circuit 13. It is configured to generate using FF1.

  The output terminal Q of the flip-flop FF3 is connected to the other input terminal of the AND circuit AND1. The inverted output terminal Qb of the flip-flop FF3 is connected to its own data input terminal D and to the other input terminal of the AND circuit AND2.

  With this configuration, the on-period signal Sig_on is divided into an odd-numbered pulse and an even-numbered pulse by the frequency dividing circuit including the flip-flop FF3 and the AND circuits AND1 and AND2, and the even-numbered pulse is supplied from the AND circuit AND1 and the odd-numbered pulse is supplied to the AND pulse. The signals are output from the circuit AND2.

  The constant current circuits CC1, CC2, the charge switch Q3, the discharge switch Q4, the capacitor C3, the comparator CP3, the inverting circuit NOT2, and the flip-flop FF4 are based on the ON period of the immediately preceding even-numbered pulse. , And functions as an odd-number-time ON-period limiting circuit for limiting the ON-time of the odd-number-pulse synchronous rectifier element Q2.

  A constant current circuit CC1, a charge switch Q3 composed of a P-type MOSFET, a discharge switch Q4 composed of an N-type MOSFET, and a constant current circuit CC2 are connected in series between an internal regulator Reg and a ground terminal. ing. The connection point between the charge switch Q3 and the discharge switch Q4 is connected to the ground terminal via the capacitor C3 and to the inverting input terminal of the comparator CP3. The reference voltage Vref3 is connected to the non-inverting input terminal of the comparator CP3, and the output terminal of the comparator CP3 is connected to one input terminal of the OR circuit OR2. The output terminal of the AND circuit AND1 is connected to the gate terminal of the charging switch Q3 via the inverting circuit NOT2. The inverting output terminal Qb of the flip-flop FF4 is connected to the gate terminal of the discharge switch Q4, the output terminal of the AND circuit AND1 is connected to the set terminal S of the flip-flop FF4, and the reset terminal R of the flip-flop FF4. And the output terminals of the AND circuit AND2 are connected to each other.

  With this configuration, during the on-period of the even-numbered pulse (period from time t3 to t4), the charge switch Q3 is turned on and the discharge switch Q4 is turned off, and the capacitor C3 is charged by the constant current of the constant current circuit CC1. Then, during the off period (the period from time t4 to t5) after the end of the even-numbered pulse, the charging switch Q3 is turned off and the discharging switch Q4 is turned off, and the charged capacitor C3 is maintained in a high resistance state. Next, the ON period of the odd-numbered pulse (period from time t1 to t2) and the off-period after the end of the odd-numbered pulse (period from time t2 to t3) are as follows: charge switch Q3 is off and discharge switch Q4 is on. The capacitor C3 is discharged by the constant current of the constant current circuit CC2.

  The reference voltage Vref3 is a threshold for detecting the completion of discharging of the capacitor C3. When the voltage of the capacitor C3 falls below the reference voltage Vref3, the output of the comparator CP3 rises. When detecting the rising of the output of the comparator CP3 via the OR circuit OR2, the one-shot pulse generation circuit OS2 outputs a pulse signal which becomes a high level for a preset predetermined period. It becomes the maximum on-time restriction signal MOTG that restricts the on-period of Q2. The constant current of the constant current circuit CC1 serving as the charging current of the capacitor C3 is set to a value slightly larger than the constant current of the constant current circuit CC2 serving as the discharging current of the capacitor C3. Thus, the time from the rising of the odd-numbered pulse (time t1) to the output of the pulse signal from the one-shot pulse generation circuit OS2 is longer than the ON period of the immediately preceding even-numbered pulse (time t3 to t4). Becomes shorter.

  The constant current circuits CC3 and CC4, the charging switch Q5, the discharging switch Q6, the capacitor C4, the comparator CP4, the inverting circuit NOT3, and the flip-flop FF5 are based on the ON period of the immediately preceding odd-numbered pulse. , Functions as an even-number ON-period limiting circuit that limits the ON period of the synchronous rectifying element Q2 of the even-number pulse.

  A constant current circuit CC3, a charge switch Q5 composed of a P-type MOSFET, a discharge switch Q6 composed of an N-type MOSFET, and a constant current circuit CC4 are connected in series between the internal regulator Reg and a ground terminal. ing. The connection point between the charge switch Q5 and the discharge switch Q6 is connected to the ground terminal via the capacitor C4 and to the inverting input terminal of the comparator CP4. The reference voltage Vref4 is connected to the non-inverting input terminal of the comparator CP4, and the output terminal of the comparator CP4 is connected to the other input terminal of the OR circuit OR2. The output terminal of the AND circuit AND2 is connected to the gate terminal of the charging switch Q5 via the inverting circuit NOT3. The inverting output terminal Qb of the flip-flop FF5 is connected to the gate terminal of the discharge switch Q6, the output terminal of the AND circuit AND2 is connected to the set terminal S of the flip-flop FF5, and the reset terminal R of the flip-flop FF5 is connected to the reset terminal R of the flip-flop FF5. , And an output terminal of the AND circuit AND1 are connected to each other.

  With this configuration, during the ON period of the odd-numbered pulse (the period from time t1 to t2), the charge switch Q5 is turned on and the discharge switch Q6 is turned off, and the capacitor C4 is charged by the constant current of the constant current circuit CC3. Then, during the off period (period from time t2 to t3) after the end of the odd-numbered pulse, the charge switch Q5 is turned off and the discharge switch Q6 is turned off, and the charged capacitor C4 is maintained in a high resistance state. Next, the on-period of the even-numbered pulse (period from time t3 to t4) and the off-period after the end of the even-numbered pulse (period from time t4 to t5) are as follows: charge switch Q5 is off and discharge switch Q6 is on. The capacitor C4 is discharged by the constant current of the constant current circuit CC4.

  The reference voltage Vref4 is a threshold for detecting completion of discharging of the capacitor C4. When the voltage of the capacitor C4 falls below the reference voltage Vref4, the output of the comparator CP4 rises. When detecting the rising of the output of the comparator CP4 via the OR circuit OR2, the one-shot pulse generation circuit OS2 outputs a pulse signal that is at a high level for a predetermined period, and the output is a synchronous rectification when an even-number pulse is generated. The maximum on-time restriction signal MOTG restricts the on-period of the element Q2. The constant current of the constant current circuit CC3 serving as the charging current of the capacitor C4 is set to a value slightly larger than the constant current of the constant current circuit CC4 serving as the discharging current of the capacitor C4. Thus, the time from the rise of the even-numbered pulse (time t3) to the output of the pulse signal from the one-shot pulse generation circuit OS2 is longer than the ON period of the immediately preceding odd-numbered pulse (time t1 to t2). Becomes shorter.

Next, the ON operation of the synchronous rectifier Q2 will be described in detail with reference to the operation of the synchronous rectifier drive 10 in the discontinuous current state shown in FIG. The waveforms shown in FIG. 6 are, from the top, the voltage V _Ns across the secondary winding Ns, the drain voltage V _Q2 of the synchronous rectifier element _Q2 , the secondary current i _Ns , the output waveform of the second comparator CP2, and the one-shot. Output waveform of pulse generation circuit OS1, output waveform of first comparator CP1, output waveform of inversion circuit NOT1, output waveform of NAND circuit NAND1, output waveform of OR circuit OR1, output waveform from output terminal Q of flip-flop FF1, maximum The on-time notification signal MOTG and the output waveform from the output terminal Q of the flip-flop FF2 are shown.

In the flyback type switching power supply device 1, the secondary-side current i _Ns has the largest energy at the moment when the magnetic flux energy stored in the transformer T is released (immediately after the switching element Q1 is turned off), and decreases with time. Therefore, the start timing of the synchronous rectifier element Q2 is a state in which the magnetic flux energy is accumulated most in the transformer T, so that the voltage V _Ns across the secondary winding Ns changes rapidly, but after the release of the magnetic flux energy ends. changes in voltage across _{V Ns} of the secondary winding Ns is slow.

  Therefore, in the present embodiment, the timing at which the synchronous rectifying element Q2 is turned on is accurately detected by utilizing the difference in the operation of releasing magnetic flux energy. That is, in the discontinuous state where the release of the magnetic flux energy is completed, the voltage fluctuation of the secondary winding Ns of the transformer T becomes slow, but in the continuous state, the voltage fluctuation of the secondary winding Ns of the transformer T becomes sharp. Therefore, it is possible to grasp the operation state of the power supply by utilizing this difference.

  When the timing (time t11, t13, t15) at which the voltage across the secondary winding Ns of the transformer T is inverted from negative to positive is detected by the second comparator CP2, the one-shot pulse generation circuit OS1 changes the pulse width Ta. The pulse signal of is output.

While the one-shot pulse generation circuit OS1 is outputting the pulse signal of the pulse width Ta, the first comparator CP1 detects the conduction of the parasitic diode D1 of the synchronous rectifier Q2, and the driving output from the first comparator CP1. When the timing notification signal Sig_A switches to a high level, the flip-flop FF2 is set, and the synchronous rectifier Q2 is turned on. That is, the second reduction in the drain voltage _{V Q2} of the secondary winding Ns of the voltage across synchronous rectifier Q2 from reverse timing (time t11) detected by the first comparator CP1 of the transformer T detected by the comparator CP2 (parasitic diode D1 When the delay time from the start of conduction to time t11a) is within a predetermined period (pulse width Ta), it is determined that the voltage fluctuation of the secondary winding Ns is steep, and the synchronous rectifier Q2 is turned on.

On the other hand, in a state where the pulse signal of the pulse width Ta is not output from the one-shot pulse generation circuit OS1, the conduction of the parasitic diode D1 of the synchronous rectifier Q2 is detected by the first comparator CP1 and output from the first comparator CP1. Even if the drive timing notification signal Sig_A switches to the high level, the synchronous rectifier Q2 is not turned on without setting the flip-flop FF2. That is, reduction in the drain voltage _{V Q2} of the secondary winding Ns synchronous rectifier Q2 from reverse timing voltage across (time t13, t15) detected by the first comparator CP1 of the transformer T detected by the second comparator CP2 (parasitic If the delay time from the start of conduction of the diode D1 to the times t13a and t15a) exceeds a predetermined period (pulse width Ta), it is determined that the voltage fluctuation of the secondary winding Ns is slow, and the synchronous rectifier Q2 is turned on. Never be.

  As described above, by determining whether to operate the synchronous rectifier element Q2 in accordance with the speed of the voltage fluctuation of the secondary winding Ns of the transformer T, the magnetic flux accumulated in the transformer T in the current discontinuous state is determined. It is possible to prevent malfunction of the synchronous rectifier element Q2 due to ringing after the completion of energy release.

Next, the OFF operation of the synchronous rectifier Q2 will be described in detail with reference to the operation of the synchronous rectifier driver 10 in the continuous current state shown in FIG. Note that the waveform shown in FIG. 7 includes, from the top, the voltage V _Ns across the secondary winding Ns, the drain voltage V _Q2 of the synchronous rectifier element _Q2 , the secondary current i _Ns , the output waveform of the second comparator CP2, and the one-shot. Output waveform of pulse generation circuit OS1, output waveform of first comparator CP1, output waveform of inversion circuit NOT1, output waveform of NAND circuit NAND1, output waveform of OR circuit OR1, output waveform from output terminal Q of flip-flop FF1, maximum 5 shows an on-time limit signal MOTG and an output waveform from the output terminal Q of the flip-flop FF2.

In the continuous state, before the release of the magnetic flux energy accumulated in the transformer T is completed, the switching element Q1 on the primary side is turned on. _Therefore, only the drain voltage V _Q2 of the synchronous rectifying element Q2 is confirmed, that is, the first comparator The off-timing cannot be achieved only by the output of CP1. Therefore, in the present embodiment, the maximum on-time limit signal MOTG generated by the maximum on-time generation circuit 13 based on the on-period signal Sig_on output from the output terminal Q of the flip-flop FF1 causes the maximum of the synchronous rectifier element Q2 to increase. Limited on-time.

  As described above, the maximum on-time generation circuit 13 stores the on-period (the period during which the on-period signal Sig_on is at a high level, times t21a to t22) one cycle before by the electric charge charged in the capacitor C3 or C4. A maximum on-time limiting signal MOTG that limits the on-period of the synchronous rectifier element Q2 is output during a shorter time than the stored on-period one cycle before. Thus, the operation of the synchronous rectifier element Q2 can be reliably stopped before the operation of the primary-side switching element Q1 starts. In the present embodiment, the on-period of the synchronous rectifier element Q2 is configured to be limited to a period obtained by reducing the on-period one cycle before by a predetermined ratio. May be configured to be limited to a period in which is reduced.

FIG. 8 shows an operation waveform of the synchronous rectifier driving device 10 in the current critical state. The waveforms shown in FIG. 8 are, from the top, the voltage V _Ns across the secondary winding Ns, the drain voltage V _Q2 of the synchronous rectifier _Q2 , the secondary current i _Ns , the output waveform of the second comparator CP2, and the one-shot. Output waveform of pulse generation circuit OS1, output waveform of first comparator CP1, output waveform of inversion circuit NOT1, output waveform of NAND circuit NAND1, output waveform of OR circuit OR1, output waveform from output terminal Q of flip-flop FF1, maximum 5 shows an on-time limit signal MOTG and an output waveform from the output terminal Q of the flip-flop FF2.

  Also in the current critical state, as shown in FIG. 8, the synchronous rectifying element Q2 is turned on at time t31a as in the ON operation described in the discontinuous state, and the synchronous rectification is performed at time t32c as in the OFF operation described in the continuous state. By turning off the element Q2, a favorable synchronous rectification operation can be realized.

In the present embodiment, the continuous state and the discontinuous state can be determined according to the fluctuation of the voltage of the secondary winding Ns of the transformer T. From the rise of the drain voltage V _Q2 of the synchronous rectifier element Q2 (re-inversion of the first comparator CP1, time t12) to the re-inversion of the voltage V _Ns across the secondary winding Ns detected by the second comparator CP2 (time t12a). If the period is longer than the predetermined period, it can be determined that the state is discontinuous. Then, the rise of the drain voltage _{V Q2} of synchronous rectifier Q2 (reversed again in the first comparator CP1), duration predetermined period until re-reversal of the voltage across _{V Ns} of the secondary winding Ns detected by the second comparator CP2 If it is less than the threshold value, it can be determined that the state is discontinuous.

As described above, by determining the continuous state and the discontinuous state, the operation of the maximum on-time generation circuit 13 may be stopped in the discontinuous state. That is, in the discontinuous state, after the release of the magnetic flux energy accumulated in the transformer T is completed, the switching element Q1 on the primary side is turned on. _Therefore, only the drain voltage V _Q2 of the synchronous rectifying element Q2 is confirmed, that is, An accurate off-timing can be grasped only by the output of one comparator CP1.

(Second embodiment)
In the second embodiment, the connection of the synchronous rectification element Q2 is changed from the secondary GND side to the secondary plus side, and the synchronous rectification element driving device 10a, as shown in FIG. The synchronous rectifier Q2, which is provided at the positive terminal of the capacitor C2 and has a drain terminal connected to the secondary winding Ns and a source terminal connected to the positive terminal of the smoothing capacitor C2, is driven.

  The synchronous rectifier driving device 10a includes a first comparator CP1, a fifth comparator CP5, a pulse generator 11, and a driving circuit 12.

  In the first comparator CP1, the source terminal of the synchronous rectifier Q2 is connected to the inverting input terminal, and the drain terminal of the synchronous rectifier Q2 is connected to the non-inverting input terminal via the offset voltage Vref1 or the offset voltage Vref2. A drive timing notification signal Sig_A for notifying the drive timing of the rectifier element Q2 is output.

In the fifth comparator CP5, the drain terminal of the synchronous rectifier Q2 is connected to the non-inverting input terminal, and the source terminal of the synchronous rectifier Q2 is connected to the non-inverting input terminal via the offset voltage Vref5. The offset voltage Vref5 is set to a different voltage from the offset voltage Vref1 and the offset voltage Vref2. The fifth comparator CP5 detects the timing at which the drain voltage _{V Q2} of synchronous rectifier Q2 intersects the offset voltage Vref5, and outputs the cross timing detected as a reference timing notification signal Sig_B.

(Third embodiment)

  Referring to FIG. 10, the synchronous rectifier driving device 10b according to the third embodiment drives a synchronous rectifier Q2 connected to the secondary GND side, as in the first embodiment.

  The synchronous rectifier driving device 10b includes a first comparator CP1, a sixth comparator CP6, a pulse generator 11, a driving circuit 12, and resistors R2 and R3.

In the sixth comparator CP6, the drain terminal of the synchronous rectifier Q2 is connected to the inverting input terminal.
The divided voltage of the output voltage (the voltage across the smoothing capacitor C2) by the resistors R2 and R3 is connected to the non-inverting input terminal. The voltage divided by the resistors R2 and R3 is set to be different from the offset voltage Vref1 and the offset voltage Vref2. The sixth comparator CP6 detects the timing at which the drain voltage _{V Q2} of synchronous rectifier Q2 intersects the divided voltage value by the resistors R2, R3, and outputs a cross timing detected as a reference timing notification signal Sig_B.

Then, as in the second embodiment and the third embodiment, the ON operation of the synchronous rectifier Q2 with reference timing notification signal Sig_B based on the drain voltage V _Q2, current discontinuity shown in FIG. 11 The operation will be described in detail with reference to the operation of the synchronous rectifier driving device 10a in the state. FIG. 11 is an operation waveform of each part of the second embodiment. From the top, the drain voltage V _Q2 of the synchronous rectifier _Q2 , the secondary current i _Ns , the output waveform of the fifth comparator CP5, and the one-shot Output waveform of pulse generation circuit OS1, output waveform of first comparator CP1, output waveform of inversion circuit NOT1, output waveform of NAND circuit NAND1, output waveform of OR circuit OR1, output waveform from output terminal Q of flip-flop FF1, maximum The on-time notification signal MOTG and the output waveform from the output terminal Q of the flip-flop FF2 are shown.

By the fifth comparator CP5, the timing below the offset voltage Vref5 drain voltage _{V Q2} is a synchronous rectifying element Q2 (time t41, t43, t45) is detected, the one-shot pulse generating circuit OS1 is a pulse signal having a pulse width Ta Is output.

While the pulse signal of the pulse width Ta is being output from the one-shot pulse generation circuit OS1, the conduction of the parasitic diode D1 of the synchronous rectifier Q2 of the synchronous rectifier Q2 is detected by the first comparator CP1, and the first comparator CP1 Is switched to a high level, flip-flop FF2 is set, and synchronous rectifier Q2 is turned on. That is, reduction in the drain voltage _{V Q2} of the drain voltage _{V Q2} is synchronous rectifier Q2 detected by the first comparator CP1 from the timing (time t41) below the offset voltage Vref5 the synchronous rectifier Q2 detected by the fifth comparator CP5 (parasitic If the delay time from the start of conduction of the diode D1 to the time t41a) is within a predetermined period (pulse width Ta), the synchronous rectifier element Q2 starts operating.

On the other hand, in a state where the pulse signal of the pulse width Ta is not output from the one-shot pulse generation circuit OS1, the conduction of the parasitic diode D1 of the synchronous rectifier Q2 of the synchronous rectifier Q2 is detected by the first comparator CP1. Even when the drive timing notification signal Sig_A output from the comparator CP1 switches to a high level, the flip-flop FF2 is not set, and the synchronous rectifier Q2 is not turned on. That is, reduction in the drain voltage _{V Q2} of synchronous rectifier Q2 to the drain voltage _{V Q2} is detected by the first comparator CP1 from the timing (time t43, t45) below the offset voltage Vref5 the synchronous rectifier Q2 detected by the fifth comparator CP5 If the delay time until (the conduction of the parasitic diode D1 starts, times t43a and t45a) exceeds a predetermined period (pulse width Ta), the operation of the synchronous rectifier element Q2 is not started.

(Fourth embodiment)
Referring to FIG. 12, the synchronous rectifier driving device 10c according to the fourth embodiment drives a synchronous rectifier Q2 connected to the secondary GND side, as in the first embodiment.

  The synchronous rectifier driving device 10c includes a first comparator CP1, a seventh comparator CP7, a pulse generator 11, a driving circuit 12, a capacitor C5, and a resistor R4.

  A series circuit including a capacitor C5 and a resistor R4 is connected between the drain terminal and the source terminal of the synchronous rectifier Q2. In the seventh comparator CP7, the connection point between the capacitor C5 and the resistor R4 is connected to the inverting input terminal, and the source terminal of the synchronous rectifier Q2 is connected to the non-inverting input terminal via the offset voltage Vref6. As a result, the seventh comparator CP7 detects a change in the voltage between both ends of the transformer T via the series circuit including the capacitor C5 and the resistor R4, and the voltage between both ends of the transformer T crosses the reference voltage determined by the offset voltage Vref6. The timing is detected, and the detected intersection timing is output as a slow / slow detection reference signal Sig_B.

As described above, the present embodiment is a synchronous rectifying device Q2 driving device for driving the synchronous rectifying device Q2 for rectifying the voltage of the secondary winding Ns of the transformer T in the switching power supply device 1, wherein the synchronous rectifying device Q2 A first detector (first comparator CP1) for detecting the on-timing of the synchronous rectifier element Q2 based on the voltage between both ends, and a second detector (second comparator) for detecting the reference timing of the voltage fluctuation of the secondary winding Ns. CP2, the fifth comparator CP5, the sixth comparator CP6, or the seventh comparator CP7), and a predetermined determination period (a pulse signal output from the one-shot pulse generation circuit OS1) from the reference timing detected by the second detection unit. The synchronous rectifier element is turned on at the ON timing detected by the first detection section, provided that the pulse width is within the pulse width Ta). And a second control unit to turn on (pulse generator 11 and the drive circuit 12).
With this configuration, it is possible to determine whether to operate the synchronous rectifier element Q2 according to the level of the voltage fluctuation of the secondary winding Ns of the transformer T. Therefore, the release of the magnetic flux energy accumulated in the transformer T is completed. A malfunction of the synchronous rectifier element Q2 due to subsequent ringing can be prevented, and a good synchronous rectification operation can be realized even in a current discontinuous state where there is a zero current period while the primary side switching element Q1 is off. be able to.

  Further, according to the present embodiment, the second detection unit (second comparator CP2) detects a timing at which the polarity of the secondary winding Ns is inverted to a rectifiable voltage polarity as a reference timing.

  Further, according to the present embodiment, the first detector detects the on-timing by comparing the voltage across the synchronous rectifier Q2 with the turn-on reference voltage (offset voltage Vref1), and detects the second timing (the fifth detector). The comparator CP5) detects the reference timing by comparing the voltage across the synchronous rectifier element Q2 with a first reference voltage (offset voltage Vref5) different from the turn-on reference voltage.

  Furthermore, according to the present embodiment, a voltage divider (resistors R2, R3) for dividing the output voltage of the switching power supply device 1 to generate a resistor divided signal is provided, and the second detector (sixth comparator CP6) is provided. ) Detects the reference timing by comparing the voltage between both ends of the synchronous rectifier element Q2 with the resistance divided signal.

Further, according to the present embodiment, a series circuit including a capacitor C5 and a resistor R4 connected to both ends of the synchronous rectifier Q2 is provided.
The second detector (seventh comparator CP7) detects a reference timing by comparing a voltage at a connection point between the capacitor C5 and the resistor R4 in the series circuit with a second reference voltage (offset voltage Vref6).

Further, the present embodiment is a synchronous rectifier Q2 driving device that drives a synchronous rectifier Q2 that rectifies the voltage of the secondary winding Ns of the transformer T in the switching power supply 1, and includes a voltage across the synchronous rectifier Q2. Is compared with a turn-on reference voltage (offset voltage Vref1) to detect the on-timing of the synchronous rectifier Q2, and to compare the voltage across the synchronous rectifier Q2 with a turn-off reference voltage (offset voltage Vref2). A first detector (first comparator CP1) for detecting the off-timing of Q2, a period from the on-timing to the off-timing detected by the first detector as a synchronous rectification period, and an on-period of the synchronous rectifying element Q2 as 1 Generate a maximum on-time limit signal MOTG that limits the period to a period shorter than the synchronous rectification period before the cycle. Maximum on time generating section (maximum ON time generation circuit 13), and a control unit for turning off the synchronous rectifier Q2 on the basis of the maximum on-time limit signal MOTG (pulse generator 11 and the drive circuit).
With this configuration, the on-period of the synchronous rectifier element Q2 can be limited to a period shorter than the synchronous rectification period one cycle before by the maximum on-time restriction signal MOTG, so that the primary-side switching element Q1 starts operating. The operation of the synchronous rectifier element Q2 can be reliably stopped beforehand, and a good synchronous rectification operation is realized even in a current continuous state in which current flows continuously while the primary-side switching element Q1 is off. be able to.

  As described above, the present invention has been described with the specific embodiments. However, it is needless to say that the above embodiments are merely examples, and can be modified without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Switching power supply 2 Controller 3 Error amplifier 10, 10a, 10b, 10c Synchronous rectifier drive 11 Pulse generator 12 Drive 13 Maximum on-time generation circuits AND1, AND2 AND circuits C1, C2 Smoothing capacitors C3, C4, C5 CC1, CC2, CC3, CC4 Constant current circuit CP1 First comparator CP2 Second comparator CP3, CP4 Comparator CP5 Fifth comparator CP6 Sixth comparator CP7 Seventh comparator DB Rectifier circuit D1 Parasitic diodes FF1, FF2, FF3, FF4, FF5 Flip-flop NOT1, NOT2, NOT3 Inverting circuit NAND1 NAND circuit OR1, OR2 OR circuit OS1, OS2 One-shot pulse generating circuit PC1 Light emitting diode PC2 Light receiving transistor Q1 switching element Q2 synchronous rectifier Q3, Q5 charging switch Q4, Q6 discharging switch R1, R2, R3, R4 resistor T trans Np 1 winding Ns 2 winding

Claims (8)

A synchronous rectifier driving device that drives a synchronous rectifier that rectifies a voltage of a secondary winding of a transformer in a switching power supply,
A first detection unit that detects an on-timing of the synchronous rectifier based on a voltage between both ends of the synchronous rectifier;
A second detector for detecting a reference timing of a voltage change of the secondary winding;
A control unit that turns on the synchronous rectifying element at the on-timing detected by the first detection unit , on condition that the reference timing is detected within a predetermined determination period from the reference timing detected by the second detection unit; , A synchronous rectifier driving device.   2. The synchronous rectifier driving device according to claim 1, wherein the second detection unit detects, as the reference timing, a timing at which the polarity of the secondary winding is inverted to a rectifiable voltage polarity. 3. The first detector detects the on-timing by comparing a voltage across the synchronous rectifier with a turn-on reference voltage,
The synchronous rectifier according to claim 1, wherein the second detector detects the reference timing by comparing a voltage across the synchronous rectifier with a first reference voltage different from the turn-on reference voltage. Drive. A voltage divider that divides an output voltage of the switching power supply to generate a resistance voltage division signal,
2. The synchronous rectifier driving device according to claim 1, wherein the second detector detects the reference timing by comparing a voltage between both ends of the synchronous rectifier with the resistance divided signal. 3. It comprises a series circuit consisting of a capacitor and a resistor connected to both ends of the synchronous rectifier,
The synchronization according to claim 1, wherein the second detection unit detects the reference timing by comparing a voltage at a connection point between the capacitor and the resistor in the series circuit with a second reference voltage. Rectifier drive. A synchronous rectifier driving device that drives a synchronous rectifier that rectifies a voltage of a secondary winding of a transformer in a switching power supply,
The on-time of the synchronous rectifier is detected by comparing the voltage between both ends of the synchronous rectifier with a turn-on reference voltage, and the synchronous rectifier is turned off by comparing the voltage across the synchronous rectifier with a turn-off reference voltage. A first detector for detecting timing;
A second detector for detecting a reference timing of a voltage change of the secondary winding;
A maximum ON period in which a period from the ON timing to the OFF timing detected by the first detection unit is a synchronous rectification period, and an ON period of the synchronous rectifying element is limited to a period shorter than the synchronous rectification period one cycle before. A maximum on-time generator for generating a time limit signal,
The synchronous rectifier is turned on at the on-timing detected by the first detector , on condition that it is within a predetermined determination period from the reference timing detected by the second detector. A synchronous rectifying element driving device, comprising: a control unit that turns off the synchronous rectifying element based on a maximum on-time limit signal or the off timing. A synchronous rectifier driving method for driving a synchronous rectifier that rectifies a voltage of a secondary winding of a transformer in a switching power supply device,
A first detection unit that detects an on-timing of the synchronous rectifier based on a voltage across the synchronous rectifier;
A second detection unit that detects a reference timing of a voltage change of the secondary winding,
The control unit that controls the driving of the synchronous rectifying element is configured to detect the ON timing detected by the first detection unit on condition that the reference timing detected by the second detection unit is within a predetermined determination period. Wherein the synchronous rectifier is turned on. A synchronous rectifier driving device that drives a synchronous rectifier that rectifies a voltage of a secondary winding of a transformer in a switching power supply,
The first detector detects the on-timing of the synchronous rectifier by comparing the voltage across the synchronous rectifier with a turn-on reference voltage, and compares the voltage across the synchronous rectifier with a turn-off reference. Detecting the off-timing of the synchronous rectifier,
A second detection unit that detects a reference timing of a voltage change of the secondary winding,
A maximum on-time generation unit sets a period from the on-timing to the off-timing detected by the first detection unit as a synchronous rectification period, and an on period of the synchronous rectification element is shorter than the synchronous rectification period one cycle before. Generate a maximum on-time limit signal that limits the period,
The control unit that controls the driving of the synchronous rectifying element is configured to detect the ON timing detected by the first detection unit on condition that the reference timing detected by the second detection unit is within a predetermined determination period. Wherein the synchronous rectifier is turned on and the synchronous rectifier is turned off based on the maximum on-time limit signal or the off timing.

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