JP6653883B2 - Ga2O3-based transistor having field plate - Google Patents

Description

The present invention relates to a Ga ₂ O ₃ -based transistor having a field plate.

Gallium oxide (Ga ₂ O ₃ ) has a wide band gap of 4.5 to 4.9 eV, and the availability of a low-cost and high-quality melt growth substrate makes it possible to use next-generation high voltage and high voltage. Research is being conducted to realize output transistors. Ga ₂ O ₃ power devices are expected to exhibit a lower theoretical on-resistance limit at a given breakdown voltage than other mainstream power devices (Si, SiC, GaN).

Conventionally, a depletion-type Ga ₂ O ₃ MOSFET (metal-oxide-semiconductor field effect transistor) formed on an Fe-doped Ga ₂ O ₃ substrate has been known as a semiconductor element composed of a Ga ₂ O ₃ crystal. (For example, see Non-Patent Document 1).

Further, as a semiconductor element having a field plate structure, a Schottky barrier diode composed of a Ga ₂ O ₃ -based crystal and a MOSFET composed of a nitride semiconductor crystal are known (for example, see Patent Documents 1 and 2). ).

  According to the semiconductor device having the field plate structure disclosed in Patent Documents 1 and 2, etc., the electric field concentration near the electrodes can be reduced, and the breakdown voltage in the off state and the current collapse can be suppressed.

JP-A-2015-2343 JP 2015-56457 A

M. Higashiwaki et al., “Depletion-Mode Ga2O3 MOSFETs on β-Ga2O3 (010) Substrates with Si-Ion-Implanted Channel and Contacts”, Tech. Dig. IEEE Int. Electron Devices Meet., Pp. 28.7.1- 4, 2013.

An object of the present invention is to provide a field plate structure capable of improving a dielectric breakdown voltage in an off state and more effectively suppressing a current collapse caused by charge / discharge to an insulating film / semiconductor interface state. An object of the present invention is to provide a Ga ₂ O ₃ -based transistor.

One embodiment of the present invention provides the following Ga ₂ O ₃ -based transistors [1] to [ 3 ] in order to achieve the above object.

[1] A Ga ₂ O ₃ -based substrate, a Ga ₂ O ₃ -based crystal layer formed on the Ga ₂ O ₃ -based substrate, and a source region and a drain region formed in the Ga ₂ O ₃ -based crystal layer A source electrode and a drain electrode respectively connected to the source region and the drain region; a gate electrode formed on a region between the source region and the drain region of the Ga ₂ O ₃ based crystal layer; A dielectric film formed on a ₂ O ₃ -based crystal layer, wherein the gate electrode is formed on the Ga ₂ O ₃ -based crystal layer via a dielectric film, and a gate electrode is formed on a bottom of the gate electrode. A field plate extending from a position directly above the edge on the drain region side toward the drain region, wherein a thickness of the dielectric film is not less than 0.2 μm and not more than 0.8 μm ; How to extend The length of the direction is Ru der than 2 [mu] m, or the thickness of the dielectric film is at 0.2μm or more and 0.4μm or less, and the extending direction of the length of the field plate portion is 1μm or more, Ga ₂ O ₃ -based transistor.

[2] The Ga ₂ O _{3 according} to [1] , wherein a thickness of the dielectric film is 0.4 μm or less, and a length of the field plate portion in an extending direction is 2.5 μm or more. System transistor.

[3] extending direction of the length of the field plate portion is 3μm or more, _Ga 2 _{O 3} based transistor according to [1] or [2].

According to the present invention, Ga ₂ O having a field plate structure capable of improving a dielectric breakdown voltage in an off state and more effectively suppressing a current collapse due to charge / discharge to an insulating film / semiconductor interface state. _{A three-} system transistor can be provided.

FIG. 1 is a vertical sectional view of a Ga ₂ O ₃ -based transistor according to the embodiment. FIG. 2 is simulation data showing the relationship between the electric field strength at the bottom edge of the gate foot on the drain region side and L _F and T. FIG. 3 is simulation data showing the relationship between the electric field strength at the bottom edge of the field plate portion on the drain region side and L _F and T. FIG. 4 is a graph showing a simulation result of an electric field profile along an off-state channel. 5, DC output drain current - is a graph of drain voltage _{(I DS -V} DS) characteristics.

[Embodiment]
(Configuration of Ga ₂ O ₃ -based transistor)
FIG. 1 is a vertical sectional view of a Ga ₂ O ₃ based transistor 1 according to the embodiment. The Ga ₂ O ₃ based transistor 1 is a depletion type normally-on MOSFET having a field plate structure.

The Ga ₂ O ₃ -based transistor 1 includes a Ga ₂ O ₃ -based substrate 10, a Ga ₂ O ₃ -based crystal layer 12 formed on the Ga ₂ O ₃ -based substrate 10 via a Ga ₂ O ₃ -based buffer layer 11. , A source region 13 and a drain region 14 formed in the Ga ₂ O ₃ -based crystal layer 12, a source electrode 15 and a drain electrode 16 respectively connected to the source region 13 and the drain region 14, and a Ga ₂ O ₃ -based crystal. A gate electrode 19 formed on a region between the source region 13 and the drain region 14 of the layer 12 via a gate insulating film 17, a dielectric film 18 formed on the Ga ₂ O ₃ -based crystal layer 12, Having.

The gate electrode 19 includes a gate foot 20 penetrating the dielectric film 18 and a gate head 21 formed on the Ga ₂ O ₃ -based crystal layer 12 with the dielectric film 18 interposed therebetween. Here, the channel length direction of the length of the bottom surface of the gate electrode 19 (bottom surface of the gate foot 20) and L _G.

Gate head 21 includes a field plate portion 22 extending in the direction of drain region 14 from a position directly above the edge of drain electrode 14 at the bottom of gate electrode 19. Here, the extending direction of the length of the field plate 22 and L _F. Preferably the length L _F is 1μm or more, more preferably 2μm or more, more preferably 3μm or more.

  Providing the field plate portion 22 makes it possible to disperse the concentration of the electric field near the edge of the bottom of the gate foot 20 on the drain region 14 side and near the edge of the bottom of the field plate portion 22 on the drain region 14 side. it can. As a result, dielectric breakdown and current collapse in the off state can be effectively suppressed.

In addition, as shown in FIG. 1, the gate head 21 may include an extending portion 23 extending from a position directly above the edge of the bottom of the gate electrode 19 on the side of the source region 13 toward the source region 13. . Here, the extending direction of the length of the extending portion 23 and L _E.

The dielectric film 18 is made of a dielectric such as SiO ₂ . Here, the thickness of the dielectric film 18 is T. The thickness T of the dielectric film 18 determines the height of the gate head 21 and affects the effect of suppressing the electric field concentration. The thickness T is preferably larger than 0.1 μm, more preferably 0.2 μm or more and 0.8 μm or less.

The dielectric film 18 also serves as a surface passivation film for passivating surface dangling bonds in the vicinity of the channel of the Ga ₂ O ₃ -based crystal layer 12 to suppress surface charges and resulting current collapse.

The Ga ₂ O ₃ based substrate 10 is a substrate made of a Ga ₂ O ₃ based crystal. Here, a Ga ₂ O ₃ crystal refers to a Ga ₂ O ₃ crystal or a Ga ₂ O ₃ crystal to which an element such as Al or In is added. For example, a _Ga 2 _{O 3} crystal Al and In are added _{(Ga x Al y In (1} -x-y)) 2 O 3 (0 <x ≦ 1,0 ≦ y <1,0 <x + y ≦ 1) It may be a crystal. When Al is added, the band gap increases, and when In is added, the band gap narrows. The Ga ₂ O ₃ crystal has, for example, a β-type crystal structure. Further, the Ga ₂ O ₃ based substrate 10 may contain impurities such as Fe for increasing the resistance.

The Ga ₂ O ₃ -based substrate 10 is obtained by slicing a Ga ₂ O ₃ -based single crystal bulk grown by a melt growth method such as an FZ (Floating Zone) method or an EFG (Edge Defined Film Fed Growth) method, for example. It is manufactured by polishing.

The Ga ₂ O ₃ -based buffer layer 11 is an unintentionally-doped (UID) Ga ₂ O ₃ -based crystal film. The Ga ₂ O ₃ -based buffer layer 11 is formed by epitaxial crystal growth using MBE (Molecular Beam Epitaxy) or the like. The Ga ₂ O ₃ -based buffer layer 11 prevents impurities contained in the Ga ₂ O ₃ -based substrate 10 for increasing resistance from diffusing into the Ga ₂ O ₃ -based crystal layer 12 and suppresses compensation of channel charge. can do.

The Ga ₂ O ₃ -based crystal layer 12 is an n-type layer in which an n-type impurity such as Si is implanted in a UID-Ga ₂ O ₃ -based crystal film, and functions as a channel layer. The Ga ₂ O ₃ -based crystal layer 12 is formed by epitaxial crystal growth using MBE or the like. The n-type impurity is doped by an ion implantation method or the like.

Source region 13 and drain region 14 is a region formed by selectively doping the n-type impurity such as Si _Ga 2 _{O 3} system crystal layer 12, _Ga 2 _{O 3} system source in the crystal layer 12 The n-type region has a higher concentration than the region other than the region 13 and the drain region 14. This n-type impurity is doped by an ion implantation method or the like.

Here, a distance between the edge of the bottom of the gate electrode 19 on the source region 13 side and the source region 13 is defined as _LGS . The distance between the edge of the bottom of the gate electrode 19 on the drain region 14 side and the drain region 14 is defined as _LGD . This gate electrode has a laminated structure of, for example, Pt / Ti / Au.

  The source electrode 15 and the drain electrode 16 are electrodes that are ohmically connected to the source region 13 and the drain region 14, respectively, and have, for example, a stacked structure of Ti / Au.

The gate insulating film 17 is made of an insulating film such as Al ₂ O ₃ .

In the Ga ₂ O ₃ -based transistor 1, the gate electrode 19 includes a field plate portion, but the source electrode 15 may include a field plate portion. In this case, the source electrode 15 is formed on the dielectric film 18, and includes a field plate portion extending in the direction of the drain region 14 from a position just above the edge of the bottom of the source electrode 15 on the drain region 14 side. The length of the extending direction of the field plate portion, by setting the thickness T of the dielectric layer 18 similarly to Ga ₂ O ₃ based transistor 1, the same field plate effect and Ga ₂ O ₃ based transistor 1 Obtainable.

  The source electrode 15 may include a plurality of field plate portions stacked via a dielectric film. Further, both the gate electrode 19 and the source electrode 15 may include a field plate portion.

Further, the field plate structure of the Ga ₂ O ₃ based transistor 1 can be applied to another Ga ₂ O ₃ based transistor such as a HEMT (High Electron Mobility Transistor). Even in such a case, by setting the length of the field plate portion in the extending direction and the thickness of the dielectric film on which the field plate portion is mounted in the same manner as in the case of the Ga ₂ O ₃ -based transistor 1, the Ga ₂ O ₃ -based transistor 1 can be formed. A field plate effect similar to that of transistor 1 can be obtained. When applied to the HEMT, a gate insulating film such as the Ga ₂ O ₃ -based transistor 1 is not formed, and the gate foot may be directly connected to the Ga ₂ O ₃ -based crystal layer.

(Effects of Embodiment)
According to the above embodiment, the concentration of the electric field is adjusted by adjusting the length of the field plate portion 22 and the thickness of the dielectric film 18, that is, the height of the field plate portion 22 to a value suitable for the Ga ₂ O ₃ channel. Is effectively alleviated, and the breakdown voltage in the off state can be improved. At the same time, current collapse can be more effectively suppressed.

The evaluation results of the simulation of the electric field concentration relaxation effect of the Ga ₂ O ₃ based transistor 1 according to the above-described embodiment are shown below.

In this embodiment, a high-resistance Ga ₂ O ₃ substrate doped with Fe and having the (010) plane as a main surface was used as the Ga ₂ O ₃ -based substrate 10. In addition, a 0.9-μm thick UID-Ga ₂ O ₃ single crystal film was used as the Ga ₂ O ₃ -based buffer layer 11. Further, a UID-Ga ₂ O ₃ single crystal film having a thickness of 0.3 μm into which Si was ion-implanted was used as the Ga ₂ O ₃ -based crystal layer 12.

Further, an Al ₂ O ₃ film having a thickness of 20 nm was used as the gate insulating film 17. Further, an SiO ₂ film was used as the dielectric film 18.

_Further, L _G, and _{L GS,} 2μm _{L GD,} the _{L E} respectively, 5 [mu] m, 15 [mu] m, and 2 [mu] m. The length L _{F of} the field plate 22 in the extending direction and the thickness T of the dielectric film 18 were set to various values in each evaluation.

FIG. 2 is simulation data showing the relationship between the electric field strength at the bottom edge of the gate foot 20 on the drain region 14 side and L _F and T. In this simulation, the scope of 0.5~10μm the _{L F,} was varied respectively in a range of 0.1~0.8μm the T. The gate-source voltage V _GS was set to −40 V (off state), and the drain-source voltage V _DS was set to 1000 V.

2, the electric field strength by regardless the thickness T of the dielectric film 18, the extending direction of the field plate portion 22 the length L _F field strength is lowered by the above 1 [mu] m, and 2μm or more Shows that the electric field intensity is further reduced when the thickness is 3 μm or more.

Ga ₂ O ₃ to the electric field intensity generated dielectric breakdown is estimated to be approximately 8 MV / cm, if T is 0.4μm or less, by the _{L F} and above 1 [mu] m, at the edge vicinity of the gate foot 20 Dielectric breakdown can be prevented. Also, T is 0.8 [mu] m, the electric field strength when _{L F} is 1μm are greater than 8 MV / _cm, is made smaller than 1000V in a practical range of _{V DS,} it is possible to prevent the dielectric breakdown.

FIG. 3 is simulation data representing the relationship between the electric field strength at the bottom edge of the field plate portion 22 on the drain region 14 side and L _F and T. In this simulation, the scope of 0.5~10μm the _{L F,} was varied respectively in a range of 0.1~0.8μm the T. The gate-source voltage V _GS was set to −40 V (off state), and the drain-source voltage V _DS was set to 1000 V.

3, the extending direction of the field plate portion 22 regardless of the length L _F, to be greater than 0.1μm thickness T of the dielectric layer 18, the dielectric breakdown at the edge near the field plate portion 22 It is shown that it becomes easy to suppress.

  2 and 3, the electric field intensity near the edge of the field plate portion 22 increases when the thickness T of the dielectric film 18 is too small, and the electric field intensity near the edge of the gate foot 20 increases when the thickness T is too large. You can see that. 2 and 3, it can be said that the thickness T of the dielectric film 18 is particularly preferably 0.2 μm or more and 0.8 μm or less.

FIG. 4 is a graph showing a simulation result of an electric field profile along a channel in an off state. Figure 4 _{L E,} L G, the position of the _{L F} correspond to those in FIG. In this simulation, to secure the T to 0.4 .mu.m, changing the _{L F} in the range of 0～3Myuemu. The gate-source voltage V _GS was set to −40 V (off state), and the drain-source voltage V _DS was set to 1000 V.

FIG. 4 shows that when the field plate portion 22 is provided (L _F ≠ 0 μm), the concentration of the electric field is caused by the bottom edge of the gate foot 20 on the drain region 14 side and the drain region 14 at the bottom of the field plate portion 22. This indicates that the peak electric field intensity is reduced.

Figure 5 is based on a simulation result of the above, actually fabricated field plate with depletion type _Ga 2 _O 3 MOSFET DC output drain current - is a graph of drain voltage _{(I DS -V} DS) characteristics. In this device structure, was 0.4 .mu.m, the _{L F} and 2.5 [mu] m T. Also, the gate length _{L G} 2 [mu] m, 200 [mu] m gate width _{W G,} the gate - and the drain distance _{L GD} and 15 [mu] m - 5 [mu] m-source distance _{L GS,} gates. During the measurement, the gate-source voltage V _GS was changed in the range of + 4V to -55V.

FIG. 5 clearly shows current saturation and pinch-off representing the operation of a normal transistor, and proves that the Ga ₂ O ₃ -based transistor 1 operates normally as a transistor. When V _GS is in the range of −28 V to −55 V, the current is off without any leakage.

In addition, when V _GS was −55 V, the breakdown voltage V _br was 755 V. This is 80% or more higher than the 415 V for the structure without a field plate disclosed in 2013 by M. Higashiwaki et al.

  Although the embodiments and examples of the present invention have been described above, the present invention is not limited to the above embodiments and examples, and various modifications can be made without departing from the gist of the invention.

  The embodiments and examples described above do not limit the invention according to the claims. Also, it should be noted that not all combinations of the features described in the embodiment and the examples are necessarily essential to the means for solving the problems of the invention.

1 ... _Ga 2 _{O 3} based transistor, 12 ... _Ga 2 _{O 3} system crystal layer, 13 ... source region, 14 ... drain region, 15 ... Source electrode, 16 ... drain electrode, 18 ... dielectric film 19 ... gate electrode, 22 ... Field plate part

Claims (3)

A Ga ₂ O ₃ based substrate;
A Ga ₂ O ₃ -based crystal layer formed on the Ga ₂ O ₃ -based substrate;
A source region and a drain region formed in the Ga ₂ O ₃ -based crystal layer;
A source electrode and a drain electrode connected to the source region and the drain region, respectively;
A gate electrode formed on a region between the source region and the drain region of the Ga ₂ O ₃ -based crystal layer;
A dielectric film formed on the Ga ₂ O ₃ -based crystal layer;
Has,
The gate electrode is formed on the Ga ₂ O ₃ -based crystal layer via a dielectric film, and extends in a direction toward the drain region from a position immediately above a bottom edge of the gate electrode on the drain region side. Including the field plate part,
The thickness of the dielectric film is at 0.2μm or more and 0.8μm or less, and the extending direction of the length of the field plate portion is Ru der than 2 [mu] m, or the thickness of the dielectric layer 0. 2 μm or more and 0.4 μm or less, and the length of the field plate portion in the extending direction is 1 μm or more;
Ga ₂ O ₃ -based transistor. The thickness of the dielectric film is 0.4 μm or less,
The length of the field plate portion in the extending direction is 2.5 μm or more;
The Ga ₂ O ₃ transistor according to claim 1. The length of the field plate in the extending direction is 3 μm or more;
The Ga ₂ O ₃ -based transistor according to claim 1.

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