JP6651966B2 - Evaluation method and method of manufacturing semiconductor device - Google Patents

Description

  The present invention relates to an evaluation method and a method for manufacturing a semiconductor device.

A feedback capacitance Crss is known as one of the characteristics of a semiconductor element (for example, see Patent Document 1).
Patent Document 1 JP-A-2006-4935

  It is preferable that the feedback capacitance Crss of the semiconductor element is measured in advance. For example, if the feedback capacitance Crss of a plurality of semiconductor elements used for the upper and lower arms of the bridge circuit varies, the switching timing varies, which may cause a problem such as short-circuit of the upper and lower arms. However, it takes time to directly measure the feedback capacitance Crss of the semiconductor element.

  According to a first aspect of the present invention, there is provided an evaluation method for evaluating a feedback capacitance of a semiconductor device. The evaluation method may include a characteristic acquisition step. In the characteristic acquiring step, a first characteristic having a correlation with the feedback capacitance may be acquired. In the characteristic obtaining step, a second characteristic having a correlation with the feedback capacitance may be obtained. The evaluation method may include an evaluation step. In the evaluation stage, the feedback capacity may be evaluated based on the first characteristic and the second characteristic. The first characteristic may have a feedback capacitance and a positive phase, and the second characteristic may have a negative correlation with the feedback capacitance.

  The first characteristic may be a characteristic according to the breakdown voltage of the semiconductor element. The second characteristic may be the on-resistance of the semiconductor device. The first characteristic may be an avalanche voltage in a steady state. The first characteristic may be an avalanche voltage in a transient state. The first characteristic may be calculated from a plurality of avalanche voltages measured in different states of the semiconductor element. The first characteristic may be calculated from a first avalanche voltage in a transient state and a second avalanche voltage in a transient state measured by applying different drain currents. The first characteristic may be calculated from the avalanche voltage in a steady state and the avalanche voltage in a transient state. The first characteristic is that the first avalanche voltage in the transient state, the second avalanche voltage in the transient state measured by applying a drain current different from the first avalanche voltage, and the first avalanche voltage and the second avalanche voltage are measured. And the third avalanche voltage in the steady state measured by applying the same drain current as any one of the avalanche voltages. The first characteristic may be calculated from an avalanche voltage of the semiconductor element, and the second characteristic may be calculated from an avalanche voltage measured on the semiconductor element in a state different from the first characteristic. In the evaluation stage, the feedback capacity may be evaluated based on a ratio of the first characteristic and the second characteristic.

  In the characteristic acquiring step, the first characteristic and the second characteristic may be acquired for the plurality of semiconductor elements. In the evaluation stage, distribution information indicating the distribution of the ratio of the first characteristic and the second characteristic for each semiconductor element may be generated.

  The evaluation method may further include a screening step. In the selection stage, a normal distribution included in the distribution information may be detected, and an abnormal semiconductor element may be selected based on the detected normal distribution. In the selection step, abnormal semiconductor elements may be selected based on the standard deviation of the normal distribution.

  The distribution information may be a histogram. In the selection stage, when a plurality of peaks are included in the histogram, a peak including a peak having a higher frequency may be detected as a normal distribution. In the characteristic acquiring step, the first characteristic and the second characteristic may be acquired for each of the plurality of semiconductor elements formed on the wafer. The semiconductor element may have a super junction structure.

  In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided. The manufacturing method may include a characteristic acquiring step. In the characteristic obtaining step, a first characteristic having a positive correlation with the feedback capacitance of the semiconductor element may be obtained for each of the plurality of semiconductor elements. In the characteristic obtaining step, a second characteristic having a negative correlation with the feedback capacitance may be obtained for each of the plurality of semiconductor elements. The manufacturing method may include an evaluation step. In the evaluation stage, the feedback capacity may be evaluated based on the first characteristic and the second characteristic. The manufacturing method may include a screening step. In the selection step, a plurality of semiconductor elements may be selected based on the evaluation result in the evaluation step. The manufacturing method may include an assembling step. In the assembling step, a semiconductor device may be assembled using the plurality of semiconductor elements selected in the selecting step.

  The above summary of the present invention is not an exhaustive listing of all features of the present invention. Further, a sub-combination of these feature groups can also be an invention.

FIG. 4 is a diagram illustrating an example of an evaluation method for evaluating a feedback capacitance Crss of a semiconductor device according to one embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a semiconductor element 200 that is an example of an evaluation target. FIG. 2 is a schematic view showing an N-type column 22 and a P-type column 24 in the semiconductor device 200. FIG. 4 is a diagram illustrating a selection step of selecting a semiconductor element based on a histogram. FIG. 4 is a diagram illustrating an example of a flow of a manufacturing method of manufacturing a semiconductor device. FIG. 4 is a diagram illustrating an example of the voltage dependence of a feedback capacitance Crss in an SJ-MOSFET. FIG. 9 is a diagram illustrating the voltage dependence of the feedback capacitance Crss in the SJ-MOSFET in which the switching loss is reduced by reducing the concentration gradient of each column. FIG. 10 is a diagram illustrating an example of measurement results of avalanche voltage BVDSS in non-defective and defective semiconductor elements. FIG. 4 is a diagram illustrating an example of a first characteristic. FIG. 4 is a diagram illustrating an example of a first characteristic. FIG. 4 is a diagram illustrating an example of a first characteristic. FIG. 4 is a diagram illustrating an example of a first characteristic. FIG. 11 is a diagram illustrating a relationship between a ratio between a first characteristic BVDSS2 / BVDSS1 illustrated in FIG. 10 and a second characteristic RDS (on) illustrated in FIG. 1 and a feedback capacitance Crss. FIG. 10 is a diagram illustrating a relationship between a feedback capacitance Crss and a ratio between a first characteristic BVDSS1 illustrated in FIG. 9 and a second characteristic RDS (on) illustrated in FIG. 1. FIG. 12 is a diagram illustrating a relationship between a ratio of a first characteristic BVDSS3-BVDSS1 illustrated in FIG. 11 and a second characteristic RDS (on) illustrated in FIG. 1 to a feedback capacitance Crss. FIG. 3 illustrates an example of a semiconductor device 300.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all combinations of the features described in the embodiments are necessarily essential to the solution of the invention.

  FIG. 1 is a diagram illustrating an example of an evaluation method for evaluating a feedback capacitance Crss of a semiconductor device according to one embodiment of the present invention. As an example, the semiconductor element is a MOSFET having a super junction (SJ: Super Junction) structure. The feedback capacitance Crss of this example is a parasitic capacitance between the gate and the drain of the SJ-MOSFET.

  In the characteristic acquiring step S102, a first characteristic having a correlation with the feedback capacitance Crss and a second characteristic having a correlation with the feedback capacitance Crss are acquired. As an example, the first characteristic has a positive phase between the feedback capacitance Crss and the second characteristic has a negative correlation with the feedback capacitance Crss. A positive correlation indicates that the corresponding characteristic value has a tendency to increase when the feedback capacitance Crss increases, and a negative correlation indicates that the corresponding characteristic value decreases when the feedback capacitance Crss decreases. To have a tendency to do so.

  In the present example, the first characteristic is a characteristic according to the breakdown voltage of the semiconductor element. As an example, the first characteristic is the avalanche voltage BVDSS at which avalanche breakdown occurs in the semiconductor element. The avalanche voltage BVDSS is a drain-source voltage measured by applying a predetermined drain current to the semiconductor element with the gate-source of the semiconductor element short-circuited. The avalanche voltage BVDSS may be a voltage measured after the drain-source voltage is in a steady state, and may be a voltage measured in a transient state in which the drain-source voltage is transiently changed. Good. In the present example, the second characteristic is the on-resistance of the semiconductor element. More specifically, the on-resistance is the resistance RDS (on) between the source and the drain when the MOSFET is in the on state.

  FIG. 1 shows the results of plotting the relationship between the feedback capacitance Crss and the avalanche voltage BVDSS and the relationship between the feedback capacitance Crss and the on-resistance RDS (on) measured for a plurality of semiconductor elements. In the example of FIG. 1, the avalanche voltage BVDSS measured in the steady state is used. Unless otherwise described herein, the avalanche voltage BVDSS refers to the avalanche voltage BVDSS measured in a steady state. FIG. 1 shows distributions obtained by directly measuring the feedback capacitance Crss, avalanche voltage BVDSS, and on-resistance RDS (on) of the semiconductor element.

  The example of FIG. 1 shows the measurement results of the semiconductor elements formed on a plurality of wafers. A plurality of semiconductor elements are formed on one wafer. When manufacturing conditions change between wafers, the feedback capacitance Crss, the avalanche voltage BVDSS, and the on-resistance RDS (on) change for each wafer. FIG. 1 shows the measurement results of semiconductor elements included in a first wafer group manufactured under normal manufacturing conditions and a second wafer group manufactured under manufacturing conditions having a predetermined error. Specifically, a distribution with a smaller feedback capacitance Crss corresponds to the second wafer group, and a distribution with a larger feedback capacitance Crss corresponds to the first wafer group.

  As shown in FIG. 1, there is a positive correlation between the feedback capacitance Crss and the avalanche voltage BVDSS. Further, there is a negative correlation between the feedback capacitance Crss and the on-resistance RDS (on).

  Next, in the evaluation step S104, the feedback capacitance Crss is evaluated based on the first characteristic and the second characteristic. By using two characteristics having a correlation with the feedback capacitance Crss, the feedback capacitance Crss can be accurately evaluated. In some cases, it is conceivable that the characteristics cannot be separated by using only one of the first characteristic and the second characteristic. However, by calculating the two characteristics, the characteristic difference can be realized.

  As an example, in the evaluation step S104, the feedback capacitance Crss is evaluated based on the ratio of the first characteristic and the second characteristic. In this example, a histogram is generated that shows the distribution of the ratio between the avalanche voltage BVDSS and the on-resistance RDS (on) for each semiconductor element. A histogram is an example of distribution information. In the evaluation step S104, the product of the first characteristic and the second characteristic may be used, the sum of the first characteristic and the second characteristic may be used, or the difference between the first characteristic and the second characteristic may be used. Good.

  FIG. 1 shows a histogram with RDS (on) / BVDSS on the horizontal axis. In the histogram, the peak with smaller RDS (on) / BVDSS corresponds to the first wafer group, and the peak with larger RDS (on) / BVDSS corresponds to the second wafer group.

  From the histogram, the variation in the feedback capacitance Crss can be evaluated. Further, in the histogram, a semiconductor element deviating from a predetermined peak can be selected. The selection of semiconductor elements may be performed on a wafer basis, on a lot basis including a plurality of wafers, on an area basis within a wafer, or on a semiconductor element basis.

  Further, the semiconductor elements can be grouped for each peak in the histogram. By using the same group of semiconductor elements as the same circuit, it is possible to provide a circuit including semiconductor elements with small variations in the feedback capacitance Crss.

  In addition, information for associating the value of RDS (on) / BVDSS with the value of the feedback capacitance Crss is obtained in advance, and the value of the feedback capacitance Crss is estimated for each semiconductor device from the measurement result of RDS (on) / BVDSS. May be.

  Note that the first characteristic and the second characteristic are preferably measured for each semiconductor element formed on the wafer. Thus, the semiconductor device can be assembled while excluding abnormal products in advance. Therefore, failure detection after assembling the semiconductor device can be reduced, and the manufacturing cost can be reduced. However, the first characteristics and the second characteristics may be measured after the semiconductor element is sealed with a resin or the like to form a semiconductor chip.

  In the characteristic acquiring step S102, the state of the semiconductor element may be controlled so that the variation in the first and second characteristics with respect to the variation in the feedback capacitance Crss becomes more apparent. For example, the first characteristic and the second characteristic may be measured with a predetermined voltage or current applied to the semiconductor element. Specifically, the first characteristic and the second characteristic may be acquired in a state where a condition equal to or less than the absolute maximum rating is applied to the semiconductor element. The conditions below the absolute maximum rating include not only current and voltage but also withstand voltage, temperature and the like.

  FIG. 2 is a cross-sectional view illustrating a semiconductor device 200 which is an example of an evaluation target. The semiconductor element 200 of this example is an SJ-MOSFET. The semiconductor device 200 includes a semiconductor substrate 10, a gate electrode 12, a gate insulating film 14, a source electrode 28, and a drain electrode 30.

  The semiconductor substrate 10 is a semiconductor substrate such as silicon. On the back surface of the semiconductor substrate 10, a drain electrode 30 formed of a conductive material such as a metal is provided. In a region in contact with the drain electrode 30, an N + type drain region 26 having a higher concentration than the P type column 24 is formed.

  Inside the semiconductor substrate 10, P-type columns 24 and N-type columns 22 are formed alternately in a direction parallel to the front surface of the semiconductor substrate 10. N-type column 22 has a region exposed on the front surface of semiconductor substrate 10.

  The P-type column 24 is formed below the P-type base region 20. In a part of the base region 20, an N + type source region 16 and a P + type contact region 18 are formed. The source region 16 and the contact region 18 have regions exposed on the front surface of the semiconductor substrate 10. Source region 16 and contact region 18 are connected to source electrode 28.

  On the front surface of semiconductor substrate 10, gate electrode 12 is arranged above base region 20 sandwiched between source region 16 and N-type column 22. Gate electrode 12 may also extend above at least a portion of source region 16 and N-type column 22. A gate insulating film 14 is provided between the gate electrode 12, the semiconductor substrate 10, and the source electrode 28.

  When the semiconductor element 200 is off, the depletion layer spreads from the PN junction between the N-type column 22 and the P-type column 24, and the N-type column 22 is depleted. Thereby, the semiconductor element 200 has a large withstand voltage. When the semiconductor element 200 is turned on, a channel is formed in the base region 20 between the source region 16 and the N-type column 22, and the depletion layer in the N-type column 22 is reduced, so that the source-drain region is formed. Electric current flows.

  FIG. 3 is a schematic diagram showing the N-type column 22 and the P-type column 24 in the semiconductor device 200. Although the N-type column 22 and the P-type column 24 are formed with a substantially constant width, the widths of the N-type column 22 and the P-type column 24 may be non-uniform due to manufacturing problems and the like. For example, a projection 32 may be formed in which the P-type column 24 projects toward the N-type column 22.

  As an example, the N-type column 22 and the P-type column 24 are formed by laminating an N-type layer and a P-type layer by a predetermined thickness from the back side of the semiconductor substrate 10. However, if the position of the N-type layer or the P-type layer is shifted in a predetermined layer due to a shift of a mask pattern or the like, the widths of the N-type column 22 and the P-type column 24 become uneven.

  When the widths of the P-type column 24 and the N-type column 22 change, the feedback capacitance Crss changes. However, in order to measure the feedback capacitance Crss of the semiconductor elements formed on the wafer, it is necessary to introduce a capacitance measuring device into the production line and connect each of the semiconductor elements to the capacitance measuring device in order. For this reason, the device cost and the measurement time increase. Further, it is not easy for the capacitance measuring device to accurately measure the fine capacitance of each semiconductor element due to the influence of the measurement environment such as wiring.

  On the other hand, the avalanche voltage BVDSS and the on-resistance RDS (on) of the semiconductor element 200 can be measured in a shorter time than the feedback capacitance Crss. Also, the avalanche voltage BVDSS and the on-resistance RDS (on) are often measured even in existing manufacturing processes. Therefore, these characteristics can often be measured without adding an apparatus and a measurement step.

  When the distance W1 between the P-type columns 24 decreases to W2, the impurity concentration balance of the P-type columns 24 and the N-type columns 22 changes, and the breakdown voltage (avalanche voltage BVDSS) decreases. In addition, since the impurity concentration of the N drift region decreases, the drift resistance increases and the on-resistance RDS (on) increases. Generally, the avalanche voltage BVDSS and the on-resistance RDS (on) each have a normal distribution.

  However, it is not always easy to evaluate the distribution of the feedback capacitance Crss based on only one of the measurement results of the avalanche voltage BVDSS and the on-resistance RDS (on). In FIG. 1, two groups having relatively large differences in the feedback capacitances Crss are plotted for the sake of simplicity, but in practice, the difference in the feedback capacitances Crss may not be so large. In this case, if only one of the measurement results of the avalanche voltage BVDSS and the on-resistance RDS (on) is used, the distribution of the two groups having different feedback capacitances Crs overlaps greatly, and the variation of the feedback capacitance Crss is accurately evaluated. Can not.

  On the other hand, both of the two characteristics (for example, the avalanche voltage BVDSS and the on-resistance RDS (on), or the plurality of avalanche voltages BVDSS measured in semiconductor devices in different states) having a correlation with the feedback capacitance Crss. By using the measurement results, the distribution of the feedback capacitance Crss can be accurately evaluated. As an example, the ratio RDS (on) / BVDSS between the on-resistance and the withstand voltage has a strong correlation with the feedback capacitance Crss, so that a distribution with a small standard deviation can be obtained. As a result, the respective distributions for the two groups having different feedback capacitances Crss become steeper, so that it becomes easier to separate the respective distributions. According to the manufacturing method of this example, the feedback capacitance Crss can be evaluated with high accuracy, in a short time, and at low cost.

  The first characteristic and the second characteristic used for evaluating the feedback capacitance Crss are not limited to the avalanche voltage BVDSS and the on-resistance RDS (on). Any characteristic having a correlation with the feedback capacitance Crss can be used as the first characteristic and the second characteristic as appropriate. For example, a characteristic such as an on-voltage of a semiconductor element may be used as one of the first characteristic and the second characteristic.

  Further, the feedback capacitance Crss may be evaluated by a method other than using the ratio of the first characteristic and the second characteristic. As an example, the case where the feedback capacitance Crss is evaluated using the product of the first characteristic and the second characteristic may be considered.

  The target for evaluating the feedback capacitance Crss is not limited to the SJ-MOSFET. If the element has two characteristics having different polarities of correlation with respect to the feedback capacitance, the feedback capacitance Crss can be evaluated by the above-described method. In addition, the feedback capacitance Crss can be similarly accurately evaluated by using a difference between two characteristics having different polarities of the correlation with respect to the feedback capacitance Crss. Further, even if a product or a sum of two characteristics having the same polarity between phases with respect to the feedback capacitance Crss is used, the feedback capacitance Crss can be similarly accurately evaluated.

  FIG. 4 is a diagram illustrating a selection step of selecting a semiconductor element based on a histogram. The histogram of the present example has a first peak 40 and a second peak 50. In the selection stage of this example, a normal distribution included in the histogram is detected based on the histogram. Then, an abnormal semiconductor element is selected based on the detected normal distribution.

  As an example, a peak having the lowest RDS (on) / BVDSS among a plurality of peaks may be detected as a normal distribution. The peak corresponds to the group having the largest return capacity Crss. Further, a peak including a peak having a higher frequency may be detected as a normal distribution among a plurality of peaks. In the example of FIG. 4, the first peak 40 is detected as a normal distribution.

  Further, a semiconductor element not included in the first peak 40 may be selected as an abnormal product. Whether it is included in the first peak 40 may be determined based on the standard deviation σ of the first peak 40. For example, a semiconductor element not included within 1σ from the average value of the first peak 40 may be selected as an abnormal product, and a semiconductor element not included within 3σ may be selected as an abnormal product, and not included within 6σ. The semiconductor element may be sorted out as an abnormal product.

  Further, when a plurality of peaks are included in the histogram, a semiconductor element not included in any of the peaks may be selected as an abnormal product. In this case, the plurality of semiconductor elements are grouped for each peak. As a result, the number of semiconductor elements excluded as abnormal products can be reduced, and variations in the feedback capacitance Crss within the group can be suppressed.

  FIG. 5 is a diagram illustrating an example of a flow of a manufacturing method for manufacturing a semiconductor device. First, in the characteristic acquiring step S102, the first characteristic and the second characteristic are acquired for each of the plurality of semiconductor elements. The characteristic acquisition step S102 is the same as the characteristic acquisition step S102 described with reference to FIGS.

  Next, in the evaluation step S104, the feedback capacitance Crss is evaluated based on the first characteristic and the second characteristic. The evaluation step S104 is the same as the evaluation step S104 described with reference to FIGS.

Next, in the selection step S106, a plurality of semiconductor elements are selected based on the evaluation result in the evaluation step S104. The selection step S106 is the same as the selection step described with reference to FIG. In the selection step S106, a plurality of semiconductor elements whose variation in the feedback capacitance Crss is equal to or less than a predetermined value are selected. For example, any peak is selected in the histogram shown in FIG. Further, a plurality of semiconductor elements having a variation within σ / 2 may be further selected, with the standard deviation of the selected peak being σ, and a plurality of semiconductor elements having a variation within σ / 4 may be further selected. .
In the selection step S106, as an example, a plurality of semiconductor elements whose variation in the feedback capacitance Crss is equal to or less than a predetermined value are selected. However, the present invention is not limited to this, and the variation in the feedback capacitance Crss is selected in an appropriate range. Sort a plurality of semiconductor elements.

  Next, in an assembly step S108, a semiconductor device is assembled using the plurality of semiconductor elements selected in the selection step S106. The semiconductor device may be an electric circuit including a plurality of semiconductor elements. According to such a manufacturing method, it is possible to manufacture a semiconductor device using a plurality of semiconductor elements having small variations in the feedback capacitance Crss.

  FIG. 6 is a diagram illustrating an example of the voltage dependency of the feedback capacitance Crss in the SJ-MOSFET. In the SJ-MOSFET, in order to improve the trade-off relation between the turn-off loss and the turn-off dv / dt, a concentration gradient may be provided in each column to suppress the depletion of the substrate. In this case, the dependence of the feedback capacitance Crss on the drain-source voltage VDS becomes gentle as shown in FIG.

  However, when a concentration gradient is provided in each column, the feedback capacitance Crss increases, and the switching loss also increases. For this reason, in recent years when the necessity of power saving has increased, the concentration gradient of each column may be reduced. As a result, the VDS dependence of the feedback capacitance Crss becomes stronger, and the feedback capacitance Crss fluctuates sharply with respect to the VDS fluctuation.

  FIG. 7 is a diagram illustrating the voltage dependence of the feedback capacitance Crss in the SJ-MOSFET in which the switching gradient is reduced by reducing the concentration gradient of each column. As described above, when the concentration gradient of each column is reduced, the waveform of the feedback capacitance Crss becomes steep. Therefore, the variation of the feedback capacitance Crss among a plurality of semiconductor elements increases.

  When a plurality of semiconductor elements having large variations in the feedback capacitance Crss are incorporated in the same semiconductor device, a deviation in the feedback capacitance Crss may cause a shift in switching timing or the like, and the semiconductor device may malfunction. On the other hand, in the semiconductor device manufactured by the manufacturing method shown in FIG. 5, a semiconductor device can be manufactured using a plurality of semiconductor elements having small variations in the feedback capacitance Crss, so that malfunction in the semiconductor device can be reduced.

  Note that, in the examples shown in FIGS. 8 to 15, the case where the feedback capacitance Crss of the defective product is smaller than the feedback capacitance Crss of the regular product is described. In this case, the peak having the highest RDS (on) / BVDSS in the histogram shown in FIG. 4 may be detected as a normal distribution.

  FIG. 8 is a diagram illustrating an example of measurement results of the avalanche voltage BVDSS in the non-defective and defective semiconductor elements. In FIG. 8, the abscissa indicates the elapsed time from the start of application of a predetermined drain current to the semiconductor element whose gate and source are short-circuited, and the ordinate indicates the avalanche voltage BVDSS (drain-source voltage).

  When a drain current is applied to a semiconductor element whose gate and source are short-circuited, the output capacitance Coss is charged by the drain current, and the avalanche voltage BVDSS gradually increases. The output capacitance Coss is the sum of the drain-source capacitance and the gate-drain capacitance. Since the feedback capacitance Crss is a gate-drain capacitance, as the feedback capacitance Crss becomes smaller, the output capacitance Coss also becomes smaller. Therefore, when the feedback capacitance Crss becomes small, the rising of the avalanche voltage BVDSS becomes steep.

  Due to the difference in the rising speed of the avalanche voltage BVDSS, there is a difference in the avalanche voltage BVDSS in the transient state between the non-defective product and the defective product. For example, assuming that the difference between the avalanche voltage BVDSS at the elapsed time T1 shown in FIG. 8 and the avalanche voltage BVDSS at the elapsed time T2 is ΔV, the difference voltage ΔV1 of the non-defective product is larger than the difference voltage ΔV2 of the defective product. In FIG. 8, the predetermined elapsed time in the transient state is T1, and the predetermined elapsed time in the steady state is T2. For example, T1 is about 2 ms, and T2 is about 20 ms. The transient state refers to a state in which the output capacitance Coss is charged by the drain current and the avalanche voltage BVDSS is increasing, and the steady state refers to a state in which the charging of the output capacitance Coss is completed and the avalanche voltage BVDSS becomes substantially constant. Point.

  In the evaluation method for evaluating the feedback capacitance Crss, a variation in the avalanche voltage BVDSS in a transient state may be used. The first characteristic may be the avalanche voltage BVDSS in the transient state. The first characteristic may be calculated from a plurality of avalanche voltages BVDSS measured in different states of the semiconductor element. The state of the semiconductor element may refer to the above-mentioned transient state and steady state. That is, the first characteristic may be calculated from the avalanche voltage BVDSS in the transient state and the avalanche voltage BVDSS in the steady state. The first characteristic may be calculated by any one of a ratio, a product, a difference, and a sum of these two avalanche voltages BVDSS. As a result, the difference in the return capacitance Crss between the good product and the defective product can be made more remarkable.

  Further, the state of the semiconductor element can be changed by the drain current id applied to the semiconductor element. That is, the first characteristic may be calculated from a plurality of avalanche voltages measured by applying different drain currents. In this case, the respective avalanche voltage is measured during the transient state. By measuring the avalanche voltage BVDSS in the transient state by changing the drain current for charging the output capacitance Coss, the difference between the feedback capacitance Crss of the good product and the defective product can be made more remarkable.

  Also, in the examples shown in FIGS. 1 to 7, the example in which the feedback capacitance Crss is evaluated using the on-resistance RDS (on) has been described, but in other examples, the feedback without using the on-resistance RDS (on) is performed. The capacity Crss may be evaluated. For example, the first characteristic may be calculated from the avalanche voltage BVDSS of the semiconductor element, and the second characteristic may be calculated from the avalanche voltage BVDSS measured on the semiconductor element in a state different from the first characteristic.

  FIG. 9 is a diagram illustrating an example of the first characteristic. The first characteristic of the present example is the first avalanche voltage BVDSS1 in the transient state. The first avalanche voltage BVDSS1 of this example was measured under the conditions of drain current id = 250 μA and elapsed time T1. In FIG. 9, the group with the smaller feedback capacitance Crss is a defective product, and the group with the larger feedback capacitance Crss is a good product. The feedback capacitance Crss may be evaluated based on the first avalanche voltage BVDSS1 shown in FIG. 9 and the RDS (on) shown in FIG.

  FIG. 10 is a diagram illustrating an example of the first characteristic. The first characteristic of the present example is calculated from two avalanche voltages BVDSS measured at the same elapsed time T in the transient state while changing the drain current. More specifically, the first characteristics include a first avalanche voltage BVDSS1 measured under the condition of drain current id = 250 μA and elapsed time T1, and a second avalanche voltage BVDSS1 measured under the condition of drain current id = 1mA and elapsed time T1. This is a ratio BVDSS2 / BVDSS1 to the avalanche voltage BVDSS2. The feedback capacity Crss may be evaluated based on BVDSS2 / BVDSS1 shown in FIG. 10 and RDS (on) shown in FIG.

  Also, the feedback capacitance Crss may be evaluated using the first avalanche voltage BVDSS1 as the first characteristic and the second avalanche voltage BVDSS2 as the second characteristic. As an example, the feedback capacitance Crss may be evaluated from BVDSS2 / BVDSS1, without using the measurement result of RDS (on).

  FIG. 11 is a diagram illustrating an example of the first characteristic. The first characteristic of this example is calculated from two avalanche voltages BVDSS measured at different elapsed times without changing the drain current. One avalanche voltage BVDSS is measured in a transient state, and the other avalanche voltage BVDSS is measured in a steady state.

  More specifically, the first characteristic is a first avalanche voltage BVDSS1 measured under the condition of drain current id = 250 μA and elapsed time T1, and a third characteristic measured under the condition of drain current id = 250 μA and elapsed time T2. The difference from the avalanche voltage BVDSS3 is BVDSS3-BVDSS1. The feedback capacity Crss may be evaluated based on BVDSS3-BVDSS1 shown in FIG. 11 and RDS (on) shown in FIG.

  Further, the feedback capacitance Crss may be evaluated using the first avalanche voltage BVDSS1 as the first characteristic and the third avalanche voltage BVDSS3 as the second characteristic. As an example, the feedback capacitance Crss may be evaluated from BVDSS3-BVDSS1, without using the measurement result of RDS (on).

  FIG. 12 is a diagram illustrating an example of the first characteristic. The first characteristic of this example is that the first avalanche voltage BVDSS1 in the transient state and the second avalanche voltage BVDSS2 in the transient state measured by applying a drain current different from the first avalanche voltage BVDSS1, And the third avalanche voltage BVDSS3 in the steady state, which is measured by applying the same drain current as one of the avalanche voltage BVDSS1 and the second avalanche voltage BVDSS2.

  More specifically, the first characteristic is a product of the first characteristic BVDSS2 / BVDSS1 shown in FIG. 10 and the first characteristic BVDSS3-BVDSS1 shown in FIG. The feedback capacitance Crss may be evaluated based on BVDSS2 × (BVDSS3-BVDSS1) / BVDSS1 shown in FIG. 12 and RDS (on) shown in FIG.

  Further, the feedback capacitance Crss may be evaluated using BVDSS2 / BVDSS1 shown in FIG. 10 as the first characteristic and BVDSS3-BVDSS1 shown in FIG. 11 as the second characteristic. As an example, the feedback capacitance Crss may be evaluated from BVDSS2 × (BVDSS3-BVDSS1) / BVDSS1, without using the measurement result of RDS (on).

  FIG. 13 is a diagram showing the relationship between the feedback capacitance Crss and the ratio of the first characteristic BVDSS2 / BVDSS1 shown in FIG. 10 to the second characteristic RDS (on) shown in FIG. By calculating the ratio between BVDSS2 / BVDSS1 and RDS (on), it can be seen that the group of regular products and the group of error products are separated on the vertical axis. For this reason, the regular product and the error product can be accurately separated.

  FIG. 14 is a diagram illustrating the relationship between the feedback capacitance Crss and the ratio of the first characteristic BVDSS1 illustrated in FIG. 9 to the second characteristic RDS (on) illustrated in FIG. Also in this example, it is possible to accurately separate the regular product from the error product.

  FIG. 15 is a diagram showing the relationship between the feedback capacitance Crss and the ratio of the first characteristic BVDSS3-BVDSS1 shown in FIG. 11 to the second characteristic RDS (on) shown in FIG. Also in this example, it is possible to accurately separate the regular product from the error product.

  In the examples shown in FIGS. 9 to 15, the difference between the characteristics may be used instead of the ratio of the characteristics, and the sum of the characteristics may be used instead of the product of the characteristics. Alternatively, the ratio of each characteristic may be used.

  FIG. 16 is a diagram illustrating an example of the semiconductor device 300. The semiconductor device 300 is a three-phase inverter circuit provided between the power supply 210 and the load 220. The load 220 is, for example, a three-phase motor. The semiconductor device 300 converts the power supplied from the power supply 210 into a three-phase signal (AC voltage) and supplies it to the load 220.

  The semiconductor device 300 has three bridges corresponding to three-phase signals. Each bridge has an upper arm 152 and a lower arm 154 provided in series between the positive wiring and the negative wiring. Each arm is provided with one or more MOSFETs 202. Instead of the MOSFET 202, a combination of a transistor and a diode such as FWD may be used. A signal of each phase is output from a connection point between the upper arm 152 and the lower arm 154.

  If the variation of the feedback capacitance Crss in the MOSFET 202 in each arm is large, the MOSFETs 202 in the upper arm 152 and the lower arm 154 may be turned on at the same time, and the upper arm 152 and the lower arm 154 may be short-circuited. On the other hand, the plurality of MOSFETs 202 in the semiconductor device 300 of the present example are selected by the method described with reference to FIGS. Therefore, the variation of the feedback capacitance Crss in the plurality of MOSFETs 202 can be reduced, and malfunctions such as current imbalance and arm short-circuit during parallel use can be suppressed.

  As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is apparent to those skilled in the art that various changes or improvements can be made to the above embodiment. It is apparent from the description of the appended claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of processes such as operations, procedures, steps, and steps in the apparatuses, systems, programs, and methods shown in the claims, the description, and the drawings is particularly “before” or “before”. It should be noted that the output can be realized in any order as long as the output of the previous process is not used in the subsequent process. Even if the operation flow in the claims, the specification, and the drawings is described using “first”, “next”, or the like for convenience, it means that it is essential to implement in this order. Not something.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 12 ... Gate electrode, 14 ... Gate insulating film, 16 ... Source region, 18 ... Contact region, 20 ... Base region, 22 ... N-type column , 24 ... P-type column, 26 ... Drain region, 28 ... Source electrode, 30 ... Drain electrode, 32 ... Protrusion, 40 ... Mine, 50 ... Mine, 200 ... Semiconductor element, 152 ... Upper arm, 154 ... Lower arm, 202 ... MOSFET, 210 ... Power supply, 220 ... Load, 300 ... Semiconductor device

Claims (17)

An evaluation method for evaluating a feedback capacitance of a semiconductor element,
A characteristic acquisition step of directly measuring and acquiring a first characteristic having a correlation with the feedback capacitance and a second characteristic having a correlation with the feedback capacitance;
An evaluation step of evaluating the feedback capacitance based on the first characteristic and the second characteristic. The evaluation method according to claim 1, wherein the first characteristic is a characteristic according to a withstand voltage of the semiconductor element, and the second characteristic is an on-resistance of the semiconductor element. The evaluation method according to claim 2, wherein the first characteristic is an avalanche voltage in a steady state. An evaluation method for evaluating a feedback capacitance of a semiconductor element,
A characteristic acquiring step of acquiring a first characteristic having a correlation with the feedback capacitance and a second characteristic having a correlation with the feedback capacitance;
An evaluation step of evaluating the feedback capacitance based on the first characteristic and the second characteristic;
With
The first property is Ri avalanche voltage der in the transient state,
The evaluation method , wherein the second characteristic is an on-resistance of the semiconductor element . An evaluation method for evaluating a feedback capacitance of a semiconductor element,
A characteristic acquiring step of acquiring a first characteristic having a correlation with the feedback capacitance and a second characteristic having a correlation with the feedback capacitance;
An evaluation step of evaluating the feedback capacitance based on the first characteristic and the second characteristic;
With
The first characteristic is calculated from a plurality of avalanche voltages measured by the semiconductor device in different states ,
The evaluation method , wherein the second characteristic is an on-resistance of the semiconductor element . The evaluation method according to claim 5, wherein the first characteristic is calculated from a first avalanche voltage in a transient state and a second avalanche voltage in a transient state, which are measured by applying different drain currents. The evaluation method according to claim 5, wherein the first characteristic is calculated from an avalanche voltage in a steady state and an avalanche voltage in a transient state. The first characteristic is:
A first avalanche voltage in a transient state;
A second avalanche voltage in a transient state measured by applying a drain current different from the first avalanche voltage, and
The evaluation method according to claim 5, wherein the third avalanche voltage in a steady state is measured by applying the same drain current as one of the first avalanche voltage and the second avalanche voltage. An evaluation method for evaluating a feedback capacitance of a semiconductor element,
A characteristic acquiring step of acquiring a first characteristic having a correlation with the feedback capacitance and a second characteristic having a correlation with the feedback capacitance;
An evaluation step of evaluating the feedback capacitance based on the first characteristic and the second characteristic;
With
The first characteristic is calculated from an avalanche voltage of the semiconductor device,
The evaluation method , wherein the second characteristic is calculated from an avalanche voltage measured by the semiconductor element in a state different from the first characteristic . An evaluation method for evaluating a feedback capacitance of a semiconductor element,
A characteristic acquiring step of acquiring a first characteristic having a correlation with the feedback capacitance and a second characteristic having a correlation with the feedback capacitance;
An evaluation step of evaluating the feedback capacitance based on the first characteristic and the second characteristic;
With
In the evaluation step, an evaluation method for evaluating the feedback capacitance based on a ratio of the first characteristic and the second characteristic . An evaluation method for evaluating a feedback capacitance of a semiconductor element,
A characteristic acquiring step of acquiring a first characteristic having a correlation with the feedback capacitance and a second characteristic having a correlation with the feedback capacitance;
An evaluation step of evaluating the feedback capacitance based on the first characteristic and the second characteristic;
With
In the characteristic acquiring step, the first characteristic and the second characteristic are acquired for a plurality of the semiconductor elements,
In the evaluation step, an evaluation method for generating distribution information indicating a distribution of a ratio of the first characteristic and the second characteristic for each of the semiconductor elements . The evaluation method according to claim 11, further comprising a detecting step of detecting a normal distribution included in the distribution information and selecting an abnormal semiconductor element based on the detected normal distribution. The evaluation method according to claim 12, wherein in the selecting step, the abnormal semiconductor element is selected based on a standard deviation of the normal distribution. The distribution information is a histogram,
The evaluation method according to claim 13, wherein, in the selecting step, when the histogram includes a plurality of peaks, a peak including a peak having a higher frequency is detected as the normal distribution. The evaluation method according to any one of claims 1 to 14, wherein in the characteristic acquiring step, the first characteristic and the second characteristic are acquired for each of the plurality of semiconductor elements formed on a wafer. . The evaluation method according to claim 1, wherein the semiconductor element has a super junction structure. A method for manufacturing a semiconductor device, comprising:
For each of the plurality of semiconductor elements, a first characteristic having a correlation with the feedback capacitance of the semiconductor element, and a characteristic acquisition step of directly measuring and acquiring a second characteristic having a correlation with the feedback capacitance,
An evaluation step of evaluating the feedback capacitance based on the first characteristic and the second characteristic;
A selecting step of selecting the plurality of semiconductor elements based on an evaluation result in the evaluating step;
An assembling step of assembling the semiconductor device using the plurality of semiconductor elements selected in the selecting step.

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