JP6645843B2 - Wireless receiving apparatus and wireless receiving method - Google Patents

Description

  The present invention relates to a wireless receiving device and a wireless receiving method.

  2. Description of the Related Art In recent years, an information communication system such as VICS (Vehicle Information and Communication System), which superimposes traffic information indicating traffic congestion information and accident information on an FM radio broadcast signal and transmits the signal, has been used. In such an information communication system, reception is performed by a wireless receiving device mounted on a mobile body such as a vehicle. Therefore, the propagation state of the radio wave changes according to the change in the positional relationship with the base station due to the movement. Therefore, such a radio receiving apparatus acquires an RSSI (Received Signal Strength Indication) value indicating a signal strength (electric field strength) of a received signal, and performs tuning in accordance with a frequency (channel) at which an RSSI value equal to or higher than a certain level is obtained. While receiving the signal.

  Further, the wireless receiving apparatus is provided with a gain control circuit that controls the gain of the amplifier according to the signal level of the received signal. The gain control circuit increases the gain to improve the signal-to-noise ratio when the signal level of the received signal is low, and distorts the signal generated in the receiver when the signal level is high. Is controlled to reduce the gain in order to reduce. For this reason, the wireless receiver is provided with a detection circuit that detects a received signal and detects a signal level.

  In an information communication system such as VICS (registered trademark), a wireless receiving apparatus uses an RSSI value to determine whether the signal strength of a received signal is at a level at which traffic information or the like can be received. Therefore, the RSSI circuit that acquires the RSSI value targets a range of low signal strength as a detection target. On the other hand, the detection circuit is a circuit that detects a signal level for performing gain control, and therefore detects a high signal strength range. Therefore, a wireless receiving apparatus in which an RSSI circuit and a detection circuit are separately provided has been proposed (for example, Patent Document 1).

JP 2001-285209 A

  Since the output of the RSSI circuit is an analog value, the output is converted to a digital value by an ADC (Analog to Digital Converter) circuit and then stored in a storage area as RSSI data. Further, since the output of the detection circuit is also an analog value, conversion to a digital value is performed by an ADC (Analog to Digital Converter) circuit. Therefore, as described above, in a radio receiving apparatus in which the RSSI circuit and the detection circuit are separately provided, two ADCs corresponding to each of the two circuits are required. For this reason, there is a problem that the area of the semiconductor integrated circuit constituting the receiving circuit increases.

  In order to solve the above problems, an object of the present invention is to provide a radio receiving apparatus and a radio receiving method that can obtain digital values of outputs of an RSSI circuit and a detection circuit while suppressing the circuit size of the receiving circuit. .

A wireless receiving apparatus according to the present invention includes a variable gain circuit that changes and outputs an amplitude of an input signal with a gain according to a gain control signal, and passes a signal component of a predetermined frequency band among output signals of the variable gain circuit. A band-pass filter to be passed, and a first signal strength for obtaining a first detection value by detecting a received electric field strength of the passed signal when a signal strength of the passed signal passing through the band-pass filter is less than a reference signal strength. A detection circuit, a second signal strength detection circuit for detecting a signal amplitude value of the pass signal and obtaining a second detection value when a signal strength of the passed signal is equal to or greater than the reference signal strength, and An analog-to-digital converter for converting a detection value or the second detection value to a digital value, and one of the first and second signal strength detection circuits and the analog-to-digital converter are switchably connected. A changeover switch that supplies the first detection value or the second detection value to the analog-to-digital converter, a changeover control unit that controls the changeover of the changeover switch, and a digital value converted by the analog-to-digital converter. The gain control signal is generated based on a storage area for storing the first detection value and the second detection value converted into a digital value by the analog-to-digital converter, and the gain in the variable gain circuit is controlled. And a gain control circuit.

A radio receiving method according to the present invention includes the steps of: obtaining an output signal by changing an amplitude of an input signal by a gain according to a gain control signal; and passing a signal component of a predetermined frequency band out of the output signal. Obtaining a first detection value by detecting a reception electric field intensity of the passing signal when the signal intensity of the passing signal is less than a reference signal intensity; and A step of detecting a signal amplitude value of the passing signal to obtain a second detection value when the signal intensity is equal to or more than a signal strength; and selectively switching one of the first detection value and the second detection value. Converting the first detection value or the second detection value into a digital value in accordance with the switching, storing the first detection value converted into a digital value, and converting the digital value into a digital value. Generating said gain control signal based on the second detection value, characterized in that it comprises a.

  According to the present invention, it is possible to obtain digital values of the outputs of the RSSI circuit and the detection circuit while suppressing the circuit scale of the receiving circuit.

FIG. 3 is a block diagram illustrating a configuration of a receiving circuit in the wireless receiving device of the present invention. FIG. 3 is a diagram schematically illustrating a relationship between an output (a) of an RSSI circuit and an output (b) of a detection circuit with respect to a received signal strength. FIG. 3 is a diagram illustrating a configuration of a SW circuit. 6 is a time chart illustrating an operation of a SW switching control signal, a gain control signal, an ADC, and a logic circuit. FIG. 9 is a block diagram illustrating a configuration of a receiving circuit according to a second embodiment. 9 is a time chart illustrating a SW switching control signal and a gain control signal, and operations of an ADC and a logic circuit according to a second embodiment. FIG. 13 is a block diagram illustrating a configuration of a receiving circuit according to a third embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a receiving circuit 10 of a wireless receiving device according to the present invention. The receiving circuit 10 includes an LNA (Low Noise Amplifier) 11, a local oscillator 12, a mixer 13, a variable gain circuit 14, a band-pass filter 15, a demodulation circuit 16, an RSSI (Received Signal Strength Indication) circuit 17, a detection circuit 18, and a switch 19. (Hereinafter, referred to as SW19), an ADC (Analog to Digital Converter) 20, and a logic circuit 21. The logic circuit 21 includes a SW switching control circuit 22, a storage area 23, and an automatic gain control circuit 24.

  The LNA 11 amplifies the high-frequency signal RF received via an antenna (not shown) and supplies the amplified high-frequency signal RF to the mixer 13 as an amplified signal AS.

  The local oscillator 12 generates a local oscillation signal FL and supplies it to the mixer 13.

  The mixer 13 generates an intermediate frequency signal IS having a lower frequency than the high frequency signal RF by mixing the local signal FL with the amplified signal AS, and supplies the intermediate frequency signal IS to the variable gain circuit 14.

  The variable gain circuit 14 receives the intermediate frequency signal IS and changes the amplitude of the intermediate frequency signal IS (input signal) with a gain according to the gain control signal GCS. The variable gain circuit 14 is configured by a variable step attenuator, and attenuates the intermediate frequency signal IS while changing the gain according to the gain control value GCV indicated in the gain control signal GCS. The variable gain circuit 14 supplies the intermediate frequency signal IS whose amplitude has been changed to the bandpass filter 15 as an amplitude converted intermediate frequency signal AIS.

  The band-pass filter 15 performs a frequency selection process on the amplitude-converted intermediate frequency signal AIS to pass only components in a predetermined frequency band, thereby generating a filter-passed signal PS from which unnecessary band components have been removed. The band pass filter 15 supplies the generated filter pass signal PS to the demodulation circuit 16, the RSSI circuit 17, and the detection circuit 18.

  The demodulation circuit 16 demodulates the filtered signal PS to restore the modulated information data and obtain a data output DO.

  The RSSI circuit 17 detects a received signal strength (received electric field strength) based on the filter passing signal PS, and obtains an RSSI value RV as an analog value. The RSSI value RV is stored in the storage area 23 through digital conversion by the ADC 20, and is used for determination of a radio wave condition at the time of tuning by a tuner (not shown) in the wireless receiver.

  The detection circuit 18 performs envelope detection on the filter-passed signal PS, removes high-frequency components, and obtains a signal amplitude value SV as an analog value. This signal amplitude value SV is supplied to the automatic gain control circuit 24 through digital conversion by the ADC 20, and is used for controlling the gain of the variable gain circuit 14.

  FIG. 2 shows the relationship between the RSSI value RV output from the RSSI circuit 17 and the received signal strength (FIG. 2A), and the relationship between the signal amplitude value SV output from the detection circuit 18 and the received signal strength (FIG. 2). It is a figure showing (b)). The horizontal axis represents the received signal strength in common logarithm.

  The RSSI circuit 17 detects a received signal strength in order to confirm the presence of a radio wave to be received. Therefore, the RSSI circuit 17 is configured to be able to detect a relatively small received signal strength. For example, as shown in FIG. 2A, the output (RSSI value RV) of the RSSI circuit 17 is proportional to the received signal strength in a range of 0 dBμV to 40 dBμV lower than the reference signal strength of 40 dBμV (that is, as shown in FIG. 2A). , The inclination becomes a straight line). When the received signal strength exceeds the reference signal strength (40 dBμV), the RSSI value RV output from the RSSI circuit 17 saturates.

  That is, the RSSI circuit 17 is a first signal strength detection circuit that detects the signal strength of the filter passing signal PS when the signal strength is less than the reference signal strength (that is, in a range of a signal strength lower than the reference signal). is there. The RSSI circuit 17 supplies the first detection value, the RSSI value RV, to the SW 19.

  On the other hand, the gain control in the variable gain circuit 14 is performed in order to suppress the deterioration of the reception characteristic due to the saturation of the output of the variable gain circuit 14 in a situation where the received signal strength is large. Accordingly, the detection circuit 18 is configured to be able to detect a relatively large received signal strength. For example, as shown in FIG. 2B, the detection circuit 18 performs a detection operation so that the signal amplitude value SV starts increasing near a point where the received signal intensity becomes 40 dBμV. When the received signal strength is equal to or more than 65 dBμV, the gain of the variable gain circuit 14 is controlled so that the signal level of the amplified intermediate frequency signal AIS becomes constant. Therefore, the signal amplitude value SV output from the detection circuit 18 is constant. Becomes

  That is, the detection circuit 18 detects the signal strength of the filtered signal PS when the signal strength is equal to or higher than the reference signal strength (that is, in the range of the reference signal strength and the signal strength higher than the reference signal strength). This is a signal strength detection circuit. The detection circuit 18 supplies the signal amplitude value SV that is the second detection value to the SW 19.

  The SW 19 is a changeover switch that switches the connection between the ADC 20 and the RSSI circuit 17 and the detection circuit 18. The SW 19 switches the connection according to the SW switching control signal SCS and supplies the ADC 20 with the RSSI value RV or the signal amplitude value SV.

  FIG. 3 is a circuit diagram showing a configuration of the SW 19. The SW 19 includes a first transfer gate 31, a second transfer gate 32, and an inverter 33.

  The first transfer gate 31 includes an NMOS transistor N1 and a PMOS transistor P1. The drain terminal of the NMOS transistor N1 and the source terminal of the PMOS transistor P1 are connected to each other via a connection terminal T1. The connection end T1 is connected to the detection circuit 18 and receives the input of the signal amplitude value SV. The source terminal of the NMOS transistor N1 and the drain terminal of the PMOS transistor P1 are connected to each other via a connection terminal T2. The connection end T2 is connected to the ADC 20. The gate terminal of the NMOS transistor N1 is connected to the SW switching control circuit 22, and receives the supply of the SW switching control signal SCS. The gate terminal of the PMOS transistor P1 is connected to the SW switching control circuit 22 via the inverter 33.

  The second transfer gate 32 includes an NMOS transistor N2 and a PMOS transistor P2. The drain terminal of the NMOS transistor N2 and the source terminal of the PMOS transistor P2 are connected to each other via a connection terminal T3. The connection end T3 is connected to the RSSI circuit 17 and receives the RSSI value RV. The source terminal of the NMOS transistor N2 and the drain terminal of the PMOS transistor P2 are connected to each other via a connection terminal T4. The connection end T4 is connected to the ADC 20. The gate terminal of the NMOS transistor N2 is connected to the SW switching control circuit 22 via the inverter 33. The gate terminal of the PMOS transistor P2 is connected to the SW switching control circuit 22, and receives the supply of the SW switching control signal SCS.

  The SW switching control signal CSC is a signal whose signal level transitions to two values of “high” and “low” in a predetermined cycle CP. During a period when the signal level of the SW switching control signal SCS is high (high-level period HCP), the NMOS transistor N1 and the PMOS transistor P1 of the first transfer gate 31 are turned on, and the signal amplitude value SV supplied from the detection circuit 18 is reduced. It is supplied to the ADC 20. On the other hand, during a period in which the signal level of the SW switching control signal SCS is low (low-level period LCP), the NMOS transistor N2 and the PMOS transistor P2 of the second transfer gate 32 are turned on, and the RSSI value RV supplied from the RSSI circuit 17 is supplied. Is supplied to the ADC 20.

  Referring again to FIG. 1, the ADC 20 converts the RSSI value RV or the signal amplitude value SV supplied from the SW 19 into a digital value DV, and supplies the digital value DV to the SW switching control circuit 22 of the logic circuit 21. In the following description, the RSSI value RV converted to a digital value DV is referred to as a digital RSSI value DRV, and the signal amplitude value SV converted to a digital value DV is referred to as a digital amplitude value DSV.

  The SW switching control circuit 22 supplies a SW switching control signal SCS to the SW 19. Further, the SW switching control circuit 22 stores the digital RSSI value DRV supplied from the ADC 20 in the storage area 23. Further, the SW switching control circuit 22 supplies the digital amplitude value DSV supplied from the ADC 20 to the automatic gain control circuit 24.

  The automatic gain control circuit 24 calculates a gain control value GCV based on the digital amplitude value DSV, generates a gain control signal GCS for controlling the gain of the variable gain circuit 14 based on the calculation result, and Supply.

  The automatic gain control circuit 24 holds, for example, an amplitude upper threshold value TH1 (for example, 65 dBμV) and an amplitude lower threshold value TH2 (for example, 40 dBμV) of a signal input to the band-pass filter 15, and performs comparison with the digital amplitude value DSV. . When the digital amplitude value DSV exceeds the amplitude upper threshold TH1, the automatic gain control circuit 24 calculates a gain control value GCV to reduce the gain of the variable gain circuit 14, and a gain control signal having a signal level corresponding thereto. Generate GCS. When the digital amplitude value DSV is lower than the amplitude lower threshold TH2, the automatic gain control circuit 24 calculates a gain control value GCV to increase the gain of the variable gain circuit 14, and a gain control signal having a signal level corresponding thereto. Generate GCS.

  Next, the operation of each part of the receiving circuit 10 will be described with reference to the time chart of FIG.

  In the low-level period LCP in which the signal level of the SW switching control signal SCS is low, the SW 19 supplies the RSSI value RV output from the RSSI circuit 17 to the DSV 20. During this time, the automatic gain control circuit 24 supplies a gain control signal GCS having a constant signal level to the variable gain circuit 14.

  The ADC 20 converts the RSSI value RV supplied from the RSSI circuit 17 via the SW 19 into a digital value DV (that is, a digital RSSI value DRV) and supplies the digital value DV to the SW switching control circuit 22 of the logic circuit 21. The SW switching control circuit 22 stores the digital RSSI value DRV in the storage area 23.

  On the other hand, in the high level period HCP in which the signal level of the SW switching control signal SCS is high, the SW 19 supplies the signal amplitude value SV output from the detection circuit 18 to the ADC 20. The ADC 20 converts the signal amplitude value SV into a digital value DV (digital amplitude value DSV). The SW switching control circuit 22 of the logic circuit 21 supplies the digital amplitude value DSV to the automatic gain control circuit 24. The automatic gain control circuit 24 calculates a gain control value GCV based on the digital amplitude value DSV, and supplies a gain control signal GCS having a signal level reflecting the gain control value GCV to the variable gain circuit 14.

  The SW switching control circuit 22 periodically switches the signal level of the SW switching control signal SCS between a high level and a low level in a cycle CP. The ADC 20 performs the conversion operation once in each of the high-level period HCP and the low-level period LCP. The logic circuit 21 stores the digital RSSI value DRV in the storage area 23 once for one low-level period LCP, and calculates the gain control value GCV based on the digital amplitude value DSV for one high-level period HCP. Perform once. Each part of the SW 19, the ADC 20, and the logic circuit 21 repeatedly performs such a series of operations.

  As described above, in the receiving circuit 10 of the present invention, the SW 19 switches periodically and supplies either the RSSI value RV or the signal amplitude value SV to the ADC 20. Then, the ADC 20 converts the RSSI value RV or the signal amplitude value SV supplied via the SW 19 into a digital value DV. Therefore, since it is not necessary to separately provide ADCs corresponding to the RSSI circuit and the detection circuit in the receiving circuit, it is possible to obtain digital values of the outputs of the RSSI circuit and the detection circuit while suppressing the circuit size.

  When the wireless receiving device having the receiving circuit 10 is, for example, a radio or television tuner used in a mobile object, the received signal strength fluctuates due to fading. The cycle of this variation is the reciprocal of the fading frequency. Assuming that the moving speed of the moving object is v (m / s) and the wavelength of the received radio wave is λ (m), the fading frequency fd (Hz) is represented by the following equation (1).

fd = v / λ (1)
Assuming that the reception frequency is 430 (MHz), which is the maximum frequency channel of television broadcasting, the wavelength of the received radio wave is 0.698 (m) (= speed of light 3 × 10 ⁸ (m / s) ÷ 430 × 10 ⁶ ). Become. Therefore, for example, assuming that the moving speed of the moving object is 80 (km / h), the fading frequency fd is 32 (Hz) (= 80 (km / h) × 1000 ÷ 3600 ÷ 0.698 (m)). Therefore, the fading cycle is 1 / fd = 31 (msec).

  Therefore, the cycle of the gain adjustment in the variable gain circuit 14 may be about several msec, and the cycle of the SW switching control signal SCS may have a period of about several msec, for example.

  Further, when the radio receiving apparatus is a receiving apparatus used for a burst data communication system, for example, it is only necessary to obtain an RSSI value during a preamble period received at the beginning of a burst in order to confirm the presence of a carrier. Therefore, the SW switching control signal SCS only needs to be maintained at the low level for a period corresponding to the preamble period.

  A wireless receiving apparatus and a receiving method according to the present embodiment will be described with reference to FIGS. Note that the same or equivalent components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 5 is a block diagram illustrating a configuration of the receiving circuit 10 in the wireless receiving device according to the present embodiment. In this embodiment, the logic circuit 21 includes an average value calculation circuit 41 in addition to the same configuration as the first embodiment (the SW switching control circuit 22, the storage area 23, and the automatic gain control circuit 24).

  When the digital RSSI value DRV is supplied from the SW 19, the ADC 20 supplies the digital RSSI value DRV to the SW switching control unit 22, as in the first embodiment. On the other hand, when the digital amplitude value DSV is supplied from the SW 19, it is supplied to the average value calculation circuit 41.

  The average value calculation circuit 41 calculates an average value after acquiring the digital amplitude value DSV from the ADC 20 a predetermined number of times. Then, the average value calculation circuit 41 supplies the calculated average value to the SW switching control unit 22 as an average amplitude value SAV.

  The SW switching control circuit 22 supplies the average amplitude value SAV supplied from the ADC 20 to the automatic gain control circuit 24.

  The automatic gain control circuit 24 calculates a gain control value GCV based on the average amplitude value SAV, generates a gain control signal GCS for controlling the gain of the variable gain circuit 14 based on the calculation result, and Supply.

  Next, the operation of each unit of the receiving circuit 10 in the present embodiment will be described with reference to the time chart of FIG.

  The signal level of the SW switching control signal SCS becomes high in a high level period HCP longer than in the first embodiment. During this high-level period HCP, the detection circuit 18 performs the envelope detection n times (n is an integer of 2 or more) to obtain n signal amplitude values SV. The SW 19 supplies the n signal amplitude values SV to the ADC 20 during the high-level period HCP.

  The ADC 20 sequentially converts the signal amplitude value SV supplied from the SW 19 into a digital amplitude value DSV, and supplies the digital amplitude value DSV to the average value calculation circuit 41. That is, the ADC 20 performs the conversion operation n times during the high-level period HCP.

  The average value calculation unit 41 calculates an average value of the n digital amplitude values DSV supplied from the ADC 20 during the high-level period HCP. The average value calculation unit 41 supplies the average value to the SW switching control circuit 22 as the average amplitude value SAV.

  The SW switching control circuit 22 supplies the average amplitude value SAV to the automatic gain control circuit 24. The automatic gain control circuit 24 calculates the gain control value GCV based on the average amplitude value SAV, and supplies the variable gain circuit 14 with a gain control signal GCS having a signal level reflecting the calculated result.

  As described above, in the receiving circuit 10 of the present embodiment, n signal amplitude values SV are supplied to the ADC 20 via the SW 19 every one high-level period HCP, and the ADC 20 performs n conversion operations. Then, the average value calculation circuit 41 calculates an average amplitude value SAV of the n digital amplitude values DSV, and the automatic gain control circuit 24 controls the gain of the variable gain circuit 14 based on the average amplitude value SAV.

  According to the receiving circuit 10 of the present embodiment, the gain control of the variable gain circuit 14 can be performed stably. For example, in a situation where the signal level of the received high-frequency signal RF greatly changes in a short time due to fading or the like, if gain control is performed every time the signal amplitude value SV is obtained, the gain control signal GCS repeats in a short time. Due to the change, the noise accompanying the switching operation at the time of the gain change increases, and there is a possibility that the reception characteristics may deteriorate due to a decrease in the SN ratio or the like. However, the receiving circuit 10 of this embodiment switches the SW 19 in a long cycle, calculates the average value of the digital amplitude values DSV acquired a plurality of times, and performs gain control. The stable gain control of the variable gain circuit 14 can be performed. Further, by setting a period sufficiently longer than the fading period as the high-level period HCP, more stable gain control can be performed.

  A wireless receiving apparatus and a receiving method according to the present embodiment will be described with reference to FIG. Note that the same or equivalent components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 7 is a block diagram illustrating a configuration of the receiving circuit 10 in the wireless receiving device according to the present embodiment. In the present embodiment, the logic circuit 21 includes a reference signal strength storage unit 42 in addition to the same configuration as the first embodiment (the SW switching control circuit 22, the storage area 23, and the automatic gain control circuit 24).

  The reference signal strength storage unit 26 stores a reference signal strength RTH (for example, 40 dBμV) serving as a reference for the switching operation in the SW 19.

  The SW switching control unit 22 compares the digital value DV (digital RSSI value DRV or digital amplitude value DSV) supplied from the ADC 20 with the reference signal strength RTH, and performs switching control of the SW 19 according to the comparison result.

  Specifically, when the digital RSSI value DRV is smaller than the reference signal strength RTH in a state where the SW 19 supplies the RSSI value RV output from the RSSI circuit 17 to the ADC 20, the SW switching control unit 22 A switch control signal SCS for maintaining the state as it is is generated and supplied to the switch SW19. When the digital RSSI value DRV becomes equal to or higher than the reference signal strength RTH, the SW switching control unit 22 generates the SW switching control signal SCS for switching the connection of the SW 19 so as to supply the signal amplitude value SV from the detection circuit 18 to the ADC 20. , SW19.

  On the other hand, when the digital amplitude value DSV is equal to or higher than the reference signal strength RTH in a state where the SW 19 supplies the signal amplitude value SV which is the output of the detection circuit 18 to the ADC 20, the SW switching control for maintaining the state as it is in the SW 19 A signal SCS is generated and supplied to SW19. When the digital amplitude value DSV becomes less than the reference signal strength RTH, the SW switching control unit 22 generates the SW switching control signal SCS for switching the connection of the SW 19 to supply the RSSI value RV from the RSSI circuit 17 to the ADC 20; Supply to SW19.

  As described above, the receiving circuit 10 of the present embodiment does not periodically switch the connection of the SW 19 at a predetermined cycle as in the first embodiment, but instead of the reference signal strength RTH and the digital RSSI value RV or the digital amplitude value. The connection of the SW 19 is switched according to the magnitude relationship with the DSV. Therefore, when the received signal strength is lower than the reference signal strength RTH, the RSSI value RV can be obtained and converted into the digital value DV a plurality of times regardless of the operation of the detection circuit 18. Similarly, when the received signal strength is equal to or higher than the reference signal strength RTH, the signal amplitude value SV can be obtained and converted into the digital value DV a plurality of times regardless of the operation of the RSSI circuit 17. Therefore, the switching of the SW 19 can be flexibly performed according to the radio wave condition.

  As described above, the radio receiving apparatus according to the present invention includes one of the first signal strength detection circuit (RSSI circuit 17) and the second signal strength detection circuit (detection circuit 18) and the analog-to-digital converter (ADC 20). And a switch (SW19) for switching the first detection value (RSSI value RV) or the second detection value (signal amplitude value SV) to the analog-to-digital converter (ADC20). The converter (ADC 20) converts the first detection value (RSSI value RV) or the second detection value (signal amplitude value SV) into a digital value (DV). Therefore, it is not necessary to separately provide an analog-to-digital converter (ADC 20) corresponding to each of the first signal strength detection circuit (RSSI circuit 17) and the second signal strength detection circuit (detection circuit 18). It is possible to convert the first detection value (RSSI value RV) and the second detection value (signal amplitude value SV) into a digital value (DV) while suppressing the noise.

  Note that the present invention is not limited to the above embodiment. For example, in the above-described embodiment, the case where the SW 19 is configured by the first and second transfer gates each including an NMOS transistor and a PMOS transistor as shown in FIG. 3 has been described. However, the configuration of the SW 19 is not limited to this, and any configuration may be used as long as it has a configuration capable of switching the output from the RSSI circuit 17 or the output from the detection circuit 18 according to the SW switching control signal SCS and supplying the output to the SW 19.

  Further, in the above-described embodiment, an example has been described in which the reference signal strength is set to 40 dBμV and the RSSI circuit 17 acquires the RSSI value RV proportional to the received signal strength in the range of 0 to 40 dBμV. However, the operation range of the RSSI circuit 17 is not limited to this. It is sufficient that the device operates at least at a received signal strength around 20 to 30 dBμV, which is the level of the reception sensitivity of the tuner that receives FM multiplex broadcast data.

  Further, in the second embodiment, the receiving circuit 10 has the average value calculating circuit 41 for calculating the average value of the n digital amplitude values DSV, and the automatic gain control circuit 24 uses the variable gain circuit based on the average amplitude value SAV. The example of performing the gain control of No. 14 has been described. However, an average value calculation circuit that calculates the average value of the plurality of digital RSSI values DRV may be provided, and the calculated average value may be stored in the storage area 23.

10 Receiver circuit 11 LNA
12 Local oscillator 13 Mixer 14 Variable gain circuit 15 Bandpass filter 16 Demodulation circuit 17 RSSI circuit 18 Detection circuit 19 SW
20 ADC
21 Logic Circuit 22 SW Switching Control Circuit 23 Storage Area 24 Automatic Gain Control Circuit 31 First Transfer Gate 32 Second Transfer Gate 33 Inverter 41 Average Calculation Circuit 42 Reference Signal Strength Storage Unit

Claims (12)

A variable gain circuit that changes the amplitude of the input signal at a gain according to the gain control signal and outputs the result;
A band-pass filter that passes a signal component of a predetermined frequency band among output signals of the variable gain circuit,
A first signal strength detection circuit for detecting a received field strength of the passed signal to obtain a first detection value when a signal strength of the passed signal passing through the bandpass filter is less than a reference signal strength;
When the signal strength of the passing signal is equal to or higher than the reference signal strength, a second signal strength detection circuit that detects a signal amplitude value of the passing signal to obtain a second detection value;
An analog-to-digital converter that converts the first detection value or the second detection value to a digital value;
One of the first and second signal strength detection circuits and the analog-to-digital converter that are switchably connected to each other to supply the first detection value or the second detection value to the analog-to-digital converter Switches and
A switching control unit that controls switching in the changeover switch;
A storage area for storing the first detection value converted to a digital value by the analog-to-digital converter;
A gain control circuit that generates the gain control signal based on the second detection value converted into a digital value by the analog-to-digital converter, and controls the gain in the variable gain circuit;
A wireless receiving device comprising: The wireless device according to claim 1, wherein the first signal strength detection circuit is an RSSI detection circuit that acquires an RSSI (Received Signal Strength Indication) value indicating the received electric field strength as the first detection value. Receiver. 2. The detection circuit according to claim 1, wherein the second signal strength detection circuit is a detection circuit that performs envelope detection on the passing signal and acquires the signal amplitude value of the passing signal as the second detection value. 3. The wireless receiving device according to 2.   4. The wireless reception device according to claim 1, wherein the switching control unit controls the switching switch to perform the switching at a predetermined cycle. 5. An average value calculation circuit that calculates an average value of n (n is an integer of 2 or more) second detection values converted into digital values by the analog-to-digital converter,
The wireless reception device according to claim 1, wherein the gain control circuit controls a gain in the variable gain circuit based on the average value.   The switching control unit performs the switching according to a comparison result obtained by comparing the first detection value or the second detection value converted into a digital value by the analog-to-digital converter with the reference signal intensity. The wireless receiver according to any one of claims 1 to 3, wherein the changeover switch is controlled. Changing the amplitude of the input signal with a gain according to the gain control signal to obtain an output signal;
Obtaining a pass signal by passing a signal component of a predetermined frequency band in the output signal;
When the signal strength of the passing signal is less than a reference signal strength, detecting a reception field strength of the passing signal to obtain a first detection value;
When the signal strength of the passing signal is equal to or greater than the reference signal strength, detecting a signal amplitude value of the passing signal to obtain a second detection value;
Selectively switching any one of the first detection value or the second detection value;
Converting the first detection value or the second detection value to a digital value according to the switching;
Storing the first detection value converted to a digital value;
Generating the gain control signal based on the second detection value converted to a digital value;
A wireless receiving method comprising:   The wireless reception method according to claim 7, wherein the first detection value is an RSSI (Received Signal Strength Indication) value. 9. The wireless reception method according to claim 7, wherein the second detection value is the signal amplitude value obtained by performing envelope detection on the passing signal.   10. The method according to claim 7, wherein the step of selectively switching one of the first detection value and the second detection value includes the step of performing the switching at a predetermined cycle. Wireless reception method. Calculating an average value of the n (n is an integer of 2 or more) second detection values converted into digital values,
The method according to claim 7, wherein generating the gain control signal based on the second detection value converted into the digital value includes generating the gain control signal based on the average value. The wireless reception method according to any one of the tenth to eleventh aspects. The step of selectively switching either the first detection value or the second detection value includes comparing the magnitude of the first detection value or the second detection value converted into a digital value with the reference signal intensity. The method according to any one of claims 7 to 9, further comprising the step of performing the switching according to the comparison result.

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