JP2017130877A - Radio receiver and radio reception method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a radio receiver and a radio reception method, enabling the acquisition of each output digital value of an RSSI circuit and a detector circuit, with the suppression of the circuit scale of a reception circuit.SOLUTION: The radio receiver includes: an RSSI circuit which detects the intensity of a signal passing through a band pass filter within a range lower than reference signal intensity, to obtain a first detection value; a detection circuit which detects in a range higher than the reference signal intensity to obtain a second detection value; an analog-to-digital converter which converts the first detection value or the second detection value into a digital value; a changeover switch which connects one of the RSSI circuit and the detection circuit to the analog-to-digital converter in a switchable manner to supply the first detection value or the second detection value to the analog-to-digital converter; a changeover control unit which controls the changeover of the changeover switch; a storage area which stores the first detection value converted into the digital value; and a gain control circuit which generates a gain control signal on the basis of the second detection value converted into the digital value, to control a gain in a variable gain circuit.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wireless reception device and a wireless reception method.

  In recent years, information communication systems such as VICS (registered trademark) (Vehicle Information and Communication System) that transmit traffic information indicating traffic jam information, accident information, and the like superimposed on an FM radio broadcast signal have been used. In such an information communication system, reception is performed in a wireless reception device mounted on a moving body such as a vehicle. Therefore, the propagation state of radio waves changes according to the change in the positional relationship with the base station due to movement. Therefore, such a wireless receiver acquires an RSSI (Received Signal Strength Indication) value indicating the signal strength (electric field strength) of the received signal, and performs tuning according to a frequency (channel) at which an RSSI value of a certain level or more is obtained. While receiving the signal.

  In addition, the wireless reception device is provided with a gain control circuit that performs gain control of the amplifier in accordance with the signal level of the received signal. The gain control circuit increases the gain to improve the signal-to-noise ratio when the signal level of the received signal is low, and distorts the signal generated in the receiver when the signal level is high. In order to reduce the gain, control is performed to reduce the gain. For this reason, the radio reception apparatus is provided with a detection circuit that detects a received signal and detects a signal level.

  In an information communication system such as VICS (registered trademark), a wireless reception device uses an RSSI value to determine whether the signal strength of a received signal is at a level at which traffic information or the like can be received. Therefore, the RSSI circuit that acquires the RSSI value has a low signal strength range as a detection target. On the other hand, the detection circuit is a circuit that detects a signal level in order to perform gain control, and therefore has a high signal intensity range as a detection target. In view of this, there has been proposed a wireless reception device in which an RSSI circuit and a detection circuit are separately provided (for example, Patent Document 1).

JP 2001-285209 A

  Since the output of the RSSI circuit is an analog value, it is converted into a digital value by an ADC (Analog to Digital Converter) circuit and then stored in the storage area as RSSI data. Further, since the output of the detection circuit is also an analog value, conversion to a digital value is performed by an ADC (Analog to Digital Converter) circuit. Therefore, in the radio reception apparatus in which the RSSI circuit and the detection circuit are separately provided as described above, two ADCs corresponding to the two circuits are necessary. For this reason, there is a problem that the area of the semiconductor integrated circuit constituting the receiving circuit increases.

  In order to solve the above-described problems, an object of the present invention is to provide a wireless reception device and a wireless reception method capable of obtaining digital values of outputs of an RSSI circuit and a detection circuit while suppressing the circuit scale of the reception circuit. .

  A radio receiving apparatus according to the present invention includes a variable gain circuit that changes an amplitude of an input signal with a gain according to a gain control signal and outputs the signal, and a signal component in a predetermined frequency band among output signals of the variable gain circuit And a first signal strength for obtaining a first detection value by detecting the signal strength of the passing signal when the signal strength of the passing signal that has passed through the bandpass filter is less than a reference signal strength. A detection circuit; a second signal strength detection circuit that detects the signal strength of the passage signal and obtains a second detection value when the signal strength of the passage signal is equal to or greater than the reference signal strength; and the first An analog-to-digital converter that converts a detection value or the second detection value into a digital value, and one of the first and second signal intensity detection circuits and the analog-to-digital converter can be switched. A changeover switch that supplies the first detection value or the second detection value to the analog-digital converter, a changeover control unit that controls a changeover in the changeover switch, and a digital value that is converted by the analog-digital converter. The gain control signal is generated based on the storage area for storing the first detection value and the second detection value converted into a digital value by the analog-to-digital converter, and the gain in the variable gain circuit is controlled. And a gain control circuit.

  The radio reception method according to the present invention includes a step of changing an amplitude of an input signal with a gain according to a gain control signal to obtain an output signal, and passing a signal component of a predetermined frequency band in the output signal to pass the signal. Obtaining a first detection value by detecting the signal strength of the passing signal when the signal strength of the passing signal is less than a reference signal strength, and the signal strength of the passing signal being the reference strength A step of detecting the signal strength of the passing signal to obtain a second detection value when the signal strength is equal to or higher than a signal strength, and a step of selectively switching either the first detection value or the second detection value; , Converting the first detection value or the second detection value into a digital value in response to the switching, storing the first detection value converted into a digital value, and converting the digital value into a digital value Generating said gain control signal a on the basis of the second detection value, characterized in that it comprises a.

  According to the present invention, it is possible to obtain digital values of the outputs of the RSSI circuit and the detection circuit while suppressing the circuit scale of the receiving circuit.

It is a block diagram which shows the structure of the receiving circuit in the radio | wireless receiver of this invention. It is a figure which shows typically the relationship between the output (a) of an RSSI circuit and the output (b) of a detection circuit with respect to received signal strength. It is a figure which shows the structure of SW circuit. It is a time chart which shows operation | movement of SW switching control signal and a gain control signal, ADC, and a logic circuit. FIG. 6 is a block diagram illustrating a configuration of a receiving circuit according to a second embodiment. 6 is a time chart illustrating an SW switching control signal, a gain control signal, an operation of an ADC, and a logic circuit in Embodiment 2. FIG. 10 is a block diagram illustrating a configuration of a receiving circuit according to a third embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a receiving circuit 10 of a radio receiving apparatus according to the present invention. The reception circuit 10 includes an LNA (Low Noise Amplifier) 11, a local oscillator 12, a mixer 13, a variable gain circuit 14, a band pass filter 15, a demodulation circuit 16, an RSSI (Received Signal Strength Indication) circuit 17, a detection circuit 18, and a switch 19. (Hereinafter referred to as SW 19), ADC (Analog to Digital Converter) 20, and logic circuit 21. The logic circuit 21 includes a SW switching control circuit 22, a storage area 23, and an automatic gain control circuit 24.

  The LNA 11 amplifies the high frequency signal RF received via an antenna (not shown) and supplies the amplified signal AS to the mixer 13.

  The local oscillator 12 generates a local transmission signal FL and supplies it to the mixer 13.

  The mixer 13 mixes the local transmission signal FL with the amplified signal AS to generate an intermediate frequency signal IS having a frequency lower than that of the high frequency signal RF, and supplies the intermediate frequency signal IS to the variable gain circuit 14.

  The variable gain circuit 14 receives the intermediate frequency signal IS and changes the amplitude of the intermediate frequency signal IS (input signal) with a gain corresponding to the gain control signal GCS. The variable gain circuit 14 includes a variable step attenuator, and attenuates the intermediate frequency signal IS while changing the gain according to the gain control value GCV indicated by the gain control signal GCS. The variable gain circuit 14 supplies the band-pass filter 15 with the intermediate frequency signal IS whose amplitude is changed as the amplitude-converted intermediate frequency signal AIS.

  The band-pass filter 15 performs a frequency selection process for allowing only the components of a predetermined frequency band to pass through the amplitude-converted intermediate frequency signal AIS, thereby generating a filter pass signal PS from which unnecessary band components have been removed. The band pass filter 15 supplies the generated filter pass signal PS to the demodulation circuit 16, the RSSI circuit 17, and the detection circuit 18.

  The demodulation circuit 16 restores the modulated information data by performing demodulation processing on the filtered signal PS, and obtains a data output DO.

  The RSSI circuit 17 detects the received signal strength (received electric field strength) based on the filter passing signal PS, and obtains an RSSI value RV as an analog value. The RSSI value RV is stored in the storage area 23 through digital conversion by the ADC 20 and is used to determine the radio wave condition during tuning in a tuner (not shown) in the wireless reception device.

  The detection circuit 18 performs envelope detection on the filtered signal PS and removes high frequency components to obtain a signal amplitude value SV as an analog value. The signal amplitude value SV is supplied to the automatic gain control circuit 24 through digital conversion by the ADC 20 and used for controlling the gain of the variable gain circuit 14.

  2 shows the relationship between the RSSI value RV that is the output of the RSSI circuit 17 and the received signal strength (FIG. 2A), and the relationship between the signal amplitude value SV that is the output of the detection circuit 18 and the received signal strength (FIG. 2). It is a figure which shows (b)). The horizontal axis represents the received signal strength as a common logarithm.

  The RSSI circuit 17 detects the received signal strength in order to confirm the presence of the radio wave to be received. Therefore, the RSSI circuit 17 is configured to detect a relatively small received signal strength. For example, as shown in FIG. 2A, the RSSI circuit 17 has an output (RSSI value RV) proportional to the received signal strength in a range of 0 dBμV to 40 dBμV, which is lower than the reference signal strength of 40 dBμV (that is, The detection operation is performed so that the inclination becomes a straight line. When the received signal strength exceeds the reference signal strength (40 dBμV), the RSSI value RV that is the output of the RSSI circuit 17 is saturated.

  That is, the RSSI circuit 17 is a first signal strength detection circuit that detects the signal strength of the filtered signal PS when the signal strength is less than the reference signal strength (that is, in a range of signal strength lower than the reference signal). is there. The RSSI circuit 17 supplies the RSSI value RV, which is the first detection value, to the SW 19.

  On the other hand, the gain control in the variable gain circuit 14 is performed in order to suppress the deterioration of the reception characteristics due to the saturation of the output of the variable gain circuit 14 in a situation where the received signal strength is large. Therefore, the detection circuit 18 is configured to detect a relatively large received signal strength. For example, as shown in FIG. 2B, the detection circuit 18 performs a detection operation so that the signal amplitude value SV starts to increase from the vicinity before the reception signal intensity reaches the reference signal intensity of 40 dBμV. When the received signal strength is 65 dBμV or more, the gain of the variable gain circuit 14 is controlled so that the signal level of the amplified intermediate frequency signal AIS is constant, so that the signal amplitude value SV that is the output of the detection circuit 18 is constant. It becomes.

  That is, the detection circuit 18 detects the signal strength of the filtered signal PS when the signal strength is equal to or higher than the reference signal strength (that is, in the range of the reference signal strength and the signal strength higher than the reference signal strength). It is a signal strength detection circuit. The detection circuit 18 supplies the signal amplitude value SV, which is the second detection value, to the SW 19.

  The SW 19 is a changeover switch that switches connection between the RSSI circuit 17 and the detection circuit 18 and the ADC 20. The SW 19 switches connection according to the SW switching control signal SCS, and supplies the RSSI value RV or the signal amplitude value SV to the ADC 20.

  FIG. 3 is a circuit diagram showing a configuration of the SW 19. SW 19 includes a first transfer gate 31, a second transfer gate 32, and an inverter 33.

  The first transfer gate 31 includes an NMOS transistor N1 and a PMOS transistor P1. The drain terminal of the NMOS transistor N1 and the source terminal of the PMOS transistor P1 are connected to each other via a connection terminal T1. The connection end T1 is connected to the detection circuit 18 and receives an input of the signal amplitude value SV. The source terminal of the NMOS transistor N1 and the drain terminal of the PMOS transistor P1 are connected to each other via the connection terminal T2. The connection end T2 is connected to the ADC 20. The gate terminal of the NMOS transistor N1 is connected to the SW switching control circuit 22 and is supplied with the SW switching control signal SCS. The gate terminal of the PMOS transistor P1 is connected to the SW switching control circuit 22 via the inverter 33.

  The second transfer gate 32 includes an NMOS transistor N2 and a PMOS transistor P2. The drain terminal of the NMOS transistor N2 and the source terminal of the PMOS transistor P2 are connected to each other via the connection terminal T3. The connection end T3 is connected to the RSSI circuit 17 and receives an RSSI value RV. The source terminal of the NMOS transistor N2 and the drain terminal of the PMOS transistor P2 are connected to each other via a connection terminal T4. The connection end T4 is connected to the ADC 20. The gate terminal of the NMOS transistor N2 is connected to the SW switching control circuit 22 via the inverter 33. The gate terminal of the PMOS transistor P2 is connected to the SW switching control circuit 22 and receives the supply of the SW switching control signal SCS.

  The SW switching control signal CSC is a signal whose signal level transitions to a binary value of “high” and “low” in a predetermined cycle CP. During the period when the signal level of the SW switching control signal SCS is high (high level period HCP), the NMOS transistor N1 and the PMOS transistor P1 of the first transfer gate 31 are turned on, and the signal amplitude value SV supplied from the detection circuit 18 is Supplied to the ADC 20. On the other hand, during a period when the signal level of the SW switching control signal SCS is low (low level period LCP), the NMOS transistor N2 and the PMOS transistor P2 of the second transfer gate 32 are turned on, and the RSSI value RV supplied from the RSSI circuit 17 is turned on. Is supplied to the ADC 20.

  Referring again to FIG. 1, the ADC 20 converts the RSSI value RV or the signal amplitude value SV supplied from the SW 19 into a digital value DV and supplies the digital value DV to the SW switching control circuit 22 of the logic circuit 21. In the following description, the RSSI value RV converted into the digital value DV is referred to as a digital RSSI value DRV, and the signal amplitude value SV converted into the digital value DV is referred to as a digital amplitude value DSV.

  The SW switching control circuit 22 supplies the SW switching control signal SCS to the SW 19. Further, the SW switching control circuit 22 stores the digital RSSI value DRV supplied from the ADC 20 in the storage area 23. Further, the SW switching control circuit 22 supplies the digital amplitude value DSV supplied from the ADC 20 to the automatic gain control circuit 24.

  The automatic gain control circuit 24 calculates a gain control value GCV based on the digital amplitude value DSV, generates a gain control signal GCS for controlling the gain of the variable gain circuit 14 based on the calculation result, and supplies the gain control signal GCS to the variable gain circuit 14. Supply.

  The automatic gain control circuit 24 holds, for example, an amplitude upper limit threshold TH1 (for example, 65 dBμV) and an amplitude lower limit threshold TH2 (for example, 40 dBμV) of a signal input to the bandpass filter 15, and compares the amplitude with a digital amplitude value DSV. . When the digital amplitude value DSV exceeds the amplitude upper limit threshold TH1, the automatic gain control circuit 24 calculates the gain control value GCV to lower the gain of the variable gain circuit 14, and a gain control signal having a signal level corresponding to the gain control value GCV. Generate a GCS. When the digital amplitude value DSV is lower than the amplitude lower limit threshold TH2, the automatic gain control circuit 24 calculates the gain control value GCV to increase the gain of the variable gain circuit 14, and a gain control signal having a signal level corresponding thereto. Generate a GCS.

  Next, the operation of each part of the receiving circuit 10 will be described with reference to the time chart of FIG.

  In the low level period LCP in which the signal level of the SW switching control signal SCS is low, the SW 19 supplies the RSSI value RV that is the output of the RSSI circuit 17 to the DSV 20. During this time, the automatic gain control circuit 24 supplies a gain control signal GCS having a constant signal level to the variable gain circuit 14.

  The ADC 20 converts the RSSI value RV supplied from the RSSI circuit 17 via the SW 19 into a digital value DV (that is, the digital RSSI value DRV), and supplies the digital value DV to the SW switching control circuit 22 of the logic circuit 21. The SW switching control circuit 22 stores the digital RSSI value DRV in the storage area 23.

  On the other hand, in the high level period HCP in which the signal level of the SW switching control signal SCS is high, the SW 19 supplies the signal amplitude value SV that is the output of the detection circuit 18 to the ADC 20. The ADC 20 converts the signal amplitude value SV into a digital value DV (digital amplitude value DSV). The SW switching control circuit 22 of the logic circuit 21 supplies the digital amplitude value DSV to the automatic gain control circuit 24. The automatic gain control circuit 24 calculates a gain control value GCV based on the digital amplitude value DSV, and supplies a gain control signal GCS having a signal level reflecting the gain control value GCV to the variable gain circuit 14.

  The SW switching control circuit 22 periodically switches the signal level of the SW switching control signal SCS between a high level and a low level with a period CP. The ADC 20 performs the conversion operation once in each of the high level period HCP and the low level period LCP. The logic circuit 21 stores the digital RSSI value DRV in the storage area 23 once for each low level period LCP, and calculates the gain control value GCV based on the digital amplitude value DSV for each high level period HCP. Perform once. Each unit of the SW 19, the ADC 20, and the logic circuit 21 repeats such a series of operations.

  As described above, in the receiving circuit 10 of the present invention, the SW 19 periodically performs switching, and supplies either the RSSI value RV or the signal amplitude value SV to the ADC 20. Then, the ADC 20 converts the RSSI value RV or the signal amplitude value SV supplied via the SW 19 into a digital value DV. Therefore, it is not necessary to separately provide ADCs corresponding to the RSSI circuit and the detection circuit in the receiving circuit, and thus the digital values of the outputs of the RSSI circuit and the detection circuit can be obtained while suppressing the circuit scale.

  In addition, when the radio | wireless receiver which has the receiving circuit 10 is a radio and a television tuner used with a mobile body, for example, a received signal strength is fluctuate | varied by fading. The period of this variation is the reciprocal of the fading frequency. When the moving speed of the moving body is v (m / s) and the wavelength of the received radio wave is λ (m), the fading frequency fd (Hz) is expressed by the following equation (1).

fd = v / λ (1)
If the reception frequency is 430 (MHz), which is the maximum frequency channel of television broadcasting, the wavelength of the reception radio wave is 0.698 (m) (= speed of light 3 × 10 ⁸ (m / s) ÷ 430 × 10 ⁶ ). Become. Therefore, for example, when the moving speed of the moving body is 80 (km / h), the fading frequency fd is 32 (Hz) (= 80 (km / h) × 1000 ÷ 3600 ÷ 0.698 (m)). Therefore, the fading cycle is 1 / fd = 31 (msec).

  Therefore, the gain adjustment period in the variable gain circuit 14 may be about several milliseconds, and the period of the SW switching control signal SCS only needs to have a period of, for example, several milliseconds.

  Further, when the wireless reception device is a reception device used in, for example, a burst data communication system, it is only necessary to obtain an RSSI value during a preamble period received at the beginning of a burst in order to confirm the presence of a carrier. Therefore, the SW switching control signal SCS only needs to be maintained at a low level for a period corresponding to the preamble period.

  The radio reception apparatus and reception method of this embodiment will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected about the structure similar or equivalent to Example 1, and description is abbreviate | omitted.

  FIG. 5 is a block diagram illustrating a configuration of the reception circuit 10 in the wireless reception device of this embodiment. In this embodiment, the logic circuit 21 includes an average value calculation circuit 41 in addition to the same configuration (SW switching control circuit 22, storage area 23, and automatic gain control circuit 24) as in the first embodiment.

  When the digital RSSI value DRV is supplied from the SW 19, the ADC 20 supplies this to the SW switching control unit 22 as in the first embodiment. On the other hand, when the digital amplitude value DSV is supplied from the SW 19, it is supplied to the average value calculation circuit 41.

  The average value calculation circuit 41 calculates the average value when the digital amplitude value DSV is acquired from the ADC 20 a predetermined number of times. Then, the average value calculation circuit 41 supplies the calculated average value to the SW switching control unit 22 as the average amplitude value SAV.

  The SW switching control circuit 22 supplies the average amplitude value SAV supplied from the ADC 20 to the automatic gain control circuit 24.

  The automatic gain control circuit 24 calculates a gain control value GCV based on the average amplitude value SAV, generates a gain control signal GCS for controlling the gain of the variable gain circuit 14 based on the calculation result, and supplies the gain control signal GCS to the variable gain circuit 14. Supply.

  Next, the operation of each part of the receiving circuit 10 in this embodiment will be described with reference to the time chart of FIG.

  The SW switching control signal SCS has a high signal level in the high level period HCP longer than that in the first embodiment. During the high level period HCP, the detection circuit 18 performs envelope detection n times (n is an integer of 2 or more) to obtain n signal amplitude values SV. The SW 19 supplies n signal amplitude values SV to the ADC 20 during the high level period HCP.

  The ADC 20 sequentially converts the signal amplitude value SV supplied from the SW 19 into a digital amplitude value DSV and supplies it to the average value calculation circuit 41. That is, the ADC 20 performs n conversion operations during the high level period HCP.

  The average value calculation unit 41 calculates an average value of n digital amplitude values DSV supplied from the ADC 20 during the high level period HCP. The average value calculation unit 41 supplies this average value to the SW switching control circuit 22 as the average amplitude value SAV.

  The SW switching control circuit 22 supplies the average amplitude value SAV to the automatic gain control circuit 24. The automatic gain control circuit 24 calculates a gain control value GCV based on the average amplitude value SAV, and supplies a gain control signal GCS having a signal level reflecting the calculated result to the variable gain circuit 14.

  As described above, in the receiving circuit 10 of the present embodiment, n signal amplitude values SV are supplied to the ADC 20 via the SW 19 for each high level period HCP, and the ADC 20 performs n conversion operations. The average value calculating circuit 41 calculates an average amplitude value SAV of the n digital amplitude values DSV, and the automatic gain control circuit 24 performs gain control of the variable gain circuit 14 based on the average amplitude value SAV.

  According to the receiving circuit 10 of the present embodiment, the gain control of the variable gain circuit 14 can be stably performed. For example, in a situation where the signal level of the received high-frequency signal RF changes greatly in a short time due to fading or the like, the gain control signal GCS is repeated in a short time if gain control is performed every time the signal amplitude value SV is acquired. By changing, the noise accompanying the switching operation at the time of gain change increases, and there is a possibility that the reception characteristics deteriorate due to a decrease in SN ratio or the like. However, the receiving circuit 10 of the present embodiment switches the SW 19 in a long cycle, calculates the average value of the digital amplitude values DSV acquired over a plurality of times, and performs gain control. The gain control of the stable variable gain circuit 14 can be performed. Further, by setting a period sufficiently longer than the fading period as the high level period HCP, more stable gain control can be performed.

  The radio reception apparatus and reception method of this embodiment will be described with reference to FIG. In addition, the same code | symbol is attached | subjected about the structure similar or equivalent to Example 1, and description is abbreviate | omitted.

  FIG. 7 is a block diagram illustrating a configuration of the reception circuit 10 in the wireless reception device of this embodiment. In this embodiment, the logic circuit 21 includes a reference signal strength storage unit 42 in addition to the same configuration (SW switching control circuit 22, storage area 23, and automatic gain control circuit 24) as in the first embodiment.

  The reference signal strength storage unit 26 stores a reference signal strength RTH (for example, 40 dBμV) serving as a reference for the switching operation in the SW 19.

  The SW switching control unit 22 compares the digital value DV (digital RSSI value DRV or digital amplitude value DSV) supplied from the ADC 20 with the reference signal strength RTH, and performs switching control of the SW 19 according to the comparison result.

  Specifically, when the digital RSSI value DRV is smaller than the reference signal strength RTH in a state in which the SW 19 supplies the RSSI value RV that is the output of the RSSI circuit 17 to the ADC 20, the SW switching control unit 22 An SW switching control signal SCS for maintaining the state as it is is generated and supplied to the SW 19. When the digital RSSI value DRV becomes equal to or higher than the reference signal strength RTH, the SW switching control unit 22 generates a SW switching control signal SCS for switching the connection of the SW 19 so as to supply the signal amplitude value SV from the detection circuit 18 to the ADC 20. , Supplied to SW19.

  On the other hand, when the digital amplitude value DSV is equal to or higher than the reference signal strength RTH in a state where the SW 19 is supplying the signal amplitude value SV that is the output of the detection circuit 18 to the ADC 20, SW switching control that maintains the state as it is in the SW19. A signal SCS is generated and supplied to the SW 19. When the digital amplitude value DSV becomes less than the reference signal strength RTH, the SW switching control unit 22 generates the SW switching control signal SCS for switching the connection of the SW 19 so as to supply the RSSI value RV from the RSSI circuit 17 to the ADC 20. Supply to SW19.

  As described above, the receiving circuit 10 of the present embodiment does not periodically switch the connection of the SW 19 at a predetermined cycle as in the first embodiment, but instead of the reference signal strength RTH and the digital RSSI value RV or the digital amplitude value. The connection of the SW 19 is switched according to the magnitude relationship with the DSV. For this reason, when the received signal strength is less than the reference signal strength RTH, the RSSI value RV can be acquired and converted into the digital value DV a plurality of times regardless of the operation of the detection circuit 18. Similarly, when the received signal strength is equal to or higher than the reference signal strength RTH, the signal amplitude value SV can be acquired a plurality of times and converted into the digital value DV regardless of the operation of the RSSI circuit 17. Therefore, switching of SW19 can be performed flexibly according to the radio wave condition.

  As described above, the wireless reception device of the present invention includes one of the first signal strength detection circuit (RSSI circuit 17) and the second signal strength detection circuit (detection circuit 18), and the analog-digital converter (ADC 20). And a changeover switch (SW19) for supplying the first detection value (RSSI value RV) or the second detection value (signal amplitude value SV) to the analog-to-digital converter (ADC20). The converter (ADC 20) converts the first detection value (RSSI value RV) or the second detection value (signal amplitude value SV) into a digital value (DV). Therefore, it is not necessary to separately provide an analog-digital converter (ADC 20) corresponding to each of the first signal strength detection circuit (RSSI circuit 17) or the second signal strength detection circuit (detection circuit 18). It is possible to convert the first detection value (RSSI value RV) and the second detection value (signal amplitude value SV) into a digital value (DV) while suppressing.

  In addition, this invention is not limited to the said embodiment. For example, in the above-described embodiment, the case has been described in which the SW 19 is configured by the first and second transfer gates each including the NMOS transistor and the PMOS transistor as shown in FIG. However, the configuration of the SW 19 is not limited to this, and any configuration may be used as long as the output from the RSSI circuit 17 or the output from the detection circuit 18 can be switched and supplied to the SW 19 in accordance with the SW switching control signal SCS.

  Further, in the above-described embodiment, an example in which the reference signal strength is 40 dBμV and the RSSI circuit 17 acquires the RSSI value RV that is proportional to the received signal strength in the range of 0 to 40 dBμV has been described. However, the operating range of the RSSI circuit 17 is not limited to this. It is sufficient that it operates at least at a received signal strength in the vicinity of 20 to 30 dBμV, which is a reception sensitivity level of a tuner receiving FM multiplex broadcast data.

  In the second embodiment, the receiving circuit 10 has the average value calculating circuit 41 for calculating the average value of the n digital amplitude values DSV, and the automatic gain control circuit 24 is a variable gain circuit based on the average amplitude value SAV. An example of performing gain control of 14 has been described. However, an average value calculation circuit that calculates an average value of a plurality of digital RSSI values DRV may be provided, and the calculated average value may be stored in the storage area 23.

10 receiving circuit 11 LNA
12 Local oscillator 13 Mixer 14 Variable gain circuit 15 Band pass filter 16 Demodulation circuit 17 RSSI circuit 18 Detection circuit 19 SW
20 ADC
21 logic circuit 22 SW switching control circuit 23 storage area 24 automatic gain control circuit 31 first transfer gate 32 second transfer gate 33 inverter 41 average value calculation circuit 42 reference signal strength storage unit

Claims (12)

A variable gain circuit that changes the amplitude of the input signal with a gain according to the gain control signal and outputs the output signal;
A bandpass filter that passes a signal component of a predetermined frequency band in the output signal of the variable gain circuit; and
A first signal strength detection circuit that detects the signal strength of the passing signal and obtains a first detection value when the signal strength of the passing signal that has passed through the bandpass filter is less than a reference signal strength;
A second signal strength detection circuit that detects the signal strength of the passing signal and obtains a second detection value when the signal strength of the passing signal is equal to or higher than the reference signal strength;
An analog-digital converter that converts the first detection value or the second detection value into a digital value;
One of the first and second signal strength detection circuits and the analog-digital converter are connected so as to be switchable, and the first detection value or the second detection value is supplied to the analog-digital converter. A switch,
A switching control unit for controlling switching in the selector switch;
A storage area for storing the first detection value converted into a digital value by the analog-digital converter;
A gain control circuit that generates the gain control signal based on the second detection value converted into a digital value by the analog-digital converter and controls the gain in the variable gain circuit;
A wireless receiver characterized by comprising:   The radio reception apparatus according to claim 1, wherein the first signal detection circuit is an RSSI detection circuit that acquires a received signal strength indication (RSSI) value as the first detection value.   3. The detection circuit according to claim 1, wherein the second signal detection circuit is a detection circuit that performs envelope detection on the passage signal and acquires an amplitude value of the passage signal as the second detection value. Wireless receiver.   The radio reception apparatus according to claim 1, wherein the switching control unit controls the changeover switch so as to perform the switching at a predetermined cycle. An average value calculation circuit for calculating an average value of n second detection values (n is an integer of 2 or more) converted into a digital value by the analog-digital converter;
The radio reception apparatus according to claim 1, wherein the gain control circuit controls a gain in the variable gain circuit based on the average value.   The switching control unit performs the switching according to a comparison result obtained by comparing magnitudes of the first detection value or the second detection value converted into a digital value by the analog-digital converter and the reference signal intensity. The radio reception apparatus according to claim 1, wherein the changeover switch is controlled. Changing the amplitude of the input signal with a gain according to the gain control signal to obtain an output signal;
Passing a signal component of a predetermined frequency band in the output signal to obtain a passing signal;
When the signal strength of the passing signal is less than a reference signal strength, detecting the signal strength of the passing signal to obtain a first detection value;
When the signal strength of the passing signal is equal to or higher than the reference signal strength, detecting the signal strength of the passing signal to obtain a second detection value;
Selectively switching one of the first detection value and the second detection value;
Converting the first detection value or the second detection value into a digital value in response to the switching;
Storing the first detection value converted into a digital value;
Generating the gain control signal based on the second detection value converted to a digital value;
A wireless reception method comprising:   The radio reception method according to claim 7, wherein the first detection value is an RSSI (Received Signal Strength Indication) value.   The radio reception method according to claim 7 or 8, wherein the second detection value is an amplitude value obtained by performing envelope detection on the passing signal.   10. The step of selectively switching either one of the first detection value or the second detection value includes a step of performing the switching at a predetermined cycle. Wireless reception method. Calculating an average value of the n second detection values (n is an integer of 2 or more) converted into a digital value;
The step of generating the gain control signal based on the second detection value converted into the digital value includes a step of controlling a gain in the variable gain circuit based on the average value. The wireless reception method according to any one of 7 to 10.   The step of selectively switching either the first detection value or the second detection value compares the first detection value or the second detection value converted into a digital value and the reference signal intensity. The wireless reception method according to claim 7, further comprising a step of controlling the selector switch so as to perform the switching according to the comparison result.

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