JP6643529B2 - Rectifier circuit, converter and electronic equipment - Google Patents

Description

  The present invention relates to a rectifier circuit that is, for example, a full-wave rectifier circuit, a converter including the rectifier circuit, and an electronic device including the converter.

  In a power supply system in which a power receiver receives power transmitted from a power transmitter and generates a DC voltage, a typical configuration of the power receiver that generates a DC voltage is, for example, a DC / DC converter such as a linear regulator or a switching regulator. A DC converter is provided (for example, refer to Patent Documents 1 and 2).

  In the receiving receiver, the power transmitted from the antenna coil of the power transmitter is received by another antenna coil, and output to the bridge-type full-wave rectifier circuit via the series resonance capacitor and the parallel resonance capacitor. The full-wave rectifier circuit rectifies the received AC voltage, outputs the rectified voltage to a DC / DC converter, and converts the rectified voltage into a desired DC voltage by the converter.

  As described above, in order for the power receiver to output a desired DC voltage, for example, a DC / DC converter such as a linear regulator or a switching regulator is required, which causes a problem that the circuit scale increases and external components increase. .

  An object of the present invention is to provide a rectifier circuit that can rectify an AC voltage and convert the voltage with a simple configuration as compared with the related art.

The rectifier circuit according to the present invention,
A first transistor connected between a first input terminal and an output terminal, a second transistor connected between the first input terminal and ground, a second input terminal and the output A third transistor connected between the second input terminal and a fourth transistor connected between the second input terminal and the ground;
A rectifier circuit comprising: a control circuit that controls on / off of the first to fourth transistors;
The control circuit turns on at least a part of a period in which two of the first to fourth transistors are off, thereby controlling an input applied to the first and second input terminals. It is characterized in that a voltage is converted into a voltage and output from the output terminal as an output voltage.

  According to the rectifier circuit of the present invention, since a linear regulator and a switching regulator are not used, the AC voltage can be rectified and converted with a simpler configuration than in the related art.

1 is a circuit diagram illustrating a configuration of a power supply system according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a current path P1 when an error signal ERROR is at a low level in the rectifier circuit of the power supply system of FIG. 1. FIG. 2 is a circuit diagram showing a current path P1 when an error signal ERROR is at a high level in the rectifier circuit of the power supply system of FIG. 1. FIG. 2 is a circuit diagram showing a current path P2 when an error signal ERROR is at a low level in the rectifier circuit of the power supply system of FIG. 1. FIG. 2 is a circuit diagram showing a current path P2 when an error signal ERROR is at a high level in the rectifier circuit of the power supply system of FIG. 1. FIG. 2 is a circuit diagram illustrating a current path P3 in the rectifier circuit of the power supply system of FIG. 1. 2 is a timing chart of each signal illustrating an operation of the power supply system of FIG. 1. FIG. 4 is a circuit diagram illustrating a configuration of a power supply system according to a second embodiment of the present invention. FIG. 9 is a circuit diagram illustrating a configuration of a power supply system according to a modification of the second embodiment of the present invention. FIG. 9 is a circuit diagram illustrating a configuration of a power supply system according to a third embodiment of the present invention. FIG. 13 is a block diagram illustrating a configuration of an error signal generator 10c used in a power supply system according to a fourth embodiment of the present invention. 8 is a timing chart of each voltage showing the operation of the error signal generator 10c in FIG. It is a circuit diagram showing an example of composition of a power supply system concerning Embodiment 5 of the present invention.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a configuration of a power supply system according to Embodiment 1 of the present invention. In FIG. 1, the power supply system includes a power supply device 1 having a power transmitter 3 and a power receiver 2. The power transmitter 3 of the power supply device 1 applies an AC voltage to the antenna coil L1 to wirelessly supply power to the antenna coil L2 electromagnetically coupled to the antenna coil L1.

  The power receiver 2 includes an antenna coil L2, a series resonance capacitor Cs, a parallel resonance capacitor Cd, a rectifier circuit 4, and a smoothing capacitor C1. Here, the series resonance capacitor Cs is connected in series with the antenna coil L2 to transmit and receive power by series resonance, and the parallel resonance capacitor Cd is provided for the power transmitter 3 to detect the power receiver 2 in the wireless power supply system. . Here, nodes at both ends of the parallel resonance capacitor Cd are defined as Nac1 and Nac2.

  The rectifier circuit 4 is different from a general diode bridge circuit, and includes six MOS transistors M1, M21, M22, M3, M41, and M42, and a control circuit 10 for controlling ON / OFF of the six MOS transistors M1 to M42. And is provided. The rectifier circuit 4 rectifies the voltage between both ends of the nodes Nac1 and Nac2 and outputs the voltage to the load 5 using the output node Nrect at one end of the smoothing output capacitor C1 as an output terminal. In FIG. 1, the source / drain of MOS transistor M1 is connected between node Nac1 and output node Nrect, and the source / drain of MOS transistor M3 is connected between node Nac2 and output node Nrect. The drains and sources of the MOS transistors M21 and M22 are connected between the node Nac1 and the ground, and the drains and sources of the MOS transistors M41 and M42 are connected between the node Nac2 and the ground.

  The control circuit 10 includes an error signal generator 10a that generates an error signal indicating a discharge phase period described with reference to FIG. For example, when the cycle of the received AC voltage is known and the voltage to be dropped by the rectifier circuit 4 and the component constants are known, the error signal generator 10a outputs the current path P2 (each transistor as shown in FIG. 3). Is turned on or off), for example, the MOS transistor M42 is turned on for a predetermined period. The error signal generator 10a generates, for example, an error signal ERROR for turning on the MOS transistor M22 for a predetermined period during the current path P1 (controlling each transistor on or off as shown in FIG. 3). If the input voltages of the nodes Nac1 and Nac2 are known, the rectified voltage Vrect at the node Nrect can be controlled to a predetermined voltage by charging / discharging the capacitor C1 by this on / off control.

  The operation of the rectifier circuit 4 configured as described above will be described below with reference to FIGS. 2A to 2E and FIG.

  FIG. 2A is a circuit diagram showing a current path P1 when the error signal ERROR is at a low level in the rectifier circuit of the power supply system of FIG. FIG. 2B is a circuit diagram showing the current path P1 when the error signal ERROR is at a high level in the rectifier circuit of the power supply system of FIG. FIG. 2C is a circuit diagram showing a current path P2 when the error signal ERROR is at a low level in the rectifier circuit of the power supply system of FIG. FIG. 2D is a circuit diagram showing a current path P2 when the error signal ERROR is at a high level in the rectifier circuit of the power supply system of FIG. FIG. 2E is a circuit diagram showing a current path P3 in the rectifier circuit of the power supply system of FIG. FIG. 3 is a timing chart of each signal showing the operation of the power supply system of FIG.

In FIG. 2A, when the error signal ERROR is at a low level, a current flows from the antenna coil L2 and returns to the antenna coil L2 through the following path.
The antenna coil L2 → the capacitor Cs → the node Nac1 → the transistor M1 → the capacitor C1 → the transistors M41 and M42 → the node Nac2 → the antenna coil L2.
The capacitor C1 is charged by the current in the current path P1, and the period of the current path P1 is a charging phase.

In FIG. 2B, the current path P1 when the error signal ERROR is at a high level flows through the following path, and the current flows from the capacitor C1 to return to the antenna coil L2.
The capacitor C1 → the transistor M1 → the transistor M22 → the transistors M41 and M42 → the node Nac2 → the antenna coil L2 → the capacitor Cs → the node Nac1 → the transistor M22 (the same applies hereinafter).
The capacitor C1 is discharged by the current of the current path P1, and the period of the current path P1 is a discharge phase.

  As shown in FIG. 2B, turning on the MOS transistor M22 when the error signal ERROR is at a high level changes the current path from that in FIG. 2A. The discharging phase is such that the capacitor C1 is discharged until the MOS transistor M22 turns off. The reason why only the MOS transistor M22 is turned on instead of turning on both the MOS transistors M21 and M22 is to enable changing the transistor size when the error signal ERROR is at the high level. The transistor size of the MOS transistor M22 is determined based on a desired output voltage, load current, and the like.

In FIG. 2C, when the error signal ERROR is at a low level, a current flows from the antenna coil L2 and returns to the antenna coil L2 through the following path.
The antenna coil L2 → the node Nac2 → the transistor M3 → the capacitor C1 → the transistors M21 and M22 → the node Nac1 → the capacitor Cs → the antenna coil L2.
The capacitor C1 is charged by the current of the current path P2, and the period of the current path P2 is a charging phase.

In FIG. 2D, when the error signal ERROR is at a high level, a current flows from the capacitor C1 through the following path and returns to the antenna coil L2.
The capacitor C1 → the transistor M3 → the transistor M42 → the transistors M21 and M22 → the node Nac1 → the capacitor Cs → the antenna coil L2 → the node Nac2 → the transistor M42 (the same applies hereinafter).

  In the case of the current path P2, when the error signal ERROR is at a high level, the rectified current path changes by turning on the MOS transistor M42. The current from the antenna coil L2 and the current from the capacitor C1 flow into the transistor M42, forming a path through which the current flows to the antenna L1 via the transistors M21 and M22. Accordingly, a discharging phase is reached in which the capacitor C1 is discharged until the transistor M42 is turned off.

In FIG. 2E, a current path P3 flows through the following path from the capacitor Cd to be discharged to the antenna coil L2.
Capacitor Cd → node Nac1 → capacitor Cs → antenna coil L2 → node Nac2 → capacitor Cd or capacitor Cd → node Nac2 → antenna coil L2 → capacitor Cs → node Nac1 → capacitor Cd.

  FIG. 3 is a timing chart of each signal showing the operation of the power supply system of FIG. Here, the MOS transistor M42 is turned on based on the error signal ERROR during the current path P2, and the MOS transistor M22 is turned on based on the error signal ERROR during the current path P1. As a result, it is possible to set the discharge phase and reduce the input voltage by a predetermined voltage drop to control the output voltage to a predetermined output voltage.

  According to the present embodiment, for example, if the cycle of the received AC voltage, the drop voltage, the component constant, and the like are known, the charge and discharge of the capacitor C1 by the on / off control of the control circuit 10 causes the node Nrect. Of the rectified voltage Vrect can be controlled to a predetermined voltage.

  In the first embodiment described above, one MOS transistor is divided into two MOS transistors M21 and M22. However, the present invention is not limited to this and may not be divided. When dividing, the size ratio between the two MOS transistors M21 and M22 is determined in consideration of the discharge current of the MOS transistor M22 on the side to be described later. Further, one MOS transistor is divided into two MOS transistors M41 and M42, but the present invention is not limited to this, and may not be divided. When dividing, the size ratio of the two MOS transistors M41 and M42 is determined in consideration of the discharge current of the MOS transistor M42 on the side to be described later. Here, the step-down voltage of the output voltage output from the converter of the rectifier circuit 4 is determined depending on the discharge current, that is, the size ratio.

Embodiment 2. FIG.
FIG. 4 is a circuit diagram showing a configuration of a power supply system according to Embodiment 2 of the present invention. 4, the power supply system according to the second embodiment differs from the power supply system according to the first embodiment in FIG. 1 in the following points.
(1) The current flowing through the MOS transistors M21 and M41 is detected to determine that the current phase is any of the current paths P1, P2, and P3, and a determination signal indicating the determination result is output to the control circuit 10A. And a current path detection circuit 13 that performs the operation.
(2) A control circuit 10A having an error signal generator 10b is provided instead of the control circuit 10 having the error signal generator 10a. The error signal generator 10b generates the above error signal ERROR based on the determination signal from the current path detection circuit 13, and the control circuit 10A turns on / off each of the MOS transistors M1 to M42 based on the generated error signal ERROR. Control off.

  According to the present embodiment, since the error signal ERROR is generated based on the determination signal from the current path detection circuit 13, the ON / OFF control of the MOS transistors M1 to M42 is performed after confirming the periods of the current paths P1 and P2. It can be carried out. As a result, on / off control can be accurately performed in terms of time. If the input voltages of the nodes Nac1 and Nac2 are known, the rectified voltage Vrect at the node Nrect can be controlled to a predetermined voltage by charging and discharging the capacitor C1 by on / off control by the control circuit 10A. it can.

Modification of the second embodiment.
FIG. 5 is a circuit diagram showing a configuration of a power supply system according to a modification of the second embodiment of the present invention. In the embodiment of FIG. 4, the current path detection circuit 13 detects the current flowing through the MOS transistors M21 and M41, and determines which of the current paths P1, P2, and P3 is the current phase. A determination signal indicating the result is output. On the other hand, in the modified example, the current path detection circuit 13A determines which phase of the current paths P1, P2, and P3 is based on voltage detection instead of current detection, and outputs a determination signal indicating a determination result. . That is, the current path detection circuit 13A detects each drain voltage of the MOS transistors M21 and M41, determines which phase is the current path P1, P2, or P3, and indicates a determination signal indicating a determination result. Is output. The other configuration is the same as that of the second embodiment, and the operation and effect are also the same.

Embodiment 3 FIG.
FIG. 6 is a circuit diagram showing a configuration of a power supply system according to Embodiment 3 of the present invention. The power supply system of FIG. 6 differs from the power supply system according to the second embodiment of FIG. 4 in the following points.
(1) A control circuit 10B having no error signal generator is provided instead of the control circuit 10A.
(2) The error signal generator 10c is provided outside the control circuit 10B. The error signal generator 10c generates an error signal ERROR based on the rectified voltage Nrect as an output voltage and outputs the error signal ERROR to the control circuit 10B when the rectified voltage Nrect is out of a predetermined voltage range. The control circuit 10B controls ON / OFF of the MOS transistors M1 to M42 based on the determination signal from the current path detection circuit 13 and the error signal ERROR as in the second embodiment.

  In the first and second embodiments, the period, the voltage drop, the component constant, and the like are restricted. However, in the third embodiment, the output voltage is fed back, and such a restriction is unnecessary.

Embodiment 4. FIG.
FIG. 7 is a block diagram showing a configuration of the error signal generator 10c used in the power supply system according to Embodiment 4 of the present invention. The power supply system according to the fourth embodiment is characterized by including the error signal generator 10c shown in FIG. The error signal generator 10c includes voltage dividing resistors R1 and R2, reference voltage sources 21 and 22, comparators 23 and 24, and a latch circuit 25.

  7, the rectified voltage Vrect is divided by voltage dividing resistors R1 and R2 connected in series, and the divided voltage Vrect_FB is input to the non-inverting input terminal of the comparator 23 and the inverting input terminal of the comparator 24. Further, the reference voltage source 21 generates a predetermined reference voltage VREFH, which is a voltage slightly lower than the maximum voltage that the divided voltage Vrect_FB can take, for example, and outputs it to the inverting input terminal of the comparator 23. The reference voltage source 22 generates, for example, a predetermined reference voltage VREFL that is slightly higher than the minimum voltage that the divided voltage Vrect_FB can take and lower than the reference voltage VREFH, and outputs it to the non-inverting input terminal of the comparator 24. Each of the comparators 23 and 24 outputs a low-level comparison result signal when the voltage input to the non-inverting input terminal is lower than the voltage input to the inverting input terminal. Further, each of the comparators 23 and 24 outputs a high-level comparison result signal when the voltage input to the non-inverting input terminal is higher than the voltage input to the inverting input terminal. The latch circuit 25 is composed of, for example, a set / reset type flip-flop. The latch circuit 25 sets and outputs the error signal ERROR to a high level based on the high-level comparison result signal from the comparator 23, and outputs the error signal ERROR to a low level based on the high-level comparison result signal from the comparator 24. Reset to.

  FIG. 8 is a timing chart of each voltage showing the operation of the error signal generator 10c of FIG. As is apparent from FIG. 8, an error signal ERROR is generated according to a change in the divided voltage corresponding to the rectified voltage Vrect. Here, the rectified voltage Vrect can be controlled to a desired voltage by setting the reference voltages VREFH and VREFL as described above and selectively switching the charge phase / discharge phase by the ERROR signal. The control circuit 10B can obtain a desired output voltage by performing control as shown in FIG. 3 based on the error signal ERROR and the current path detection signal.

Embodiment 5 FIG.
FIG. 9 is a circuit diagram showing a configuration example of a power supply system according to Embodiment 5 of the present invention. The power supply system according to the fifth embodiment is a power supply system for an electronic device 6 such as a mobile phone, a smart phone, and a personal computer. The power supply system includes a power supply device 1 and an electronic device 6. The electronic device 6 includes the power receiver 2 and the load 5 that is a load circuit of the electronic device 6. Power receiver 2 includes rectifier circuit 4 for constituting an AC / DC converter. Here, the rectifier circuit 4 is the rectifier circuit according to the first to fourth embodiments.

  As described above, according to the present embodiment, the power supply system can be applied to the electronic device 6.

Summary of Embodiment.
The rectifier circuit according to the first aspect includes:
A first transistor connected between a first input terminal and an output terminal, a second transistor connected between the first input terminal and ground, a second input terminal and the output A third transistor connected between the second input terminal and a fourth transistor connected between the second input terminal and the ground;
A rectifier circuit comprising: a control circuit that controls on / off of the first to fourth transistors;
The control circuit turns on at least a part of a period in which two of the first to fourth transistors are off, thereby controlling an input applied to the first and second input terminals. It is characterized in that a voltage is converted into a voltage and output from the output terminal as an output voltage.

The rectifier circuit according to a second aspect is the rectifier circuit according to the first aspect, wherein the control circuit includes the rectifier circuit in at least a part of a rectification current period in which the first and fourth transistors are on. The voltage is converted by turning on the second transistor,
The control circuit performs voltage conversion by turning on the fourth transistor in at least a part of a rectified current period in which the second and third transistors are on.

The rectifier circuit according to a third aspect is the rectifier circuit according to the second aspect,
The second transistor is divided into a fifth transistor and a sixth transistor, and both the fifth and sixth transistors are turned on during a rectified current period in which the second transistor is turned on. When turning on the second transistor for voltage conversion, turning on one of the fifth and sixth transistors;
The fourth transistor is divided into a seventh transistor and an eighth transistor, and both the seventh and eighth transistors are turned on during a rectified current period in which the fourth transistor is turned on. When turning on the fourth transistor for voltage conversion, one of the seventh and eighth transistors is turned on.

The rectifier circuit according to a fourth aspect is the rectifier circuit according to the third aspect,
The fifth transistor and the sixth transistor are formed at a predetermined size ratio,
The seventh transistor and the eighth transistor are formed at a predetermined size ratio.

The rectifier circuit according to a fifth aspect is the rectifier circuit according to any one of the first to fourth aspects,
The rectifier circuit detects that a rectified current is flowing through the second transistor and outputs a first detection signal, and detects that a rectified current is flowing through the fourth transistor and generates a second detection signal. A first detection circuit that outputs a detection signal of
The control circuit converts the voltage by turning on the fourth transistor based on the first detection signal, and converts the voltage by turning on the second transistor based on the second detection signal. It is characterized by the following.

The rectifier circuit according to a sixth aspect is the rectifier circuit according to the fifth aspect,
The rectifier circuit further includes a second detection circuit that detects a voltage of the output terminal,
The control circuit converts the voltage by turning on the fourth transistor based on the first detection signal and the detected voltage, and performs the voltage conversion based on the second detection signal and the detected voltage. Voltage conversion is performed by turning on the second transistor.

The rectifier circuit according to a seventh aspect is the rectifier circuit according to the fifth aspect,
The rectifier circuit compares the voltage of the output terminal with a first threshold voltage and a second threshold voltage that is lower than the first threshold voltage. A comparison circuit that outputs a comparison result signal until the voltage becomes equal to or less than the second threshold voltage after exceeding the first threshold voltage;
The control circuit converts the voltage by turning on the fourth transistor based on the first detection signal and the comparison result signal, and performs the second conversion based on the second detection signal and the comparison result signal. Is turned on to convert the voltage.

A converter according to an eighth aspect includes:
An antenna coil for receiving power from the power transmitter,
A series resonance capacitor connected in series with the antenna coil,
A parallel resonance capacitor connected in parallel with the antenna coil,
After receiving the power, rectify a voltage obtained through the series resonance capacitor and the parallel resonance capacitor, a rectifier circuit according to any one of first to seventh aspects,
An output capacitor for smoothing and outputting the rectified voltage.

An electronic device according to a ninth aspect includes:
The converter according to the eighth aspect is provided.

  In the above embodiment, since a linear regulator and a switching regulator are not required on the output side of the rectifier circuit 4 to obtain a predetermined output voltage, the circuit scale can be reduced and the number of external components can be reduced.

  In the above embodiment, each transistor connected between each input node Nac1 and Nac2 of the rectifier circuit 4 and the ground is divided into two transistors M21 and M22; M41 and M42, respectively. Then, both of the transistors M21 and M22; M41 and M42 are turned on during a part of the current path P1 or P2. Further, when turning on / off according to the output voltage or the like of the rectifier circuit 4, only one of the transistors M22 and M42 is used, so that the size ratio of each pair of transistors depends on the specified output voltage and the assumed load current. Can be set individually.

  In the above embodiment, when the current path is not used in the rectifier circuit 4, the control is performed so that the transistors M <b> 1 to M <b> 42 are not turned on (current path P <b> 3) regardless of the output voltage value of the rectifier circuit 4. Can not drop sharply.

  In the fourth embodiment described above, an error signal ERROR is generated by comparing a divided voltage obtained by dividing the output voltage Vrect of the rectifier circuit 4 with the reference voltages VREFH and VREFL, and only one of the transistors M22 and M42 is turned on. To lower the input voltage by a predetermined voltage. Thereby, it can be configured to obtain a predetermined output voltage.

1. Power supply device,
2. Power receiver,
3. Power transmitter,
4 ... Rectifier circuit,
5 ... load,
6 ... Electronic equipment,
10, 10A, 10B ... control circuit,
10a, 10b, 10c ... error signal generator,
11, 12 ... current detector,
13, 13A ... current path detection circuit,
21, 22 ... reference voltage source,
23, 24 ... Comparator,
25 ... Latch circuit,
Cs, Cd, C1 ... capacitors,
L1, L2 ... antenna coil,
M1, M3, M21, M22, M41, M42 ... MOS transistors,
Nac1, Nac2, Nrect ... nodes,
P1, P2, P3 ... rectified current paths,
R1, R2: voltage dividing resistors.

JP 2004-187417 A JP 2014-168342 A

Claims (8)

A first transistor connected between a first input terminal and an output terminal, a second transistor connected between the first input terminal and ground, a second input terminal and the output A third transistor connected between the second input terminal and a fourth transistor connected between the second input terminal and the ground;
A rectifier circuit comprising: a control circuit that controls on / off of the first to fourth transistors;
The control circuit performs voltage conversion by turning on the second transistor in at least a part of a rectified current period in which the first and fourth transistors are on,
The rectifier circuit, wherein the control circuit converts the voltage by turning on the fourth transistor in at least a part of a rectification current period in which the second and third transistors are on . The second transistor is divided into a fifth transistor and a sixth transistor, and both the fifth and sixth transistors are turned on during a rectified current period in which the second transistor is turned on. When turning on the second transistor for voltage conversion, turning on one of the fifth and sixth transistors;
The fourth transistor is divided into a seventh transistor and an eighth transistor, and both the seventh and eighth transistors are turned on during a rectified current period in which the fourth transistor is turned on. , the fourth time to be turned on for the transistor voltage conversion, rectifying circuit according to claim 1, wherein turning on the one of the transistors in the seventh and eighth. The fifth transistor and the sixth transistor are formed at a predetermined size ratio,
The rectifier circuit according to claim 2, wherein the seventh transistor and the eighth transistor are formed at a predetermined size ratio. The rectifier circuit detects that a rectified current is flowing through the second transistor and outputs a first detection signal, and detects that a rectified current is flowing through the fourth transistor and generates a second detection signal. A first detection circuit that outputs a detection signal of
The control circuit converts the voltage by turning on the fourth transistor based on the first detection signal, and converts the voltage by turning on the second transistor based on the second detection signal. The rectifier circuit according to any one of claims 1 to 3 , wherein: The rectifier circuit further includes a second detection circuit that detects a voltage of the output terminal,
The control circuit converts the voltage by turning on the fourth transistor based on the first detection signal and the detected voltage, and performs the voltage conversion based on the second detection signal and the detected voltage. The rectifier circuit according to claim 4, wherein voltage conversion is performed by turning on the second transistor. The rectifier circuit compares the voltage of the output terminal with a first threshold voltage and a second threshold voltage that is lower than the first threshold voltage. A comparison circuit that outputs a comparison result signal until the voltage becomes equal to or less than the second threshold voltage after exceeding the first threshold voltage;
The control circuit converts the voltage by turning on the fourth transistor based on the first detection signal and the comparison result signal, and performs the second conversion based on the second detection signal and the comparison result signal. The rectifier circuit according to claim 4, wherein voltage conversion is performed by turning on said transistor. An antenna coil for receiving power from the power transmitter,
A series resonance capacitor connected in series with the antenna coil,
A parallel resonance capacitor connected in parallel with the antenna coil ,
The rectifier circuit according to any one of claims 1 to 6 , wherein after receiving the power, the voltage obtained through the series resonance capacitor and the parallel resonance capacitor is rectified . An electronic apparatus comprising the rectifier circuit according to claim 7 .

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