JP6639740B1 - Semiconductor device, power conversion device, and method of manufacturing semiconductor device - Google Patents

Semiconductor device, power conversion device, and method of manufacturing semiconductor device Download PDF

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JP6639740B1
JP6639740B1 JP2019520761A JP2019520761A JP6639740B1 JP 6639740 B1 JP6639740 B1 JP 6639740B1 JP 2019520761 A JP2019520761 A JP 2019520761A JP 2019520761 A JP2019520761 A JP 2019520761A JP 6639740 B1 JP6639740 B1 JP 6639740B1
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祥 小杉
祥 小杉
麻緒 澤川
麻緒 澤川
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Abstract

半導体装置（１）は、絶縁回路基板（１０）と、絶縁層（１４）とを備える。絶縁回路基板（１０）は、第１導体層（１２）を含む。第１導体層（１２）は、本体部（１５）と、突出部（１６）とを含む。絶縁層（１４）は、本体部（１５）の第４主面（１５ｂ）及び第１側面（１５ｃ）と突出部（１６）の第６主面（１６ｂ）及び第２側面（１６ｃ）との上に形成されている。第１凸状角部（１５ｄ）における絶縁層（１４）の第３厚さ（ｔ3）と、第２凸状角部（１６ｄ）における絶縁層（１４）の第４厚さ（ｔ4）と、第３凸状角部（１６ｅ）における絶縁層（１４）の第５厚さ（ｔ5）とは、各々、第４主面（１５ｂ）上に形成されている絶縁層（１４）の第６厚さ（ｔ6）よりも大きい。そのため、半導体装置（１）の絶縁破壊電圧を増加させることができる。The semiconductor device (1) includes an insulating circuit board (10) and an insulating layer (14). The insulated circuit board (10) includes a first conductor layer (12). The first conductor layer (12) includes a main body (15) and a protrusion (16). The insulating layer (14) is formed between the fourth main surface (15b) and the first side surface (15c) of the main body (15) and the sixth main surface (16b) and the second side surface (16c) of the protrusion (16). Is formed on. A third thickness (t3) of the insulating layer (14) at the first convex corner (15d), a fourth thickness (t4) of the insulating layer (14) at the second convex corner (16d), The fifth thickness (t5) of the insulating layer (14) at the third convex corner (16e) is the sixth thickness of the insulating layer (14) formed on the fourth main surface (15b). (T6). Therefore, the breakdown voltage of the semiconductor device (1) can be increased.

Description

本発明は、半導体装置、電力変換装置及び半導体装置の製造方法に関する。   The present invention relates to a semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device.

特開２００６−６００６５号公報（特許文献１）は、絶縁配線基板と、パワー半導体素子と、絶縁膜とを備える半導体装置が開示されている。絶縁配線基板は、絶縁基板と、絶縁基板上に形成されている導体層とを含んでいる。パワー半導体素子は、絶縁配線基板上に搭載されている。絶縁膜は、導体層上に形成されている。   Japanese Patent Laying-Open No. 2006-60065 (Patent Document 1) discloses a semiconductor device including an insulated wiring board, a power semiconductor element, and an insulating film. The insulated wiring board includes an insulated substrate and a conductor layer formed on the insulated substrate. The power semiconductor element is mounted on an insulated wiring board. The insulating film is formed on the conductor layer.

特開２００６−６００６５号公報JP 2006-60065 A

半導体装置の使用状態において、パワー半導体素子には、数百ボルトを超える高い電圧が印加される。そのため、特許文献１に開示された半導体装置の使用状態において、導体層の角部から沿面放電が発生して、絶縁膜に絶縁破壊が発生することがあった。本発明は、上記の課題を鑑みてなされたものであり、その目的は、絶縁破壊電圧を増加させることができる半導体装置を提供することである。本発明の別の目的は、絶縁破壊電圧を増加させることができる電力変換装置を提供することである。   In a use state of the semiconductor device, a high voltage exceeding several hundred volts is applied to the power semiconductor element. Therefore, in the use state of the semiconductor device disclosed in Patent Document 1, creeping discharge may occur from a corner of the conductor layer, and dielectric breakdown may occur in the insulating film. The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of increasing a dielectric breakdown voltage. Another object of the present invention is to provide a power converter capable of increasing a breakdown voltage.

本発明の半導体装置は、絶縁回路基板と、半導体素子と、絶縁層とを備える。絶縁回路基板は、絶縁基板と、導体層とを含む。絶縁基板は、第１主面と、第１主面とは反対側の第２主面とを含む。導体層は、絶縁基板の第１主面上に設けられている。導体層は、本体部と、突出部とを含む。本体部は、第１主面に接触する第３主面と、第３主面とは反対側の第４主面と、第３主面と第４主面とを接続する第１側面とを含む。突出部は、第１側面から突出している。突出部は、第１主面に接触する第５主面と、第５主面とは反対側の第６主面と、第５主面と第６主面とを接続し、かつ、第１側面とは反対側の第２側面とを含む。第５主面と第６主面の間の第１距離によって規定される突出部の第１厚さは、第３主面と第４主面との間の第２距離によって規定される本体部の第２厚さよりも小さい。   The semiconductor device of the present invention includes an insulated circuit board, a semiconductor element, and an insulating layer. The insulated circuit board includes an insulated board and a conductor layer. The insulating substrate includes a first main surface and a second main surface opposite to the first main surface. The conductor layer is provided on the first main surface of the insulating substrate. The conductor layer includes a main body and a protrusion. The main body includes a third main surface that contacts the first main surface, a fourth main surface opposite to the third main surface, and a first side surface that connects the third main surface and the fourth main surface. Including. The protrusion protrudes from the first side surface. The protruding portion connects the fifth main surface in contact with the first main surface, the sixth main surface opposite to the fifth main surface, the fifth main surface and the sixth main surface, and And a second side opposite to the side. The first thickness of the protrusion defined by the first distance between the fifth major surface and the sixth major surface is a main body defined by the second distance between the third major surface and the fourth major surface. Is smaller than the second thickness.

半導体素子は、導体層に接合されている。絶縁層は、第４主面と第１側面と第６主面と第２側面との上に形成されている。第４主面と第１側面とが交差することによって形成される本体部の第１凸状角部における絶縁層の第３厚さと、第５主面と第２側面とが交差することによって形成される突出部の第２凸状角部における絶縁層の第４厚さと、第６主面と第２側面とが交差することによって形成される突出部の第３凸状角部における絶縁層の第５厚さとは、各々、第１凸状角部以外の第４主面上に形成されている絶縁層の第６厚さよりも大きい。   The semiconductor element is joined to the conductor layer. The insulating layer is formed on the fourth main surface, the first side surface, the sixth main surface, and the second side surface. The third thickness of the insulating layer at the first convex corner of the main body formed by the intersection of the fourth main surface and the first side surface, and the intersection of the fifth main surface and the second side surface. The fourth thickness of the insulating layer at the second convex corner of the protrusion to be formed and the insulation layer at the third convex corner of the protrusion formed by the intersection of the sixth main surface and the second side surface. The fifth thickness is larger than the sixth thickness of the insulating layer formed on the fourth main surface other than the first convex corner.

本発明の半導体装置の製造方法は、絶縁回路基板の導体層に半導体素子を接合することを備える。絶縁回路基板は、絶縁基板と導体層とを含む。絶縁基板は、第１主面と、第１主面とは反対側の第２主面とを含む。導体層は、絶縁基板の第１主面上に設けられている。導体層は、本体部と、突出部とを含む。本体部は、第１主面に接触する第３主面と、第３主面とは反対側の第４主面と、第３主面と第４主面とを接続する第１側面とを含む。突出部は、第１側面から突出している。突出部は、第１主面に接触する第５主面と、第５主面とは反対側の第６主面と、第５主面と第６主面とを接続し、かつ、第１側面とは反対側の第２側面とを含む。第５主面と第６主面の間の第１距離によって規定される突出部の第１厚さは、第３主面と第４主面との間の第２距離によって規定される本体部の第２厚さよりも小さい。   A method for manufacturing a semiconductor device according to the present invention includes joining a semiconductor element to a conductor layer of an insulated circuit board. The insulated circuit board includes an insulating board and a conductor layer. The insulating substrate includes a first main surface and a second main surface opposite to the first main surface. The conductor layer is provided on the first main surface of the insulating substrate. The conductor layer includes a main body and a protrusion. The main body includes a third main surface that contacts the first main surface, a fourth main surface opposite to the third main surface, and a first side surface that connects the third main surface and the fourth main surface. Including. The protrusion protrudes from the first side surface. The protruding portion connects the fifth main surface in contact with the first main surface, the sixth main surface opposite to the fifth main surface, the fifth main surface and the sixth main surface, and And a second side opposite to the side. The first thickness of the protrusion defined by the first distance between the fifth major surface and the sixth major surface is a main body defined by the second distance between the third major surface and the fourth major surface. Is smaller than the second thickness.

本発明の半導体装置の製造方法は、絶縁層を第４主面と第１側面と第６主面と第２側面との上に形成することをさらに備える。第４主面と第１側面とが交差することによって形成される導体層の第１凸状角部における絶縁層の第３厚さと、第５主面と第２側面とが交差することによって形成される突出部の第２凸状角部における絶縁層の第４厚さと、第６主面と第２側面とが交差することによって形成される突出部の第３凸状角部における絶縁層の第５厚さとは、各々、第１凸状角部以外の第４主面上に形成されている絶縁層の第６厚さよりも大きい。   The method for manufacturing a semiconductor device according to the present invention further includes forming an insulating layer on the fourth main surface, the first side surface, the sixth main surface, and the second side surface. The third thickness of the insulating layer at the first convex corner of the conductor layer formed by the intersection of the fourth main surface and the first side surface, and the intersection of the fifth main surface and the second side surface. The fourth thickness of the insulating layer at the second convex corner of the protrusion to be formed and the insulation layer at the third convex corner of the protrusion formed by the intersection of the sixth main surface and the second side surface. The fifth thickness is larger than the sixth thickness of the insulating layer formed on the fourth main surface other than the first convex corner.

本発明の電力変換装置は、主変換回路と、制御回路とを備える。主変換回路は、実施の形態１の半導体装置を有し、かつ、入力される電力を変換して出力し得るように構成されている。制御回路は、主変換回路を制御する制御信号を主変換回路に出力し得るように構成されている。   The power conversion device of the present invention includes a main conversion circuit and a control circuit. The main conversion circuit includes the semiconductor device of the first embodiment, and is configured to convert input power and output the converted power. The control circuit is configured to output a control signal for controlling the main conversion circuit to the main conversion circuit.

絶縁層は、本体部の第１凸状角部と突出部の第２凸状角部及び第３凸状角部とに局所的に厚く形成されている。本発明の半導体装置及び電力変換装置の絶縁破壊電圧は増加する。本発明の半導体装置の製造方法によれば、増加された絶縁破壊電圧を有する半導体装置が製造され得る。半導体装置の使用中に、絶縁層に絶縁破壊が発生することが抑制され得る。   The insulating layer is locally thickly formed at the first convex corner of the main body and at the second convex corner and the third convex corner of the protrusion. The breakdown voltage of the semiconductor device and the power converter of the present invention increases. According to the method of manufacturing a semiconductor device of the present invention, a semiconductor device having an increased breakdown voltage can be manufactured. During the use of the semiconductor device, occurrence of dielectric breakdown in the insulating layer can be suppressed.

実施の形態１に係る半導体装置の概略断面図である。FIG. 2 is a schematic sectional view of the semiconductor device according to the first embodiment; 実施の形態１に係る半導体装置の、図１に示される領域ＩＩの概略部分拡大断面図である。FIG. 2 is a schematic partial enlarged sectional view of a region II shown in FIG. 1 of the semiconductor device according to the first embodiment; 実施の形態１に係る半導体装置の製造方法のフローチャートを示す図である。FIG. 4 is a diagram showing a flowchart of the method for manufacturing the semiconductor device according to the first embodiment. 実施の形態１の実施例において、第１導体層及び第２導体層上に絶縁層を電着法により形成する際に、第１導体層の周りに形成される電界強度分布を示す図である。FIG. 7 is a diagram showing an electric field intensity distribution formed around the first conductor layer when an insulating layer is formed on the first conductor layer and the second conductor layer by an electrodeposition method in the example of the first embodiment. . 第１の比較例において、第１導体層及び第２導体層上に絶縁層を電着法により形成する際に、第１導体層の周りに形成される電界強度分布を示す図である。FIG. 9 is a view showing an electric field intensity distribution formed around the first conductor layer when an insulating layer is formed on the first conductor layer and the second conductor layer by the electrodeposition method in the first comparative example. 第２の比較例において、第１導体層及び第２導体層上に絶縁層を電着法により形成する際に、第１導体層の周りに形成される電界強度分布を示す図である。FIG. 9 is a diagram showing an electric field intensity distribution formed around the first conductor layer when an insulating layer is formed on the first conductor layer and the second conductor layer by the electrodeposition method in the second comparative example. 第３の比較例において、第１導体層及び第２導体層上に絶縁層を電着法により形成する際に、第１導体層の周りに形成される電界強度分布を示す図である。FIG. 13 is a diagram showing an electric field intensity distribution formed around the first conductor layer when an insulating layer is formed on the first conductor layer and the second conductor layer by an electrodeposition method in a third comparative example. 第１導体層及び第２導体層上に絶縁層を電着法により形成する際に、本体部の第１凸状角部と突出部の第２凸状角部及び第３凸状角部とにおける電界強度が０．２ｋＶ以上となる、突出部の突出長さと第１厚さを示す図である。When forming an insulating layer on the first conductor layer and the second conductor layer by electrodeposition, the first convex corner of the main body, the second convex corner and the third convex corner of the protrusion, FIG. 4 is a diagram showing a protrusion length and a first thickness of a protrusion at which the electric field intensity becomes 0.2 kV or more. 実施の形態２に係る電力変換システムの構成を示すブロック図である。FIG. 9 is a block diagram illustrating a configuration of a power conversion system according to a second embodiment.

以下、本発明の実施の形態を説明する。なお、同一の構成には同一の参照番号を付し、その説明は繰り返さない。   Hereinafter, embodiments of the present invention will be described. Note that the same components are denoted by the same reference numerals, and description thereof will not be repeated.

実施の形態１．
図１及び図２を参照して、実施の形態１に係る半導体装置１を説明する。半導体装置１は、絶縁回路基板１０と、半導体素子２０，２０ａと、絶縁層１４とを主に備える。半導体装置１は、封止部材３７をさらに備えてもよい。半導体装置１は、ケース３０をさらに備えてもよい。半導体装置１は、絶縁層１４ｂをさらに備えてもよい。一例として、半導体装置１は、半導体素子２０，２０ａとしてパワー半導体素子を備えるパワー半導体モジュールであってもよい。Embodiment 1 FIG.
The semiconductor device 1 according to the first embodiment will be described with reference to FIGS. The semiconductor device 1 mainly includes an insulating circuit board 10, semiconductor elements 20, 20a, and an insulating layer 14. The semiconductor device 1 may further include a sealing member 37. The semiconductor device 1 may further include a case 30. The semiconductor device 1 may further include an insulating layer 14b. As an example, the semiconductor device 1 may be a power semiconductor module including a power semiconductor element as the semiconductor elements 20 and 20a.

絶縁回路基板１０は、絶縁基板１１と、第１導体層１２とを含む。絶縁基板１１は、第１主面１１ａと、第１主面１１ａとは反対側の第２主面１１ｂとを含む。絶縁基板１１は、特に限定されないが、窒化アルミニウム（ＡｌＮ）製であってもよい。第１主面１１ａは絶縁基板１１のおもて面であり、第２主面１１ｂは絶縁基板１１の裏面である。   The insulating circuit board 10 includes an insulating substrate 11 and a first conductor layer 12. The insulating substrate 11 includes a first main surface 11a and a second main surface 11b opposite to the first main surface 11a. The insulating substrate 11 is not particularly limited, but may be made of aluminum nitride (AlN). The first main surface 11a is a front surface of the insulating substrate 11, and the second main surface 11b is a back surface of the insulating substrate 11.

第１導体層１２は、絶縁基板１１の第１主面１１ａ上に設けられている。第１導体層１２は、特に限定されないが、銅またはアルミニウム製であってもよい。第１導体層１２は、本体部１５と、突出部１６とを含む。本体部１５は、第１主面１１ａに接触する第３主面１５ａと、第３主面１５ａとは反対側の第４主面１５ｂと、第３主面１５ａと第４主面１５ｂとを接続する第１側面１５ｃとを含む。本体部１５は、第４主面１５ｂと第１側面１５ｃとが交差することによって形成される第１凸状角部１５ｄを含む。本体部１５は、第４主面１５ｂと第１側面１５ｃとが交差することによって形成される第１稜線１５ｉを含む。第３主面１５ａは本体部１５の裏面であり、第４主面１５ｂは本体部１５のおもて面である。   The first conductor layer 12 is provided on the first main surface 11 a of the insulating substrate 11. The first conductor layer 12 is not particularly limited, but may be made of copper or aluminum. The first conductor layer 12 includes a main body 15 and a protrusion 16. The main body 15 includes a third main surface 15a in contact with the first main surface 11a, a fourth main surface 15b opposite to the third main surface 15a, a third main surface 15a, and a fourth main surface 15b. And a first side surface 15c to be connected. The main body 15 includes a first convex corner 15d formed by the intersection of the fourth main surface 15b and the first side 15c. The main body 15 includes a first ridgeline 15i formed by the intersection of the fourth main surface 15b and the first side surface 15c. The third main surface 15a is a back surface of the main body 15, and the fourth main surface 15b is a front surface of the main body 15.

突出部１６は、本体部１５の第１側面１５ｃから突出している。第１側面１５ｃからの突出部１６の突出長さＬは、例えば、１００μｍ以上であってもよく、２００μｍ以上であってもよく、５００μｍ以上であってもよい。第１側面１５ｃからの突出部１６の突出長さＬは、例えば、８００μｍ以下であってもよい。突出部１６は、第１主面１１ａに接触する第５主面１６ａと、第５主面１６ａとは反対側の第６主面１６ｂと、第５主面１６ａと第６主面１６ｂとを接続し、かつ、第１側面１５ｃとは反対側の第２側面１６ｃとを含む。第４主面１５ｂの平面視において、本体部１５の外周全周に形成されている。突出部１６において、第５主面１６ａは突出部１６の裏面であり、第６主面１６ｂは突出部１６のおもて面である。   The protruding portion 16 protrudes from the first side surface 15 c of the main body 15. The protrusion length L of the protrusion 16 from the first side surface 15c may be, for example, 100 μm or more, 200 μm or more, or 500 μm or more. The protrusion length L of the protrusion 16 from the first side surface 15c may be, for example, 800 μm or less. The projecting portion 16 includes a fifth main surface 16a in contact with the first main surface 11a, a sixth main surface 16b opposite to the fifth main surface 16a, a fifth main surface 16a, and a sixth main surface 16b. And a second side surface 16c opposite to the first side surface 15c. The fourth main surface 15 b is formed on the entire outer periphery of the main body 15 in a plan view. In the protrusion 16, the fifth main surface 16 a is the back surface of the protrusion 16, and the sixth main surface 16 b is the front surface of the protrusion 16.

突出部１６は、第５主面１６ａと第２側面１６ｃとが交差することによって形成される第２凸状角部１６ｄを含む。突出部１６は、第５主面１６ａと第２側面１６ｃとが交差することによって形成される第２稜線１６ｉを含む。突出部１６は、第６主面１６ｂと第２側面１６ｃとが交差することによって形成される第３凸状角部１６ｅを含む。突出部１６は、第６主面１６ｂと第２側面１６ｃとが交差することによって形成される第３稜線１６ｊを含む。第５主面１６ａと第６主面１６ｂの間の第１距離によって規定される突出部１６の第１厚さｔ1は、第３主面１５ａと第４主面１５ｂとの間の第２距離によって規定される本体部１５の第２厚さｔ2よりも小さい。第１厚さｔ1は、例えば、４０μｍ以下であってもよく、２０μｍ以下であってもよい。The protruding portion 16 includes a second convex corner portion 16d formed by intersecting the fifth main surface 16a and the second side surface 16c. The protrusion 16 includes a second ridgeline 16i formed by the intersection of the fifth main surface 16a and the second side surface 16c. The protruding portion 16 includes a third convex corner portion 16e formed by the intersection of the sixth main surface 16b and the second side surface 16c. The protruding portion 16 includes a third ridgeline 16j formed by the intersection of the sixth main surface 16b and the second side surface 16c. The first thickness t 1 of the protrusion 16 defined by the first distance between the fifth main surface 16a and the sixth main surface 16b is equal to the second thickness between the third main surface 15a and the fourth main surface 15b. smaller than the second thickness t 2 of the main body portion 15 which is defined by the distance. The first thickness t 1 may be, for example, 40 μm or less, or may be 20 μm or less.

半導体素子２０，２０ａは、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）または金属酸化物半導体電界効果トランジスタ（ＭＯＳＦＥＴ）のようなパワー半導体素子であってもよい。半導体素子２０，２０ａは、還流ダイオードのようなダイオードであってもよい。半導体素子２０，２０ａは、シリコン（Ｓｉ）、炭化珪素（ＳｉＣ）または窒化ガリウム（ＧａＮ）のような半導体材料で形成されてもよい。半導体素子２０，２０ａは、それぞれ、はんだのような導電接合部材２１，２１ａを介して、第１導体層１２に接合されている。   The semiconductor devices 20 and 20a may be power semiconductor devices such as an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET). The semiconductor elements 20, 20a may be diodes such as freewheeling diodes. The semiconductor elements 20, 20a may be formed of a semiconductor material such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). The semiconductor elements 20, 20a are respectively joined to the first conductor layer 12 via conductive joining members 21, 21a such as solder.

絶縁層１４は、例えば、ポリイミド系樹脂層またはエポキシ系樹脂層であってもよい。絶縁層１４は、第４主面１５ｂと、第１側面１５ｃと、第６主面１６ｂと、第２側面１６ｃとの上に形成されている。絶縁層１４は、第４主面１５ｂと、第１側面１５ｃと、第６主面１６ｂと、第２側面１６ｃとの上に連続的に形成されてもよい。本体部１５の第１凸状角部１５ｄにおける絶縁層１４の第３厚さｔ3は、第１凸状角部１５ｄ以外の第４主面１５ｂ上に形成されている絶縁層１４の第６厚さｔ6よりも大きい。本明細書において、絶縁層１４の第３厚さｔ3は、本体部１５の第１稜線１５ｉと絶縁層１４の表面との間の最短距離として定義される。The insulating layer 14 may be, for example, a polyimide resin layer or an epoxy resin layer. The insulating layer 14 is formed on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c. The insulating layer 14 may be continuously formed on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c. The third thickness t 3 of the insulating layer 14 at the first convex corner 15d of the main body 15 is equal to the sixth thickness of the insulating layer 14 formed on the fourth main surface 15b other than the first convex corner 15d. greater than the thickness t 6. In the present specification, the third thickness t 3 of the insulating layer 14 is defined as the shortest distance between the first ridgeline 15i of the main body 15 and the surface of the insulating layer 14.

突出部１６の第２凸状角部１６ｄにおける絶縁層１４の第４厚さｔ4は、第１凸状角部１５ｄ以外の第４主面１５ｂ上に形成されている絶縁層１４の第６厚さｔ6よりも大きい。本明細書において、絶縁層１４の第４厚さｔ4は、突出部１６の第２稜線１６ｉと絶縁層１４の表面との間の最短距離として定義される。突出部１６の第３凸状角部１６ｅにおける絶縁層１４の第５厚さｔ5は、第１凸状角部１５ｄ以外の第４主面１５ｂ上に形成されている絶縁層１４の第６厚さｔ6よりも大きい。本明細書において、絶縁層１４の第４厚さｔ4は、突出部１６の第３稜線１６ｊと絶縁層１４の表面との間の最短距離として定義される。The fourth thickness t 4 of the insulating layer 14 at the second convex corner 16 d of the protrusion 16 is the sixth thickness of the insulating layer 14 formed on the fourth main surface 15 b other than the first convex corner 15 d. greater than the thickness t 6. In the present specification, the fourth thickness t 4 of the insulating layer 14 is defined as the shortest distance between the second ridgeline 16i of the protrusion 16 and the surface of the insulating layer 14. Sixth third convex corners fifth thickness t 5 of the insulating layer 14 in 16e, the first convex corners other than 15d fourth major surface 15b insulating layer formed on 14 of the protrusion 16 greater than the thickness t 6. In the present specification, the fourth thickness t 4 of the insulating layer 14 is defined as the shortest distance between the third ridge line 16j of the protrusion 16 and the surface of the insulating layer 14.

第３厚さｔ3は、第１凸状角部１５ｄ以外の第１側面１５ｃ上に形成されている絶縁層１４の第７厚さｔ7、及び、第３凸状角部１６ｅ以外の第６主面１６ｂ上に形成されている絶縁層１４の第８厚さｔ8よりも大きくてもよい。第４厚さｔ4は、第１凸状角部１５ｄ以外の第１側面１５ｃ上に形成されている絶縁層１４の第７厚さｔ7、及び、第３凸状角部１６ｅ以外の第６主面１６ｂ上に形成されている絶縁層１４の第８厚さｔ8よりも大きくてもよい。第５厚さｔ5は、第１凸状角部１５ｄ以外の第１側面１５ｃ上に形成されている絶縁層１４の第７厚さｔ7、及び、第３凸状角部１６ｅ以外の第６主面１６ｂ上に形成されている絶縁層１４の第８厚さｔ8よりも大きくてもよい。第２凸状角部１６ｄ及び第３凸状角部１６ｅ以外の第２側面１６ｃ上に形成されている絶縁層１４の第９厚さｔ9は、第７厚さｔ7及び第８厚さｔ8よりも大きくてもよい。Third thickness t 3 is the seventh thickness t 7 of the first convex corner portion 15d other than the first side surface 15c insulating layer formed on 14, and, other than the third convex corners 16e first The thickness may be larger than the eighth thickness t 8 of the insulating layer 14 formed on the sixth main surface 16b. The fourth thickness t 4 is the seventh thickness t 7 of the insulating layer 14 formed on the first side surface 15c other than the first convex corner 15d, and the fourth thickness t 4 other than the third convex corner 16e. The thickness may be larger than the eighth thickness t 8 of the insulating layer 14 formed on the sixth main surface 16b. Fifth thickness t 5, the seventh thickness t 7 of the first convex corner portion 15d other than the first side surface 15c insulating layer formed on 14, and, other than the third convex corners 16e first The thickness may be larger than the eighth thickness t 8 of the insulating layer 14 formed on the sixth main surface 16b. The ninth thickness t 9 of the insulating layer 14 formed on the second side face 16 c other than the second convex corners 16 d and the third convex corners 16 e is the seventh thickness t 7 and the eighth thickness it may be greater than t 8.

第１凸状角部１５ｄ上に形成されている絶縁層１４は、本体部１５の外周全周にわたって、同じ断面形状を有している。なお、断面は、第４主面１５ｂ及び第１側面１５ｃに垂直な断面である。第２凸状角部１６ｄ上に形成されている絶縁層１４は、突出部１６の外周全周にわたって、同じ断面形状を有している。第３凸状角部１６ｅ上に形成されている絶縁層１４は、突出部１６の外周全周にわたって、同じ断面形状を有している。なお、断面は、第６主面１６ｂ及び第１側面１５ｃに垂直な断面である。   The insulating layer 14 formed on the first convex corner portion 15d has the same cross-sectional shape over the entire outer periphery of the main body portion 15. The section is a section perpendicular to the fourth main surface 15b and the first side surface 15c. The insulating layer 14 formed on the second convex corner 16 d has the same cross-sectional shape over the entire outer periphery of the protrusion 16. The insulating layer 14 formed on the third convex corner 16e has the same cross-sectional shape over the entire outer periphery of the protrusion 16. The cross section is a cross section perpendicular to the sixth main surface 16b and the first side surface 15c.

絶縁回路基板１０は、第２導体層１３をさらに含んでもよい。第２導体層１３は、絶縁基板１１の第２主面１１ｂ上に設けられている。第２導体層１３は、第１導体層１２と同様に構成されてもよい。具体的には、第２導体層１３は、本体部１７と、突出部１８とを含んでもよい。絶縁層１４ｂは、絶縁層１４と同様に、第２導体層１３の本体部１７及び突出部１８上に形成されてもよい。例えば、絶縁層１４ｂは、本体部１７の外周全周にわたって、同じ断面形状を有している。絶縁層１４ｂは、突出部１８の外周全周にわたって、同じ断面形状を有している。絶縁層１４ｂは、例えば、ポリイミド系樹脂層またはエポキシ系樹脂層であってもよい。   The insulated circuit board 10 may further include a second conductor layer 13. The second conductor layer 13 is provided on the second main surface 11b of the insulating substrate 11. The second conductor layer 13 may be configured similarly to the first conductor layer 12. Specifically, the second conductor layer 13 may include a main body 17 and a protrusion 18. The insulating layer 14b may be formed on the main body portion 17 and the protruding portion 18 of the second conductor layer 13, similarly to the insulating layer 14. For example, the insulating layer 14 b has the same cross-sectional shape over the entire outer periphery of the main body 17. The insulating layer 14b has the same cross-sectional shape over the entire outer periphery of the protrusion 18. The insulating layer 14b may be, for example, a polyimide resin layer or an epoxy resin layer.

ケース３０は、ベース部３１と、外囲体３２と、蓋部３５とを含んでもよい。外囲体３２は、ベース部３１と、蓋部３５とに接続されている。ベース部３１と、外囲体３２と、蓋部３５とは、ポリフェニレンサルファイド（ＰＰＳ）樹脂のような電気的絶縁性を有する樹脂から構成されてもよい。絶縁回路基板１０は、ベース部３１に接合されてもよい。具体的には、絶縁回路基板１０の第２導体層１３は、接着剤層２８を介して、ベース部３１に接着されてもよい。接着剤層２８は、例えば、シリコーン樹脂接着剤のような樹脂接着剤で構成されてもよい。ケース３０は、リード端子３３，３３ａをさらに含んでもよい。   The case 30 may include a base 31, an outer enclosure 32, and a lid 35. The outer enclosure 32 is connected to the base 31 and the lid 35. The base part 31, the outer enclosure 32, and the lid part 35 may be made of an electrically insulating resin such as polyphenylene sulfide (PPS) resin. The insulating circuit board 10 may be joined to the base 31. Specifically, the second conductor layer 13 of the insulated circuit board 10 may be bonded to the base portion 31 via the adhesive layer 28. The adhesive layer 28 may be made of, for example, a resin adhesive such as a silicone resin adhesive. Case 30 may further include lead terminals 33 and 33a.

半導体素子２０，２０ａは、導電ワイヤ２２ａ，２２ｂ，２２ｃ，２２ｄを介して、リード端子３３，３３ａに電気的に接続されてもよい。具体的には、導電ワイヤ２２ａは、はんだのような導電接合部材（図示せず）を用いて、リード端子３３と第１導体層１２とに接続されてもよい。導電ワイヤ２２ｂは、はんだのような導電接合部材（図示せず）を用いて、第１導体層１２と半導体素子２０とに接続されてもよい。導電ワイヤ２２ｃは、はんだのような導電接合部材（図示せず）を用いて、半導体素子２０と半導体素子２０ａとに接続されてもよい。導電ワイヤ２２ｄは、はんだのような導電接合部材（図示せず）を用いて、半導体素子２０ａとリード端子３３ａとに接続されてもよい。リード端子３３，３３ａは、ケース３０の外部に配置されている電源（図示せず）に接続されている。   The semiconductor elements 20, 20a may be electrically connected to the lead terminals 33, 33a via the conductive wires 22a, 22b, 22c, 22d. Specifically, the conductive wire 22a may be connected to the lead terminal 33 and the first conductive layer 12 using a conductive joining member (not shown) such as solder. The conductive wire 22b may be connected to the first conductive layer 12 and the semiconductor element 20 using a conductive bonding member (not shown) such as solder. The conductive wire 22c may be connected to the semiconductor element 20 and the semiconductor element 20a using a conductive bonding member (not shown) such as solder. The conductive wire 22d may be connected to the semiconductor element 20a and the lead terminal 33a using a conductive bonding member (not shown) such as solder. The lead terminals 33 and 33a are connected to a power supply (not shown) arranged outside the case 30.

半導体装置１は、封止部材３７をさらに備えてもよい。封止部材３７は、半導体素子２０，２０ａと本体部１５と突出部１６とを封止している。封止部材３７は、絶縁基板１１をさらに封止してもよい。封止部材３７は、導電ワイヤ２２ａ，２２ｂ，２２ｃ，２２ｄを封止してもよい。封止部材３７は、電気的絶縁性を有している。封止部材３７は、一例として、絶縁性シリコーンゲルであってもよい。絶縁層１４は、封止部材３７より高い絶縁耐圧を有している。   The semiconductor device 1 may further include a sealing member 37. The sealing member 37 seals the semiconductor elements 20, 20a, the main body 15, and the protruding portion 16. The sealing member 37 may further seal the insulating substrate 11. The sealing member 37 may seal the conductive wires 22a, 22b, 22c, 22d. The sealing member 37 has an electrical insulating property. The sealing member 37 may be, for example, an insulating silicone gel. The insulating layer 14 has a higher dielectric strength than the sealing member 37.

図３を参照して、本実施の形態の半導体装置１の製造方法を説明する。
本実施の形態の半導体装置１の製造方法は、絶縁回路基板１０の第１導体層１２に半導体素子２０，２０ａを接合することを備える（Ｓ１）。図１及び図２に示されるように、絶縁回路基板１０は、絶縁基板１１と第１導体層１２とを含む。絶縁基板１１は、第１主面１１ａと、第１主面１１ａとは反対側の第２主面１１ｂとを含む。第１導体層１２は、絶縁基板１１の第１主面１１ａ上に設けられている。第１導体層１２は、本体部１５と、突出部１６とを含む。本体部１５は、第１主面１１ａに接触する第３主面１５ａと、第３主面１５ａとは反対側の第４主面１５ｂと、第３主面１５ａと第４主面１５ｂとを接続する第１側面１５ｃとを含む。With reference to FIG. 3, a method for manufacturing semiconductor device 1 of the present embodiment will be described.
The method for manufacturing the semiconductor device 1 according to the present embodiment includes joining the semiconductor elements 20 and 20a to the first conductor layer 12 of the insulated circuit board 10 (S1). As shown in FIGS. 1 and 2, the insulated circuit board 10 includes an insulating substrate 11 and a first conductor layer 12. The insulating substrate 11 includes a first main surface 11a and a second main surface 11b opposite to the first main surface 11a. The first conductor layer 12 is provided on the first main surface 11 a of the insulating substrate 11. The first conductor layer 12 includes a main body 15 and a protrusion 16. The main body 15 includes a third main surface 15a in contact with the first main surface 11a, a fourth main surface 15b opposite to the third main surface 15a, a third main surface 15a, and a fourth main surface 15b. And a first side surface 15c to be connected.

突出部１６は、第１側面１５ｃから突出している。突出部１６は、第１主面１１ａに接触する第５主面１６ａと、第５主面１６ａとは反対側の第６主面１６ｂと、第５主面１６ａと第６主面１６ｂとを接続し、かつ、第１側面１５ｃとは反対側の第２側面１６ｃとを含む。第５主面１６ａと第６主面１６ｂの間の第１距離によって規定される突出部１６の第１厚さｔ1は、第３主面１５ａと第４主面１５ｂとの間の第２距離によって規定される本体部１５の第２厚さｔ2よりも小さい。The protruding portion 16 protrudes from the first side surface 15c. The projecting portion 16 includes a fifth main surface 16a in contact with the first main surface 11a, a sixth main surface 16b opposite to the fifth main surface 16a, a fifth main surface 16a, and a sixth main surface 16b. And a second side surface 16c opposite to the first side surface 15c. The first thickness t 1 of the protrusion 16 defined by the first distance between the fifth main surface 16a and the sixth main surface 16b is equal to the second thickness between the third main surface 15a and the fourth main surface 15b. smaller than the second thickness t 2 of the main body portion 15 which is defined by the distance.

図３に示されるように、本実施の形態の半導体装置１の製造方法は、絶縁層１４を、本体部１５の第４主面１５ｂ及び第１側面１５ｃと突出部１６の第６主面１６ｂ及び第２側面１６ｃとの上に形成すること（Ｓ２）をさらに備える。絶縁層１４は、例えば、ポリイミド系樹脂層またはエポキシ系樹脂層であってもよい。   As shown in FIG. 3, in the method for manufacturing the semiconductor device 1 of the present embodiment, the insulating layer 14 is formed by forming the fourth main surface 15 b and the first side surface 15 c of the main body 15 and the sixth main surface 16 b And forming on the second side surface 16c (S2). The insulating layer 14 may be, for example, a polyimide resin layer or an epoxy resin layer.

図２に示されるように、第１導体層１２の第１凸状角部１５ｄにおける絶縁層１４の第３厚さｔ3は、第１凸状角部１５ｄ以外の第４主面１５ｂ上に形成されている絶縁層１４の第６厚さｔ6よりも大きい。突出部１６の第２凸状角部１６ｄにおける絶縁層１４の第４厚さｔ4は、第１凸状角部１５ｄ以外の第４主面１５ｂ上に形成されている絶縁層１４の第６厚さｔ6よりも大きい。突出部１６の第３凸状角部１６ｅにおける絶縁層１４の第５厚さｔ5は、第１凸状角部１５ｄ以外の第４主面１５ｂ上に形成されている絶縁層１４の第６厚さｔ6よりも大きい。As shown in FIG. 2, the third thickness t 3 of the insulating layer 14 at the first convex corners 15d of the first conductor layer 12 is on the fourth main surface 15b other than the first convex corners 15d. It is larger than the sixth thickness t 6 of the formed insulating layer 14. The fourth thickness t 4 of the insulating layer 14 at the second convex corner 16 d of the protrusion 16 is the sixth thickness of the insulating layer 14 formed on the fourth main surface 15 b other than the first convex corner 15 d. greater than the thickness t 6. Sixth third convex corners fifth thickness t 5 of the insulating layer 14 in 16e, the first convex corners other than 15d fourth major surface 15b insulating layer formed on 14 of the protrusion 16 greater than the thickness t 6.

第３厚さｔ3は、第１凸状角部１５ｄ以外の第１側面１５ｃ上に形成されている絶縁層１４の第７厚さｔ7、及び、第３凸状角部１６ｅ以外の第６主面１６ｂ上に形成されている絶縁層１４の第８厚さｔ8よりも大きくてもよい。第４厚さｔ4は、第１凸状角部１５ｄ以外の第１側面１５ｃ上に形成されている絶縁層１４の第７厚さｔ7、及び、第３凸状角部１６ｅ以外の第６主面１６ｂ上に形成されている絶縁層１４の第８厚さｔ8よりも大きくてもよい。第５厚さｔ5は、第１凸状角部１５ｄ以外の第１側面１５ｃ上に形成されている絶縁層１４の第７厚さｔ7、及び、第３凸状角部１６ｅ以外の第６主面１６ｂ上に形成されている絶縁層１４の第８厚さｔ8よりも大きくてもよい。第２凸状角部１６ｄ及び第３凸状角部１６ｅ以外の第２側面１６ｃ上に形成されている絶縁層１４の第９厚さｔ9は、第７厚さｔ7及び第８厚さｔ8よりも大きくてもよい。Third thickness t 3 is the seventh thickness t 7 of the first convex corner portion 15d other than the first side surface 15c insulating layer formed on 14, and, other than the third convex corners 16e first The thickness may be larger than the eighth thickness t 8 of the insulating layer 14 formed on the sixth main surface 16b. The fourth thickness t 4 is the seventh thickness t 7 of the insulating layer 14 formed on the first side surface 15c other than the first convex corner 15d, and the fourth thickness t 4 other than the third convex corner 16e. The thickness may be larger than the eighth thickness t 8 of the insulating layer 14 formed on the sixth main surface 16b. Fifth thickness t 5, the seventh thickness t 7 of the first convex corner portion 15d other than the first side surface 15c insulating layer formed on 14, and, other than the third convex corners 16e first The thickness may be larger than the eighth thickness t 8 of the insulating layer 14 formed on the sixth main surface 16b. The ninth thickness t 9 of the insulating layer 14 formed on the second side face 16 c other than the second convex corners 16 d and the third convex corners 16 e is the seventh thickness t 7 and the eighth thickness it may be greater than t 8.

絶縁層１４を形成すること（Ｓ２）は、電着法によって絶縁層１４を第４主面１５ｂと第１側面１５ｃと第６主面１６ｂと第２側面１６ｃとの上に形成することと、絶縁層１４を加熱硬化することとを含んでもよい。具体的には、半導体素子２０，２０ａが搭載された絶縁回路基板１０を、絶縁層１４を構成する絶縁材料を含む溶液が入った電着槽（図示せず）内に浸漬する。そして、第１導体層１２と溶液との間に電圧を印加する。この電圧は、パルス電圧であってもよい。こうして、第４主面１５ｂと第１側面１５ｃと第６主面１６ｂと第２側面１６ｃとの上に、絶縁層１４が同時に形成される。それから、絶縁層１４は加熱硬化される。   Forming the insulating layer 14 (S2) includes forming the insulating layer 14 on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c by an electrodeposition method; Heat curing the insulating layer 14 may be included. Specifically, the insulated circuit board 10 on which the semiconductor elements 20 and 20a are mounted is immersed in an electrodeposition tank (not shown) containing a solution containing an insulating material constituting the insulating layer 14. Then, a voltage is applied between the first conductor layer 12 and the solution. This voltage may be a pulse voltage. Thus, the insulating layer 14 is simultaneously formed on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c. Then, the insulating layer 14 is cured by heating.

本実施の形態では、第１導体層１２上に絶縁層１４を電着法により形成する際に、本体部１５の第１凸状角部１５ｄと、突出部１６の第２凸状角部１６ｄ及び第３凸状角部１６ｅとに電界が集中する。本体部１５の第１凸状角部１５ｄと、突出部１６の第２凸状角部１６ｄ及び第３凸状角部１６ｅとに、局所的に高い電界が印加される（図４を参照）。そのため、本体部１５の第１凸状角部１５ｄと、突出部１６の第２凸状角部１６ｄ及び第３凸状角部１６ｅとの上に、選択的に、より厚い絶縁層１４が形成される。なお、図４に示される本実施の形態の実施例では、突出部１６は、０．１ｍｍの突出長さＬと、１０μｍの第１厚さｔ1とを有している。In the present embodiment, when the insulating layer 14 is formed on the first conductor layer 12 by the electrodeposition method, the first convex corner 15 d of the main body 15 and the second convex corner 16 d of the protrusion 16 are formed. The electric field concentrates on the third convex corners 16e. A locally high electric field is applied to the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16 (see FIG. 4). . Therefore, a thicker insulating layer 14 is selectively formed on the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16. Is done. In the example of the present embodiment shown in FIG. 4, the protrusion 16 has a protrusion length L of 0.1 mm and a first thickness t 1 of 10 μm.

これに対し、図５に示される第１の比較例では、第１導体層１２は、突出部１６を含まない。第１導体層１２上に絶縁層１４を電着法により形成する際に、絶縁基板１１に接する第１導体層１２の凸状角部１５ｇに、十分に高い電圧が印加されない。第１導体層１２の凸状角部１５ｇに、厚い絶縁層１４が形成されない。そのため、第１の比較例の半導体装置の使用状態において半導体素子２０，２０ａに高い電圧が印加されると、第１導体層１２の凸状角部１５ｇから沿面放電が発生して、絶縁層１４に絶縁破壊が発生することがあった。   On the other hand, in the first comparative example shown in FIG. 5, the first conductor layer 12 does not include the protrusion 16. When the insulating layer 14 is formed on the first conductor layer 12 by the electrodeposition method, a sufficiently high voltage is not applied to the convex corners 15g of the first conductor layer 12 that are in contact with the insulating substrate 11. The thick insulating layer 14 is not formed on the convex corners 15g of the first conductor layer 12. Therefore, when a high voltage is applied to the semiconductor elements 20 and 20a in the use state of the semiconductor device of the first comparative example, a creeping discharge is generated from the convex corner portion 15g of the first conductor layer 12, and the insulating layer 14 In some cases, dielectric breakdown occurred.

図６に示される第２の比較例では、突出部１６は、０．１ｍｍの突出長さＬと、５０μｍの第１厚さｔ1とを有している。第２の比較例では、第１導体層１２上に絶縁層１４を電着法により形成する際に、突出部１６の第２凸状角部１６ｄに、十分に高い電圧が印加されない。突出部１６の第２凸状角部１６ｄに、厚い絶縁層１４が形成されない。そのため、第２の比較例の半導体装置の使用状態において半導体素子２０，２０ａに高い電圧が印加されると、突出部１６の第２凸状角部１６ｄから沿面放電が発生して、絶縁層１４に絶縁破壊が発生することがあった。In the second comparative example shown in FIG. 6, the protrusion 16 has a protrusion length L of 0.1 mm and a first thickness t 1 of 50 μm. In the second comparative example, when the insulating layer 14 is formed on the first conductor layer 12 by the electrodeposition method, a sufficiently high voltage is not applied to the second convex corners 16d of the protrusions 16. The thick insulating layer 14 is not formed on the second convex corner portion 16d of the protrusion 16. Therefore, when a high voltage is applied to the semiconductor elements 20 and 20a in the use state of the semiconductor device of the second comparative example, a creeping discharge is generated from the second convex corner portion 16d of the protruding portion 16 and the insulating layer 14 In some cases, dielectric breakdown occurred.

図７に示される第３の比較例では、突出部１６は、１．０ｍｍの突出長さＬと、１０μｍの第１厚さｔ1とを有している。第３の比較例では、第１導体層１２上に絶縁層１４を電着法により形成する際に、本体部１５の第１凸状角部１５ｄに、十分に高い電圧が印加されない。本体部１５の第１凸状角部１５ｄに、厚い絶縁層１４が形成されない。そのため、第３の比較例の半導体装置の使用状態において半導体素子２０，２０ａに高い電圧が印加されると、本体部１５のの第１凸状角部１５ｄから沿面放電が発生して、絶縁層１４に絶縁破壊が発生することがあった。In the third comparative example shown in FIG. 7, the protrusion 16 has a protrusion length L of 1.0 mm and a first thickness t 1 of 10 μm. In the third comparative example, when the insulating layer 14 is formed on the first conductor layer 12 by the electrodeposition method, a sufficiently high voltage is not applied to the first convex corner 15d of the main body 15. The thick insulating layer 14 is not formed on the first convex corner 15d of the main body 15. Therefore, when a high voltage is applied to the semiconductor elements 20 and 20a in the use state of the semiconductor device of the third comparative example, surface discharge occurs from the first convex corner portion 15d of the main body portion 15, and the insulating layer In some cases, insulation breakdown occurred in 14.

突出部１６の突出長さＬ及び第１厚さｔ1が図８の斜線領域内にある場合、第１導体層１２上に絶縁層１４を電着法により形成する際に、本体部１５の第１凸状角部１５ｄと突出部１６の第２凸状角部１６ｄ及び第３凸状角部１６ｅとに、０．２ｋＶ／ｍｍ以上の電界強度を有する電界が発生する。一例では、第１側面１５ｃからの突出部１６の突出長さＬは１００μｍ以上であり、第１厚さｔ1は２０μｍ以下であるとき、本体部１５の第１凸状角部１５ｄと突出部１６の第２凸状角部１６ｄ及び第３凸状角部１６ｅとに、０．２ｋＶ／ｍｍ以上の電界強度を有する電界が発生する。別の例では、第１側面１５ｃからの突出部１６の突出長さＬは５００μｍ以上であり、第１厚さｔ1は４０μｍ以下であるとき、本体部１５の第１凸状角部１５ｄと突出部１６の第２凸状角部１６ｄ及び第３凸状角部１６ｅとに、０．２ｋＶ／ｍｍ以上の電界強度を有する電界が発生する。そのため、絶縁層１４は、本体部１５の第１凸状角部１５ｄと突出部１６の第２凸状角部１６ｄ及び第３凸状角部１６ｅとに局所的に厚く形成される。半導体装置１の絶縁破壊電圧は増加する。半導体装置１の使用状態において半導体素子２０，２０ａに高い電圧が印加されても、絶縁層１４に絶縁破壊が発生することが抑制され得る。When the protruding length L and the first thickness t 1 of the protruding portion 16 are within the shaded region in FIG. 8, when the insulating layer 14 is formed on the first conductor layer 12 by the electrodeposition method, An electric field having an electric field strength of 0.2 kV / mm or more is generated at the first convex corner 15d and the second convex corner 16d and the third convex corner 16e of the protrusion 16. In one example, when the projection length L of the projection 16 from the first side surface 15c is 100 μm or more and the first thickness t 1 is 20 μm or less, the first convex corner 15d of the main body 15 and the projection An electric field having an electric field strength of 0.2 kV / mm or more is generated in the second convex corners 16d and the third convex corners 16e of the sixteen. In another example, when the protruding length L of the protruding portion 16 from the first side surface 15c is 500 μm or more and the first thickness t 1 is 40 μm or less, the first protruding corner portion 15d of the main body portion 15 An electric field having an electric field strength of 0.2 kV / mm or more is generated at the second convex corner 16d and the third convex corner 16e of the protrusion 16. Therefore, the insulating layer 14 is locally thickly formed on the first convex corners 15 d of the main body 15 and the second convex corners 16 d and the third convex corners 16 e of the protrusion 16. The breakdown voltage of the semiconductor device 1 increases. Even when a high voltage is applied to the semiconductor elements 20 and 20a in the use state of the semiconductor device 1, occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.

絶縁層１４を第４主面１５ｂと第１側面１５ｃと第６主面１６ｂと第２側面１６ｃとの上に形成すること（Ｓ２）は、第４主面１５ｂと第１側面１５ｃと第６主面１６ｂと第２側面１６ｃとの上に絶縁層１４を電着する前に、第１導体層１２の表面の酸化層を除去することを含んでもよい。例えば、第１導体層１２に電圧を印加することによって、第１導体層１２の表面の酸化層が予め除去されてもよい。   Forming the insulating layer 14 on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c (S2) includes forming the fourth main surface 15b, the first side surface 15c, and the Before electrodepositing the insulating layer 14 on the main surface 16b and the second side surface 16c, removing the oxide layer on the surface of the first conductor layer 12 may be included. For example, the oxide layer on the surface of the first conductor layer 12 may be removed in advance by applying a voltage to the first conductor layer 12.

絶縁層１４ｂは、絶縁層１４と同様の工程によって、第２導体層１３の本体部１７と突出部１８との上に形成されてもよい。絶縁層１４ｂは、絶縁層１４と同時に形成されてもよい。   The insulating layer 14b may be formed on the main body portion 17 and the protruding portion 18 of the second conductor layer 13 by the same process as the insulating layer 14. The insulating layer 14b may be formed simultaneously with the insulating layer 14.

図３に示されるように、本実施の形態の半導体装置１の製造方法は、封止部材３７によって、半導体素子２０，２０ａと本体部１５と突出部１６とを封止すること（Ｓ３）をさらに備える。絶縁層１４は、封止部材３７より高い絶縁耐圧を有している。具体的には、半導体素子２０，２０ａが搭載された絶縁回路基板１０がケース３０内に取り付けられる。絶縁回路基板１０の第２導体層１３は、接着剤層２８を介して、ベース部３１に接着されてもよい。それから、ケース３０の内部に封止樹脂を注入した後、封止樹脂を硬化させる。こうして、封止部材３７が形成されてもよい。   As shown in FIG. 3, the method of manufacturing the semiconductor device 1 of the present embodiment includes sealing the semiconductor elements 20 and 20 a, the main body 15, and the protrusion 16 with the sealing member 37 (S <b> 3). Further prepare. The insulating layer 14 has a higher dielectric strength than the sealing member 37. Specifically, the insulated circuit board 10 on which the semiconductor elements 20 and 20a are mounted is mounted in the case 30. The second conductor layer 13 of the insulated circuit board 10 may be bonded to the base 31 via the adhesive layer 28. Then, after injecting the sealing resin into the inside of the case 30, the sealing resin is cured. Thus, the sealing member 37 may be formed.

本実施の形態の変形例では、半導体装置１は、ケース３０を備えていなくてもよい。半導体素子２０，２０ａと、絶縁回路基板１０と、導電ワイヤ２２ａ，２２ｂ，２２ｃ，２２ｄと、リード端子３３，３３ａの一部とは、トランスファーモールド法によって、封止部材３７で封止されてもよい。   In a modification of the present embodiment, the semiconductor device 1 does not need to include the case 30. The semiconductor elements 20, 20a, the insulated circuit board 10, the conductive wires 22a, 22b, 22c, 22d, and some of the lead terminals 33, 33a may be sealed with the sealing member 37 by the transfer molding method. Good.

本実施の形態の半導体装置１及びその製造方法の効果を説明する。
本実施の形態の半導体装置１は、絶縁回路基板１０と、半導体素子２０，２０ａと、絶縁層１４とを備える。絶縁回路基板１０は、絶縁基板１１と、第１導体層１２とを含む。絶縁基板１１は、第１主面１１ａと、第１主面１１ａとは反対側の第２主面１１ｂとを含む。第１導体層１２は、絶縁基板１１の第１主面１１ａ上に設けられている。第１導体層１２は、本体部１５と、突出部１６とを含む。本体部１５は、第１主面１１ａに接触する第３主面１５ａと、第３主面１５ａとは反対側の第４主面１５ｂと、第３主面１５ａと第４主面１５ｂとを接続する第１側面１５ｃとを含む。突出部１６は、第１側面１５ｃから突出している。突出部１６は、第１主面１１ａに接触する第５主面１６ａと、第５主面１６ａとは反対側の第６主面１６ｂと、第５主面１６ａと第６主面１６ｂとを接続し、かつ、第１側面１５ｃとは反対側の第２側面１６ｃとを含む。第５主面１６ａと第６主面１６ｂの間の第１距離によって規定される突出部１６の第１厚さｔ1は、第３主面１５ａと第４主面１５ｂとの間の第２距離によって規定される本体部１５の第２厚さｔ2よりも小さい。The effects of the semiconductor device 1 of the present embodiment and the method of manufacturing the same will be described.
The semiconductor device 1 of the present embodiment includes an insulated circuit board 10, semiconductor elements 20, 20a, and an insulating layer 14. The insulating circuit board 10 includes an insulating substrate 11 and a first conductor layer 12. The insulating substrate 11 includes a first main surface 11a and a second main surface 11b opposite to the first main surface 11a. The first conductor layer 12 is provided on the first main surface 11 a of the insulating substrate 11. The first conductor layer 12 includes a main body 15 and a protrusion 16. The main body 15 includes a third main surface 15a in contact with the first main surface 11a, a fourth main surface 15b opposite to the third main surface 15a, a third main surface 15a, and a fourth main surface 15b. And a first side surface 15c to be connected. The protruding portion 16 protrudes from the first side surface 15c. The projecting portion 16 includes a fifth main surface 16a in contact with the first main surface 11a, a sixth main surface 16b opposite to the fifth main surface 16a, a fifth main surface 16a, and a sixth main surface 16b. And a second side surface 16c opposite to the first side surface 15c. The first thickness t 1 of the protrusion 16 defined by the first distance between the fifth main surface 16a and the sixth main surface 16b is equal to the second thickness between the third main surface 15a and the fourth main surface 15b. smaller than the second thickness t 2 of the main body portion 15 which is defined by the distance.

半導体素子２０，２０ａは、第１導体層１２に接合されている。絶縁層１４は、第４主面１５ｂと第１側面１５ｃと第６主面１６ｂと第２側面１６ｃとの上に形成されている。第４主面１５ｂと第１側面１５ｃとが交差することによって形成される本体部１５の第１凸状角部１５ｄにおける絶縁層１４の第３厚さｔ3と、第５主面１６ａと第２側面１６ｃとが交差することによって形成される突出部１６の第２凸状角部１６ｄにおける絶縁層１４の第４厚さｔ4と、第６主面１６ｂと第２側面１６ｃとが交差することによって形成される突出部１６の第３凸状角部１６ｅにおける絶縁層１４の第５厚さｔ5とは、各々、第１凸状角部１５ｄ以外の第４主面１５ｂ上に形成されている絶縁層１４の第６厚さｔ6よりも大きい。The semiconductor elements 20 and 20a are joined to the first conductor layer 12. The insulating layer 14 is formed on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c. The third thickness t 3 of the insulating layer 14 at the first convex corner portion 15d of the main body 15 formed by the intersection of the fourth main surface 15b and the first side surface 15c, and the fifth main surface 16a and the fifth The fourth thickness t 4 of the insulating layer 14 at the second convex corner 16 d of the protrusion 16 formed by the intersection of the two side surfaces 16 c, and the sixth main surface 16 b and the second side surface 16 c intersect. the fifth thickness t 5 of the insulating layer 14 in the third convex corner portion 16e of the projecting portion 16 which is formed by, respectively, are formed on the fourth major surface 15b other than the first convex corner 15d It is larger than the sixth thickness t 6 of the insulating layer 14.

絶縁層１４は、本体部１５の第１凸状角部１５ｄと突出部１６の第２凸状角部１６ｄ及び第３凸状角部１６ｅとに局所的に厚く形成されている。半導体装置１の絶縁破壊電圧が増加する。半導体装置１の使用中に、絶縁層１４に絶縁破壊が発生することが抑制され得る。   The insulating layer 14 is locally thickly formed on the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16. The breakdown voltage of the semiconductor device 1 increases. During the use of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.

本実施の形態の半導体装置１では、第３厚さｔ3と第４厚さｔ4と第５厚さｔ5とは、各々、第１凸状角部１５ｄ以外の第１側面１５ｃ上に形成されている絶縁層１４の第７厚さｔ7、及び、第３凸状角部１６ｅ以外の第６主面１６ｂ上に形成されている絶縁層１４の第８厚さｔ8よりも大きくてもよい。絶縁層１４は、本体部１５の第１凸状角部１５ｄと突出部１６の第２凸状角部１６ｄ及び第３凸状角部１６ｅとに局所的に厚く形成されている。半導体装置１の絶縁破壊電圧が増加する。半導体装置１の使用中に、絶縁層１４に絶縁破壊が発生することが抑制され得る。In the semiconductor device 1 of the present embodiment, the third thickness t 3 , the fourth thickness t 4, and the fifth thickness t 5 are respectively formed on the first side surface 15c other than the first convex corner 15d. It is larger than the seventh thickness t 7 of the formed insulating layer 14 and the eighth thickness t 8 of the insulating layer 14 formed on the sixth main surface 16b other than the third convex corners 16e. You may. The insulating layer 14 is locally thickly formed on the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16. The breakdown voltage of the semiconductor device 1 increases. During the use of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.

本実施の形態の半導体装置１では、第２凸状角部１６ｄ及び第３凸状角部１６ｅ以外の第２側面１６ｃ上に形成されている絶縁層１４の第９厚さｔ9は、第７厚さｔ7及び第８厚さｔ8よりも大きくてもよい。絶縁層１４は、本体部１５の第１凸状角部１５ｄと突出部１６の第２側面１６ｃの全体とに局所的に厚く形成されている。半導体装置１の絶縁破壊電圧が増加する。半導体装置１の使用中に、絶縁層１４に絶縁破壊が発生することが抑制され得る。In the semiconductor device 1 of the present embodiment, the ninth thickness t 9 of the insulating layer 14 formed on the second side face 16 c other than the second convex corner 16 d and the third convex corner 16 e is 7 may be greater than the thickness t 7 and 8 the thickness t 8. The insulating layer 14 is locally thicker on the first convex corners 15 d of the main body 15 and on the entire second side surface 16 c of the protrusion 16. The breakdown voltage of the semiconductor device 1 increases. During the use of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.

本実施の形態の半導体装置１では、第１側面１５ｃからの突出部１６の突出長さＬは１００μｍ以上であり、第１厚さｔ1は２０μｍ以下であってもよい。絶縁層１４は、第４主面１５ｂと第１側面１５ｃと第６主面１６ｂと第２側面１６ｃとの上に、一度の工程で形成され得る。半導体装置１は、効率的に製造され得る構造を有している。In semiconductor device 1 of the present embodiment, protrusion length L of protrusion 16 from first side surface 15c may be not less than 100 μm, and first thickness t 1 may be not more than 20 μm. The insulating layer 14 can be formed on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c in one step. The semiconductor device 1 has a structure that can be manufactured efficiently.

本実施の形態の半導体装置１では、第１側面１５ｃからの突出部１６の突出長さＬは５００μｍ以上であり、第１厚さｔ1は４０μｍ以下であってもよい。絶縁層１４は、第４主面１５ｂと第１側面１５ｃと第６主面１６ｂと第２側面１６ｃとの上に、一度の工程で形成され得る。半導体装置１は、効率的に製造され得る構造を有している。In semiconductor device 1 of the present embodiment, protrusion length L of protrusion 16 from first side face 15c may be 500 μm or more, and first thickness t 1 may be 40 μm or less. The insulating layer 14 can be formed on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c in one step. The semiconductor device 1 has a structure that can be manufactured efficiently.

本実施の形態の半導体装置１の製造方法は、絶縁回路基板１０の第１導体層１２に半導体素子２０，２０ａを接合することを備える（Ｓ１）。絶縁回路基板１０は、絶縁基板１１と第１導体層１２とを含む。絶縁基板１１は、第１主面１１ａと、第１主面１１ａとは反対側の第２主面１１ｂとを含む。第１導体層１２は、絶縁基板１１の第１主面１１ａ上に設けられている。第１導体層１２は、本体部１５と、突出部１６とを含む。本体部１５は、第１主面１１ａに接触する第３主面１５ａと、第３主面１５ａとは反対側の第４主面１５ｂと、第３主面１５ａと第４主面１５ｂとを接続する第１側面１５ｃとを含む。突出部１６は、第１側面１５ｃから突出している。突出部１６は、第１主面１１ａに接触する第５主面１６ａと、第５主面１６ａとは反対側の第６主面１６ｂと、第５主面１６ａと第６主面１６ｂとを接続し、かつ、第１側面１５ｃとは反対側の第２側面１６ｃとを含む。第５主面１６ａと第６主面１６ｂの間の第１距離によって規定される突出部１６の第１厚さｔ1は、第３主面１５ａと第４主面１５ｂとの間の第２距離によって規定される本体部１５の第２厚さｔ2よりも小さい。The method for manufacturing the semiconductor device 1 according to the present embodiment includes joining the semiconductor elements 20 and 20a to the first conductor layer 12 of the insulated circuit board 10 (S1). The insulating circuit board 10 includes an insulating substrate 11 and a first conductor layer 12. The insulating substrate 11 includes a first main surface 11a and a second main surface 11b opposite to the first main surface 11a. The first conductor layer 12 is provided on the first main surface 11 a of the insulating substrate 11. The first conductor layer 12 includes a main body 15 and a protrusion 16. The main body 15 includes a third main surface 15a in contact with the first main surface 11a, a fourth main surface 15b opposite to the third main surface 15a, a third main surface 15a, and a fourth main surface 15b. And a first side surface 15c to be connected. The protruding portion 16 protrudes from the first side surface 15c. The projecting portion 16 includes a fifth main surface 16a in contact with the first main surface 11a, a sixth main surface 16b opposite to the fifth main surface 16a, a fifth main surface 16a, and a sixth main surface 16b. And a second side surface 16c opposite to the first side surface 15c. The first thickness t 1 of the protrusion 16 defined by the first distance between the fifth main surface 16a and the sixth main surface 16b is equal to the second thickness between the third main surface 15a and the fourth main surface 15b. smaller than the second thickness t 2 of the main body portion 15 which is defined by the distance.

本実施の形態の半導体装置１の製造方法は、絶縁層１４を第４主面１５ｂと第１側面１５ｃと第６主面１６ｂと第２側面１６ｃとの上に形成すること（Ｓ２）をさらに備える。第４主面１５ｂと第１側面１５ｃとが交差することによって形成される第１導体層１２の第１凸状角部１５ｄにおける絶縁層１４の第３厚さｔ3と、第５主面１６ａと第２側面１６ｃとが交差することによって形成される突出部１６の第２凸状角部１６ｄにおける絶縁層１４の第４厚さｔ4と、第６主面１６ｂと第２側面１６ｃとが交差することによって形成される突出部１６の第３凸状角部１６ｅにおける絶縁層１４の第５厚さｔ5とは、各々、第１凸状角部１５ｄ以外の第４主面１５ｂ上に形成されている絶縁層１４の第６厚さｔ6よりも大きい。The method of manufacturing the semiconductor device 1 of the present embodiment further includes forming the insulating layer 14 on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c (S2). Prepare. The third thickness t 3 of the insulating layer 14 at the first convex corner 15d of the first conductor layer 12 formed by the intersection of the fourth main surface 15b and the first side surface 15c, and the fifth main surface 16a The thickness t 4 of the insulating layer 14 at the second convex corner 16 d of the protrusion 16 formed by the intersection of the second side face 16 c and the sixth main face 16 b and the second side face 16 c are different from each other. a fifth thickness t 5 of the insulating layer 14 in the third convex corner portion 16e of the projecting portion 16 formed by crossing each, on the fourth major surface 15b other than the first convex corner 15d It is larger than the sixth thickness t 6 of the formed insulating layer 14.

絶縁層１４は、本体部１５の第１凸状角部１５ｄと突出部１６の第２凸状角部１６ｄ及び第３凸状角部１６ｅとに局所的に厚く形成されている。本実施の形態の半導体装置１の製造方法によれば、増加された絶縁破壊電圧を有する半導体装置１が製造され得る。半導体装置１の使用中に、絶縁層１４に絶縁破壊が発生することが抑制され得る。   The insulating layer 14 is locally thickly formed on the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16. According to the method of manufacturing semiconductor device 1 of the present embodiment, semiconductor device 1 having an increased breakdown voltage can be manufactured. During the use of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.

本実施の形態の半導体装置１の製造方法では、第３厚さｔ3と第４厚さｔ4と第５厚さｔ5とは、各々、第１凸状角部１５ｄ以外の第１側面１５ｃ上に形成されている絶縁層１４の第７厚さｔ7、及び、第３凸状角部１６ｅ以外の第６主面１６ｂ上に形成されている絶縁層１４の第８厚さｔ8よりも大きくてもよい。絶縁層１４は、本体部１５の第１凸状角部１５ｄと突出部１６の第２凸状角部１６ｄ及び第３凸状角部１６ｅとに局所的に厚く形成されている。本実施の形態の半導体装置１の製造方法によれば、増加された絶縁破壊電圧を有する半導体装置１が製造され得る。半導体装置１の使用中に、絶縁層１４に絶縁破壊が発生することが抑制され得る。In the method for manufacturing the semiconductor device 1 of the present embodiment, the third thickness t 3 , the fourth thickness t 4, and the fifth thickness t 5 are each equal to the first side face other than the first convex corner portion 15d. The seventh thickness t 7 of the insulating layer 14 formed on the upper surface 15c and the eighth thickness t 8 of the insulating layer 14 formed on the sixth main surface 16b other than the third convex corners 16e. It may be larger than. The insulating layer 14 is locally thickly formed on the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16. According to the method of manufacturing semiconductor device 1 of the present embodiment, semiconductor device 1 having an increased breakdown voltage can be manufactured. During the use of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.

本実施の形態の半導体装置１の製造方法では、第２凸状角部１６ｄ及び第３凸状角部１６ｅ以外の第２側面１６ｃ上に形成されている絶縁層１４の第９厚さｔ9は、第７厚さｔ7及び第８厚さｔ8よりも大きくてもよい。絶縁層１４は、本体部１５の第１凸状角部１５ｄと突出部１６の第２側面１６ｃの全体とに局所的に厚く形成されている。本実施の形態の半導体装置１の製造方法によれば、増加された絶縁破壊電圧を有する半導体装置１が製造され得る。半導体装置１の使用中に、絶縁層１４に絶縁破壊が発生することが抑制され得る。In the method for manufacturing the semiconductor device 1 of the present embodiment, the ninth thickness t 9 of the insulating layer 14 formed on the second side face 16c other than the second convex corner 16d and the third convex corner 16e. May be larger than the seventh thickness t 7 and the eighth thickness t 8 . The insulating layer 14 is locally thicker on the first convex corners 15 d of the main body 15 and on the entire second side surface 16 c of the protrusion 16. According to the method of manufacturing semiconductor device 1 of the present embodiment, semiconductor device 1 having an increased breakdown voltage can be manufactured. During the use of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.

本実施の形態の半導体装置１の製造方法では、絶縁層１４は、第４主面１５ｂと第１側面１５ｃと第６主面１６ｂと第２側面１６ｃとの上に同時に形成されてもよい。本実施の形態の半導体装置１の製造方法によれば、増加された絶縁破壊電圧を有する半導体装置１が効率的に製造され得る。   In the method of manufacturing semiconductor device 1 of the present embodiment, insulating layer 14 may be formed simultaneously on fourth main surface 15b, first side surface 15c, sixth main surface 16b, and second side surface 16c. According to the method of manufacturing semiconductor device 1 of the present embodiment, semiconductor device 1 having an increased breakdown voltage can be manufactured efficiently.

本実施の形態の半導体装置１の製造方法では、絶縁層１４を形成することは、電着法によって絶縁層１４を形成することを含んでもよい。本実施の形態の半導体装置１の製造方法によれば、増加された絶縁破壊電圧を有する半導体装置１が製造され得る。   In the method for manufacturing the semiconductor device 1 of the present embodiment, forming the insulating layer 14 may include forming the insulating layer 14 by an electrodeposition method. According to the method of manufacturing semiconductor device 1 of the present embodiment, semiconductor device 1 having an increased breakdown voltage can be manufactured.

本実施の形態の半導体装置１の製造方法では、第１側面１５ｃからの突出部１６の突出長さＬは１００μｍ以上であり、第１厚さｔ1は２０μｍ以下であってもよい。本実施の形態の半導体装置１の製造方法によれば、増加された絶縁破壊電圧を有する半導体装置１が効率的に製造され得る。In the method of manufacturing semiconductor device 1 of the present embodiment, protrusion length L of protrusion 16 from first side surface 15c may be equal to or greater than 100 μm, and first thickness t 1 may be equal to or less than 20 μm. According to the method of manufacturing semiconductor device 1 of the present embodiment, semiconductor device 1 having an increased breakdown voltage can be manufactured efficiently.

本実施の形態の半導体装置１の製造方法では、第１側面１５ｃからの突出部１６の突出長さＬは５００μｍ以上であり、第１厚さｔ1は４０μｍ以下であってもよい。本実施の形態の半導体装置１の製造方法によれば、増加された絶縁破壊電圧を有する半導体装置１が効率的に製造され得る。In the method of manufacturing semiconductor device 1 of the present embodiment, projecting length L of projecting portion 16 from first side surface 15c may be 500 μm or more, and first thickness t 1 may be 40 μm or less. According to the method of manufacturing semiconductor device 1 of the present embodiment, semiconductor device 1 having an increased breakdown voltage can be manufactured efficiently.

実施の形態２．
本実施の形態は、実施の形態１に係る半導体装置１を電力変換装置に適用したものである。特に限定されるものではないが、本実施の形態の電力変換装置２００が、三相のインバータである場合について説明する。Embodiment 2 FIG.
In the present embodiment, the semiconductor device 1 according to the first embodiment is applied to a power converter. Although not particularly limited, a case where power conversion device 200 of the present embodiment is a three-phase inverter will be described.

図９に示される電力変換システムは、電源１００、電力変換装置２００、負荷３００から構成される。電源１００は、直流電源であり、電力変換装置２００に直流電力を供給する。電源１００は、特に限定されないが、例えば、直流系統、太陽電池または蓄電池で構成されてもよいし、交流系統に接続された整流回路またはＡＣ／ＤＣコンバータで構成されてもよい。電源１００は、直流系統から出力される直流電力を別の直流電力に変換するＤＣ／ＤＣコンバータによって構成されてもよい。   The power conversion system illustrated in FIG. 9 includes a power supply 100, a power conversion device 200, and a load 300. Power supply 100 is a DC power supply, and supplies DC power to power conversion device 200. The power supply 100 is not particularly limited, but may be configured by, for example, a DC system, a solar cell, or a storage battery, or may be configured by a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 100 may be configured by a DC / DC converter that converts DC power output from a DC system into another DC power.

電力変換装置２００は、電源１００と負荷３００の間に接続された三相のインバータであり、電源１００から供給された直流電力を交流電力に変換し、負荷３００に交流電力を供給する。電力変換装置２００は、図９に示されるように、直流電力を交流電力に変換して出力する主変換回路２０１と、主変換回路２０１を制御する制御信号を主変換回路２０１に出力する制御回路２０３とを備えている。   The power converter 200 is a three-phase inverter connected between the power supply 100 and the load 300, converts DC power supplied from the power supply 100 into AC power, and supplies AC power to the load 300. As shown in FIG. 9, power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs the same, and a control circuit that outputs a control signal for controlling main conversion circuit 201 to main conversion circuit 201. 203.

負荷３００は、電力変換装置２００から供給された交流電力によって駆動される三相の電動機である。なお、負荷３００は、特に限定されるものではないが、各種電気機器に搭載された電動機であり、例えば、ハイブリッド自動車、電気自動車、鉄道車両、エレベーター、または、空調機器向けの電動機として用いられる。   Load 300 is a three-phase electric motor driven by AC power supplied from power conversion device 200. The load 300 is not particularly limited, but is a motor mounted on various electric devices, and is used, for example, as a motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.

以下、電力変換装置２００の詳細を説明する。主変換回路２０１は、スイッチング素子（図示せず）と還流ダイオード（図示せず）を備えている。スイッチング素子が電源１００から供給される電圧をスイッチングすることによって、主変換回路２０１は、電源１００から供給される直流電力を交流電力に変換して、負荷３００に供給する。主変換回路２０１の具体的な回路構成は種々のものがあるが、本実施の形態に係る主変換回路２０１は２レベルの三相フルブリッジ回路であり、６つのスイッチング素子とそれぞれのスイッチング素子に逆並列された６つの還流ダイオードとから構成され得る。主変換回路２０１の各スイッチング素子及び各還流ダイオードとして、上述した実施の形態１の半導体装置１に含まれる半導体素子２０，２０ａが適用され得る。主変換回路２０１を構成する半導体装置２０２として、上述した実施の形態１の半導体装置１が適用され得る。６つのスイッチング素子は２つのスイッチング素子ごとに直列接続され上下アームを構成し、各上下アームはフルブリッジ回路の各相（Ｕ相、Ｖ相及びＷ相）を構成する。そして、各上下アームの出力端子、すなわち主変換回路２０１の３つの出力端子は、負荷３００に接続される。   Hereinafter, the details of the power conversion device 200 will be described. The main conversion circuit 201 includes a switching element (not shown) and a free wheel diode (not shown). When the switching element switches the voltage supplied from the power supply 100, the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. Although there are various specific circuit configurations of the main conversion circuit 201, the main conversion circuit 201 according to the present embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and each switching element. And six freewheeling diodes in anti-parallel. The semiconductor elements 20 and 20a included in the semiconductor device 1 of the above-described first embodiment can be applied as each switching element and each return diode of the main conversion circuit 201. As the semiconductor device 202 forming the main conversion circuit 201, the semiconductor device 1 of the above-described first embodiment can be applied. The six switching elements are connected in series for every two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, and W phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.

また、主変換回路２０１は、各スイッチング素子を駆動する駆動回路（図示せず）を備えている。駆動回路は、半導体装置２０２に内蔵されてもよいし、半導体装置２０２の外部に設けられてもよい。駆動回路は、主変換回路２０１に含まれるスイッチング素子を駆動する駆動信号を生成して、主変換回路２０１のスイッチング素子の制御電極に駆動信号を供給する。具体的には、制御回路２０３からの制御信号に従い、スイッチング素子をオン状態にする駆動信号とスイッチング素子をオフ状態にする駆動信号とを各スイッチング素子の制御電極に出力する。   The main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. The drive circuit may be built in the semiconductor device 202 or may be provided outside the semiconductor device 202. The drive circuit generates a drive signal for driving a switching element included in the main conversion circuit 201, and supplies the drive signal to a control electrode of the switching element of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203, a driving signal for turning on the switching element and a driving signal for turning off the switching element are output to the control electrodes of each switching element.

本実施の形態に係る電力変換装置２００では、主変換回路２０１に含まれる半導体装置２０２として、実施の形態１に係る半導体装置１が適用される。そのため、本実施の形態に係る電力変換装置２００は、低コストかつ高い信頼性を有する。   In power conversion device 200 according to the present embodiment, semiconductor device 1 according to the first embodiment is applied as semiconductor device 202 included in main conversion circuit 201. Therefore, power conversion device 200 according to the present embodiment has low cost and high reliability.

本実施の形態では、２レベルの三相インバータに本発明を適用する例を説明したが、これに限られるものではなく、種々の電力変換装置に適用することができる。本実施の形態では２レベルの電力変換装置としたが、３レベルの電力変換装置であってもよいし、マルチレベルの電力変換装置であってもよい。電力変換装置が単相負荷に電力を供給する場合には、単相のインバータに本発明が適用されてもよい。電力変換装置が直流負荷等に電力を供給する場合には、ＤＣ／ＤＣコンバータまたはＡＣ／ＤＣコンバータに本発明が適用されてもよい。   In the present embodiment, an example in which the present invention is applied to a two-level three-phase inverter has been described. However, the present invention is not limited to this, and can be applied to various power converters. In the present embodiment, a two-level power converter is used. However, a three-level power converter or a multi-level power converter may be used. When the power converter supplies power to a single-phase load, the present invention may be applied to a single-phase inverter. When the power converter supplies power to a DC load or the like, the present invention may be applied to a DC / DC converter or an AC / DC converter.

本発明が適用された電力変換装置は、負荷が電動機の場合に限定されるものではなく、例えば、放電加工機もしくはレーザー加工機の電源装置、または、誘導加熱調理器もしくは非接触器給電システムの電源装置に組み込まれ得る。本発明が適用された電力変換装置は、太陽光発電システムまたは蓄電システム等のパワーコンディショナーとして用いられ得る。   The power conversion device to which the present invention is applied is not limited to the case where the load is an electric motor, for example, a power supply device of an electric discharge machine or a laser processing machine, or an induction heating cooker or a non-contact device power supply system. It can be incorporated into a power supply. The power conversion device to which the present invention is applied can be used as a power conditioner of a photovoltaic power generation system or a power storage system.

今回開示された実施の形態１及び実施の形態２はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した説明ではなく請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることを意図される。   The first and second embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

１，２０２ 半導体装置、１０ 絶縁回路基板、１１ 絶縁基板、１１ａ 第１主面、１１ｂ 第２主面、１２ 第１導体層、１３ 第２導体層、１４，１４ｂ 絶縁層、１５，１７ 本体部、１５ａ 第３主面、１５ｂ 第４主面、１５ｃ 第１側面、１５ｄ 第１凸状角部、１５ｇ 凸状角部、１５ｉ 第１稜線、１６，１８ 突出部、１６ａ 第５主面、１６ｂ 第６主面、１６ｃ 第２側面、１６ｄ 第２凸状角部、１６ｅ 第３凸状角部、１６ｉ 第２稜線、１６ｊ 第３稜線、２０，２０ａ 半導体素子、２１，２１ａ 導電接合部材、２２ａ，２２ｂ，２２ｃ，２２ｄ 導電ワイヤ、２８ 接着剤層、３０ ケース、３１ ベース部、３２ 外囲体、３３，３３ａ リード端子、３５ 蓋部、３７ 封止部材、１００ 電源、２００ 電力変換装置、２０１ 主変換回路、２０３ 制御回路、３００ 負荷。   1,202 semiconductor device, 10 insulated circuit board, 11 insulated substrate, 11a first main surface, 11b second main surface, 12 first conductor layer, 13 second conductor layer, 14, 14b insulating layer, 15, 17 main body , 15a Third principal surface, 15b Fourth principal surface, 15c First side surface, 15d First convex corner, 15g Convex corner, 15i First ridgeline, 16, 18 Projection, 16a Fifth principal surface, 16b Sixth main surface, 16c second side surface, 16d second convex corner, 16e third convex corner, 16i second ridge, 16j third ridge, 20, 20a semiconductor element, 21, 21a conductive bonding member, 22a , 22b, 22c, 22d conductive wire, 28 adhesive layer, 30 case, 31 base, 32 enclosure, 33, 33a lead terminal, 35 lid, 37 sealing member, 100 power supply, 200 power conversion device, 2 01 main conversion circuit, 203 control circuit, 300 load.

Claims (15)

絶縁基板と導体層とを含む絶縁回路基板を備え、前記絶縁基板は、第１主面と、前記第１主面とは反対側の第２主面とを含み、前記導体層は前記絶縁基板の前記第１主面上に設けられており、前記導体層は本体部と突出部とを含み、さらに、
前記導体層に接合されている半導体素子と、
絶縁層とを備え、
前記本体部は、前記第１主面に接触する第３主面と、前記第３主面とは反対側の第４主面と、前記第３主面と前記第４主面とを接続する第１側面とを含み、
前記突出部は、前記第１側面から８００μｍ以下の突出長さで突出しており、
前記突出部は、前記第１主面に接触する第５主面と、前記第５主面とは反対側の第６主面と、前記第５主面と前記第６主面とを接続し、かつ、前記第１側面とは反対側の第２側面とを含み、
前記第５主面と前記第６主面の間の第１距離によって規定される前記突出部の第１厚さは、前記第３主面と前記第４主面との間の第２距離によって規定される前記本体部の第２厚さよりも小さく、
前記絶縁層は、前記第４主面と前記第１側面と前記第６主面と前記第２側面との上に形成されており、
前記第４主面と前記第１側面とが交差することによって形成される前記本体部の第１凸状角部における前記絶縁層の第３厚さと、前記第５主面と前記第２側面とが交差することによって形成される前記突出部の第２凸状角部における前記絶縁層の第４厚さと、前記第６主面と前記第２側面とが交差することによって形成される前記突出部の第３凸状角部における前記絶縁層の第５厚さとは、各々、前記第１凸状角部以外の前記第４主面上に形成されている前記絶縁層の第６厚さよりも大きく、
前記第１側面からの前記突出部の前記突出長さは１００μｍ以上であり、
前記第１厚さは２０μｍ以下である、半導体装置。 An insulating circuit board including an insulating substrate and a conductive layer, wherein the insulating substrate includes a first main surface and a second main surface opposite to the first main surface; And the conductor layer includes a main body and a protrusion,
A semiconductor element joined to the conductor layer,
With an insulating layer,
The main body section connects a third main surface in contact with the first main surface, a fourth main surface opposite to the third main surface, and the third main surface and the fourth main surface. And a first aspect,
The protrusion has a protrusion length of 800 μm or less from the first side surface,
The protruding portion connects a fifth main surface that contacts the first main surface, a sixth main surface opposite to the fifth main surface, and connects the fifth main surface and the sixth main surface. And a second side opposite to the first side,
A first thickness of the protrusion defined by a first distance between the fifth main surface and the sixth main surface is determined by a second distance between the third main surface and the fourth main surface. Less than a defined second thickness of the body,
The insulating layer is formed on the fourth main surface, the first side surface, the sixth main surface, and the second side surface,
A third thickness of the insulating layer at a first convex corner of the main body formed by the intersection of the fourth main surface and the first side surface; and a fifth main surface and the second side surface. Are intersected by a fourth thickness of the insulating layer at a second convex corner of the projection formed by the intersection of the sixth main surface and the second side surface. The fifth thickness of the insulating layer at the third convex corner portion is larger than the sixth thickness of the insulating layer formed on the fourth main surface other than the first convex corner portion. And
The projecting length of the projecting portion from the first side surface is 100 μm or more,
The semiconductor device , wherein the first thickness is 20 μm or less . 絶縁基板と導体層とを含む絶縁回路基板を備え、前記絶縁基板は、第１主面と、前記第１主面とは反対側の第２主面とを含み、前記導体層は前記絶縁基板の前記第１主面上に設けられており、前記導体層は本体部と突出部とを含み、さらに、An insulating circuit board including an insulating substrate and a conductive layer, wherein the insulating substrate includes a first main surface and a second main surface opposite to the first main surface; And the conductor layer includes a main body and a protrusion,
前記導体層に接合されている半導体素子と、A semiconductor element joined to the conductor layer,
絶縁層とを備え、With an insulating layer,
前記本体部は、前記第１主面に接触する第３主面と、前記第３主面とは反対側の第４主面と、前記第３主面と前記第４主面とを接続する第１側面とを含み、The main body section connects a third main surface in contact with the first main surface, a fourth main surface opposite to the third main surface, and the third main surface and the fourth main surface. And a first aspect,
前記突出部は、前記第１側面から８００μｍ以下の突出長さで突出しており、The protrusion has a protrusion length of 800 μm or less from the first side surface,
前記突出部は、前記第１主面に接触する第５主面と、前記第５主面とは反対側の第６主面と、前記第５主面と前記第６主面とを接続し、かつ、前記第１側面とは反対側の第２側面とを含み、The protruding portion connects a fifth main surface that contacts the first main surface, a sixth main surface opposite to the fifth main surface, and connects the fifth main surface and the sixth main surface. And a second side opposite to the first side,
前記第５主面と前記第６主面の間の第１距離によって規定される前記突出部の第１厚さは、前記第３主面と前記第４主面との間の第２距離によって規定される前記本体部の第２厚さよりも小さく、A first thickness of the protrusion defined by a first distance between the fifth main surface and the sixth main surface is determined by a second distance between the third main surface and the fourth main surface. Less than a defined second thickness of the body,
前記絶縁層は、前記第４主面と前記第１側面と前記第６主面と前記第２側面との上に形成されており、The insulating layer is formed on the fourth main surface, the first side surface, the sixth main surface, and the second side surface,
前記第４主面と前記第１側面とが交差することによって形成される前記本体部の第１凸状角部における前記絶縁層の第３厚さと、前記第５主面と前記第２側面とが交差することによって形成される前記突出部の第２凸状角部における前記絶縁層の第４厚さと、前記第６主面と前記第２側面とが交差することによって形成される前記突出部の第３凸状角部における前記絶縁層の第５厚さとは、各々、前記第１凸状角部以外の前記第４主面上に形成されている前記絶縁層の第６厚さよりも大きく、A third thickness of the insulating layer at a first convex corner of the main body formed by the intersection of the fourth main surface and the first side surface; and a fifth main surface and the second side surface. Are intersected by a fourth thickness of the insulating layer at a second convex corner of the projection formed by the intersection of the sixth main surface and the second side surface. The fifth thickness of the insulating layer at the third convex corner portion is larger than the sixth thickness of the insulating layer formed on the fourth main surface other than the first convex corner portion. ,
前記第１側面からの前記突出部の前記突出長さは５００μｍ以上であり、The protrusion length of the protrusion from the first side surface is 500 μm or more,
前記第１厚さは４０μｍ以下である、半導体装置。The semiconductor device, wherein the first thickness is 40 μm or less. 前記第３厚さと前記第４厚さと前記第５厚さとは、各々、前記第１凸状角部以外の前記第１側面上に形成されている前記絶縁層の第７厚さ、及び、前記第３凸状角部以外の前記第６主面上に形成されている前記絶縁層の第８厚さよりも大きい、請求項１または請求項２に記載の半導体装置。 The third thickness, the fourth thickness, and the fifth thickness are respectively a seventh thickness of the insulating layer formed on the first side surface other than the first convex corner portion, and 3. The semiconductor device according to claim 1, wherein the thickness of the insulating layer formed on the sixth main surface other than the third convex corner portion is larger than an eighth thickness. 4. 前記第２凸状角部及び前記第３凸状角部以外の前記第２側面上に形成されている前記絶縁層の第９厚さは、前記第７厚さ及び前記第８厚さよりも大きい、請求項３に記載の半導体装置。 A ninth thickness of the insulating layer formed on the second side surface other than the second convex corners and the third convex corners is larger than the seventh thickness and the eighth thickness. The semiconductor device according to claim 3 . 前記絶縁層は、ポリイミド系樹脂層またはエポキシ系樹脂層である、請求項１から請求項４のいずれか１項に記載の半導体装置。 The insulating layer is a polyimide resin layer or epoxy resin layer, the semiconductor device according to any one of claims 1 to 4. 封止部材をさらに備え、
前記封止部材は、前記半導体素子と前記本体部と前記突出部とを封止し、
前記絶縁層は、前記封止部材より高い絶縁耐圧を有している、請求項１から請求項５のいずれか１項に記載の半導体装置。 Further comprising a sealing member,
The sealing member seals the semiconductor element, the main body, and the protrusion,
The insulating layer has a higher dielectric breakdown voltage than the sealing member, a semiconductor device according to any one of claims 1 to 5. 請求項１から請求項６のいずれか１項記載の前記半導体装置を有し、かつ、入力される電力を変換して出力し得るように構成されている主変換回路と、
前記主変換回路を制御する制御信号を前記主変換回路に出力し得るように構成されている制御回路とを備える、電力変換装置。 A main conversion circuit comprising the semiconductor device according to any one of claims 1 to 6 , and configured to convert input power and output the converted power,
And a control circuit configured to output a control signal for controlling the main conversion circuit to the main conversion circuit. 絶縁回路基板の導体層に半導体素子を接合することを備え、前記絶縁回路基板は、絶縁基板と前記導体層とを含み、前記絶縁基板は、第１主面と、前記第１主面とは反対側の第２主面とを含み、前記導体層は前記絶縁基板の前記第１主面上に設けられており、前記導体層は、本体部と突出部とを含み、前記本体部は、前記第１主面に接触する第３主面と、前記第３主面とは反対側の第４主面と、前記第３主面と前記第４主面とを接続する第１側面とを含み、前記突出部は前記第１側面から８００μｍ以下の突出長さで突出しており、前記突出部は、前記第１主面に接触する第５主面と、前記第５主面とは反対側の第６主面と、前記第５主面と前記第６主面とを接続し、かつ、前記第１側面とは反対側の第２側面とを含み、前記第５主面と前記第６主面の間の第１距離によって規定される前記突出部の第１厚さは、前記第３主面と前記第４主面との間の第２距離によって規定される前記本体部の第２厚さよりも小さく、
絶縁層を前記第４主面と前記第１側面と前記第６主面と前記第２側面との上に形成することをさらに備え、
前記第４主面と前記第１側面とが交差することによって形成される前記導体層の第１凸状角部における前記絶縁層の第３厚さと、前記第５主面と前記第２側面とが交差することによって形成される前記突出部の第２凸状角部における前記絶縁層の第４厚さと、前記第６主面と前記第２側面とが交差することによって形成される前記突出部の第３凸状角部における前記絶縁層の第５厚さとは、各々、前記第１凸状角部以外の前記第４主面上に形成されている前記絶縁層の第６厚さよりも大きく、
前記第１側面からの前記突出部の前記突出長さは１００μｍ以上であり、
前記第１厚さは２０μｍ以下である、半導体装置の製造方法。 Bonding a semiconductor element to a conductor layer of an insulated circuit board, wherein the insulated circuit board includes an insulated board and the conductor layer, the insulated board has a first main surface, and the first main surface A second main surface on the opposite side, the conductor layer is provided on the first main surface of the insulating substrate, the conductor layer includes a main body and a protrusion, and the main body includes: A third main surface contacting the first main surface, a fourth main surface opposite to the third main surface, and a first side surface connecting the third main surface and the fourth main surface. Wherein the projecting portion projects from the first side surface with a projecting length of 800 μm or less, and the projecting portion has a fifth main surface in contact with the first main surface and an opposite side to the fifth main surface. A sixth main surface, the fifth main surface and the sixth main surface are connected to each other, and the second main surface includes a second side surface opposite to the first side surface. A first thickness of the protrusion defined by a first distance between the six main surfaces is a first thickness of the main body defined by a second distance between the third main surface and the fourth main surface. 2 less than the thickness,
Further comprising forming an insulating layer on the fourth main surface, the first side surface, the sixth main surface, and the second side surface,
A third thickness of the insulating layer at a first convex corner of the conductor layer formed by intersection of the fourth main surface and the first side surface; and a fifth main surface and the second side surface. Are intersected by a fourth thickness of the insulating layer at a second convex corner of the projection formed by the intersection of the sixth main surface and the second side surface. The fifth thickness of the insulating layer at the third convex corner portion is larger than the sixth thickness of the insulating layer formed on the fourth main surface other than the first convex corner portion. And
The projecting length of the projecting portion from the first side surface is 100 μm or more,
The method for manufacturing a semiconductor device , wherein the first thickness is 20 μm or less . 絶縁回路基板の導体層に半導体素子を接合することを備え、前記絶縁回路基板は、絶縁基板と前記導体層とを含み、前記絶縁基板は、第１主面と、前記第１主面とは反対側の第２主面とを含み、前記導体層は前記絶縁基板の前記第１主面上に設けられており、前記導体層は、本体部と突出部とを含み、前記本体部は、前記第１主面に接触する第３主面と、前記第３主面とは反対側の第４主面と、前記第３主面と前記第４主面とを接続する第１側面とを含み、前記突出部は前記第１側面から８００μｍ以下の突出長さで突出しており、前記突出部は、前記第１主面に接触する第５主面と、前記第５主面とは反対側の第６主面と、前記第５主面と前記第６主面とを接続し、かつ、前記第１側面とは反対側の第２側面とを含み、前記第５主面と前記第６主面の間の第１距離によって規定される前記突出部の第１厚さは、前記第３主面と前記第４主面との間の第２距離によって規定される前記本体部の第２厚さよりも小さく、Bonding a semiconductor element to a conductor layer of an insulated circuit board, wherein the insulated circuit board includes an insulated board and the conductor layer, and the insulated board has a first main surface and a first main surface. A second main surface on the opposite side, the conductor layer is provided on the first main surface of the insulating substrate, the conductor layer includes a main body and a protrusion, and the main body includes: A third main surface contacting the first main surface, a fourth main surface opposite to the third main surface, and a first side surface connecting the third main surface and the fourth main surface. Wherein the projecting portion projects from the first side surface with a projecting length of 800 μm or less, and the projecting portion has a fifth main surface in contact with the first main surface and an opposite side to the fifth main surface. A sixth main surface, the fifth main surface and the sixth main surface are connected to each other, and the second main surface includes a second side surface opposite to the first side surface. A first thickness of the protrusion defined by a first distance between the six main surfaces is a first thickness of the main body defined by a second distance between the third main surface and the fourth main surface. 2 less than the thickness,
絶縁層を前記第４主面と前記第１側面と前記第６主面と前記第２側面との上に形成することをさらに備え、Further comprising forming an insulating layer on the fourth main surface, the first side surface, the sixth main surface, and the second side surface,
前記第４主面と前記第１側面とが交差することによって形成される前記導体層の第１凸状角部における前記絶縁層の第３厚さと、前記第５主面と前記第２側面とが交差することによって形成される前記突出部の第２凸状角部における前記絶縁層の第４厚さと、前記第６主面と前記第２側面とが交差することによって形成される前記突出部の第３凸状角部における前記絶縁層の第５厚さとは、各々、前記第１凸状角部以外の前記第４主面上に形成されている前記絶縁層の第６厚さよりも大きく、A third thickness of the insulating layer at a first convex corner of the conductor layer formed by intersection of the fourth main surface and the first side surface; and a fifth main surface and the second side surface. Are intersected by a fourth thickness of the insulating layer at a second convex corner of the projection formed by the intersection of the sixth main surface and the second side surface. The fifth thickness of the insulating layer at the third convex corner portion is larger than the sixth thickness of the insulating layer formed on the fourth main surface other than the first convex corner portion. ,
前記第１側面からの前記突出部の前記突出長さは５００μｍ以上であり、The protrusion length of the protrusion from the first side surface is 500 μm or more,
前記第１厚さは４０μｍ以下である、半導体装置の製造方法。The method for manufacturing a semiconductor device, wherein the first thickness is 40 μm or less. 前記第３厚さと前記第４厚さと前記第５厚さとは、各々、前記第１凸状角部以外の前記第１側面上に形成されている前記絶縁層の第７厚さ、及び、前記第３凸状角部以外の前記第６主面上に形成されている前記絶縁層の第８厚さよりも大きい、請求項８または請求項９に記載の半導体装置の製造方法。 The third thickness, the fourth thickness, and the fifth thickness are respectively a seventh thickness of the insulating layer formed on the first side surface other than the first convex corner portion, and The method of manufacturing a semiconductor device according to claim 8 , wherein the thickness of the insulating layer formed on the sixth main surface other than the third convex corner portion is larger than an eighth thickness. 前記第２凸状角部及び前記第３凸状角部以外の前記第２側面上に形成されている前記絶縁層の第９厚さは、前記第７厚さ及び前記第８厚さよりも大きい、請求項１０に記載の半導体装置の製造方法。   A ninth thickness of the insulating layer formed on the second side surface other than the second convex corners and the third convex corners is larger than the seventh thickness and the eighth thickness. A method for manufacturing a semiconductor device according to claim 10. 前記絶縁層は、前記第４主面と前記第１側面と前記第６主面と前記第２側面との上に同時に形成される、請求項８から請求項１１のいずれか１項に記載の半導体装置の製造方法。 12. The device according to claim 8 , wherein the insulating layer is formed simultaneously on the fourth main surface, the first side surface, the sixth main surface, and the second side surface. 13. A method for manufacturing a semiconductor device. 前記絶縁層を形成することは、電着法によって前記絶縁層を形成することを含む、請求項８から請求項１２のいずれか１項に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 8 , wherein forming the insulating layer includes forming the insulating layer by an electrodeposition method. 前記絶縁層は、ポリイミド系樹脂層またはエポキシ系樹脂層である、請求項８から請求項１３のいずれか１項に記載の半導体装置の製造方法。 The insulating layer is a polyimide resin layer or epoxy resin layer, a method of manufacturing a semiconductor device according to any one of claims 13 claim 8. 封止部材によって、前記半導体素子と前記本体部と前記突出部とを封止することをさらに備え、
前記絶縁層は、前記封止部材より高い絶縁耐圧を有している、請求項８から請求項１４のいずれか１項に記載の半導体装置の製造方法。 The method further comprises sealing the semiconductor element, the main body, and the protrusion with a sealing member,
The insulating layer, said has a higher dielectric breakdown voltage than that of the sealing member, a method of manufacturing a semiconductor device according to any one of claims 14 to claim 8.
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