JP6639714B2 - Storage device - Google Patents

Description

  This embodiment relates to a storage device.

  2. Description of the Related Art Conventionally, a storage device used by being incorporated in a host device such as a server is known.

JP 2012-216672 A

  It is preferable that this type of storage device can be used with less inconvenience in each case where it is incorporated in a plurality of server devices having different specifications.

  The storage device according to the present embodiment is a storage device connectable to the first device or the second device, and includes a memory, a control circuit, an interface circuit, and a switch control circuit. The memory stores data. The control circuit controls writing of data to the memory and reading of data from the memory. The interface circuit has at least a first terminal, a second terminal, and a third terminal through which the first power of the first voltage is supplied to the storage device. The switch control circuit controls the connection state indicating that power corresponding to the first power is supplied to the control circuit and the memory, and controls the power corresponding to the first power, based on the states of the first terminal and the second terminal. The switching control between the circuit and the cut-off state indicating not being supplied to the memory is executed. While the storage device and the first device are connected, the first terminal is in the first state, and the second terminal is configured such that the second power of the second voltage is supplied to the storage device via the second terminal. In the second state. While the storage device and the second device are connected, the first terminal is in a third state different from the first state, and the second terminal is a control signal from the second device to the storage device via the second terminal. The state becomes the fourth state indicating input.

FIG. 1 is an exemplary perspective view of a server device including the storage device of the embodiment. FIG. 2 is an exemplary exploded perspective view of the storage device according to the embodiment. FIG. 3 is a schematic and exemplary block diagram of the server device of the embodiment. FIG. 4 is a schematic and exemplary block diagram of the storage device according to the embodiment. FIG. 5 is a table showing pin assignments of the SAS power supply interface. FIG. 6 is a table showing the electrical states of the pins P1 to P3 of the SAS power supply interface for each interface specification (SAS1, SAS2, SAS2.1, SAS3) of the server device. FIG. 7 is a schematic and exemplary circuit diagram of a switch control unit included in the storage device of the embodiment. FIG. 8 is a table showing the potentials of the components of the switch control unit included in the storage device of the embodiment, the states of the switches, and the specifications of the corresponding interface of the server device. FIG. 9 is an exemplary sequence diagram illustrating transmission of a signal between the server device and the storage device according to the embodiment. FIG. 10 is a schematic and exemplary block diagram of a storage device according to a first modification. FIG. 11 is a schematic and exemplary block diagram of a storage device according to a second modification. FIG. 12 is a schematic and exemplary flowchart of a procedure of processing by the storage device of the second modification. FIG. 13 is an exemplary perspective view of an electronic device in which the storage device of the embodiment is incorporated.

  Hereinafter, exemplary embodiments and modifications of the storage device and the server device (host device) will be disclosed. The configurations and controls (technical features) of the embodiments described below, and the actions and results (effects) brought by the configurations and controls are examples. Further, the embodiments and the modified examples exemplified below include the same components. Hereinafter, similar components are denoted by common reference numerals, and redundant description will be omitted.

<Embodiment>
FIG. 1 is an exemplary perspective view of a server device including the storage device of the embodiment. The data center 1 includes, for example, various devices such as a plurality of server farms 2, routers and switching hubs, and various components such as cables connecting the devices. FIG. 1 shows one server farm 2. FIG. 1 shows a state in which one server module 5 is pulled out to the front in the front-rear direction.

  The server farm 2 includes a rack 3, a plurality of module enclosures 4, a plurality of server modules 5, and the like. A plurality of server modules 5 are stored in each module enclosure 4. The module enclosure 4 storing a plurality of server modules 5 forms a rack-mount type server. The server in the data center 1 is not limited to this, and may be another server such as a blade server. The data center 1, the server farm 2, and the server module 5 are examples of a server device, and may be referred to as a host device, a host system, a server system, a storage system, and the like.

  The rack 3 has two columns 3a. The support 3a is provided with a plurality of screw holes. The two columns 3a are spaced apart from each other. The module enclosure 4 can be inserted between the two columns 3a.

  The module enclosure 4 has an enclosure case 11 and a mounting member 12. The module enclosure 4 may further include a power supply unit stored in the enclosure case 11. For example, four module slots 13 are provided in the enclosure case 11.

  The mounting member 12 extends laterally from the front end of the enclosure case 11 toward the outside of the enclosure case 11. A hole corresponding to the screw hole of the column 3 a is provided in the mounting member 12. The mounting member 12 is fixed to the column 3a of the rack 3 by, for example, screws or bolts. Thus, the module enclosure 4 is attached to the rack 3.

  The server module 5 can be inserted into the module slot 13 of the enclosure case 11. When the server module 5 is inserted into the module slot 13, for example, power can be supplied from a power supply unit of the module enclosure 4. The server module 5 may be supplied with power from another device.

  The server module 5 includes, for example, a module case 21, a module board 22, a control unit 23, a plurality of memories 24, a plurality of fans 25, and a plurality of storage devices 100. The module case 21 is an example of a first housing, and may be referred to as, for example, a wall. The module substrate 22 is an example of a first substrate, and may be referred to as, for example, a wiring board or a circuit board. The fan 25 is an example of a blower, and may be referred to as, for example, a cooling device. The control unit 23 is, for example, a CPU (central processing unit). The storage device 100 can also be called an apparatus, a storage, a device, an electronic device, a module, a component, or the like. In the present embodiment, the storage device 100 is, for example, a solid state drive (SSD), but may be another device such as a hard disk drive (HDD) or a hybrid hard disk drive (hybrid HDD). Further, the storage device 100 does not need to have a housing depending on a usage mode and an applied device.

  The module case 21 is, for example, formed in a substantially rectangular box shape whose upper part is opened and extends in the front-rear direction. Note that the shape of the module case 21 is not limited to this, and may be, for example, a box shape having an upper part closed. The module case 21 accommodates a module substrate 22, a control unit 23, a memory 24, a fan 25, a storage device 100, other components, and the like.

  The module case 21 has a front panel 27. The front panel 27 is a wall provided at a front end of the module case 21. Various connectors such as a USB connector are provided on the front panel 27.

  The module substrate 22 is, for example, a printed wiring board. Note that the module substrate 22 may be another substrate. The control unit 23, the memory 24, the fan 25, the storage device 100, other components, and the like can be mounted on the module board 22 directly or via other components.

  The fan 25 is disposed between the control unit 23 and the memory 24 and the storage device 100 in the front-back direction. By the operation of the fan 25, a flow of air in the front-rear direction may be generated inside the module case 21. The control unit 23, the memory 24, the storage device 100, and other components can be cooled by the airflow generated by the fan 25. The air flow generated by the fan 25 may flow in another direction.

  The storage devices 100 are housed in drive cages attached to the front panel 27, for example.

  FIG. 2 is an exemplary exploded perspective view of the storage device according to the embodiment. 2, the storage device 100 includes, for example, a case 101, a circuit board 102, a plurality of memories 103, a controller 104, a plurality of data buffers 105, a plurality of capacitors 106, an interface unit 107, and the like.

  The case 101 can be referred to as, for example, a cover, a cover, a wall, or the like. The circuit board 102 may be referred to as, for example, a board or a wiring board. The memory 103 can also be referred to as, for example, a storage unit, an element, a component, or the like. The controller 104 can also be called, for example, a control unit, an arithmetic processing unit, an element, a component, or the like. The interface unit 107 may be referred to as, for example, a connector or a connection unit.

  The case 101 has a plurality of members (parts) such as an upper case 111, a frame 112, and a lower case 113, for example. The case 101 is configured by integrating a plurality of members with each other by a fixing tool such as a screw. The case 101 has a plurality of walls 101a, and the components of the storage device 100, that is, the circuit board 102, the memory 103, the controller 104, the data buffer 105, the capacitor 106, and the like are provided in a space surrounded by the walls 101a. Is housed. The case 101 is made of, for example, a metal material such as an aluminum alloy.

  FIG. 3 is a schematic and exemplary block diagram of the server device of the embodiment. The control unit 23 of the server module 5 as a server device has a host control unit 231, an abnormality detection unit 232, a control signal generation unit 233, and the like. The host control unit 231 controls the operation of each unit of the server module 5, writing of data to the plurality of storage devices 100, reading of data from the plurality of storage devices 100, and the like. The abnormality detection unit 232 detects an abnormality that has occurred in the storage device 100. An abnormality of the storage device 100 is detected, for example, when there is no response to a command within a predetermined time, or when writing or reading of data in the storage device 100 is assumed or does not end after a predetermined time. be able to. The control signal generation unit 233 generates a control signal for executing power-on reset when the abnormality detection unit 232 detects an abnormality to be subjected to power-on reset in the storage device 100. The control signal is, for example, a power disable (power disable) signal. The power disable signal is a request for the storage device 100 to shut off the switches SW1 and SW2 (see FIG. 7) provided on the power line in the storage device 100.

  The interface unit 107 of the storage device 100 and the interface unit 234 of the server module 5 are connected to each other, and the pins provided on the interface units 107 and 234 are electrically connected to each other, so that the control unit 23 and the storage unit are stored. Data transmission with the device 100 is performed.

  FIG. 4 is a schematic and exemplary block diagram of the storage device according to the embodiment. The storage device 100 includes a switch control circuit 120a, a power supply circuit 130, a processing unit 140, and the like. The switch control circuit 120a is an example of the switch control unit 120. In the present embodiment, a plurality of elements (electronic components) are mounted on the circuit board 102 by being mounted on the circuit board 102. The power supply circuit 130 includes a switch, a fuse, and the like. The switch control circuit 120a (the switch control unit 120) and the power supply circuit 130 will be described later in detail. Power is supplied from the power supply circuit 130 to each unit included in the processing unit 140. Although FIG. 4 illustrates the memory 103, the controller 104, the data buffer 105, and the like one by one, the number is not limited to one. The processing unit 140 is a name for convenience. The processing unit 140 may be an integrated one-package SSD.

  The memory 103 is a nonvolatile memory, for example, a NAND flash memory. The memory 103 is not limited to a NAND flash memory, and may be a RERAM (resistance random access memory), a FERAM (ferroelectric random access memory), or the like. The memory 103 stores user data transmitted from the outside of the storage device 100 (host device, server device), system data used only inside the storage device 100, and the like. The memory 103 has a memory cell array in which a plurality of memory cells (not shown) are arranged in a matrix. Each memory cell can store two or more values. The memory 103 has a plurality of memory chips.

  The data buffer 105 temporarily holds data. The data buffer 105 is, for example, a DRAM (dynamic static random access memory). The data buffer 105 is not limited to a DRAM, but may be an SRAM (static random access memory) or the like. The data buffer 105 may be provided independently of the controller 104, or may be implemented as an embedded memory inside a chip of the controller 104.

  The controller 104 controls the storage device 100. The function of the controller 104 can be realized by, for example, a processor that executes firmware stored in the memory 103 or a ROM (read only memory) of the controller 104, hardware, or the like. The controller 104 reads data from and writes data to the memory 103 in accordance with a command from the host device.

  The interface unit 107 has a plurality of pins (terminals) for transmitting electric signals, electric power, and the like to and from an external device. The interface unit 107 is configured based on serial attached SCSI (SAS).

  FIG. 5 is a table showing an example of the pin assignment of the power supply interface conforming to the SAS. As shown in FIG. 5, in the SAS power supply interface, a total of 15 pins P1 to P15 (terminals) are set, of which pins P4 to P6 are ground and pins P7 to P9 are pins. Power of 5 [V], ground to pins P10 to P12, and power of 12 [V] to pins P13 to P15 are respectively allocated. In addition, power of 3.3 [V] is allocated to the pins P1 to P3 in SAS1, SAS2, and SAS2.1. On the other hand, in the SAS3, the pin P1 and the pin P2 are allowed to be assigned (vender specific) by the host device (server device) vendor, and the pin P3 is assigned by the host device vendor or by the host device. Assignment of a control signal (power disable) for stopping supply of power to the storage device is permitted. In the storage device connected to the host device, it is specified in SAS1, SAS2, and SAS2.1 that the pins P1 to P3 are electrically connected to each other, and in the SAS3, the pins P1 and P2 are electrically connected to each other. Connection is specified.

  As described above, in the SAS standard, the pin assignment of the pins P1 to P3 is different between the legacy system of SAS1, SAS2, and SAS2.1 and the new system of SAS3.

  There are host devices that are still operating and are compliant with SAS1, SAS2, and SAS2.1, and storage devices that are compliant with SAS3 are not only host devices that are compliant with SAS3, but are also compliant with these SAS1, SAS2, and SAS2.1. It is desirable to be able to be incorporated (connected) to a host device that has been established.

  However, as described above, when the pin assignment differs depending on the standard, a storage device conforming to one standard may be difficult to use with a host device of another standard. Specifically, for example, for the above-described SAS power interface, a storage device using a control signal (power disable) of the pin P3 compliant with the SAS3 is connected to the pin P3 compliant with the SAS1 or the like, for example. When incorporated in a host device to which [V] power is supplied, the potential of the pin P3 of the storage device is always 3.3 [V]. In this case, the storage device performs an operation when the control signal by the pin P3 is always at the high level. A switch that switches between power supply and supply stop is provided in the storage device compatible with power disable, and the high level of the control signal by the pin P3 is a command to shut off (switch off, stop power supply) the switch. . Accordingly, in this case, the storage device maintains the switch-off state based on 3.3 [V] of P3, that is, the high level of the power disable, so that power is not supplied to the storage device. Therefore, a storage device using a P3 control signal (power disable) compliant with SAS3 may not be used as it is in a server device compliant with SAS1.

  The storage device 100 of the present embodiment is provided with a switch control unit 120 that can avoid such a situation. The switch control unit 120 controls the switches based on the electrical states of the pins P1 to P3, using the fact that the electrical states of the pins P1 to P3 differ depending on the host device standard and control signals from the host device. . The host device is, for example, the data center 1, the server farm 2, the server module 5, or the like. The pins P1 to P3 and the above-described pins P4 to P15 are included in the interface unit 107.

FIG. 6 is a table showing the electrical states of the pins P1 to P3 for each interface device specification (SAS1, SAS2, SAS2.1, SAS3). FIG. 6 shows the electrical states of the pins P1 to P3 for the following four specifications (1) to (4). It has been found that the types (1) to (4) are typical specifications existing at the present time.
(1) A host device to which 3.3 [V] is applied according to SAS 1/2 / 2.1 (2) A 3.3 [V] is not applied according to SAS 1/2 / 2.1 Host device (3) Host device that complies with SAS3 and supports power disable (4) Host device that complies with SAS3 and does not support power disable In FIG. 6, H indicates a high level, L indicates a low level, and NC indicates an unconnected state. Is shown. In addition, the disconnected state may be referred to as an open state, a floating state, or the like. SW indicates a switch, C indicates a connected state of the switch, AC indicates a constantly connected state of the switch, and S indicates a disconnected state of the switch. As described above, since the pins P1 and P2 are also electrically connected to each other in the SAS 3, the electrical states of the pins P1 and P2 are the same. The switch control unit 120 of the present embodiment sets the state of the switch as shown in FIG. 6 according to the combination of the electrical states (for example, the potentials) of the pins P1, P2 and the pin P3 shown in FIG. By doing so, even if the host device is connected to any one of (1) to (4), the desired processing is executed while avoiding the occurrence of the above-mentioned inconvenient event. Is done. In the present embodiment, the pins P1 and P2 are examples of a first terminal, P3 is an example of a second terminal, and P7 to P9 and P13 to P15 are examples of a third terminal.

  FIG. 7 is a schematic and exemplary circuit diagram of the switch control unit 120. As shown in FIG. 7, in the present embodiment, the switch control unit 120 has a logic circuit 160 including logic gates such as a NOT circuit 161 (inverter) and an AND circuit 162. That is, the switch control unit 120 performs the logical operation using the high level and the low level set by the electrical state (for example, the potential) of the pin P1 (or the pin P2) and the pin P3 to perform the switches SW1 and SW2 (FIG. A signal Ss for switching between connection and disconnection of SW 6) is generated. The high level and the low level can be set, for example, according to the magnitude of a preset potential threshold. In the case of SAS, the high level is set to about 3.3 [V] as the potential of the power supply, and the low level is set to about 0 [V] as the potential of the ground. Note that the logic circuit 160 illustrated in FIG. 7 is an example, and the switch control unit 120 may include a logic circuit including a logic gate equivalent to and different from the circuit illustrated in FIG. As described above, since the pin P2 is electrically connected to the pin P1, in this specification, the pin P1 may be described as a representative of the pin P1 and the pin P2.

  In the case of the non-connection state (NC), the pins P1 to P3 are not electrically connected to both the conductor of the power supply potential and the conductor of the ground potential in the host device. In this case, the potentials of the pins P1 to P3 are different from the power supply potential and the ground potential (different potentials) (floating state). Therefore, it is possible to identify a floating state by having a structure for detecting another potential. In the floating state, the impedance is large, so that the floating state can be identified by the impedance. In the case of the present embodiment, as an example, a pull-down circuit 150 having a resistor Rp (pull-down resistor) is provided between the pin P1 and the ground GND and between the pin P3 and the ground GND. . Thereby, the switch control unit 120 treats the non-connection state as the same as the low level, and can relatively easily perform the arithmetic processing. In the example of FIG. 6, there is no problem caused by setting the non-connection state to low level. Further, the resistance value of the resistor Rp is set to a value that can maintain the high level when the pins P1 and P3 are at the high level. The resistor Rp and the pull-down circuit 150 connected to the pin P1 are an example of a first resistor and a first pull-down circuit, and the resistor Rp and the pull-down circuit 150 connected to the pin P3 are Is an example of the pull-down circuit of FIG.

  Further, as shown in FIG. 7, in the switch control unit 120, a resistor Rh is provided in series with the pin P1, and a resistor Rh is provided in series with the pin P3. With such a configuration, even when the power suddenly rises when the switches SW1 and SW2 are switched from the cutoff state to the connection state, energy can be consumed by the resistor Rh. That is, it is possible to suppress a sharp rise in power in a portion of the switch control unit 120 opposite to the host device with respect to the resistor Rh. In the present embodiment, the resistor Rh is provided between the processing unit 140 and the pins P1 and P3 and between the logic gate (such as the NOT circuit 161 and the AND circuit 162) and the pins P1 and P3. .

  A capacitor Cf is provided between the pin P1 and the ground GND, and a capacitor Cf is provided between the pin P3 and the ground GND. Thereby, high frequency components can be removed from the power input to the switch control unit 120 from the pin P1 or the pin P3.

  In the logic circuit 160, the NOT circuit 161 inverts the high level and the low level of the potential of the pin P1 and outputs the result. The AND circuit 162 outputs a logical product of the potential level of the output of the NOT circuit 161 and the potential level of the pin P3. The switches SW1 and SW2 are configured to be cut off when the potential of the output of the AND circuit 162 is at a high level.

FIG. 8 shows the level of the signal Ss output from the logic circuit 160 and the state of the switches corresponding to the potential levels of the pins P1 and P2. As can be seen from FIG.
(A) When the pin P1 is at the high level and the pin P3 is at the high level, the signal Ss as the output of the logic circuit 160 is at the low level. In this case, the switches SW1 and SW2 are in the connected state. This case corresponds to (1) in FIG.
(B) When the pin P1 is at the low level and the pin P3 is at the low level, the signal Ss as the output of the logic circuit 160 is at the low level, and in this case, the switches SW1 and SW2 are connected. This case corresponds to the case where P3 in FIG. 6 (2) and (3) is L, and the case where P1 in FIG. 6 (4) is L or NC.
(C) When the pin P1 is at the low level and the pin P3 is at the high level, the signal Ss as the output of the logic circuit 160 is at the high level. In this case, the switches SW1 and SW2 are turned off. This case corresponds to the case where P3 in FIG.
(D) When the pin P1 is at a high level and the pin P3 is at a low level, the signal Ss of the logic circuit 160 is at a low level, and in this case, the switches SW1 and SW2 are connected. This case corresponds to the case where P1 in FIG.
As described above, according to the switch control unit 120 of the present embodiment, all the cases shown in FIG. 6 can be handled. That is, the storage device according to the present embodiment is connected to the switch SW1 regardless of which of the host devices (1) to (4) conforming to the typical SAS interface shown in FIG. , SW2 can be executed without being unintentionally shut off.

  In the present embodiment, the delay circuit 170 is provided between the logic circuit 160 and the switches SW1 and SW2, that is, between the AND circuit 162 and the switches SW1 and SW2. The delay circuit 170 has a capacitor Cd provided between the logic circuit 160 (AND circuit 162) and the ground GND. The transmission of the signal Ss from the switch control unit 120 to the switches SW1 and SW2 can be delayed by the delay circuit 170. Further, the delay circuit 170 can remove high frequency components from the signal Ss. In the power supply circuit 130, between the switches P1 to P9 to which power of 5 [V] is supplied and the switch SW1, and between the pins P13 to P15 to which power of 12 [V] is supplied and the switch SW2. Are provided with fuses 131, respectively.

  Further, as shown in FIG. 7, in this embodiment, the power supply of the logic circuit 160 is introduced from the power supply circuit 130. That is, the switch control unit 120 is configured to be operable with power supplied via the pins P7 to P9 or the pins P13 to P15. However, as described above, the switch control unit 120 operates at 3.3 [V], whereas the pins P7 to P9 operate at 5 [V] and the pins P13 to P15 operate at 12 [V]. Therefore, between the pins P7 to P9 or the pins P13 to P15 and the logic circuit 160, a potential adjusting unit 163 for converting the potential from 5 [V] or 12 [V] to 3.3 [V] is provided. ing. The potential adjusting unit 163 can be configured as, for example, an LDO (low drop out, voltage regulator) or a DDC (DC-DC converter). Note that the potential adjustment unit 163 only needs to obtain 3.3 [V] from one of 5 [V] and 12 [V].

  FIG. 9 shows a procedure of processing in the host device and the storage device compatible with power disable. As shown in FIG. 9, when detecting an abnormality (SH1), the host device transmits a control signal (power disable) to the storage device 100 (SH2). Transmission of the control signal at SH2 corresponds to a change in the potential of the pin P3 from a low level to a high level. When a change in the potential of the pin P3 (a change in the electrical state) occurs (SS1), the storage device 100 performs a data protection process (SS2). The data protection process in SS2 is also called PLP (power loss protection). Specifically, the controller 104 executes, as the PLP, completion of data reading or writing, discarding of a queue, backup of a logical-physical address conversion table, and the like. In the present embodiment, since the above-described delay circuit 170 (see FIG. 7) is provided, PLP processing in SS2 can be executed more reliably. That is, the processing time of the PLP can be more reliably secured. Next, at the timing after the end of the PLP processing, the switches SW1 and SW2 are turned off by the signal Ss output by the calculation in the logic circuit 160 of the switch control unit 120 based on the change in the potential of the pin P3 ( SS3). On the other hand, the host device measures an elapsed time after the transmission of the control signal (power disable), and transmits a control signal (power enable) to the storage device 100 when a predetermined time has elapsed (SH4) (SH4). Transmission of the control signal at SH4 corresponds to a change in the potential of the pin P3 from a high level to a low level. In the storage device 100, when a change in the potential of the pin P3 from a high level to a low level (change in an electrical state) occurs (SS4), the logic circuit 160 of the switch control unit 120 based on the change in the potential of the pin P3. The switches SW1 and SW2 are connected by the signal Ss output by the calculation in (5) (SS5). Thereby, the storage device 100 is restarted.

  In the storage device 100 of the present embodiment, the states of the switches SW1 and SW2 according to the potentials (electrical states) of the pin P1 (first terminal) and the pin P3 (second terminal) are different.

  Specifically, as shown in FIG. 8A, when the potential of the pin P3 is at a high level and the potential of the pin P1 is at a high level, the switches SW1 and SW2 are connected. Is controlled as follows. Since this case is the case of the specification (1) shown in FIG. 6, the expected state is that the switches SW1 and SW2 are connected. The device of the specification (1) in FIG. 6, that is, the device of the specification in which 3.3 [V] is applied to the pins P1 to P3 in accordance with SAS1, SAS2, and SAS2.1 is the first device in the present embodiment. It is an example of the device.

  Also, as shown in FIG. 8C, when the potential of the pin P3 is at a high level and the potential of the pin P1 is at a low level, the switches SW1 and SW2 are controlled to be in a cutoff state. You. In this case, since the potential of the pin P3 of the specification (3) shown in FIG. 6 is at the high level, the expected state is that the switches SW1 and SW2 are in the cut-off state. The device having the specification (3) in FIG. 6, that is, the device conforming to the SAS3 and having the specification corresponding to the power disable is an example of the second device in the present embodiment. As described above, in the present embodiment, the non-connection state (NC) of the pin P1 and the pin P3 can be treated as a low level by the pull-down circuit 150.

  Further, as shown in FIGS. 8B and 8D, when the potential of the pin P3 is at a low level, the switches SW1 and SW2 are connected regardless of the potential of the pin P1. Controlled. In this case, since the potential of the pin P3 of the specifications (2), (4), and (3) shown in FIG. 6 is at a low level, the switches SW1 and SW2 are connected. This is the expected state. The device of the specification (2) and the device of the specification (4) in FIG. 6, that is, a device that conforms to SAS1, SAS2, and SAS2.1 and has a specification in which 3.3 [V] is not applied to the pins P1 to P3. A device that conforms to SAS3 and does not support power disable is an example of a third device in the present embodiment.

  As described above, according to the present embodiment, the switch control unit 120 switches between the connection state and the cutoff state of the switches SW1 and SW2 according to the electrical states of the pins P1 and P2. , It is easy to obtain the desired connection state of the switches SW1 and SW2.

  In the present embodiment, the switch control unit 120 has the logic circuit 160. Thereby, the switch control unit 120 that controls the switches SW1 and SW2 to the expected state according to the specification and the control signal can be obtained as a relatively simple configuration.

<First Modification>
FIG. 10 is a schematic and exemplary block diagram of a storage device according to a first modification. As shown in FIG. 10, in the storage device 100A of this modification, the switch control unit 120 is configured as a switch control element 120b. The switch control element 120b can be configured as a semiconductor element or an integrated circuit such as an ASIC (application specific integrated circuit), an FPGA (field programmable gate array), and a PLD (programmable logic device). According to this modification, the same effect (result) as in the above embodiment can be obtained.

<Second modification>
FIG. 11 is a schematic and exemplary block diagram of a storage device according to a second modification. As shown in FIG. 11, in the storage device 100B of this modification, the switch control unit 120c (120) is included in the controller 104. That is, the controller 104 executes the arithmetic processing according to a program (software) such as firmware, thereby realizing the function of the switch control unit 120c as well as the function of the storage control unit 104a. According to the present modification, the same effects (results) as those of the above embodiment can be obtained.

  FIG. 12 is a schematic and exemplary flowchart of a procedure of processing by the storage device of the second modification. FIG. 12 illustrates a process by the power disable. First, the controller 104 functioning as the switch control unit 120c (120) detects the potential (electrical state) of the pins P1 and P3 (terminal) (S1), and the potential of the pin P3 is at a high level (S2). If the potentials of the pins P1 and P2 are low or different from the high and low levels (Yes in S3), a data protection process such as PLP is executed (S4). ), The switches SW1 and SW2 are controlled to be turned off (S5). Next, the controller 104 detects the electric potential (electrical state) of the pins P1 and P3 (terminal) (S6), and the electric potential of the pin P3 is at the low level or at another level different from the high level and the low level. If (S7: Yes), the switches SW1 and SW2 are controlled to be in the connected state (S8). By this S8, the storage device 100B is restarted. In the case of No in S2 and No in S3, the flow of FIG. 12 is not executed. If No in S7, the process returns to S6.

  Further, the storage device 100 according to the above-described embodiment or the modified example or equivalent thereto can be applied to other than the server device. FIG. 13 is an exemplary perspective view of an electronic device in which the storage device of the embodiment is incorporated. As shown in FIG. 13, the storage device 100 can be used by being housed in an electronic device 50 such as a personal computer. The electronic device 50 includes housings 51 and 52, a display 53, an input device 54, and the like. The housing 51 and the housing 52 are rotatably connected via a hinge 56. The display 53 is housed in the housing 51 with the display surface 53a exposed, and the input device 54 is housed in the housing 52 with the input unit 54a exposed. The display 53 is, for example, an LCD, an OELD, or the like. The input device 54 is, for example, a keyboard, a pointing device, a click button, or the like. The housing 52 houses a CPU 57 (central processing unit), a circuit board 55 on which electronic components (not shown) such as a controller are mounted, and a storage device 100. The circuit board 55 and the storage device 100 are electrically connected via wiring such as a flexible printed wiring board, a connector 58 provided in the electronic device 50, an interface unit 107 of the storage device 100 connected to the connector 58, and the like. It is connected to the. The interface units 58 and 107 transmit signals between the electronic device 50 and the storage device 100. The electronic device 50 is an example of a host device, and the CPU 57 is an example of a host control unit 231 (control unit 23). Note that the host control unit 231 may be other than the CPU 57. The electronic device is not limited to a clamshell type personal computer, but may be a desktop type personal computer or another electronic device.

  As mentioned above, although the embodiment of the present invention was illustrated, the above-mentioned embodiment is an example and is not intended to limit the scope of the invention. These embodiments can be implemented in other various forms, and various omissions, replacements, combinations, and changes can be made without departing from the spirit of the invention. These embodiments are included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalents. Further, the configuration and shape of each embodiment and each modified example can be partially replaced and implemented. In addition, the specifications (structure, type, direction, shape, size, length, width, thickness, height, number, arrangement, position, material, etc.) of each configuration and shape are appropriately changed and implemented. can do.

  100, 100A, 100B storage device, 103 memory, 104 controller, 107 interface unit, 120 switch control unit, 160 logic circuit, 161 NOT circuit, 162 AND circuit, 163 potential adjustment unit, 170 … Delay circuit, P1, P2 ... pin (first terminal), P3 ... pin (second terminal), P7 to P9, P13 to P15 ... pin (third terminal), SW1, SW2 ... switch.

Claims (18)

A storage device connectable to the first device or the second device,
A memory for storing data,
A control circuit that controls writing of data to the memory and reading of data from the memory;
At least, a first terminal, a second terminal, a first terminal of the first voltage of the first voltage is supplied to the storage device, an interface circuit having a,
Based on the states of the first terminal and the second terminal, a connection state indicating that power corresponding to the first power is supplied to the control circuit and the memory, and the power corresponding to the first power is A control circuit and a switch control circuit for performing switching control of a cutoff state indicating that the memory is not supplied to the memory,
While the storage device and the first device are connected, the first terminal is in the first state, and the second terminal is configured to store a second power of a second voltage through the second terminal. It is in the second state indicating that it is supplied to the device,
While the storage device and the second device are connected, the first terminal is in a third state different from the first state, and the second terminal is the second terminal from the second device to the storage device. A storage device which is in a fourth state indicating that a control signal is input through two terminals.   The switch control circuit is in the connection state when the first terminal is in the first state, and the connection state and the connection state according to the control signal when the first terminal is in the third state. 2. The storage device according to claim 1, wherein the switching control is performed based on a state of the first terminal so as to switch to a cutoff state. 3. When the storage device is connected to a connectable third device,
A third power of a third voltage is supplied to the storage device via the third terminal,
The first power and the control signal are not input to the storage device via the second terminal, and
The storage device according to claim 1, wherein the switch control circuit executes the switching control so as to be in the connection state.   When the potential of the second terminal is a low level lower than the high level or another level different from the low level and the high level, the connection state is established regardless of the potential of the first terminal. Item 2. The storage device according to item 1.   The storage device according to claim 1, wherein the switch control circuit includes a logic circuit that performs a logic operation based on a potential level of the first terminal and the second terminal. A storage device connectable to the first device or the second device,
A memory for storing data,
A first control circuit that controls writing of data to the memory and reading of data from the memory,
An interface having at least a first terminal, a second terminal, and a third terminal for supplying a first power of a first voltage to the storage device when the storage device and the second device are connected. Circuit and
Based on the states of the first terminal and the second terminal, a connection state indicating that power corresponding to the first power is supplied to the first control circuit and the memory, and a connection state corresponding to the first power. And a cutoff state indicating that power is not supplied to the first control circuit and the memory, and a second control circuit that performs a switching control,
While the storage device and the first device are connected, the first terminal and the second terminal are in the same state,
A storage device, wherein a control signal is input from the second device to the storage device via the second terminal while the storage device and the second device are connected.   The second control circuit is in the connected state when the first terminal and the first device are connected, and when the first terminal is connected to the second device, the control signal is 7. The storage device according to claim 6, wherein switching control is executed based on a state of the first terminal so that the connection state is switched between the connection state and the cutoff state. When the storage device is connected to a connectable third device,
A first power is supplied to the storage device via the third terminal,
The second power of the second voltage and the control signal are not input to the storage device via the second terminal, and
The storage device according to claim 6, wherein the second control circuit executes switching control so as to be in the connection state.   When the potential of the second terminal is a low level lower than the high level or another level different from the high level and the low level, the connection state is established regardless of the potential of the first terminal. Item 7. The storage device according to Item 6. A storage device connectable to the first device or the second device,
A memory for storing data,
A first control circuit that controls writing of data to the memory and reading of data from the memory,
At least, a first terminal, an interface circuit having a second terminal,
A first state indicating that the interface circuit and the first control circuit are electrically connected, based on the states of the first terminal and the second terminal, and the interface circuit and the first control circuit. A second state that indicates that is electrically interrupted, and a second control circuit that performs switching control of,
While the storage device and the first device are connected, the first terminal is in the third state, and the second terminal is configured such that the first power of the first voltage is supplied to the storage device via the second terminal. Is in the fourth state, indicating that
While the storage device and the second device are connected, the first terminal is in a fifth state different from the third state, and the second terminal has a control signal transmitted from the second device to the second terminal. The storage device is in a sixth state indicating that the input is made to the storage device via a.   The second control circuit, the storage device and the second device, so as to be in the first state based on the state of the first terminal while the storage device and the first device are connected The storage device according to claim 10, wherein the switching control is performed such that the first state and the second state are switched according to the control signal while the terminal is connected. When the storage device is connected to a connectable third device,
A third power of a third voltage is supplied to the storage device,
The second power of the second voltage and the control signal are not input to the storage device, and
The storage device according to claim 10, wherein the second control circuit executes switching control so as to be in the first state.   When the potential of the first terminal is at a high level and the potential of the second terminal is at a high level, the first state is established, and the potential of the first terminal is at a low level or a high level and a low level. 11. The storage device according to claim 10, wherein the second state is established when the level is different from the level and the potential of the second terminal is at a high level.   When the potential of the second terminal is a low level lower than the high level or another level different from the high level and the low level, the first state is established regardless of the potential of the first terminal, The storage device according to claim 10. The first terminal is a P1 pin or a P2 pin of a power supply interface of the SAS standard,
The storage device according to claim 10, wherein the second terminal is a P3 pin of the power supply interface.   When the potential of the first terminal is high and the potential of the second terminal is high, the connection state is established, and the potential of the first terminal is low or lower than high. 7. The storage device according to claim 1, wherein the cutoff state is established when the level of the second terminal is different from a level and a low level and the potential of the second terminal is at a high level. 8. The first terminal is a P1 pin or a P2 pin of a power supply interface of the SAS standard,
The second terminal is a P3 pin of the power supply interface,
7. The storage device according to claim 1, wherein the third terminal is any one of a P7 pin, a P8 pin, a P9 pin, a P13 pin, a P14 pin, and a P15 pin of the power supply interface.   The storage device according to claim 6, wherein the second control circuit includes a logic circuit that performs a logic operation based on a potential level of the first terminal and the second terminal.

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