JP6639037B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply for converting an input voltage into a desired voltage and supplying the converted voltage to an electronic device, and more particularly to a switching power supply that realizes highly accurate output voltage control using a low-cost digital processor.

(Output voltage control of switching power supply by digital processor)
2. Description of the Related Art Conventionally, Patent Document 1 discloses a technique for controlling an output voltage of a switching power supply device by a digital processor.

  The switching power supply device of Patent Literature 1 obtains a target voltage signal Vob by smoothing a reference pulse Vrp output from a reference pulse generator controllable by a digital processor by a pulse smoothing circuit.

  The output voltage Vo of the switching power supply is controlled by an error amplifier circuit so as to be a predetermined value proportional to the target voltage signal Vob. The reference pulse Vrp is a square wave having a predetermined cycle and a predetermined duty, and the target voltage Vob is determined by the amplitude and the duty of the reference pulse Vrp.

Assuming that the voltage when the reference pulse Vrp is at the H level is VH, the voltage when the reference pulse Vrp is at the L level is VL, and the duty is d, the target voltage Vob is
Vob = (VH−VL) × d + VL
Becomes For example, when VH = 5 volts, VL = 0 volts, and d = 0.5, a target voltage Vob = 2.5 volts is obtained. Therefore, the resolution for setting the output voltage Vo of the switching power supply device is determined by the resolution for setting the duty d of the reference pulse Vrp.

  The square wave output from the reference pulse generation unit generates a count value by counting the clock signal Vck of the clock generator with a counter, and when the count value reaches the register setting value R1, the voltage level of the reference pulse Vrp is changed. When the count value reaches the register set value R2, the operation of resetting the count value at the same time as setting the voltage level of the reference pulse Vrp to the H level is repeated.

  Therefore, the cycle of the clock signal Vck and the register setting value R2 determine the cycle of the square wave of the reference pulse Vrp, and the register setting value R1 determines the duty of the reference pulse Vrp.

  At this time, since the duty d of the reference pulse Vrp is R1 / R2, the setting resolution of the duty d is the register setting value R2. For example, when the cycle of the clock signal Vck is 100 nsec and the register setting value R2 is 10000, the cycle of the reference pulse Vrp is 1 ms, and the setting resolution of the duty d is 10000.

  When the register set value R1 is 5000, the duty d is 0.5, and 2.5 volts is obtained as the target voltage Vob. When the register setting value R1 is 5001, the duty d is 0.5001, and 2.505 volts is obtained as the target voltage Vob. Here, the register setting values R1 and R2 are values set by the digital processor.

  In order to set the output voltage Vo of the switching power supply with a high resolution using a digital processor, it is common to use a high-resolution DA converter, but a digital processor having a high-resolution DA converter is very difficult. Due to the high cost, general-purpose low-cost digital processors often do not have a DA converter, or have a low resolution even if they do.

  Even a general-purpose low-cost digital processor is provided with a clock generator and a reference pulse generation unit. Therefore, the technology of Patent Document 1 is used to control the output voltage with high resolution even when using a low-cost digital processor. It is possible to do.

(Variable output voltage control of switching power supply unit by externally input voltage)
Patent Document 2 discloses a technique for varying the output voltage of a switching power supply with a voltage signal input from the outside.

  In the switching power supply device of Patent Document 2, a voltage obtained by dividing the output voltage by a resistor is input to one end of an input of an error amplifier, and the other end of the input of the error amplifier is a control voltage terminal. The error amplifier controls the output voltage of the switching power supply device so that the output voltage is proportional to the voltage applied to the control voltage terminal.

  This allows the error amplifier to perform control so that the output voltage of the switching power supply becomes a voltage proportional to the voltage applied to the control voltage terminal, for example, a sine wave to the control voltage terminal. By inputting, the output voltage of the switching power supply can be shaped into a sine wave.

  By the way, in the switching power supply device of Patent Document 2, since the voltage applied to the control voltage terminal is directly input to the error amplifier, the output voltage of the switching power supply device becomes a voltage proportional to the voltage applied to the control voltage terminal. Could only be controlled.

  On the other hand, the switching power supply disclosed in Patent Document 3 converts a control voltage (analog value) for varying the output voltage of the switching power supply into a digital value by a digital processor, and then switches the switching power supply based on the digital value. Techniques for controlling the output voltage of the device have been disclosed.

  In the switching power supply device of Patent Document 3, a processing unit of a digital processor converts an analog voltage (control voltage for varying an output voltage) input to an external input terminal into a digital value voltage setting signal using an AD converter. Converted to Vtrm (k) and acquired.

  The processing unit calculates the self-target value VR (k) according to the voltage setting signal Vtrm (k) and other given conditions, sets the voltage of the reference power supply to the self-target value VR (k), and supplies the self-target value VR (k) to the error amplifier. Output. As a result, control is performed so that the output voltage Vo of the switching power supply becomes a predetermined value proportional to the voltage VR (k) of the reference power supply.

  By using the technique of Patent Literature 3, the processing unit of the switching power supply device can set the output voltage Vo with an analog value input to the external input terminal, and can vary the output voltage. Can be set freely, such as proportional, inversely proportional, linear, logarithmic, and variable width limiting. In addition, during the operation of the switching power supply device, for example, switching to voltage setting by a communication function can be freely performed.

  Note that Patent Document 3 does not specify a technique for generating the self-target voltage VR (k) using the reference power supply. However, by using Patent Document 1, the self-target voltage VR (k) of the reference power supply is generated. can do.

JP 2014-128110 A JP-A-6-222847 JP 2013-138557 A

  By the combination of Patent Document 1 and Patent Document 3, the switching power supply device can process both the acquisition of the control voltage for varying the output voltage and the setting of the output voltage by the digital processor. However, in a switching power supply device combining these conventional examples, there is the following problem when trying to obtain a wide output voltage variable range using a low-cost digital processor.

When a low-cost digital processor is used for control, the output voltage can be set to a sufficiently high resolution by using the technique of Patent Document 1. Here, an AD converter provided in a low-cost digital processor generally has a low resolution such as 8 bits or 10 bits. Therefore, when a control voltage for setting an output voltage is converted into a digital value using the technique of Patent Document 3, for example, a 10-bit AD converter can obtain a digital value only in 2 ¹⁰ = 1024 steps.

For example, the output voltage of a switching power supply that can output about 6.144 volts as the maximum output voltage and about 0 volts as the minimum output voltage is converted into a digital value by converting the control voltage into a digital value using an AD converter with a resolution of 10 bits. When setting the output voltage, the resolution of the output voltage setting is
(6.144 volts-0 volts) / 2 ¹⁰ = 6 millivolts. In this case, the digital processor controls the output voltage Vo of the switching power supply with respect to the digital value NDG from the AD converter according to the equation (1).
Vo = NDG x 6 millivolts (1)
Here, the digital value NDG is an integer of NDG = 0 to 1023.

  Although the setting resolution of the output voltage can be sufficiently increased by the technique of Patent Document 1, when the resolution of the AD converter for converting the control voltage for varying the output voltage into a digital value is low, as a result, This makes it impossible to set the output voltage Vo of the switching power supply at a high resolution.

  For example, in the switching power supply of the formula (1), it is not possible to set a voltage of a portion of 6 millivolts or less. This problem becomes conspicuous when the output voltage variable range is widened. For example, in a switching power supply device, if the variable range of the output voltage is halved, the variable range of the output voltage is halved with respect to a change in the control voltage for varying the output voltage. The output voltage can be set in steps.

(Problem of quantization fluctuation of AD converter)
Next, a problem of the output voltage setting caused by the quantization fluctuation of the AD converter will be described. The operation of the AD converter will be described below using a general successive conversion type AD converter as an example. The AD converter circuit includes a reference voltage circuit that outputs an analog reference voltage VADref, a comparison voltage generation circuit that outputs an analog comparison voltage VADcmp, a voltage comparator, and an AD converter control circuit.

The comparison voltage VADcmp generated by the comparison voltage generation circuit is generated as a voltage obtained by dividing the reference voltage VADref from the reference voltage circuit, and is a voltage corresponding to the divided information ADdiv given to the comparison voltage generation circuit from the AD converter control circuit. Occurs. In a 10-bit AD converter, the divided voltage information ADdiv is given an integer of 0 to 1023, and the comparison voltage VADcmp is as shown in Expression (2).
VADcmp = VADRef / 1024 × ADdiv (2)

  The comparison voltage VADcmp from the comparison voltage generation circuit and the control voltage VTRM for varying the output voltage are input to the voltage comparator in the AD converter circuit. The AD converter control circuit changes the comparison voltage VADcmp from the comparison voltage generation circuit by scanning the divided voltage information ADdiv. Then, each time the divided voltage information ADdiv is changed, the voltage comparator compares the comparison voltage VADcmp with the control voltage VTRM. As a result of the comparison operation, when the voltage value of the control voltage VTRM and the voltage value of the comparison voltage VADcmp become closest, the comparison operation is completed, and the value of the divided voltage information ADdiv is output as an AD measurement value (digital value) NADmeas.

  Here, the operation of the successive conversion type AD converter will be described on the assumption that 5.120 V is applied as the reference voltage VADRef.

  A switching power supply device that controls an output voltage by using an AD measured value NADmeas output from an AD converter as a digital value NDG of Expression (1) is considered. In this switching power supply, when 4.000 volts is applied to the control voltage VTRM, 800 is obtained as the AD measured value NADmeas from equation (2), and 4.800 volts is output as the output voltage Vo according to equation (1). When 4.005 volts is applied to the control voltage VTRM, 801 is obtained as the AD measured value NADmeas from equation (2), and 4.806 volts is output as the output voltage Vo according to equation (1).

  Here, when the control voltage VTRM is provided with an intermediate voltage of 4.000 volts and 4.005 volts, that is, 4.0025 volts, an operation of converting a voltage portion smaller than the resolution of the AD converter into a digital value is performed. The AD measurement value NADmeas is either 800 or 801 with a probability of 50%.

  This is a general phenomenon called “quantization fluctuation” of the AD converter, and the comparison operation is completed when the voltage value of the control voltage VTRM and the comparison voltage VADcmp of the previous AD converter becomes closest. The operation of "outputting the value of the pressure information ADdiv as the AD measurement value NADmeas" and the "reference voltage VADRef of the reference voltage circuit of the AD converter circuit, the control voltage VTRM for varying the output voltage Vo, etc." Voltage fluctuations ".

  Hereinafter, for simplification, it is assumed that there is no voltage fluctuation in the reference voltage VADref, and an AD measurement value NADmeas for the voltage fluctuation of the control voltage VTRM is considered.

  When the conversion operation of the AD converter is performed while the voltage fluctuation in the direction slightly higher than 4.0025 volts is generated from the control voltage VTRM, when the divided voltage information ADdiv is 801, the values of the control voltage VTRM and the comparison voltage VADcmp are changed. Since it is closest, 801 is output as the AD measurement value NADmeas.

  Further, if the conversion operation of the AD converter is performed while the voltage fluctuation in the direction slightly lower than 4.0025 volts is generated from the control voltage VTRM, when the divided voltage information ADdiv is 800, the control voltage VTRM and the comparison voltage VADcmp are used. Is closest, 800 is output as the AD measurement value NADmeas.

  Since the voltage fluctuation occurs uniformly with the control voltage VTRM at 4.0025 volts as the center, the AD measurement value NADmeas is output at 800% or 801 with a probability of 50%. .

  When the control voltage VTRM is larger than 4.000 V volts and smaller than 4.0025 volts, the probability of outputting 800 as the AD measured value NADmeas is higher than the probability of outputting 801.

  At this time, the probability that the AD measurement value NADmeas outputs 800 increases as the control voltage VTRM is closer to 4.000 volts. Conversely, when the control voltage VTRM is greater than 4.0025 volts and less than 4.005 volts, the probability of outputting 801 as the AD measured value NADmeas is higher than the probability of outputting 800.

  As described above, in the switching power supply device that controls the output voltage Vo based on the AD measurement value NADmeas output from the successive approximation type AD converter, when the AD measurement value NADmeas fluctuates due to quantization fluctuation, the fluctuation in the output voltage Vo occurs. Will happen. For example, in the case of a switching power supply in which the output voltage Vo is controlled according to the equation (1), if the AD measurement value NADmeas fluctuates by 1, the output voltage Vo fluctuates by 6 millivolts.

  The fluctuation of the output voltage Vo of the switching power supply due to the quantization fluctuation appears as an output ripple of the switching power supply. By using a high-resolution A / D converter, it is possible to reduce the output ripple of the switching power supply device caused by the quantization fluctuation of the A / D converter. The power supply becomes expensive.

  As another method, there is a method of adding an LC filter for removing a ripple to the output of the switching power supply. However, since the fluctuation occurs irregularly and at a low frequency, the output ripple of the switching power supply also varies irregularly. In order to eliminate this, a large LC filter capable of removing low-frequency ripple must be attached to the output of the switching power supply, resulting in an increase in the size and cost of the switching power supply. I will.

(Current solutions and problems for AD converter resolution)
The output ripple of the switching power supply device caused by the low resolution of the AD converter can be reduced to a level at which no practical problem occurs by increasing the resolution of the AD converter.

  As a method for artificially improving the resolution of a low-resolution AD converter, a method called oversampling is used in digital audio equipment and the like. Oversampling is a method of improving the resolution by using a value obtained by integrating the measured value of the AD converter a predetermined number of times.

  In the oversampling, the resolution is improved by using the probability of the fluctuation of the AD measurement value NADmeas generated due to the above-mentioned quantization fluctuation. Since the probability of the fluctuation of the AD measurement value NADmeas is determined by the voltage of a portion smaller than the resolution of the AD converter, the information obtained by integrating the sampling results of the AD converter can obtain information lower than the resolution of the AD converter. Become.

  It is known that the number of bits of the resolution that is improved with respect to the number of integrations by oversampling is as shown in Table 1. For example, if the conversion result of the 10-bit AD converter is integrated 4096 times, the resolution will be improved by 6 bits, and the same resolution as when a 16-bit AD converter is used will be obtained.

  When the resolution is improved by applying oversampling, there is a problem that it takes a long time to obtain a measurement result. For example, when trying to obtain a resolution equivalent to 13 bits by performing oversampling by using an AD converter with a sampling period of 100 μsec and a resolution of 10 bits, 64 samplings are required from Table 1. In this case, 100 μsec × 64 times = 6400 μsec is required.

  In the switching power supply, when oversampling is used when the control voltage VTRM for varying the output voltage is obtained by the AD converter, when the control voltage VTRM input to the control input terminal is changed, the switching power supply The time required for the output voltage Vo to respond becomes longer.

  In the switching power supply device of Patent Document 3, for example, it is possible to shape the output voltage Vo of the switching power supply device into a sine wave shape by inputting a sine wave to the control input terminal. In the power supply device, when the control voltage VTRM input to the control input terminal is changed, the time required for the output voltage Vo to respond becomes longer, which makes it difficult to shape the output voltage Vo with respect to the control voltage VTRM. Occurs.

  The present invention suppresses generation of output ripple of a switching power supply device due to quantization fluctuation of an AD converter even when output voltage control is performed using a low-cost digital processor having only a low-resolution AD converter; It is an object of the present invention to provide a switching power supply device capable of shortening a response time of an output voltage to a control input terminal.

To achieve this object, the switching power supply of the present invention has the following configuration. In addition, reference numerals of signals and information in the drawings are shown in parentheses.
(First invention: switching power supply device for controlling output voltage)
The present invention is a switching power supply device including a power conversion unit and an output control unit,
The power converter includes a switching element and an output smoothing circuit, and converts an input voltage to an intermittent voltage by turning on and off the switching element, and converts the intermittent voltage to a DC voltage by an output smoothing circuit to generate an output voltage (Vo). And the output voltage (Vo) is controlled by the control reference value (R1) given from the output control unit,
The output control unit receives a control voltage (VTRM) for controlling the output voltage (Vo) of the power conversion unit, and sets a control reference value (R1) for setting the output voltage (Vo) to the power conversion unit. A circuit for outputting, comprising an AD converter and an arithmetic unit including an AD measured value integration processing unit, an AD measured value fluctuation response processing unit, and a setting information generation processing unit,
The AD converter receives the control voltage (VTRM), generates an AD measurement value (NADmeas) which is a digital value from the input control voltage (VTRM), and outputs the AD measurement value to the arithmetic unit.
The AD measurement value integration processing unit generates an AD integration value (NADsum), which is a value obtained by integrating the AD measurement value (NADmeas) by a predetermined integration number (m), and outputs the value to the AD measurement value fluctuation response processing unit.
The AD measurement value variation response processing unit obtains a difference between a value obtained by multiplying the AD measurement value (NADmeas) by the number of integrations (m) and the AD integration value (NADsum), and the difference is equal to or greater than a predetermined variation determination value (a) or If it exceeds, the AD operation value (NADcalc) is set to a value obtained by multiplying the AD measurement value (NADmeas) by the number of integrations (m) and output to the setting information generation processing unit, and the difference is determined to be a predetermined fluctuation determination value (a). If less than or equal to or less than, the AD operation value (NADcalc) is set to the AD integrated value (NADsum) and output to the setting information generation processing unit.
The setting information generation processing unit generates a control reference value (R1) based on the AD operation value (NADcalc) and outputs the control reference value (R1) to the power conversion unit.
It is characterized by the following.

(Second invention: switching power supply device for controlling output current)
According to another aspect of the present invention, there is provided a switching power supply device including a power conversion unit and an output control unit,
The power converter includes a switching element and an output smoothing circuit, converts an input voltage into an intermittent voltage by turning on and off the switching element, converts the intermittent voltage into a DC voltage by an output smoothing circuit, and outputs an output voltage (Vo) and an output current ( A circuit for generating Io), wherein an output current (Io) is controlled by a control reference value (R1) given from an output control unit;
The output control unit receives a control voltage (ITRM) for controlling the output current (Io) of the power conversion unit and sets a control reference value (R1) for setting the output current (Io) to the power conversion unit. A circuit for outputting, comprising an AD converter and an arithmetic unit including an AD measured value integration processing unit, an AD measured value fluctuation response processing unit, and a setting information generation processing unit,
The AD converter receives the control voltage (ITRM), generates an AD measurement value (NADmeas) which is a digital value from the input control voltage (ITRM), and outputs it to the arithmetic unit.
The AD measurement value integration processing unit generates an AD integration value (NADsum), which is a value obtained by integrating the AD measurement value (NADmeas) by a predetermined integration number (m), and outputs the value to the AD measurement value fluctuation response processing unit.
The AD measurement value variation response processing unit obtains a difference between a value obtained by multiplying the AD measurement value (NADmeas) by the number of integrations (m) and the AD integration value (NADsum), and the difference is equal to or greater than a predetermined variation determination value (a) or If it exceeds, the AD operation value (NADcalc) is set to a value obtained by multiplying the AD measurement value (NADmeas) by the number of integrations (m) and output to the setting information generation processing unit, and the difference is determined to be a predetermined fluctuation determination value (a). If less than or equal to or less than, the AD operation value (NADcalc) is set to the AD integrated value (NADsum) and output to the setting information generation processing unit.
The setting information generation processing unit generates a control reference value (R1) based on the AD operation value (NADcalc) and outputs the control reference value (R1) to the power conversion unit.
It is characterized by the following.

(Simplification of calculation by setting value of pulse cycle setting register)
The power converter includes a control reference voltage generator to which a control reference value (R1) is input from the output controller.
The control reference voltage generator includes a reference pulse generator and a smoothing circuit.
The reference pulse generation unit includes a counter to which a clock signal is input, a pulse cycle setting register, a duty setting register, and a pulse control unit that outputs a reference pulse to a smoothing circuit.
The counter outputs a count value obtained by counting the clock signal to the pulse control unit,
The pulse control unit resets the count value of the counter when the count value matches the set value (R2) of the pulse cycle setting register, sets the reference pulse to a predetermined voltage level at the same time, and sets the count value to the duty setting register. Inverts the voltage level of the reference pulse when it is equal to the set value (R1), and outputs a square wave reference pulse having a predetermined cycle, duty and duty resolution,
In the pulse cycle setting register, the pulse cycle control reference value (R2) in which the resolution of the duty of the reference pulse is a value obtained by dividing the product of the resolution of the AD converter and the number of integrations m by 2 n (n is an integer). ) Is set,
The control reference value (R1) output from the output control unit is set in the duty setting register.
The smoothing circuit generates a control reference voltage by smoothing the reference pulse output from the pulse control unit.

(Effect of the first invention)
The present invention is a switching power supply device including a power conversion unit and an output control unit, wherein the power conversion unit includes a switching element and an output smoothing circuit, and converts an input voltage into an intermittent voltage by turning on and off the switching element, and The output smoothing circuit converts the voltage into a DC voltage to generate an output voltage (Vo). The output voltage is controlled by a control reference value (R1) given from an output control unit. A control voltage (VTRM) for controlling the output voltage (Vo) of the power converter, and a control reference value (R1) for setting the output voltage (Vo) to the power converter. The AD converter includes an AD converter and an arithmetic unit including an AD measurement value integration processing unit, an AD measurement value fluctuation response processing unit, and a setting information generation processing unit. A trawl voltage (VTRM) is input, an AD measurement value (NADmeas), which is a digital value, is generated from the input control voltage (VTRM) and output to the arithmetic unit. An AD integrated value (NADsum), which is a value obtained by integrating the value (NADmeas) by a predetermined integration number (m), is output to the AD measured value fluctuation response processing unit. A difference between a value obtained by multiplying the value (NADmeas) by the number of times of integration (m) and an AD integrated value (NADsum) is obtained. If the difference is equal to or greater than a predetermined fluctuation determination value (a), the AD operation value (NADcalc) is calculated. A value obtained by multiplying the AD measurement value (NADmeas) by the number of integrations (m) is output to the setting information generation processing unit, and when the difference is less than or less than the predetermined fluctuation determination value (a), The AD operation value (NADcalc) is set to the AD integrated value (NADsum) and output to the setting information generation processing unit, and the setting information generation processing unit generates the control reference value (R1) based on the AD operation value (NADcalc). As a result, the following effects can be obtained.

  In the present invention, even when a low-resolution AD converter is used, generation of output ripple due to quantization fluctuation is suppressed by oversampling (AD measurement value integration processing), and the control voltage (VTRM) caused by oversampling can be varied. The response delay of the output voltage (Vo) with respect to is solved by simultaneously performing the AD measurement value integration processing (oversampling) and the AD measurement value fluctuation response processing, so that even a low-cost digital processor can achieve high-precision control and high-speed control. You will be able to achieve both.

(Effect of the second invention)
According to another aspect of the present invention, there is provided a switching power supply device including a power conversion unit and an output control unit, wherein the power conversion unit includes a switching element and an output smoothing circuit, and controls an input voltage by turning on and off the switching element. A circuit for converting an intermittent voltage to a direct current voltage by an output smoothing circuit to generate an output voltage (Vo) and an output current (Io). The output current (Io) is supplied from an output control unit. The control voltage (ITRM) for controlling the output current (Io) of the power conversion unit is input to the output control unit, and the output current (Io) is supplied to the power conversion unit. A circuit for outputting a control reference value (R1) for setting an A / D converter, comprising an A / D converter, an A / D measurement value integration processing unit, an A / D measurement value fluctuation response processing unit, and a setting information generation processing unit. The AD converter receives a control voltage (ITRM), generates an AD measurement value (NADmeas) as a digital value from the input control voltage (ITRM), and outputs the digital value to the arithmetic unit. Then, the AD measurement value integration processing unit generates an AD integration value (NADsum), which is a value obtained by integrating the AD measurement value (NADmeas) by a predetermined integration number (m), and outputs the value to the AD measurement value fluctuation response processing unit. , The D-measurement-variation response processing unit obtains a difference between a value obtained by multiplying the AD measurement value (NADmeas) by the number of integrations (m) and the AD integration value (NADsum), and the difference is equal to or greater than a predetermined variation determination value (a). Or, if it exceeds, set the AD operation value (NADcalc) to the value obtained by multiplying the AD measurement value (NADmeas) by the number of integrations (m), and output it to the setting information generation processing unit, If the value is less than or less than the predetermined change determination value (a), the AD calculation value (NADcalc) is set to the AD integrated value (NADsum) and output to the setting information generation processing unit. Since the control reference value (R1) is generated based on the value (NADcalc) and output to the power conversion unit, the following effects can be obtained.

  In the present invention, even when a low-resolution AD converter is used, generation of oscillation of the output current (Io) due to quantization fluctuation is suppressed by oversampling (AD measurement value integration processing), and control voltage caused by oversampling is suppressed. The response delay of the output current (Io) with respect to the variation of (ITRM) is solved by simultaneously performing the AD measurement value integration processing (oversampling) and the AD measurement value fluctuation response processing. And high-speed control can be achieved at the same time.

(Effects of calculation by setting value of pulse cycle setting register)
The power converter includes a control reference voltage generator to which a control reference value (R1) from the output controller is input. The control reference voltage generator includes a reference pulse generator and a smoothing circuit. The reference pulse generation unit includes a counter to which a clock signal is input, a pulse cycle setting register, a duty setting register, and a pulse control unit that outputs a reference pulse to a smoothing circuit, and the counter counts the clock signal. The count value is output to the pulse control unit, and the pulse control unit resets the count value to the counter when the count value matches the set value (R2) of the pulse period setting register and simultaneously sets the reference pulse to a predetermined voltage level. When the count value matches the set value (R1) of the duty setting register, the voltage level of the reference pulse is inverted, and A square wave reference pulse having a period, a duty, and a duty resolution is output. The pulse period setting register stores the duty resolution of the reference pulse as the product of the resolution of the AD converter and the number of integrations m to the power of 2 n. Is set as the pulse cycle control reference value (R2), which is a value obtained by dividing by (2), the control reference value (R1) output from the output control unit is set in the duty setting register, and the smoothing circuit is set. Generates the control reference voltage by smoothing the reference pulse output from the pulse control unit. Therefore, the generation of the control reference voltage based on the control reference value (R1) from the output control unit is performed by a counter and a pulse cycle. The operation is performed by a circuit constituting a reference pulse generation unit including a setting register, a duty setting register, and a pulse control unit, and a smoothing circuit. Effect can be obtained.

  According to the present invention, an AD integrated value (NADsum) which is an integrated result obtained by integrating the AD measured value (NADmeas) obtained by oversampling by a predetermined integration number (m) is directly added, or a correction value is added or subtracted or registered. Can be handled as a control reference value (R1) only by performing a simple operation of about the bit shift of the digital processor. Therefore, the operation of the digital processor can be simplified. High-speed operation is possible, and an LC filter circuit composed of a large coil and a capacitor for reducing ripples and a high-resolution AD converter are not required, so that the size and cost of the switching power supply device can be reduced.

FIG. 2 is a block diagram illustrating an embodiment of a switching power supply device that controls an output voltage by a control voltage. Flow chart showing the processing operation of the AD measurement value integration processing unit Flowchart showing the processing operation of the AD measurement value fluctuation response processing unit Time chart showing the operation of the reference pulse generator FIG. 1 is a block diagram illustrating an embodiment of a switching power supply device that controls an output current by a control voltage.

[Embodiment of Switching Device According to First Invention]
FIG. 1 is a circuit block diagram showing an embodiment of a switching power supply device for controlling an output voltage.

  As shown in FIG. 1, the switching power supply of the present embodiment includes a power converter 10 and an output controller 12.

[Circuit configuration of power conversion unit]
(Step-down chopper circuit)
The power converter 10 includes a step-down chopper circuit as a power supply circuit that converts an input voltage Vin to the input terminals 11a and 11b into an output voltage Vo and outputs the output voltage Vo to the load from the output terminals 25a and 25b.

  In the step-down chopper circuit of the power conversion unit 10, a drain of a switching element 14 using a MOS-FET is connected to a positive input terminal 11a, and an anode of a rectifying diode 16 and one end of an inductor 18 are connected to a source of the switching element 14. Is connected, one end of the capacitor 20 is connected to the other end of the inductor 18, and the other end of the capacitor 20 and the cathode of the diode 16 are connected to the negative input terminal 11b.

  The step-down chopper circuit converts the input voltage Vin from the input terminals 11 a and 11 b into an intermittent voltage by turning on and off the switching element 14, rectifies the intermittent voltage by the diode 16, and comprises the inductor 18 and the capacitor 20. The voltage is converted into a DC voltage by smoothing with a smoothing circuit, and an output voltage Vo is generated and supplied to the load from output terminals 25a and 25b.

  In the present embodiment, a non-insulating type step-down chopper is used for the power conversion unit 10. However, any circuit capable of power conversion by turning on and off the switching element may be used. For example, an insulation type forward converter or flyback A converter may be used.

  Further, the power conversion unit 10 includes a control reference voltage generation unit 28, a feedback control circuit 26, and a PWM control circuit 30.

(Control reference voltage generator)
The power conversion unit 10 controls the output voltage Vo so as to follow the control reference value R1 input from the output control unit 12. Therefore, the power conversion unit 10 is provided with a control reference voltage generation unit 28. Then, the control reference voltage generator 28 converts the input control reference value R1 into a control reference voltage VoRef and outputs it to the feedback control circuit 26. The details of the control reference voltage generator 28 will be clarified later.

(Feedback control circuit)
The feedback control circuit 26 includes an error amplifier 32. The error amplifier 32 receives a control reference voltage VoRef and an output detection voltage Vsens which is a voltage proportional to the output voltage Vo divided by the resistors 22 and 24. The error amplifier 32 outputs to the PWM control circuit 30 a feedback signal VFB that changes according to an error between the control reference voltage VoRef and the output detection voltage Vsens.

  That is, the error amplifier 32 of the feedback control circuit 26 performs control such that the feedback signal VFB decreases when Vsens> VoRef, and performs control such that the feedback signal VFB increases when Vsens <VoRef.

(PWM control circuit)
The PWM control circuit 30 includes a PWM comparator 50 and a triangular wave oscillator 48. The triangular wave oscillator 48 outputs a triangular wave signal Vtri having a predetermined frequency and amplitude. The PWM comparator 50 receives the triangular wave signal Vtri and the feedback signal VFB and outputs a switching control signal VGS for turning on and off the switching element 14 based on the result of comparing the triangular wave signal Vtri and the feedback signal VFB.

  That is, the PWM control circuit 30 performs control so that the switching control signal VGS becomes H level when VFB> Vtri, and performs control so that the switching control signal VGS becomes L level when VFB <Vtri.

  Thus, the switching frequency of the switching power supply is determined by the frequency of the triangular wave oscillator 48. The on-duty of the switching element 14 is controlled by the voltage level of the feedback signal VFB. When the feedback signal VFB increases, the on-duty of the switching element 14 increases, and when the feedback signal VFB decreases, the on-duty of the switching element 14 decreases. Become.

[Output control unit]
The output control unit 12 is a function implemented by a digital processor. The output control unit 12 is a circuit that receives a control voltage VTRM at a control voltage input terminal 15 and performs a calculation to output a control reference value R1. It comprises a part 54.

(AD converter)
The control voltage VTRM is input from the control voltage input terminal 15 to the AD converter 52, and performs an operation of converting the control voltage VTRM, which is an analog voltage, into an AD measurement value NADmeas, which is a digital value. The AD measurement value NADmeas is updated to a new value at the sampling cycle TAD of the AD converter 52, and is output to the arithmetic unit 54. The AD converter 52 of the present embodiment is a successive conversion type AD converter, and performs the same operation as that described in the conventional example.

  In the circuit of the AD converter 52, a reference voltage generation circuit 58 that outputs a reference voltage VADref of an analog voltage, a comparison voltage generation circuit 60 that outputs a comparison voltage VADcmp of an analog voltage, a voltage comparator 56, and an AD converter control circuit 62 Is provided.

  The comparison voltage VADcmp generated by the comparison voltage generation circuit 60 is generated as a voltage obtained by dividing the reference voltage VADref from the reference voltage generation circuit 58, and the divided voltage information supplied to the comparison voltage generation circuit 60 from the AD converter control circuit 62. A voltage corresponding to ADdiv is generated. For example, in the 10-bit AD converter 52, the divided voltage information ADdiv is given an integer of 0 to 1023, and the comparison voltage VADcmp is represented by the above-described equation (2).

  The voltage comparator 56 receives the comparison voltage VADcmp of the comparison voltage generation circuit 60 and the control voltage VTRM for varying the output voltage. The AD converter control circuit 62 changes the comparison voltage VADcmp from the comparison voltage generation circuit 60 by scanning the divided voltage information ADdiv. Each time the division information ADdiv is changed, the voltage comparator 56 compares the comparison voltage VADcmp with the control voltage VTRM. The AD converter control circuit 62 completes the comparison operation when the voltage value of the control voltage VTRM and the voltage value of the comparison voltage VADcmp become the closest as a result of the comparison operation, and converts the value of the divided voltage information ADdiv to the AD measurement value (digital value) NADmeas. Is output to the arithmetic unit 54.

(Calculation unit)
The arithmetic unit 54 includes a CPU serving as hardware of a digital processor, a memory storing an arithmetic program, and the like. The arithmetic unit 54 includes an AD measurement value integration processing unit 64, an AD measurement value fluctuation response processing unit 66, and setting information generation. The processing unit 68 has a processing function.

(AD measurement value integration processing section)
The AD measurement value integration processing unit 64 generates an AD integration value NADsum which is a value obtained by integrating the AD measurement value NADmeas obtained every time the AD converter 52 performs sampling by a predetermined integration number m, and performs an AD measurement value fluctuation response process. Output to the unit 66. The integration of the AD measurement value NADmeas by the AD measurement value integration processing unit 64 is performed for each sampling cycle TAD of the AD converter 52. Therefore, the update cycle of the AD integrated value NADsum is
(Sampling cycle TAD of AD converter 52) × (integration count m)
Becomes

FIG. 2 is a flowchart showing the calculation processing of the AD measurement value integration processing unit, and the following calculation processing is executed. As shown in FIG. 2, the AD measurement value integration processing unit 64 resets the integration variable S to 0 in step S <b> 1, sets the counter variable C to the integration count m, and sets C = m. Subsequently, proceeding to step S2, when confirming that the AD measured value NADmeas from the AD converter 52 has been updated, proceeding to step S3, the AD measured value NADmeas is integrated into the integrating variable S, and S = S + NADmeas.
Then, the counter variable C is decremented by one to obtain C = C-1.

  Subsequently, the process proceeds to step S4, where it is determined whether or not the cumulative number C has reached 0, and the process from step S2 is repeated until it reaches 0.

  If it is confirmed in step S4 that the integration count C has reached 0, the process proceeds to step S5, where the AD integration value NADsum is updated, and the updated AD integration value NADsum is sent to the AD measurement value variation response processing unit 66 in step S6. Output.

(AD measurement value fluctuation response processing unit)
The AD measured value variation response processing unit 66 compares the AD measured value NADmeas output from the AD converter 52 with the AD integrated value NADsum output from the AD measured value integration processing unit 64, and calculates the AD integrated value NADsum and the AD measured value NADmeas. Is multiplied by the above integration number m, and when the difference is equal to or greater than the variation determination value a, it is detected that the AD measurement value NADmeas has a variation.

When the AD measurement value fluctuation response processing unit 66 detects that there is a fluctuation, (AD measurement value NADmeas) × (integration number m)
Is output as the AD operation value NADcalc, and when it is detected that there is no change, the AD integrated value NADsum is output as it is as the AD operation value NADcalc.

  The AD measured value variation response processing unit 66 compares the AD integrated value NADsum with the AD measured value for each sampling cycle TAD of the AD converter 52, which is a cycle at which the AD measured value NADmeas is updated to a new value, and Since the NADcalc is output to the setting information generation processing, it is possible to respond to the fluctuation of the control voltage VTRM at high speed even if the AD converter 52 performs oversampling (AD measurement value integration processing) for increasing the resolution.

  FIG. 3 is a flowchart showing the calculation processing of the AD measurement value fluctuation response processing unit. As shown in FIG. 3, when confirming that the AD measurement value NADmeas has been updated in step S11, the AD measurement value fluctuation response processing unit 66 proceeds to step S12, in which the AD integration value NADsum and the integration count are added to the AD measurement value NADmeas. The absolute value of the difference from the value multiplied by m is obtained and compared with the variation determination value a. If the absolute value is less than the variation determination value a, the process proceeds to step S13, where it is recognized that there is no variation in the AD measurement value NADmeas. The AD integration value NADsum is substituted for the calculation value NADcalc, and the process proceeds to step S15 to output the AD calculation value NADcalc to the setting information generation processing unit 68.

If it is determined in step S12 that the fluctuation determination value is equal to or more than a, the process proceeds to step S14, where it is recognized that there is a fluctuation in the AD measurement value NADmeas, and the AD operation value NADcalc is calculated as (AD measurement value NADmeas) × (integration count m).
Then, the process proceeds to step S15 to output the AD operation value NADcalc to the setting information generation processing unit 68.

(Setting information generation processing unit)
The setting information generation processing unit 68 generates a control reference value R1 by performing a calculation based on the AD calculation value NADcalc input from the AD measurement value fluctuation response processing unit 66, and controls the control value provided in the power conversion unit 10. Input to the reference voltage generator 28.

  Further, the setting information generation processing unit 68 generates a pulse period control reference value R2 that is a value (n is an integer) obtained by dividing the product of the resolution of the AD converter 52 and the number of integrations m by 2 n, and performs power conversion. It is input to the control reference voltage generator 28 provided in the unit 10.

[Control reference voltage generator]
The control reference voltage generation unit 28 provided in the power conversion unit 10 receives the control reference value R1 and the pulse cycle control reference value R2 from the calculation unit 54, and generates a control reference voltage VoRef. The control reference voltage generator 28 according to the present embodiment includes a reference pulse generator 36 and a smoothing circuit 44.

(Reference pulse generator)
The reference pulse generation unit 36 includes a counter 38, a pulse control unit 40, a duty setting register 41 in which a duty setting register setting value R1 is set by inputting a control reference value R1, and a pulse width control reference value. A pulse cycle setting register 42 is provided in which a pulse cycle setting value R2 is set by inputting R2. The counter 38 outputs a count value NCT by counting the clock signal Vck from the clock generator 34 as shown in FIG. As shown in FIG. 4B, the count value NCT is initially zero, and increases by 1 when the clock signal Vck is counted.

  The pulse control unit 40 receives the count value NCT of the counter 38, the duty setting register setting value R1 of the duty setting register 41, and the pulse cycle setting value R2 of the pulse cycle setting register 42, and sets the count value NCT. As shown in FIG. 4C, the voltage level of the reference pulse Vrp is controlled by the values of the values R1 and R2.

  The voltage level of the reference pulse Vrp is initially at the H level, but at time t1 when the count value NCT increases and coincides with the register setting value R1 for duty setting, the voltage level of the reference pulse Vrp is inverted to the L level. And Further, at time t2 when the count value NCT increases and coincides with the pulse cycle set value R2, the voltage level of the reference pulse Vrp is reset to the H level, and the counter 38 is also reset so that the count value NCT becomes zero.

  By repeating this operation, the reference pulse Vrp has a cycle defined by the cycle of the clock signal Vck and the value of the pulse width control reference value R2, and has a duty cycle defined by the value of the control reference value R1. Is generated, and the reference pulse Vrp is output to the smoothing circuit 44.

  The smoothing circuit 44 outputs the control reference voltage VoRef of the DC voltage by smoothing the input reference pulse Vrp with the resistor 45 and the capacitor 46.

(Pulse cycle control reference value R2)
The setting information generation processing unit 68 provided in the output control unit 12 determines that the resolution of the duty of the reference pulse generation unit 36 is a value obtained by dividing the product of the resolution of the AD converter 52 and the number of integrations m by 2 n. , A pulse cycle control reference value R2 is set.
R2 = (resolution of AD converter × integration number m) / 2 ⁿ (3)

  By setting the pulse period control reference value R2 to this setting, it becomes possible to speed up the operation required for the setting information generation processing unit 68, and this is highly effective when a low-cost digital processor is used.

  Here, if n = 0, then 2n = 1, so that the pulse period control reference value R2 obtained by equation (3) is substantially equal to the maximum value of the AD calculation value NADcalc. Accordingly, the setting information generation processing unit 68 can output a result obtained by performing an operation of adding (or subtracting) the correction value to the AD operation value NADcalc as the pulse cycle control reference value R2. . The correction value here is a value given for correcting an error caused by the AD converter 52 and peripheral circuit components (for example, a resistor or the like), and the digital processor can perform addition and subtraction at high speed.

  When the duty resolution of the reference pulse generation unit 36 may be set low, the pulse period control reference value R2 is reduced by setting n = 1 or more to increase the frequency of the reference pulse Vrp. Thus, the size of the resistor 45 and the capacitor 46 of the smoothing circuit 44 can be reduced.

  In this case, when generating the pulse period control reference value R2, the correction value is added (or subtracted) to a value obtained by dividing the AD operation value NADcalc by 2 n. Digital processors require a great deal of time for general multiplication and division. However, binary arithmetic can be performed by bit shifting of a register, so that it is limited to multiplication and division of 2 n. And can be processed at high speed.

  In the present embodiment, the AD converter 52, the arithmetic unit 54, and the reference pulse generating unit 36 are shown as being built in a low-cost digital processor. I do not care. Further, the power conversion unit 10 generates the control reference voltage VoRef from the control reference value R1 in the control reference voltage generation unit 28 so that the output voltage Vo becomes a voltage proportional to the control reference voltage VoRef. Although a circuit is configured, for example, the switching element 14 is configured to be controlled by a digital processor, and the output voltage Vo is controlled from the control reference value R1, that is, the configuration does not include the control reference voltage generation unit 28. It does not matter.

[Operation of switching power supply unit]
Next, the operation of the switching power supply device shown in FIG. 1 will be described by substituting actual numerical values.

(Operation when control voltage VTRM is constant)
First, a case where the control voltage VTRM has a constant value will be described. It is assumed that 4.0025 volts is applied as the control voltage VTRM applied to the control voltage input terminal 15 of the switching power supply device as in the conventional example.

  It is assumed that the AD converter 52 has a resolution of 10 bits and a sampling period TAD of 100 μsec, and that the reference voltage VADref of the AD converter 52 is 5.120 volts as in the conventional example.

  The AD converter 52 converts the control voltage VTRM, which is an analog value, into an AD measured value NADmeas, which is a digital value, every 100 μsec of the sampling period TAD. As the resolution of the AD converter 52 and the reference voltage VADref are given the same values as in the description of the conventional example, similarly to the conventional example, the AD measurement value NADmeas is 800% with a 50% probability due to quantization fluctuation. Or it becomes 801.

When the number of integrations m is set to m = 64 in the AD measurement value integration processing unit 64, the AD integration value NADsum is a value obtained by integrating the value of 800 or 801 with a probability of 50% only 64 times.
NADsum = 800 × (64/2) + 801 × (64/2) = 51232.
Becomes

Since the number of times of integration m is m = 64, the AD integrated value NADsum can have the same resolution as the measured value of the 13-bit AD converter from Table 1 described above. In addition, the AD measurement value integration processing unit 64
(TAD × m) = (100 μsec × 64 times) = 6400 μsec
The AD integrated value NADsum is output to the AD measured value fluctuation response processing unit 66 in the cycle of.

  In the AD measurement value change response processing unit 66, it is assumed that a = 128 is given as the change determination value a. The AD measurement value variation response processing unit 66 adds the number of integration m = 64 to the AD integration value NADsum input from the AD measurement value integration processing unit 64 and the AD measurement value NADmeas input from the AD converter 52 according to the flowchart of FIG. The difference from the multiplied value is calculated, and the AD calculation value NADcalc is calculated from the result of comparison with the fluctuation determination value a = 128.

Since the AD measurement value NADmeas is 800 or 801, the value obtained by multiplying the AD measurement value NADmeas by the integration number m is:
800 × 64 = 51200 or 801 × 64 = 51264
Becomes

Since the AD integrated value NADsum is 51232, the difference from the value obtained by multiplying the AD measured value NADmeas by the integration number m is
| 51232-51200 | = 32, and
| 51232-51264 = | -32 | = 32
And the difference is 32 in each case.

  Here, when the difference 32 is compared with the fluctuation determination value a = 128, all the differences are equal to or smaller than the fluctuation determination value, and therefore, the AD measured value fluctuation response processing unit 66 calculates the AD integrated value NADsum = 51232 as the AD operation value. It outputs to the setting information generation processing unit 68 as NADcalc. Further, the AD measurement value fluctuation response processing unit 66 outputs the AD operation value NADcalc to the setting information generation processing unit 68 every sampling cycle TAD = 100 μsec of the AD converter 52.

The setting information generation processing unit 68 generates the reference pulse so that the duty resolution of the reference pulse generation unit 36 becomes 65536 which is a value obtained by multiplying the resolution 10 bits (2 ¹⁰ = 1024) of the AD converter 52 by the number of integrations m = 64. The pulse period control reference value R2 is output to the unit 36. Further, the setting information generation processing unit 68 outputs the AD operation value NADcalc = 51232 input from the AD measurement value fluctuation response processing unit 66 to the reference pulse generation unit 36 as the control reference value R1.

The reference pulse generator 36 outputs 5 volts as the H level and 0 volts as the L level. According to the condition given from the setting information generation processing unit 68, that is, the control reference value R1 = 51232 set in the duty setting register 41 and the pulse cycle control reference value R2 = 65536 set in the pulse cycle setting register 42, The pulse generation unit 36
R1 / R2 = 51232/65536 ≒ 0.78174
To the smoothing circuit 44.

The control reference voltage VoRef obtained by smoothing the rectangular wave of the reference pulse Vrp by the smoothing circuit 44 is:
VoRef = 5 × 0.78174 ≒ 3.990 volts.

Here, as in the conventional example, assuming that the switching power supply device capable of outputting the output voltage Vo = 0 to 6.144 volts is controlled by the control reference voltage VoRef = 0 to 5 volts, the output is expressed by equation (4). The voltage Vo is controlled.
Vo = 6.144V / 5V × VoRef (4)
As a result, the output voltage Vo = 4.803 volts is output from the power converter 10.

  In the conventional example, since the output voltage is controlled by the AD measurement value ADmeas of the AD converter having the resolution of 10 bits, Vo = 4.800 volts and Vo = 4.806 volts are output in a like-like distribution by quantization fluctuation. And a large ripple of 6 millivolts has occurred, but in this embodiment, since the output voltage Vo is controlled by the AD operation value ADcalc obtained by the integration processing, a large ripple caused by quantization fluctuation is eliminated, and Vo is eliminated. = 4.803 volts stable output voltage can be obtained.

(Operation when the control voltage VTRM is varied)
Next, a case where the control voltage VTRM is varied will be described. Consider a case where the control voltage VTRM is varied from 4.0025 volts to 4.5 volts. At this time, the AD converter 52 outputs the AD measurement value NADmeas = 900 to the AD measurement value integration processing unit 64 and the AD measurement value fluctuation response processing unit 66 at every sampling cycle TAD = 100 μsec.

  The AD measurement value integration processing unit 64 generates the AD integration value NADsum = 900 × 64 = 57600 by integrating the AD measurement value NADmeas every m = 64 times every 100 μsec. Further, the AD measurement value integration processing unit 64 outputs the AD integration value NADsum to the AD measurement value fluctuation response processing unit 66 every 100 μsec × 64 times = 6400 μsec.

  Here, the information immediately after changing the control voltage VTRM is reflected on the AD integrated value NADsum at least after 6400 μsec. Therefore, during a period of 6400 μsec from immediately after the control voltage VTRM is varied until the AD integrated value NADsum is updated to the new value of 57600, the value of 51232 at the time of the control voltage VTRM = 4.025 volts is AD integrated. The value is output to the AD measured value variation response processing unit 66 as the value NADsum.

  The AD measurement value variation response processing unit 66 calculates a value obtained by multiplying the AD measurement value NADmeas = 900 output from the AD converter 52 by the integration count m = 64 every sampling period TAD = 100 μsec of the AD converter 52, that is, 900 × 64 = The difference between 57600 and the AD integrated value NADsum output from the AD measured value integration processing unit 64 is calculated and compared with the fluctuation determination value a = 128.

Since the AD integrated value NADsum = 51232 after 6400 μsec after varying the control voltage VTRM, the difference is
| 57600-51232 | = 6368
Since the fluctuation determination value a is larger than 128, the AD measured value fluctuation response processing unit 66 detects that the fluctuation is equal to or larger than the fluctuation determination value, and sets the AD operation value NADcalc to the AD integrated value NADmeas × m = 57600. This is output to the setting information generation processing unit 68.

  Although the value immediately after the control voltage VTRM is changed is reflected in the AD integrated value NADsum, there is a response delay of 6400 μsec. However, the AD calculated value NADcalc Since the value can follow the control voltage VTRM, the variable information of the control voltage VTRM can be reflected on the output voltage Vo of the switching power supply in a short time.

(Advantages of the first embodiment)
In the embodiment of the switching power supply device shown in FIG. 1, even when the low-resolution AD converter 52 is used, generation of output ripple due to quantization fluctuation is suppressed by oversampling (AD measured value integration processing), and oversampling is performed. The response delay of the output voltage Vo with respect to the variation of the control voltage VTRM caused by the above is solved by simultaneously performing the processing of the AD measurement value integration processing unit 64 and the AD measurement value fluctuation response processing unit 66. This makes it possible to achieve both precision control and high-speed control.

  In addition, the integration result obtained by oversampling can be handled as a value for setting the output voltage Vo directly or by simply performing a simple operation such as adding or subtracting a correction value or a bit shift of a register. Therefore, even a low-cost digital processor can control the output voltage with high resolution, eliminating the need for an LC filter circuit composed of large coils and capacitors for ripple reduction and a high-resolution AD converter, and switching. The power supply device can be reduced in size and cost.

[Embodiment of Switching Device According to Second Invention]
(Circuit configuration and function)
FIG. 5 is a circuit block diagram showing an embodiment of the switching power supply device for controlling the output current, wherein the output current Io of the switching power supply device can be set by the control voltage ITRM.

  As shown in FIG. 5, in the present embodiment, the control reference voltage generator 28 outputs the control reference voltage IoRef, and the feedback control circuit 26 of the power converter 10 outputs an output such as a current detection resistor. The output current detection signal Isens detected by the current detector 70 and the control reference voltage IoRef are input. Other configurations and functions are the same as those in the embodiment of FIG. 1, and therefore, are denoted by the same reference numerals and description thereof is omitted. Thus, the output current Io can be controlled by the control voltage ITRM.

(Advantages of this embodiment)
According to the switching power supply of the present embodiment, even when the low-resolution AD converter 52 is used, the generation of the oscillation of the output current Io due to the quantization fluctuation is suppressed by the oversampling (AD measurement value integration processing). The response delay of the output current Io with respect to the variation of the control voltage ITRM due to the sampling is solved by simultaneously performing the processes of the AD measurement value integration processing unit 64 and the AD measurement value fluctuation response processing unit 66. High-precision control and high-speed control can both be achieved.

  Further, since the integration result obtained by oversampling can be handled directly or as a value for setting the output current Io by a simple operation such as addition or subtraction of a correction value or bit shift of a register, Even a low-cost digital processor can control the output current Io with high resolution, eliminating the need for an LC filter circuit composed of large coils and capacitors for ripple reduction and a high-resolution AD converter. It is possible to reduce the size and cost.

[Modification of the present invention]
The present invention includes appropriate modifications without impairing the objects and advantages thereof, and is not limited by the numerical values shown in the above embodiments.

10: Power conversion unit 12: Output control unit 14: Switching element 15: Control voltage input terminal 16: Diode 18: Inductors 20, 46: Capacitors 22, 24, 45: Resistor 26: Feedback control circuit 28: Control reference voltage generation Unit 30: PWM control circuit 32: Error amplifier 34: Clock generation unit 36: Reference pulse generation unit 38: Counter 40: Pulse control unit 41: Duty setting register 42: Pulse cycle setting register 44: Smoothing circuit 48: Triangular wave oscillator 50: PWM comparator 52: AD converter 54: Operation unit 56: Voltage comparator 58: Reference voltage generation circuit 60: Comparison voltage generation circuit 62: AD converter control circuit 64: AD measurement value integration processing unit 66: AD measurement value fluctuation response processing Unit 68: setting information generation processing unit 70: output power Detector

Claims (3)

A switching power supply device including a power conversion unit and an output control unit,
The power converter includes a switching element and an output smoothing circuit, converts an input voltage into an intermittent voltage by turning on and off the switching element, and converts the intermittent voltage into a DC voltage by the output smoothing circuit to generate an output voltage. A circuit, wherein the output voltage is controlled by a control reference value provided from the output control unit,
The output control unit, a control voltage for controlling the output voltage of the power conversion unit is input, a circuit that outputs a control reference value for setting the output voltage to the power conversion unit, An AD converter, and an arithmetic unit having an AD measurement value integration processing unit, an AD measurement value fluctuation response processing unit, and a setting information generation processing unit,
The AD converter receives the control voltage, generates an AD measurement value that is a digital value from the input control voltage, and outputs the AD measurement value to the arithmetic unit.
The AD measurement value integration processing unit generates an AD integration value that is a value obtained by integrating the AD measurement value a predetermined number of times, and outputs the AD integration value to the AD measurement value variation response processing unit.
The AD measurement value variation response processing unit obtains a difference between a value obtained by multiplying the AD measurement value by the integration count and the AD integration value. If the difference is equal to or greater than a predetermined variation determination value, the AD calculation value Is set to a value obtained by multiplying the AD measurement value by the integration count and output to the setting information generation processing unit. If the difference is less than or less than a predetermined fluctuation determination value, the AD calculation value is added to the AD integration value. Set a value and output it to the setting information generation processing unit,
The setting information generation processing unit generates the control reference value based on the AD operation value and outputs the control reference value to the power conversion unit.
A switching power supply device characterized by the above-mentioned.
A switching power supply device including a power conversion unit and an output control unit,
The power conversion unit includes a switching element and an output smoothing circuit, converts an input voltage into an intermittent voltage by turning on and off the switching element, converts the intermittent voltage into a DC voltage by the output smoothing circuit, and outputs an output voltage and an output current. Wherein the output current is controlled by a control reference value given from the output control unit,
The output control unit is a circuit that receives a control voltage for controlling the output current of the power conversion unit and outputs a control reference value for setting the output current to the power conversion unit, An AD converter, and an arithmetic unit having an AD measurement value integration processing unit, an AD measurement value fluctuation response processing unit, and a setting information generation processing unit,
The AD converter receives the control voltage, generates an AD measurement value that is a digital value from the input control voltage, and outputs the AD measurement value to the arithmetic unit.
The AD measurement value integration processing unit generates an AD integration value that is a value obtained by integrating the AD measurement value a predetermined number of times, and outputs the AD integration value to the AD measurement value variation response processing unit.
The AD measurement value variation response processing unit obtains a difference between a value obtained by multiplying the AD measurement value by the integration count and the AD integration value. If the difference is equal to or greater than a predetermined variation determination value, the AD calculation value is calculated. Is set to a value obtained by multiplying the AD measurement value by the integration count and output to the setting information generation processing unit. If the difference is less than or less than a predetermined fluctuation determination value, the AD calculation value is added to the AD integration value. Set a value and output it to the setting information generation processing unit,
The setting information generation processing unit generates the control reference value based on the AD operation value and outputs the control reference value to the power conversion unit.
A switching power supply device characterized by the above-mentioned.
The switching power supply according to claim 1 or 2,
The power conversion unit includes a control reference voltage generation unit to which the control reference value is input from the output control unit,
The control reference voltage generator includes a reference pulse generator and a smoothing circuit,
The reference pulse generation unit includes a counter to which a clock signal is input, a pulse cycle setting register, a duty setting register, and a pulse control unit that outputs a reference pulse to the smoothing circuit.
The counter outputs a count value obtained by counting the clock signal to the pulse control unit,
The pulse control unit resets the count value of the counter when the count value matches the set value of the pulse cycle setting register, sets a reference pulse to a predetermined voltage level at the same time, and sets the count value to the duty cycle. Inverts the voltage level of the reference pulse when it matches the set value of the setting register, and outputs a square wave reference pulse having a predetermined cycle, duty and duty resolution,
The pulse cycle setting register has a pulse cycle control reference in which the resolution of the duty of the reference pulse is a value (n is an integer) obtained by dividing the product of the resolution of the AD converter and the number of times of integration m by 2 n. Value is set,
In the duty setting register, a control reference value output from the output control unit is set,
The switching power supply device, wherein the smoothing circuit generates a control reference voltage by smoothing the reference pulse output from the pulse control unit.

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