JP6630449B2 - 他のキャッシュでのエントリの可用性に基づくキャッシュエントリの置換 - Google Patents

他のキャッシュでのエントリの可用性に基づくキャッシュエントリの置換 Download PDF

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JP6630449B2
JP6630449B2 JP2018555745A JP2018555745A JP6630449B2 JP 6630449 B2 JP6630449 B2 JP 6630449B2 JP 2018555745 A JP2018555745 A JP 2018555745A JP 2018555745 A JP2018555745 A JP 2018555745A JP 6630449 B2 JP6630449 B2 JP 6630449B2
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cache
entry
data
controller
response
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JP2019517689A5 (enExample
JP2019517689A (ja
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ジェームス モイヤー ポール
ジェームス モイヤー ポール
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Human Computer Interaction (AREA)
JP2018555745A 2016-06-13 2016-09-14 他のキャッシュでのエントリの可用性に基づくキャッシュエントリの置換 Active JP6630449B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/180,807 US10152425B2 (en) 2016-06-13 2016-06-13 Cache entry replacement based on availability of entries at another cache
US15/180,807 2016-06-13
PCT/US2016/051661 WO2017218022A1 (en) 2016-06-13 2016-09-14 Cache entry replacement based on availability of entries at another cache

Publications (3)

Publication Number Publication Date
JP2019517689A JP2019517689A (ja) 2019-06-24
JP2019517689A5 JP2019517689A5 (enExample) 2019-10-10
JP6630449B2 true JP6630449B2 (ja) 2020-01-15

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JP2018555745A Active JP6630449B2 (ja) 2016-06-13 2016-09-14 他のキャッシュでのエントリの可用性に基づくキャッシュエントリの置換

Country Status (6)

Country Link
US (1) US10152425B2 (enExample)
EP (1) EP3433743B1 (enExample)
JP (1) JP6630449B2 (enExample)
KR (1) KR102453192B1 (enExample)
CN (1) CN109154912B (enExample)
WO (1) WO2017218022A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10268558B2 (en) * 2017-01-13 2019-04-23 Microsoft Technology Licensing, Llc Efficient breakpoint detection via caches
US10528519B2 (en) * 2017-05-02 2020-01-07 Mellanox Technologies Ltd. Computing in parallel processing environments
US10534710B2 (en) * 2018-06-22 2020-01-14 Intel Corporation Non-volatile memory aware caching policies
US10740220B2 (en) 2018-06-27 2020-08-11 Microsoft Technology Licensing, Llc Cache-based trace replay breakpoints using reserved tag field bits
US10970222B2 (en) * 2019-02-28 2021-04-06 Micron Technology, Inc. Eviction of a cache line based on a modification of a sector of the cache line
US12111832B2 (en) * 2021-05-21 2024-10-08 Oracle International Corporation Techniques for a deterministic distributed cache to accelerate SQL queries
US11822480B2 (en) 2021-08-31 2023-11-21 Apple Inc. Criticality-informed caching policies
US11886342B2 (en) * 2021-12-01 2024-01-30 International Business Machines Corporation Augmenting cache replacement operations
US12019542B2 (en) * 2022-08-08 2024-06-25 Google Llc High performance cache eviction

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69629331T2 (de) 1995-06-02 2004-02-12 Sun Microsystems, Inc., Mountain View System und Verfahren zur Bereitstellung einer flexiblen Speicherhierarchie
US6725337B1 (en) * 2001-05-16 2004-04-20 Advanced Micro Devices, Inc. Method and system for speculatively invalidating lines in a cache
US20070186045A1 (en) * 2004-07-23 2007-08-09 Shannon Christopher J Cache eviction technique for inclusive cache systems
US8214601B2 (en) * 2004-07-30 2012-07-03 Hewlett-Packard Development Company, L.P. Purging without write-back of cache lines containing spent data
US20060155934A1 (en) * 2005-01-11 2006-07-13 Ramakrishnan Rajamony System and method for reducing unnecessary cache operations
US20070094450A1 (en) * 2005-10-26 2007-04-26 International Business Machines Corporation Multi-level cache architecture having a selective victim cache
US7774549B2 (en) * 2006-10-11 2010-08-10 Mips Technologies, Inc. Horizontally-shared cache victims in multiple core processors
US9058272B1 (en) * 2008-04-25 2015-06-16 Marvell International Ltd. Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addresses
US8782348B2 (en) 2008-09-09 2014-07-15 Via Technologies, Inc. Microprocessor cache line evict array
US8949540B2 (en) 2009-03-11 2015-02-03 International Business Machines Corporation Lateral castout (LCO) of victim cache line in data-invalid state
US8285936B2 (en) 2009-10-20 2012-10-09 The Regents Of The University Of Michigan Cache memory with power saving state
US8667222B2 (en) * 2011-04-01 2014-03-04 Intel Corporation Bypass and insertion algorithms for exclusive last-level caches
US9003126B2 (en) * 2012-09-25 2015-04-07 Intel Corporation Apparatus, system and method for adaptive cache replacement in a non-volatile main memory system
US9176879B2 (en) 2013-07-19 2015-11-03 Apple Inc. Least recently used mechanism for cache line eviction from a cache memory
US20160055100A1 (en) * 2014-08-19 2016-02-25 Advanced Micro Devices, Inc. System and method for reverse inclusion in multilevel cache hierarchy
US9990289B2 (en) 2014-09-19 2018-06-05 Advanced Micro Devices, Inc. System and method for repurposing dead cache blocks
US9836399B2 (en) * 2015-03-27 2017-12-05 Intel Corporation Mechanism to avoid hot-L1/cold-L2 events in an inclusive L2 cache using L1 presence bits for victim selection bias

Also Published As

Publication number Publication date
WO2017218022A1 (en) 2017-12-21
US10152425B2 (en) 2018-12-11
CN109154912A (zh) 2019-01-04
US20170357446A1 (en) 2017-12-14
EP3433743A4 (en) 2019-11-06
EP3433743A1 (en) 2019-01-30
KR20190008269A (ko) 2019-01-23
EP3433743B1 (en) 2023-02-15
KR102453192B1 (ko) 2022-10-11
CN109154912B (zh) 2024-01-12
JP2019517689A (ja) 2019-06-24

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