JP6618783B2 - Packet multiplex transmission apparatus, packet multiplex transmission method and system - Google Patents

Description

  The present invention relates to a packet multiplex transmission apparatus, a packet multiplex transmission method, and a system, and more particularly to a technique for packetizing and multiplexing video signals and other signals.

  As a technique for non-compressed multiplex transmission of a plurality of signals, for example, a plurality of video signals conforming to HD-SDI (High Density Serial Digital Interface) and SD-SDI (Standard Density Serial Digital Interface), for example, disclosed in Patent Document 1 There is one that uses technology to packetize and multiplex each video signal. This method (hereinafter referred to as a packet multiplex transmission method) is simpler and smaller in size than a method using wavelength division multiplexing (WDM) in which optical signals of different wavelengths are simultaneously mounted. There are advantages. Compared to the method of packet multiplexing and transmission after synchronous synchronization processing is performed by the frame synchronizer function that removes the sync signal for each video signal and re-adds the common clock, the video frame is skipped or the same There is no inconvenience that frames overlap.

  On the other hand, the situation where a device that performs uncompressed multiplex transmission of a plurality of video signals is desired includes a case where a relay is performed from a music concert venue or a sports stadium such as baseball or soccer. When the packet multiplex transmission method is applied to such a situation, a plurality of video devices (such as a TV camera) operating in various places are connected to the transmission device, and the transmission device packet-multiplexes a plurality of video signals without compression. The signal is transmitted to a receiving device such as a relay car outside the field via one signal line (optical fiber cable). On the receiving side, a series of transmitted video signals can be demultiplexed, and a plurality of video signals can be individually displayed or recorded (recorded) on a video recording device. When relaying or the like using a plurality of cameras, at least one set of video signals that are desired to be switched or combined and displayed on one screen may be included. In that case, in general, a set of video devices that output the set of video signals operate in synchronization with each other using an external synchronization signal called a so-called GenLock.

  However, in the case of the packet multiplexing method, since the multiplexing is performed sequentially from the video signal that has been packetized, the waiting time (transmission delay time) until the transmission of the video signal may be indefinite. When video signals are simply displayed individually or recorded on a video recording device on the receiving side, the video signals output from video devices that are not synchronized with each other by an external synchronization signal (hereinafter externally synchronized) Transmission delay time is indefinite on the transmission side, not only for video signals that are synchronized with each other by an external synchronization signal (hereinafter also referred to as externally synchronized video signals). There will be no problem. However, if it is assumed that a set of externally synchronized video signals is switched or combined, if the transmission delay time is indefinite for each video signal, there is a problem that the video synchronization phase on the receiving side is not aligned. . In other words, when connected to a device called a “switcher” that switches and synthesizes multiple video signals used in the field of broadcasting, image misalignment or video disturbance occurs. There is a problem to do.

  As a means for solving this problem, it is conceivable to manage the display time of the video having the same time information on both the transmission side and the reception side. Therefore, the absolute delay amount tends to increase. Although there is no problem with compressed video and storage video based on MPEG, which originally has a large delay, an increase in the absolute delay amount is not preferable for a real-time video transmission apparatus that transmits uncompressed video.

JP 2004-200767 A

  An object of the present invention is to realize a low delay function and a fixed delay function that can keep fluctuations in the transmission delay time of an externally synchronized video signal within a range where there is no problem in operation.

  Another object of the present invention is to enable packet multiplex transmission in which not only externally synchronized video signals but also video signals not externally synchronized and other types of data are mixed.

  Another object of the present invention is to make it possible to select, as desired, which one of priority is given to the low delay and fixed delay function and the improvement of transmission efficiency.

Therefore, in the first embodiment of the present invention, a packet multiplexing transmission apparatus that packetizes and multiplexes a plurality of signals and transmits each of at least one set of signals included in the plurality of signals. A packet generation unit that shifts and fixes the generation cycle and packetizes in order, and a set of packets corresponding to the set of signals generated by the packet generation unit is multiplexed in a fixed order, and And a multiplexing unit that continuously transmits the transmission delay time to the transmission line, and the set of signals are synchronized with each other by an external synchronization signal and connected from the multiplexing unit via the transmission line is a set of signals is a set of the video signal to be switched or combined and displayed at the receiver of the receiving device that is, the packet generating means provided corresponding to said plurality of signals A plurality of packet generators, and each of the plurality of packet generators indicates whether or not the signal is included in the set of signals and, if included, the order of packetization. When the information can be set, each of the plurality of packet generation units performs packetization of the signal according to the set information when the information indicating the order is included, and the multiplexing unit, The set of packets each having a fixed transmission delay time is transmitted at a constant period, and a packet not having the fixed transmission delay time is a packet of a signal other than the set of signals. There is provided a packet multiplex transmission apparatus that allows transmission to the transmission path without overlapping a transmission period of a set of packets.

Further, according to the second aspect of the present invention, there is provided a packet multiplex transmission method for packetizing and multiplexing a plurality of signals, and transmitting each of at least one set of signals included in the plurality of signals. A packet generation step that shifts and fixes the generation cycle and packetizes in sequence, and a set of packets corresponding to the set of signals generated by the packet generation step is multiplexed in a fixed order by the multiplexing unit. And a multiplexing step in which each transmission delay time is fixed and continuously transmitted, and the set of signals are synchronized with each other by an external synchronization signal and connected from the multiplexing unit via a transmission path. is a set of signals is a set of the video signal to be switched or combined and displayed at the receiver of the reception device, wherein the packet generation step, corresponding to said plurality of signals A plurality of generated packet generators, and each of the plurality of packet generators indicates whether the signal is included in the set of signals and, if included, the order of packetization. When the information can be set, and each of the plurality of packet generation units includes the information indicating the order in the set information, the packetization of the set of signals is performed in accordance with the information, and the multiplexing is performed. In the converting step, the set of packets each having a fixed transmission delay time are transmitted at a constant period, and the transmission delay time is a packet of a signal other than the set of signals. There is provided a packet multiplex transmission method for transmitting a packet not to be transmitted without overlapping a transmission period of the set of packets.

  Furthermore, according to a third aspect of the present invention, there is provided a packet multiplex transmission system comprising the packet multiplex transmission apparatus and a reception apparatus that restores the plurality of signals from the packets transmitted from the multiplexing unit. .

  According to the present invention, at least one set of signals included in a plurality of signals is packetized in order by shifting and fixing the generation cycle, and a set of signals corresponding to the set of signals. The packets are multiplexed in a fixed order, and each transmission delay time is fixed and transmitted continuously. At this time, the set of packets each having a fixed transmission delay time is transmitted at a constant period, and packets of signals other than the set of signals that are not fixed to the transmission delay time It is transmitted without overlapping the packet transmission period. Accordingly, it is possible to realize a low delay function and a fixed delay function that can keep fluctuations in transmission delay time of a set of video signals and the like that are externally synchronized within a range in which there is no problem in operation. Further, not only video signals that are externally synchronized, but also video signals that are not externally synchronized, and data in other formats can be mixed appropriately. Furthermore, it is possible to select, as desired, which one of the low delay and fixed delay functions and the improvement of transmission efficiency is prioritized for packet multiplexing.

It is a block diagram which shows the structural example of the video transmission system to which the packet multiplexing transmission apparatus which concerns on one Embodiment of this invention is applied. 2 is a timing chart for explaining the operation of packet multiplexing processing of the packet multiplexing transmission apparatus in FIG. It is a block diagram which shows the structural example of the video transmission system to which the packet multiplexing transmission apparatus which concerns on a comparative example is applied. 4 is a timing chart for explaining the operation of packet multiplexing processing of the packet multiplexing transmission apparatus in FIG. 3. FIG. 4 is an explanatory diagram for explaining a problem that a shift between two video signals to be combined occurs when the configuration of FIG. 3 is adopted. It is a block diagram which shows the structural example of the packet generation part of the packet multiplex transmission apparatus which concerns on one Embodiment of this invention. It is a block diagram which shows the structural example of the packet generation circuit arrange | positioned at the packet generation part of FIG. (A) is a block diagram which shows the structural example of the data conversion processing part arrange | positioned at the packet generation circuit of FIG. 7, (b) is a block diagram which shows the structural example of the data conversion processing part which concerns on a comparative example. It is a timing chart for demonstrating operation | movement of the data conversion process part shown to Fig.8 (a). It is a timing chart for demonstrating operation | movement of the data conversion process part shown in FIG.8 (b). It is a timing chart for demonstrating that transmission delay time is reduced by the data conversion process part shown to Fig.8 (a). It is a timing chart for demonstrating the operation | movement at the time of the stuffing process by the packet generation part which concerns on one Embodiment of this invention. (A) And (b) is a timing chart for demonstrating the multiplexing process of the packet by the selector which concerns on one Embodiment of this invention. It is a block diagram which shows the structural example of the selector which concerns on one Embodiment of this invention. (A) And (b) is a timing chart for demonstrating the aspect with which a delay fixed packet and a free packet are multiplexed by the selector which concerns on one Embodiment of this invention. It is a timing chart for explaining a countermeasure when a free packet does not fit in a free slot.

Hereinafter, the present invention will be described in detail with reference to the drawings.
(Definition)
In the following description, “video signal” is compatible with UART (Universal Asynchronous Receiver Transmitter) in addition to uncompressed video signals conforming to SDI standards such as HD-SDI signal, SD-SDI signal, 3G-SDI signal, etc. And compressed video signals such as data conforming to LAN standards such as Ethernet (registered trademark). “General data” refers to data having a format different from that of a video signal, such as an audio signal, while the term “signal” is a generic term for video signals and general data.

  FIG. 1 shows a configuration example of a video transmission system according to an embodiment of a packet multiplex transmission system of the present invention. A packet multiplex transmission apparatus T on a transmission side and a reception apparatus R on a reception side are connected via a transmission line F. Connected.

  The packet multiplex transmission apparatus T deletes the control unit 1 and n (n is an integer of 2 or more) signals S-1 to Sn (hereinafter, if one of them is not specified, the branch number is deleted. This is referred to as “signal S.” Packet generators 11-1 to 11-n provided corresponding to other signals (the same applies to other signals) (hereinafter, if one of them is not specified, the branch number is deleted, and “ It is referred to as “packet generation unit 11”. The same applies to other components), packet memories 21-1 to 21-n, and selector unit 30. The packet generation units 11-1 to 11-n are based on packet generation control data PCC-1 to PCC-n set by the control unit 1 based on signals S-1 to Sn input from cameras and other devices. Packetize. The packetized data (hereinafter referred to as packet data) PKT-1 to PKT-n is written into the packet memories 21-1 to 21-n based on the write control signals WC-1 to WC-n. Each of the packet memories 21-1 to 21-n notifies the control unit 1 of its own state by status signals ST-1 to ST-n, while reading control signals RC-1 to RC supplied from the control unit 1 are provided. Based on −n, packet data PKTM-1 to PKTM-n are output to the selector unit 30. The selector unit 30 multiplexes the packet data PKTM-1 to PKTM-n based on the control signal SC from the control unit 1 and transmits the multiplexed data via a transmission path F that can be a single-core optical fiber cable, for example.

  The receiving device R includes a control unit 51, a selector unit 60, depacket processing units 71-1 to 71-n, and depacket memories 81-1 to 81-n. The control unit 51 controls the selector unit 60 based on packet information included in the transmitted multiplexed data. The selector unit 60 separates the multiplexed packet data PKT-1 to PKT-n and supplies them to the depacket processing units 71-1 to 71-n. The depacket processing units 71-1 to 71-n perform a depacketization process and write in the depacket memories 81-1 to 81-n. Therefore, the signals S1 to Sn are restored by appropriately reading the data written in the depacket memories 81-1 to 81-n.

  Here, it is assumed that the packet multiplex transmission apparatus T is configured to accept inputs of n = 6 signals S-1 to S-6. Of these signals, for example, signals S-1 to S-4 are video signals that conform to HD-SDI and are externally synchronized. Further, the signal S-5 conforms to HD-SDI and is not externally synchronized, and the signal S-6 is another signal (such as an audio signal) having a different format and is not externally synchronized. To do. That is, the externally synchronized signals S-1 to S-4 are a set of video signals that are desired to be switched or combined and displayed in the image receiving device (monitor M; see FIG. 5) of the receiving device R. .

  In this case, the packet generators 11-1 to 11-n (= 11-6) send the signals S-1 to S-6 based on the packet generation control data PCC-1 to PCC-n (= PCC-6). Packetize. At that time, for the video signals S-1 to S-4 that are externally synchronized because it is desired to be switched or synthesized, a packet is generated using a common reference timing pulse (system clock) in the system. Based on the control data PCC-1 to PCC-4, the time when the packet generation units 11-1 to 11-4 start packetization processing and the period from there are set appropriately, the packet length, the packet output order, and By fixing the multiplexing order, it is possible to continuously multiplex while fixing the packet generation interval of the video signals S-1 to S-4. As a result, the generation processing period of the packet data PKT-1 to PKT-4, the order of the multiplex processing, and the transmission delay time can be fixed and reduced. In this sense, a video signal and its set that are externally synchronized because it is desired to be switched or combined and displayed on the receiving side are referred to as “transmission delay time fixed signal” and “transmission delay time fixed signal” below. Referred to as a "group".

  The operation of the packet multiplexing process for the transmission delay time fixed signal group will be described with reference to FIG. 2. First, in the packet generation units 11-1 to 11-4, the generation processing periods of the packets PKT-1 to PKT-4 are shifted from each other. In addition, writing to the packet memories 21-1 to 21-4 is performed. As a result, the output waiting time of the packet memories 21-1 to 21-4 until selection and reading by the selector unit 30 is also fixed, and can be substantially zero. Furthermore, since the multiplex transmission can be realized with the output order of the packets S-1 to S-4 from the selector unit 30 fixed, it is possible to specify the depacket memories 81-1 to 81-4 after the transmission to the receiving device R. The time until the completion of writing the amount of packet data does not vary. In other words, each of the depacket memories 81-1 to 81-4 is always written at a fixed cycle once every four times. As a result, it is not necessary to increase the memory capacity in consideration of the out of order, and the transmission delay time fluctuations of the transmission delay time fixed signals S-1 to S-4 can be within a range that does not cause a problem. Therefore, the transmission delay time fixed signal switching processing and synthesis processing can be performed in a state where the synchronization phases are aligned.

(Description of comparative example)
The packet generators S-5 and S-6 to which signals that are not externally synchronized are input perform packet generation operations individually using the sampling clocks of their own signals, and write them to the packet memories 21-5 and 21-6. I do. However, the frequency of the video clock is generally not exactly the same even within the standardized range. This is because there is a manufacturing variation in the crystal oscillator used for generating the sampling clock, and a frequency variation is also caused by environmental conditions (temperature, etc.). As a result, the transmission delay time becomes indefinite on the transmission side, but this is not a problem when it is not assumed that the video signal switching process or the synthesis process is performed on the reception apparatus side.

  However, as described above, when packetizing and multiplexing a set of video signals that are externally synchronized in order to perform video signal switching processing and synthesis processing on the receiving device side, the transmission delay time is video. If it becomes indefinite for each signal, there arises a problem that the video synchronization phase on the receiving side is not aligned. That is, in order to restore a plurality of video signals S-1 to S-4 multiplexed and transmitted without fixing the transmission delay time, the depacket memories 81-1 to 81-4 on the receiving side need to be restored. It is necessary not to cause an overflow / underflow, and for this purpose, it is conceivable to employ a method of starting reading when a write completion condition for a specific amount of packet data to each depacket memory is satisfied. However, since the time until writing of a specific amount of packet data to each depacket memory is not constant, the read control start time varies. As a result, there is no problem when the video signals are individually displayed or recorded, but the synchronization phases are not aligned, so that when the switching process or the synthesizing process is performed, a video position shift or a video disturbance occurs.

  FIG. 3 shows a configuration example of a video transmission system according to a comparative example using the technique disclosed in Patent Document 1. In this comparative example, the video signals S-1 to S-4 are externally synchronized signals, but the transmission delay time is not fixed.

  In order to deal with such a problem using the configuration shown in FIG. 3, it is possible to adjust the output phase with respect to the external synchronization signal by the signal source of the video signals S-1 to S-4, that is, each camera, to obtain a preferable state. It is. That is, for the purpose of multiplexing in the order of the video signals S-1, S-2, S-3, and S-4, the external synchronization signal such as GENLOCK is adjusted, and the packet as shown at time (i) in FIG. It is possible to obtain generation output, memory output and selector output. However, since such adjustment is performed with respect to the transmission delay time at that time, the effect is not continuous. For example, the adjustment is performed on a certain day and the transmission device, that is, the packet multiplexing transmission device T is used. When the power is turned off at night and the power is turned on when the next day is used, a packet is generated from each of the packet generators 11-1 ′ to 11-4 ′ because the transmission delay time is not fixed. Timing may not match each other. As a result, the packet generation order changes before and after each other, so that an output waiting time of the packet memories 21-1 'to 21-4' is generated, which can vary. For this reason, the output waiting time of the packet memories 21-1 ′ to 21-4 ′ until the selector unit 30 ′ selects and reads out fluctuates, so that the multiplex transmission is performed as shown in the points (ii) and (iii). Will change the order of what can be realized. As a result, after the transmission to the receiving device R, the time until the completion of writing a specific amount of packet data to the depacket memories 81-1 to 81-4 varies.

  Here, as shown in FIG. 5, the same sphere is photographed by two cameras A and B, and the respective video signals SA and SB are packetized and multiplexed by the packet multiplexing transmission device T and demultiplexed by the receiving device R. Further, consider a case in which the video signal of camera A and the video signal of camera B are combined on the screen of video monitor M on the left and right halves via switcher SW. If the adjustment of the cameras A and B is set so that the transmission delay time fluctuation does not become a problem, the right and left shift of the sphere synthesized on the screen of the monitor M does not occur. However, as long as the adjustment is performed based on the transmission delay time at that time, if the transmission delay time changes, the right and left displacement of the sphere on the monitor screen may occur again. Then, for example, even if adjustment settings are made during the preparation of the previous day, the transmission delay time fluctuates when the next day is used, and the effect of the adjustment settings cannot be guaranteed. Can occur.

(Details of packet generator)
In this embodiment, the transmission delay time is fixed to a plurality of signals to be subjected to packet multiplexing regardless of the type (video signal, audio signal, etc.) and format (SDI, UART, etc.) of the signal to be packet multiplexed. Regardless of whether or not a signal group is included, it is possible to cope. Further, whether or not to fix the transmission delay time can be individually performed for each signal. That is, in the present embodiment, flexible packet multiplexing can be performed for a plurality of signals to be transmitted by appropriately performing settings based on the packet generation control data PCC-1 to PCC-n. Details of the configuration applied to the packet multiplexing transmission apparatus T for that purpose will be described below.

  FIG. 6 is a block diagram illustrating a configuration example of the packet generation unit. FIG. 7 is a block diagram illustrating a configuration example of a packet generation circuit disposed in the packet generation unit. 8A is a block diagram showing a configuration example of a data conversion processing unit arranged in the packet generation circuit of FIG. 7, and FIG. 8B is a block diagram showing a configuration example of a data conversion processing unit according to a comparative example. is there. Note that the configurations shown in FIGS. 6 and 7 are employed in any of the packet generation units 11-1 to 11-n.

  In this embodiment, one packet includes a header and a packet body. The header is a head portion of a packet on which information for identifying whether the signal is a transmission delay time fixed signal and the like in addition to the type of signal to be packetized. The packet body is composed of a part for placing a series of valid data corresponding to the signal S and an invalid data part added thereto. Hereinafter, a process of placing valid data and invalid data on the packet body is referred to as a payload generation process, and a process of filling a surplus portion with invalid data is referred to as a stuffing process. In other words, the payload generation processing period includes a valid data generation processing period and a stuffing processing period. The reason for adding invalid data is to make a packet body length having a margin in order to reliably put a series of valid data on the packet body, and to fill the surplus portion generated for that purpose. For a signal that is not a fixed transmission delay time signal, a stuffing process is performed to make up for a fraction of the packet body length when the data of the signal is placed on the packet body. That is, the meaning of the stuffing process differs between the transmission delay time fixed signal and the signal that is not.

  In FIG. 6, a signal VPS for setting various parameters and a reference timing pulse RTP are input from the control unit 1 to the packet generation control pulse generation circuit 100. The various parameters include a parameter that defines a payload processing period to be performed on the transmission delay time fixed signal. Specifically, in synchronization with the reference timing pulse RTP supplied from the control unit 1, a control pulse CP instructing the start of payload generation processing is generated together with a timeout parameter TOP described later, which is a condition for defining the payload generation processing period. To do. The video data included in the signal S is written into the FIFO memory 140 for clock conversion at a timing synchronized with the video clock of the video equipment itself such as a camera. On the other hand, the data read signal R synchronized with the system clock is supplied from the packet generation circuit 120 to the FIFO memory 140, whereby the video data D is read and transferred to the packet generation circuit 120.

  FIG. 7 shows a configuration example of the packet generation circuit 120. The packet generation control pulse CP from the packet generation control pulse generation circuit 100, the data D read from the FIFO memory 140, the additional information data from the control unit 1, and the data amount Packet generation control data PCC including a parameter DAP, a timeout parameter TOP, and other various parameters is input. The packet generation circuit 120 includes an additional information generation unit 121, a header generation unit 123, a data conversion processing unit 130, and an assembly processing unit 127.

  The additional information generation unit 121 generates additional information based on the additional information data, and supplies the additional information to the header generation unit 123 to generate a packet header. The additional information indicates whether or not the signal to be packetized is a fixed transmission delay time signal, and if so, the output and multiplexing order of the generated packet between the fixed transmission delay time signals. Data such as identifiers. In this embodiment, if the signal is a fixed transmission delay time, a natural number of “1” or more is set in the header corresponding to the order, and is set to “0” if the signal is not a fixed transmission delay time. That is, in the example of FIG. 1, numerical values “1” to “4” are assigned to the signals S-1 to S-4, while all of the signals S-5 and S-6 are assigned. “0” is assigned. The header is combined with the head of the packet body generated by the data conversion processing unit 130 described below by the assembly processing unit 127, and the packet is completed by the combination and output to the packet memory 21 at the next stage. The data conversion processing unit 130 reads the data from the FIFO type memory 140 by supplying the data read control signal R to the FIFO type memory 140 in synchronization with the system clock during the payload generation processing period.

  FIG. 8A shows a configuration example of the main part of the data conversion processing unit 130, which includes a timeout condition calculation unit 131, a data amount calculation unit 133, an OR circuit 135, and a payload generation processing unit 137. The timeout condition calculation unit 131 includes a payload generation processing start point indicated by the packet generation control pulse CP output from the packet generation control pulse generation circuit 100 and a payload generation processing period from the timeout parameter TOP supplied from the control unit 1. Is calculated based on the timeout parameter TOP that defines the transmission delay time signal, and a timeout condition indicating the point in time when the valid data generation processing for the transmission delay time fixed signal is completed is calculated, and the timeout signal TO is output. The data amount calculation unit 133 calculates the data amount read from the FIFO type memory 140 and outputs a signal DA indicating that the data amount specified based on the data amount parameter supplied from the control unit 1 has been reached. These signals are input to the OR circuit 135, and the valid data generation processing is terminated by the OR output. That is, for the transmission delay time fixed signal, even if the data amount does not reach the value indicated by the data amount parameter DAP, the payload generation processing unit 137 aborts the valid data generation processing if the timeout condition is satisfied, Stuff the surplus of the specified payload.

  As described above, in the present embodiment, packetization with respect to a fixed transmission delay time signal is not performed depending on the video clock of each video signal, but the operation of each packet generator is defined by a common system clock. A fixed individual timeout parameter was set for each signal. As a result, as shown in FIG. 9, for example, for the video signals S-1 and S-2, even if there is a variation in the frequency of the video clock, that is, the video clock frequency f1 of the signal S-1 <the video of the signal S-2. Even at the clock frequency f2, the size of the payload generation processing period and the packet generation cycle are constant without overflowing the FIFO memory 140.

  On the other hand, as shown in the comparative example of FIG. 8B, the data amount calculation unit 133 outputs the signal DA when the maximum payload data that can be stored in the packet does not have the timeout condition calculation unit 131. In the configuration, as shown in FIG. 10, the time when the data input necessary for generating valid data for the video signals S-1 and S-2 is completed does not match due to the variation in the frequency of the video clock of both signals. Then, the packet generation periods become inconsistent and the transmission delay time fluctuates, which causes the problem described with reference to FIGS.

  However, there is no problem even if such an operation is performed on a signal that is not a fixed transmission delay time signal. The configuration of FIG. 8A according to the present embodiment is characterized in that it can be shared regardless of whether it is a transmission delay time fixed signal. That is, if the packet generation control pulse CP and the timeout parameter TOP are not supplied, the timeout condition calculation unit does not output the timeout signal TO, and only the signal DA from the data amount calculation unit 133 is valid for the payload generation processing unit 137. Because it becomes.

  Further, according to the present embodiment, as shown in FIG. 11, the packet generation control pulse CP has an appropriate phase relationship for each transmission delay time fixed signal (for example, each of the video signals S-1 and S-2). As a result, it is possible to easily shift the output phase of the packet main body PKTB and the final packet PKT in FIG. 7 in terms of time, and as a result, both fixing and reducing the transmission delay time can be realized simultaneously.

  In the present embodiment, the timeout condition is calculated based on the payload generation processing start point instructed from the packet generation control pulse generation circuit 100 and the timeout parameter TOP that defines the payload generation processing period supplied from the control unit 1. I tried to do it. However, the time-out condition may be determined by directly instructing the start point and end point of the payload generation process from the control unit 1.

(Example of how to determine an appropriate timeout value)
As described above, the timeout parameter defines the period from the start of the payload generation process specified by the packet generation control pulse CP, the valid data generation process period is cut off by the time condition, and the remaining payload portion is stuffed. Parameter value for Therefore, it is strongly desirable that the timeout parameter is appropriately determined so that a necessary and sufficient stuffing generation processing period is ensured. Therefore, the present inventor has paid attention to the following conditions. That is,
・ Condition 1: Even if there is a variation in the video clock frequency of each transmission delay time fixed signal, valid data can be sequentially loaded on the payload without causing overflow of the FIFO memory 140, and Condition 2: Video clock The stuffing process that increases or decreases due to frequency variation is completed before the arrival of the next packet generation control pulse CP;
It is. Then, the video data amount at the maximum value of the video clock frequency of the transmission delay time fixed signal corresponds to the condition 1, and the stuff processing time at the minimum value of the video clock frequency fluctuation of the transmission delay time fixed signal corresponds to the condition 2.

Here, in order to satisfy the condition 1, the amount of video data per second (hereinafter referred to as the bit rate) at the maximum value of the video clock frequency of the transmission delay time fixed signal is Bin_max, and payload generation processing up to the time-out point If the possible bit rate is Bout,
Bout> Bin_max (Formula 1)
is required.

Further, in order to satisfy the condition 2, if the period Tcp of the packet generation control pulse, the time-out point is Tto, and the stuffing processing time is Ts_max,
Tcp> Tto + Ts_max (Formula 2)
Is required.

  Therefore, since a value that satisfies both Expression 1 and Expression 2 is an appropriate timeout value, the timeout parameter may be set based on this value.

  By using the timeout parameter appropriately set as described above, the amount of data in the FIFO memory temporarily increases even when there is a stuffing processing period in which valid data generation is stopped as shown in FIG. Since this is processed at the time of the next generation of valid data, the data of the signal S can be transmitted without being lost.

(Enable / Disable of fixed transmission delay)
As is apparent from the above description, in the present embodiment, “0” is set for a signal that is not a fixed transmission delay time signal, and a numerical value “1 to n” is set for a fixed transmission delay time signal. By setting and setting the payload generation processing period, the transmission delay time can be individually set for each signal, including whether or not the signal is fixed. This is because the packet multiplexing transmission apparatus according to the present embodiment does not depend on the type of signal (video signal, audio signal, etc.) and format (SDI, UART, etc.) to be transmitted, and a plurality of packets to be packet multiplexed. Regardless of whether the transmission delay time fixed signal group is included in these signals, it means that they have a configuration that can be shared by both. That is, even if the video signal is externally synchronized, if switching or combining is not required, or if priority is given to transmission efficiency, “0” is set in the additional information, and payload generation is performed. By appropriately setting the processing period, the transmission delay time fixing function can be turned off. Further, by performing the above setting not only for video signals but also for general data, it is possible to set on / off of the transmission delay time fixing function.

  These setting processes can be performed using an application program that runs on a personal computer PC connected to the control unit 1 as shown in FIG. For example, the processing first recognizes the connection state and signal type of the device that generates the signal S via the status signal ST of the packet memory, and accepts input of content set by the user for each signal, The setting content may be written to the packet generator 11 via the packet generation control data PCC. Alternatively, when the packet multiplex transmission apparatus T or its control unit 1 itself has a console or the like that accepts a user's setting input, these processes may be performed as the operation of the control unit.

(Packet multiplexing and transmission)
As shown in FIG. 7, the header of the packet body generated by the data conversion processing unit 130 during the payload generation period is combined with a header by the assembly processing unit 127, and is output and expanded as a packet to the packet memory 21. . The packet is supplied to the selector 30 according to the read control signals RC1 to RCn from the control unit 1, multiplexed by the selector 30, and sent to the receiving device via the transmission path F. At the time of multiplexing, the selector 30 identifies additional information in the header of the packet, and if it is a packet corresponding to a transmission delay time fixed signal, that is, if it is a packet with a numerical value of “1” or more added, the set order. Are continuously multiplexed and transmitted. On the other hand, if the packet does not correspond to the fixed transmission delay time signal, the transmission can be performed after the transmission of a series of fixed delay packets, for example.

  Hereinafter, detailed examples of packet multiplexing and transmission will be described. In the following description, a packet generated corresponding to a transmission delay time fixed signal is referred to as a delay fixed packet, and signals other than the transmission delay time fixed signal, that is, general data or compression that does not require the transmission delay to be fixed. A packet generated corresponding to video data is referred to as a free packet. As described above, the fixed delay packet has a fixed packet body length and thus has a fixed length, and is generated at a constant cycle in the order according to the identifier described as additional information of the header. . The order of transmission to the multiplexing or receiving apparatus R can also be determined according to this identifier, that is, the generation order of the delay fixed packet can be made equal to the multiplexing or transmission order, but is not limited to this.

  Delay fixed packets are transmitted at regular intervals according to a fixed period pulse that defines the transmission timing to the receiving device R. These equally spaced periods are generated according to the system clock and are hereinafter referred to as a sequence. Here, when the transmission path F corresponds to a transmission rate of 10 Gbps and the delay fixed packet is 1.5 Gbps, the phase of the fixed period pulse for each delay fixed packet is appropriately set as shown in FIG. As shown in FIG. 5B, a maximum of six delay fixed packets FDP1 to FDP6 are allocated to a slot that does not overlap in time (hereinafter referred to as a delay fixed slot) and multiplexed as shown in FIG. 1 Gbps (= 10 Gbps−1.5 Gbps × 6), which is a surplus after multiplexing of fixed delay packets, can be allocated to free packets as free slots.

  FIG. 14 shows a configuration example of a selector that functions as a multiplexing unit that performs such multiplexing and transmission. The selector 30 includes separation units 31-1 to 31-n that separate the fixed delay packet / free packet corresponding to the outputs PKTM-1 to PKTM-n from the packet memories 21-1 to 21-n. This separation is made up of the identifier included in the additional information carried in the header, that is, whether or not the transmission delay time is fixed, and if so, the output and multiplexing between the transmission delay time fixed signals of the generated packets. This is performed based on the data indicating the order. That is, the numerical value described in the identifier can be used to sort the free packet and the fixed delay packet. Delay fixed packet buffers 32D-1 to 32D-n and free packet buffers 32F-1 to 32F-n are connected to the delay fixed packet / free packet separators 31-1 to 31-n, respectively, depending on the identification. Packets are stored in these buffers.

  The fixed-cycle pulse / free slot generation unit 33 generates a fixed-cycle pulse based on the reference timing pulse (system clock) RTP and supplies it to the delayed fixed packet read control unit 35, and a free slot which becomes an excess in one sequence Is generated and supplied to the free packet read control unit 37.

  The delay fixed packet read control unit 35 sends, to the delay fixed packet buffers 32D-1 to 32D-n, control signals including data designating delay fixed slot numbers corresponding to the multiplexing order of the delay fixed packets in synchronization with the fixed period pulses. Supply. The delay fixed packet buffers 32D-1 to 32D-n output the stored delay fixed packets when the designated delay fixed slot number is input. On the other hand, the free packet read control unit 37 instructs the free packet buffers 32F-1 to 32F-n to output free packets based on a signal indicating the free slot period in the order of arrival of free packets. The delay fixed packets and free packets read from the delay fixed packet buffers 32D-1 to 32D-n are sent to the transmission line F via the OR circuit 39. As shown in FIG. 15 (a), in this example, six delay fixed packets are successively read out in the designated multiplexing order, and then free packets are read out so as to be allocated to one sequence of surplus. Therefore, the fixed delay packets FDP1 to FDP6 and the free packet are output in this order from the OR circuit 39 and sent to the transmission line F.

  When a delay fixed packet that is packetized and multiplexed as described above and output from the packet multiplexing transmission device T is received by the receiving device R, the receiving device R needs to reproduce the phase of the reference timing pulse at the time of packetization. In this case, the timing of the delay fixed packet that arrives first can be reproduced as the reference timing pulse.

  In the present embodiment, the fixed delay packets are generated at the timing determined as described above, and the time slot numbers are assigned in the generation order. Therefore, it is not necessary to change the order of the fixed delay packets. Therefore, the fixed delay packet can be transmitted through the same route regardless of the time slot number. Since the selector 30 operates in synchronization with the reference timing pulse (system clock), the fixed delay packet input from the packet memory passes through the fixed delay packet path and is output with almost no waiting. On the other hand, the free packet is sorted from the fixed delay packet and passes through a different route. During the period in which the fixed delay packet is transmitted, the free packet is stored in the buffer in the route and waits for the start of the free slot period. When the free slot period starts, the buffered free packets are sent out as shown in FIG. Free packets are sent in first-come-first-served basis, in order from the earliest arrival to the buffers 37F-1 to 37F-n.

  Thus, in the present embodiment, the selector 30 including the packet multiplexing circuit suitable for multiplexing the delay fixed packet and the free packet is configured. In other words, while managing the multiplexing order of the delay fixed packets, it is multiplexed with the free packets to realize multiplex transmission of various data. However, it is also possible to multiplex only ordinary packets that do not consider the fixed transmission delay time. In this case, for example, “0” may be written in the identifiers of the headers of all packets.

  In this embodiment, the delay fixed packet and the free packet can be multiplexed. If the number of the delay fixed packets is less than the maximum value that can be accommodated in one sequence (less than 6 in the above example), FIG. As shown in (b), it is possible to multiplex more free packets by discriminating the maximum value of the identifier or the fixed delay slot number (4 in the example in the figure) and assigning the free delay fixed slot to the free slot. .

Here, when the free slot period ends, if the free packet protrudes from the free slot period, as shown in FIG. 16, it overlaps in time with the fixed delay slot located in the next sequence, and the packet can be transmitted correctly. It can disappear. In order to prevent this, it is determined whether or not the packet that is currently targeted for multiplexing fits in the remaining period of the free slot period, and transmission is permitted only when the packet does not fit. The free packet read control unit 37 may be configured to perform control for waiting for transmission until the free slot period starts. Also, the longer the packet length of a free packet, the higher the possibility that it will not fit in the remaining free slot period, so that period will be wasted time during which data cannot be placed. In such a case, adjustment may be made such that the free packet is set short or the free packet has a fixed length and the free slot period is an integral multiple of the free packet.
(Other)
The present invention is not limited to the above-described embodiment and the modifications described in various places, and appropriate modifications and changes can be made.

  For example, whether or not it is a transmission delay time fixed signal, and if so, the numerical value written in the identifier to indicate packetization or multiplexing order can be determined as appropriate, and it is not essential to be a numerical value.

  In the above-described embodiment, a free slot is assigned after a series of fixed delay slots in one sequence. However, the number of fixed delay slots is known from the identifier, and therefore the free slot period in one sequence is recognized in advance. Since this is possible, the fixed delay slot group may be allocated after the free slot period.

  Further, in the above-described embodiment, the case where there is one set of transmission delay time fixed signal groups that are desired to be switched and combined together is exemplified, but there may be two or more sets. Also in this case, the multiplexing or transmission order in one sequence can be determined as appropriate. For example, the first delay fixed slot group, the free slot, and the second transmission delay time fixed signal corresponding to the first transmission delay time fixed signal group. The order of multiplexing and transmission can be determined in the order of the second delay fixed slot group corresponding to the group.

DESCRIPTION OF SYMBOLS 1 Control part 11-1 to 11-n, 11-1 'to 11-n' Packet generation part 21-1 to 21-n, 21-1 'to 21-n' Packet memory 30, 30 'Selector 51 Control part 60 selectors 71-1 to 71-n depacket processing unit 81-1 81-n depacket memory 100 packet generation control pulse generation circuit 120 packet generation circuit 121 additional information generation unit 123 header generation unit 127 assembly processing unit 130 data conversion processing unit 131 timeout condition calculation unit 133 data amount calculation unit 135 OR circuit 137 packet body generation processing unit 140 FIFO type memory T packet multiplex transmission device R reception device S-1 to Sn signal PCC-1 to PCC-n packet generation control data PKT-1 to PKT-n packet data PKTM-1 to PKTM-n packet Memory output 31-1 to 31-n Delay fixed packet / free packet separator 32D-1 to 32D-n Delay fixed packet buffer 32F-1 to 32F-n Free packet buffer 33 Fixed period pulse / free slot generator 35 Delay fixed Packet read controller 35 Free packet read controller

Claims (8)

A packet multiplex transmission device for packetizing and multiplexing a plurality of signals,
For at least one set of signals included in the plurality of signals, a packet generation unit that sequentially packetizes each of the signals by shifting and fixing the generation period;
A multiplexing unit that multiplexes a set of packets corresponding to the set of signals generated by the packet generation means in a fixed order, and continuously transmits each packet to a transmission line with a fixed transmission delay time; ,
With
The set of signals is a set of video signals that are synchronized with each other by an external synchronization signal and are switched or combined and displayed in a receiver of a receiver connected via a transmission line from the multiplexing unit. Signal,
The packet generation means includes a plurality of packet generation units provided corresponding to the plurality of signals, and each of the plurality of packet generation units includes whether the signal is included in the set of signals. And if it is included, information indicating the order of packetization can be set, and each of the plurality of packet generators can include information indicating the order in the set information. And packetizing the signal according to
The multiplexing unit is configured to transmit the set of packets each having a fixed transmission delay time at a constant period, and to transmit the set of packets that are packets of signals other than the set of signals. A packet multiplex transmission apparatus characterized in that a packet that is not fixed is transmitted to the transmission line without overlapping a transmission period of the set of packets.   The fixed period is determined in accordance with the transmission rate of the transmission path, and the multiplexing unit is configured to transmit the transmission delay time in a surplus period in which the set of packets is continuously transmitted in the period. The packet multiplex transmission apparatus according to claim 1, wherein the packet multiplex transmission apparatus is controlled so that a packet whose packet is not fixed is transmitted.   The multiplexing unit is configured to separate a packet whose transmission delay time is fixed from a packet whose transmission delay time is not fixed, and the separated packet whose transmission delay time is fixed and a packet which is not fixed 2. A plurality of buffers that are individually stored, and a control unit that controls reading from the plurality of buffers based on whether or not the transmission delay time is fixed in the transmission. 3. The packet multiplex transmission apparatus according to 2.   The packet multiplexing transmission apparatus according to claim 1, wherein the multiplexing unit also performs multiplexing according to the information indicating the order. The set of packets have equal packet lengths provided with a header carrying the information and a packet body including valid data corresponding to a signal to be packetized and an invalid data portion added thereto. claims 1 and packet multiplexing transmission apparatus according to any one of 4. Wherein for each of the plurality of packet generator, a packet multiplexing transmission apparatus according to any one of claims 1 to 5, characterized in that is further comprises a control unit capable to set the information. A packet multiplex transmission method for packetizing and multiplexing a plurality of signals for transmission,
For at least one set of signals included in the plurality of signals, a packet generation step of packetizing each of them in a sequence with the generation period shifted and fixed;
Multiplexing step of multiplexing a set of packets corresponding to the set of signals generated by the packet generation step in an order fixed by a multiplexing unit , and continuously transmitting with a fixed transmission delay time When,
With
The set of signals is a set of video signals that are synchronized with each other by an external synchronization signal and are switched or combined and displayed in a receiver of a receiver connected via a transmission line from the multiplexing unit. Signal,
The packet generation step uses a plurality of packet generation units provided corresponding to the plurality of signals, and each of the plurality of packet generation units includes whether or not the signal is included in the set of signals. And, if included, information indicating the order of packetization can be set, and each of the plurality of packet generators includes information indicating the order in the set information. Packetizing the set of signals according to:
In the multiplexing step, the set of packets each having a fixed transmission delay time is transmitted at a constant period, and the transmission delay time is a packet of a signal other than the set of signals. A packet multiplex transmission method characterized in that a packet that is not fixed is transmitted without overlapping a transmission period of the set of packets. The packet multiplex transmission device according to any one of claims 1 to 6 ,
A receiving device for restoring the plurality of signals from a packet transmitted from the multiplexing unit;
A packet multiplex transmission system characterized in that