JP6610522B2 - Switching regulator - Google Patents

Description

  The present invention relates to a current mode control type switching regulator that obtains a desired output voltage by switching and executing a step-down operation, a step-up / step-down operation, and a step-up operation.

  Conventionally, in a switching regulator capable of performing both step-down and step-up operations, the input voltage is monitored, and the step-down mode in which the step-down operation is performed and the step-up mode in which the step-up operation is performed are switched according to the monitoring result. Has been done. However, in this case, when the operation mode is switched, it is necessary to change the duty to an operable limit value. For this reason, the operation may be unstable and the output voltage may not be controlled.

  As a countermeasure against such a problem, for example, when switching from the step-down mode to the step-up mode, it is conceivable to fully turn on a switching element such as a transistor with a duty of 100%. However, in this case, when the transistor is shifted from the duty controlled state to the full-on state, the output voltage sharply rises and the output voltage may be out of the voltage range required for the specification. In order to improve such a point, it is also considered that a step-up / step-down mode in which a step-up / step-down operation is performed is provided to suppress fluctuations in output voltage when switching between the step-down mode and the step-up mode (for example, see Patent Document 1). ).

JP 2012-170199 A

  In the step-up / step-down mode, current consumption tends to be larger than in other operation modes. Therefore, it is desirable that the operation in the step-up / step-down mode is limited to a relatively short period during which the step-down mode is changed to the step-up mode or from the step-up mode to the step-down mode. In recent years, current mode control, which has high regulation characteristics and is superior to voltage mode control, tends to be employed as the operation of the switching regulator.

  However, if the buck-boost mode is provided in current mode control, the mode switching may not be successful. Therefore, it is not possible to switch to an appropriate operation mode according to the input voltage, and as a result, there is a possibility that problems such as fluctuations in the output voltage not being suppressed and an increase in loss may occur.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a switching regulator that can suppress fluctuations in output voltage and increase in loss.

  The switching regulator (1, 41, 51, 71) according to claim 1 switches between a step-down operation for stepping down the input voltage, a step-up / step-down operation for stepping up / down the input voltage, and a step-up operation for stepping up the input voltage. It is a current mode control type switching regulator that obtains a desired output voltage by executing. The switching regulator includes two step-down switching elements (Q1, Q2) that are switched when executing a step-down operation, two step-up switching elements (Q3, Q4) that are switched when executing a step-up operation, An inductor (L1), a current detection unit (2), and an output voltage detection unit (N) connected between the interconnection node (Nd) of the step-down switching element and each interconnection node (Nu) of the two step-down switching elements. 3), an error amplifying unit (4), a step-down side comparator (5), a step-down side driving unit (9), a step-up side comparator (6), and a step-up side driving unit (11).

  The current detection unit outputs a current detection signal corresponding to the current flowing through the inductor. The output voltage detector outputs an output detection voltage corresponding to the output voltage. The error amplifier outputs an error signal corresponding to the difference between the reference voltage corresponding to the target value of the output voltage and the output detection voltage. The step-down comparator compares the current detection signal with the error signal. The step-down side drive unit drives the step-down side switching element based on the output signal of the step-down side comparator and the step-down side clock signal. The boost side comparator compares the current detection signal with a signal obtained by subtracting a predetermined offset from the error signal. The step-up side drive unit drives the step-up side switching element based on the output signal of the step-up side comparator and the step-up side clock signal.

  In the above configuration, the configuration of the comparator that compares the current detection signal and the error signal is different from the configuration of a general buck-boost type and current mode control switching regulator. That is, in a general configuration, there is one such comparator, whereas in the above configuration, separate comparators are provided on the step-down side and the step-up side. Further, in the above configuration, an offset is provided for the error signal input to the two comparators. With such a configuration, switching between the step-up / step-down operation and the step-up operation is performed smoothly. Therefore, according to the above configuration, it is possible to perform switching to an appropriate operation according to the input voltage, so that an excellent effect of suppressing fluctuations in output voltage and an increase in loss can be obtained.

The switching regulator according to claim 1 further includes a first step-up operation limiting unit (10) that invalidates driving of the step-up side switching element by the step-up side drive unit during a period in which the input voltage is equal to or higher than a predetermined threshold voltage. . According to such a configuration, switching between the step-down operation and the step-up / step-down operation is performed smoothly, and thus the effect of suppressing fluctuations in output voltage and increase in loss is further enhanced.

According to a second aspect of the present invention , the switching regulator further includes a delay circuit (42, 53) and a second boosting operation limiting unit (43). The delay circuit delays the step-up clock signal by a predetermined delay time with respect to the step-down clock signal. The second boosting operation limiting unit invalidates the driving of the boosting side switching element by the boosting side driving unit for a period determined based on the delay time. According to such a configuration, switching between the step-down operation and the step-up / step-down operation is performed smoothly, so that the effect of suppressing fluctuations in output voltage and an increase in loss is further enhanced.

The figure which shows typically the structure of the switching regulator which concerns on 1st Embodiment. The figure which shows typically the waveform of the signal and voltage of each part which concern on 1st Embodiment. The figure which shows typically the operation state of each part at the time of pressure | voltage fall operation | movement which concerns on 1st Embodiment. The figure which shows typically the operation state of each part at the time of the pressure | voltage rise / fall operation | movement concerning 1st Embodiment. The figure which shows typically the operation state of each part at the time of the pressure | voltage rise operation which concerns on 1st Embodiment. The figure for demonstrating the determination method of the offset which concerns on 1st Embodiment. The figure which shows typically the structure of the switching regulator which concerns on 2nd Embodiment. The figure which shows typically the waveform of the signal and voltage of each part which concern on 2nd Embodiment. The figure which shows typically the structure of the switching regulator which concerns on 3rd Embodiment. The figure which shows typically the specific structure of the delay circuit which concerns on 3rd Embodiment. The figure which shows typically the structure of the switching regulator which concerns on 4th Embodiment.

Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. In each embodiment, substantially the same components are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

  A switching regulator 1 shown in FIG. 1 is a current mode control type buck-boost switching regulator. The switching regulator 1 includes a step-down operation for stepping down a power supply voltage VDD (hereinafter referred to as input voltage VDD) input through the power supply terminal Pd, a step-up / step-down operation for stepping up / down the input voltage VDD, and a step-up operation for stepping up the input voltage VDD. Are executed so as to obtain a desired output voltage Vout.

  The input voltage VDD is supplied from, for example, an in-vehicle battery (not shown), and its fluctuation range is relatively large. Specifically, the input voltage VDD varies over a range from a voltage value higher than a target value (for example, 6 V) of the output voltage Vout to a voltage value lower than the target value of the output voltage Vout.

  The output voltage Vout of the switching regulator 1 is supplied to, for example, an in-vehicle device (not shown) through the output terminal Po. The switching regulator 1 includes a capacitor Co, transistors Q1 to Q4, an inductor L1, a current detection unit 2, an output voltage detection unit 3, an error amplifier 4, comparators 5 and 6, flip-flops 7 and 8, a step-down side drive unit 9, a first A boosting operation limiting unit 10 and a boosting side driving unit 11 are provided.

  The switching regulator 1 is configured as a semiconductor integrated circuit (IC). Note that all the circuit elements constituting the switching regulator 1 may be provided inside the IC, or some circuit elements (for example, the capacitor Co, the transistors Q1 to Q4, etc.) may be provided outside the IC. The capacitor Co is for smoothing the output voltage Vout, and is connected between the output terminal Po and a ground terminal Pg to which a circuit reference potential GND is applied.

  Transistors Q1-Q4 are all N-channel type MOS transistors. The transistors Q1 and Q2 are switched when the step-down operation is executed, and correspond to step-down switching elements. The transistors Q3 and Q4 are switched when the boosting operation is performed, and correspond to boosting side switching elements. When the step-up / step-down operation is performed, all of the transistors Q1 to Q4 are switched.

  The drain of the transistor Q1 is connected to the power supply terminal Pd via the shunt resistor Rs constituting the current detection unit 2, and the source thereof is connected to the drain of the transistor Q2. The source of the transistor Q2 is connected to the ground terminal Pg. The drain of the transistor Q3 is connected to the output terminal Po, and its source is connected to the drain of the transistor Q4. The source of the transistor Q4 is connected to the ground terminal Pg. The inductor L1 is connected between the interconnection node Nd of the transistors Q1 and Q2 and the interconnection node Nu of the transistors Q3 and Q4.

  The current detection unit 2 detects a current flowing through the inductor L1, and outputs a current detection signal Sa corresponding to the current. The current detection unit 2 includes the shunt resistor Rs and the current detection amplifier 12 described above. The voltage of one terminal of the shunt resistor Rs, that is, the input voltage VDD is applied to the non-inverting input terminal of the current detection amplifier 12. The inverting input terminal of the current detection amplifier 12 is supplied with the voltage of the other terminal of the shunt resistor Rs, that is, the drain voltage of the transistor Q1. With such a configuration, the current detection signal Sa corresponding to the current flowing through the inductor L1 is output from the output terminal of the current detection amplifier 12.

  The output voltage detector 3 detects the output voltage Vout, and outputs an output detection voltage Vd corresponding to the output voltage Vout. The output voltage detector 3 includes resistors R1 and R2 connected in series between the output terminal Po and the ground terminal Pg. In such a configuration, the voltage of the interconnection node N1 of the resistors R1 and R2, that is, the divided voltage obtained by dividing the output voltage Vout by the voltage dividing circuit including the resistors R1 and R2, is output as the output detection voltage Vd. .

  The error amplifier 4 corresponds to an error amplifier, and a reference voltage Vr corresponding to a target value of the output voltage Vout is input to a non-inverting input terminal. The reference voltage Vr is generated by a reference voltage generation unit 13 including a band gap reference circuit, for example. The output detection voltage Vd is input to the inverting input terminal of the error amplifier 4. The error amplifier 4 outputs an error signal Sb obtained by amplifying the difference between the reference voltage Vr and the output detection voltage Vd.

  The comparator 5 corresponds to a step-down comparator, and the current detection signal Sa is input to its inverting input terminal, and the error signal Sb is input to its non-inverting input terminal. The comparator 6 corresponds to a boost side comparator, and the current detection signal Sa is input to its inverting input terminal. An error signal Sc that is a signal obtained by subtracting a predetermined offset from the error signal Sb is input to the non-inverting input terminal of the comparator 6. Such an offset is realized by an offset voltage source 14 provided between the output terminal of the error amplifier 4 and the non-inverting input terminal of the comparator 6.

  The flip-flop 7 is an RS type, and the output signal of the comparator 5 is input to its reset terminal R bar, and the clock signal CLK is input to its set terminal S. In the figure, the terminal R bar is indicated by “-” on the R. The clock signal CLK has a frequency (for example, 2 MHz) corresponding to the switching period in the switching regulator 1 and is generated by the clock generation circuit 15. In this case, the clock signal CLK corresponds to both the step-down clock signal and the step-up clock signal. A signal output from the output terminal Q of the flip-flop 7 is given to the step-down drive unit 9.

  The step-down side drive unit 9 includes an AND circuit 16, an OR circuit 17, and inverting buffers 18-23. The output signal of the flip-flop 7 is input to one input terminal of the AND circuit 16 and one input terminal of the OR circuit 17. The output signal of the AND circuit 16 is given to the gate of the transistor Q1 through the inverting buffers 18 and 19. In this case, the output signal of the inverting buffer 19 is a drive signal Sg1 for driving the gate of the transistor Q1.

  The drive signal Sg1 is input to the other input terminal of the OR circuit 17 via the inverting buffers 20 and 21. The output signal of the OR circuit 17 is given to the gate of the transistor Q2 through the inverting buffer 22. In this case, the output signal of the inverting buffer 22 is a drive signal Sg2 for driving the gate of the transistor Q2. The drive signal Sg2 is input to the other input terminal of the AND circuit 16 via the inverting buffer 23.

  The flip-flop 8 is an RS type, and the output signal of the comparator 6 is input to its reset terminal R bar, and the clock signal CLK is input to its set terminal S. A signal output from the output terminal Q of the flip-flop 8 is given to the first boosting operation limiting unit 10.

  The first boosting operation limiting unit 10 invalidates the driving of the transistors Q3 and Q4 by the boosting side driving unit 11 during a period when the input voltage VDD is equal to or higher than the threshold voltage Vth. The first boosting operation limiting unit 10 A buffer 26 is provided. An input voltage VDD and a threshold voltage Vth are input to the VDD monitor 24. The threshold voltage Vth is set to a predetermined voltage value that is higher than the target value of the output voltage Vout.

  The VDD monitor 24 includes a voltage dividing circuit using a resistor, a comparator, and the like, and outputs a low level signal (hereinafter referred to as L level) that is 0 V, for example, during a period when the input voltage VDD is equal to or higher than the threshold voltage Vth. The VDD monitor 24 outputs a high level (hereinafter, referred to as H level) signal that is 5 V, for example, during a period when the input voltage VDD is less than the threshold voltage Vth. The output signal of the flip-flop 8 and the output signal of the VDD monitor 24 are input to each input terminal of the AND circuit 25. The output signal of the AND circuit 25 is given to the booster side drive unit 11 via the inversion buffer 26.

  The step-up side drive unit 11 includes an AND circuit 27, an OR circuit 28, and inverting buffers 29 to 34. The output signal of the inverting buffer 26 of the first boosting operation limiting unit 10 is input to one input terminal of the AND circuit 27 and one input terminal of the OR circuit 28. The output signal of the AND circuit 27 is given to the gate of the transistor Q3 through the inverting buffers 29 and 30. In this case, the output signal of the inverting buffer 30 is a drive signal Sg3 for driving the gate of the transistor Q3.

  The drive signal Sg3 is input to the other input terminal of the OR circuit 28 via the inverting buffers 31 and 32. The output signal of the OR circuit 28 is given to the gate of the transistor Q4 via the inverting buffer 33. In this case, the output signal of the inverting buffer 33 is a drive signal Sg4 for driving the gate of the transistor Q4. The drive signal Sg4 is input to the other input terminal of the AND circuit 27 via the inverting buffer 34.

Next, the operation of the above configuration will be described with reference to FIGS.
[1] Step-down operation When the input voltage VDD is equal to or higher than the threshold voltage Vth, the switching regulator 1 performs only the step-down operation. During the step-down operation, the “state A” and “state B” shown in FIG. 3 are alternately repeated as the operation states of the transistors Q1 to Q4.

  That is, when the transistor Q3 is fixed on and the transistor Q4 is fixed off, the transistors Q1 and Q2 are complementarily turned on and off to perform a step-down operation for stepping down the input voltage VDD. Specifically, such an operation is realized as follows.

  That is, in this case, since the input voltage VDD is equal to or higher than the threshold voltage Vth, the output signal of the VDD monitor 24 becomes L level. Therefore, regardless of the level of the output signal of the flip-flop 8, the drive signal Sg3 becomes H level and the drive signal Sg4 becomes L level. That is, the driving of the transistors Q3 and Q4 by the boost side driving unit 11 is invalidated. As a result, the transistor Q3 is fixed on and the transistor Q4 is fixed off. As a result, as shown in FIG. 2, the voltage at the node Nu is fixed at a voltage substantially equal to the output voltage Vout.

  On the other hand, the transistors Q1 and Q2 are driven by the step-down side drive unit 9 as follows. That is, when the clock signal CLK changes from the L level to the H level, the flip-flop 7 is set. As a result, the drive signal Sg1 becomes H level and the drive signal Sg2 becomes L level. Therefore, as in “state A” shown in FIG. 3, the transistor Q1 is turned on and the transistor Q2 is turned off.

  In such a state A, as shown in FIG. 2, the voltage at the node Nd is substantially equal to the input voltage VDD. Therefore, a current flows from the power supply terminal Pd to the output terminal Po through the shunt resistor Rs and the inductor L1. The current detection signal Sa rises according to such a current. When the current detection signal Sa rises and reaches the error signal Sb, an L level signal is output from the comparator 5 and the flip-flop 7 is reset.

  As a result, the drive signal Sg1 becomes L level and the drive signal Sg2 becomes H level. Therefore, as in “state B” shown in FIG. 3, the transistor Q1 is turned off and the transistor Q2 is turned on. In such a state B, as shown in FIG. 2, the voltage at the node Nd is substantially equal to the reference potential GND (0 V). In the state B, a reflux current flows from the ground terminal Pg to the output terminal Po through the inductor L1. That is, in the state B, since no current flows through the shunt resistor Rs, the current detection signal Sa becomes L level (0 V).

  As described above, when the input voltage VDD is equal to or higher than the threshold voltage Vth, the transistors Q1 and Q2 are switched by the step-down side drive unit 9 while the drive of the transistors Q3 and Q4 by the step-up side drive unit 11 is disabled. As a result, only the step-down operation is executed.

[2] Step-up / step-down operation When the input voltage VDD is less than the threshold voltage Vth and higher than the output voltage Vout, the switching regulator 1 performs both step-up and step-down operations, that is, step-up / step-down operations. At the time of the step-up / step-down operation, as the operation states of the transistors Q1 to Q4, “state A”, “state B”, and “state C” shown in FIG. 4 are repeated in the order shown.

  In this case, when the state A → the state B → the state A transits, the transistors Q1 and Q2 are complementarily turned on and off while the transistor Q3 is fixed on and the transistor Q4 is fixed off. A step-down operation for stepping down the input voltage VDD is performed. In this case, when the state A → the state C → the state A is transited, the transistors Q3 and Q4 are complementarily turned on / off in a state where the transistor Q1 is fixed on and the transistor Q2 is fixed off. Thus, a boosting operation for boosting the input voltage VDD is performed. Specifically, such an operation is realized as follows.

  That is, in this case, since the input voltage VDD is less than the threshold voltage Vth, the output signal of the VDD monitor 24 becomes H level. Therefore, the drive signals Sg3 and Sg4 change according to the output signal of the flip-flop 8. That is, the driving of the transistors Q3 and Q4 by the boost side driving unit 11 is validated.

  In this case, the transistors Q1 to Q4 are switched as follows. That is, when the clock signal CLK changes from the L level to the H level, both the flip-flops 7 and 8 are set. As a result, the drive signal Sg1 becomes H level and the drive signal Sg2 becomes L level. Further, the drive signal Sg3 becomes L level and the drive signal Sg4 becomes H level. Therefore, as in "state C" shown in FIG. 4, the transistors Q1 and Q4 are turned on and the transistors Q2 and Q3 are turned off.

  In such a state C, as shown in FIG. 2, the voltage at the node Nd becomes substantially equal to the input voltage VDD, and the voltage at the node Nu becomes substantially equal to 0V. Therefore, a current flows from the power supply terminal Pd to the ground terminal Pg via the shunt resistor Rs and the inductor L1. The current detection signal Sa rises according to such a current. When the current detection signal Sa rises and reaches the error signal Sc, an L level signal is output from the comparator 6 and the flip-flop 8 is reset.

  As a result, the drive signal Sg3 becomes H level and the drive signal Sg4 becomes L level. Therefore, as in "state A" shown in FIG. 4, the transistors Q1 and Q3 are turned on and the transistors Q2 and Q4 are turned off. In such a state A, as shown in FIG. 2, the voltage at the node Nd becomes substantially equal to the input voltage VDD, and the voltage at the node Nu becomes substantially equal to the output voltage Vout.

  Therefore, a current flows from the power supply terminal Pd to the output terminal Po through the shunt resistor Rs and the inductor L1. The current detection signal Sa rises according to such a current. Note that the rising slope of the current detection signal Sa in the state A is smaller than the rising slope of the current detection signal Sa in the state C.

  When the current detection signal Sa rises and reaches the error signal Sb, an L level signal is output from the comparator 5 and the flip-flop 7 is reset. As a result, the drive signal Sg1 becomes L level and the drive signal Sg2 becomes H level. Therefore, as in “state B” shown in FIG. 4, the transistors Q1 and Q4 are turned off and the transistors Q2 and Q3 are turned on. In such a state B, as shown in FIG. 2, the voltage of the node Nd is substantially equal to 0V. In the state B, a reflux current flows from the ground terminal Pg to the output terminal Po through the inductor L1. That is, in the state B, since no current flows through the shunt resistor Rs, the current detection signal Sa becomes L level.

  Thus, when the input voltage VDD is less than the threshold voltage Vth and higher than the output voltage Vout, the step-down operation is performed by switching the transistors Q1 and Q2 by the step-down side drive unit 9, and the step-up side drive unit 11, the transistors Q3 and Q4 are switched to perform the step-down operation.

[3] Boosting Operation When the input voltage VDD is equal to or lower than the output voltage Vout, the switching regulator 1 performs only the boosting operation. During the step-up operation, the “state A” and “state C” shown in FIG. 5 are alternately repeated as the operation states of the transistors Q1 to Q4.

  That is, in the state where the transistor Q1 is fixed on and the transistor Q2 is fixed off, the transistors Q3 and Q4 are complementarily turned on and off to perform a boosting operation for boosting the input voltage VDD. Specifically, such an operation is realized as follows.

  That is, in this case, since the input voltage VDD is less than the threshold voltage Vth, the output signal of the VDD monitor 24 becomes H level. Therefore, the drive signals Sg3 and Sg4 change according to the output signal of the flip-flop 8. That is, the driving of the transistors Q3 and Q4 by the boost side driving unit 11 is validated.

  In this case, the transistors Q1 to Q4 are driven as follows. That is, when the clock signal CLK changes from the L level to the H level, both the flip-flops 7 and 8 are set. As a result, the drive signal Sg1 becomes H level and the drive signal Sg2 becomes L level. Further, the drive signal Sg3 becomes L level and the drive signal Sg4 becomes H level. Therefore, as in “state C” shown in FIG. 5, the transistors Q1 and Q4 are turned on, and the transistors Q2 and Q3 are turned off.

  In such a state C, as shown in FIG. 2, the voltage at the node Nd becomes substantially equal to the input voltage VDD, and the voltage at the node Nu becomes substantially equal to 0V. Therefore, a current flows from the power supply terminal Pd to the ground terminal Pg via the shunt resistor Rs and the inductor L1. The current detection signal Sa rises according to such a current. When the current detection signal Sa rises and reaches the error signal Sc, an L level signal is output from the comparator 6 and the flip-flop 8 is reset.

  As a result, the drive signal Sg3 becomes H level and the drive signal Sg4 becomes L level. Therefore, as in “state A” shown in FIG. 5, the transistors Q1 and Q3 are turned on, and the transistors Q2 and Q4 are turned off. In this case, the input voltage VDD is equal to or lower than the output voltage Vout. Therefore, in the state A, the current flowing through the inductor L1 changes from rising to lowering.

  For this reason, the flip-flop 7 is not reset in the state A, the drive signal Sg1 is fixed at the H level, and the drive signal Sg2 is fixed at the L level. As a result, the transistor Q1 is fixed on and the transistor Q2 is fixed off. Thereby, as shown in FIG. 2, the voltage of the node Nd is fixed at a voltage substantially equal to the input voltage VDD.

  As described above, when the input voltage VDD is equal to or lower than the output voltage Vout, the transistors Q3 and Q4 are switched by the boost side driver 11 while the transistor Q1 is fixed on and the transistor Q2 is fixed off. As a result, only the boosting operation is executed.

[4] Offset Determination Method In this embodiment, since the switching between the step-up / step-down operation and the step-up operation can be performed reliably, the offset generated by the offset voltage source 14 is determined as follows. That is, as described above, in the “state C”, a current flows from the power supply terminal Pd to the ground terminal Pg via the shunt resistor Rs and the inductor L1, so that the current detection signal Sa rises and reaches the error signal Sc. Then, the transistor Q3 is turned from off to on and the transistor Q4 is turned from on to off, thereby shifting to the “state A”.

  However, as shown in FIG. 6, from the time ta when the current detection signal Sa reaches the error signal Sc to the time tb when the transistors Q3 and Q4 are actually switched on and off and the current detection signal Sa starts to decrease, the comparator 5, 6, there is a circuit delay time ΔT due to circuit operations such as the step-down side drive unit 9 and the step-up side drive unit 11. If the current detection signal Sa reaches the error signal Sb during such a circuit delay time ΔT, even if it should not be switched to the step-up / step-down operation, it is erroneously switched to the step-up / step-down operation. Therefore, in the present embodiment, the offset is set to a value such that the current detection signal Sa does not reach the error signal Sb during the circuit delay time ΔT.

Specifically, the offset Vof is determined as follows. That is, the step-up / step-down operation is switched to the step-up operation when the input voltage VDD becomes equal to the output voltage Vout. Further, the increment ΔVsen of the current detection signal Sa from the time ta when the current detection signal Sa reaches the error signal Sc is expressed by the following equation (1). However, the resistance value of the shunt resistor Rs is Rs, and the inductance value of the inductor L1 is L.
ΔVsen = Rs × L × Vout × ΔT (1)

If the offset Vof is smaller than the increment ΔVsen of the current detection signal Sa, the operation may be erroneously switched as described above. Therefore, in this embodiment, the offset Vof is set to a value equal to or larger than ΔVsen, that is, a value satisfying the following expression (2).
Vof ≧ ΔVsen = Rs × L × Vout × ΔT (2)

According to this embodiment described above, the following effects can be obtained.
In the switching regulator 1 of the present embodiment, different from the configuration of a general buck-boost type and current mode control switching regulator, separate comparators 5 and 6 are provided on the step-down side and the step-up side. Further, an offset is provided so that the error signal Sc input to the step-up comparator 6 is lower than the error signal Sb input to the step-down comparator 5.

  According to such a configuration, when the input voltage VDD is higher than the output voltage Vout, that is, when the input voltage VDD to be step-up / step-down operation is given, the step-up / step-down operation is performed, and the input voltage VDD is changed to the output voltage Vout. In the following cases, that is, when the input voltage VDD to be boosted is given, the boosting operation is executed.

  In addition, the switching regulator 1 performs the first boost operation for invalidating the driving of the transistors Q3 and Q4 by the boost side drive unit 11 during a period in which the input voltage VDD is equal to or higher than the threshold voltage Vth set to a value higher than the output voltage Vout. A limiting unit 10 is provided. According to such a configuration, when the input voltage VDD is equal to or higher than the threshold voltage Vth, that is, when the input voltage VDD for performing the step-down operation is given, the step-down operation is performed, and the input voltage VDD is the threshold voltage. When it is less than Vth, that is, when the input voltage VDD for performing the step-up / step-down operation is given, the step-up / step-down operation is performed.

  As described above, the switching regulator 1 is provided with the separate comparators 5 and 6 on the step-down side and the step-up side and also provides the offset so that the step-up / step-down operation and the step-up operation can be appropriately switched according to the input voltage VDD. It has become. Further, the switching regulator 1 is provided with the first step-up operation limiting unit 10 so that the step-down operation and the step-up / step-down operation can be appropriately switched according to the input voltage VDD. Therefore, according to the present embodiment, since it is possible to switch to an appropriate operation according to the input voltage VDD, it is possible to suppress an increase in the output voltage Vout and an increase in loss. can get.

  The offset is determined based on the circuit delay time ΔT accompanying the circuit operations of the comparators 5 and 6, the step-down side drive unit 9, and the step-up side drive unit 11. Specifically, in the present embodiment, the offset is set to a value such that the current detection signal Sa does not reach the error signal Sb during the circuit delay time ΔT. In this way, when the input voltage VDD is equal to or lower than the output voltage Vout, it is not erroneously switched to the step-up / step-down operation. Therefore, switching to an appropriate operation according to the input voltage VDD is performed more reliably. Can do.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. 7 and 8.
As shown in FIG. 7, the switching regulator 41 of the present embodiment includes a delay circuit 42 and a second boosting operation limiting unit 43 instead of the first boosting operation limiting unit 10 with respect to the switching regulator 1 of the first embodiment. Is different. The delay circuit 42 receives the clock signal CLK generated by the clock generation circuit 15 and outputs a delayed clock signal delayed by a predetermined delay time with respect to the clock signal CLK.

  In the present embodiment, the clock signal CLK corresponds to the step-down clock signal, and the delayed clock signal output from the delay circuit 42 corresponds to the step-up clock signal. Therefore, in the following description, the clock signal CLK is referred to as “step-down clock signal CLKD” and the delayed clock signal is referred to as “step-up clock signal CLKU”. The step-down clock signal CLKD is input to the set terminal S of the step-down flip-flop 7. The boost side clock signal CLKU is supplied to the second boost operation limiter 43.

  The second boosting operation limiting unit 43 invalidates the driving of the transistors Q3 and Q4 by the boosting side driving unit 11 during a period determined based on the delay time in the delay circuit 42, and includes an AND circuit 44 and an inverting buffer 45. It has. The boost-side clock signal CLKU and the output signal of the flip-flop 7 are input to the input terminals of the AND circuit 44, respectively.

  The output signal of the AND circuit 44 is input to the set terminal S of the flip-flop 8 on the boost side. The output signal of the flip-flop 8 is input to the inverting buffer 45. The output signal of the inverting buffer 45 is input to one input terminal of the AND circuit 27 and one input terminal of the OR circuit 28 of the booster side drive unit 11.

The delay time in the delay circuit 42 is determined as follows in order to surely switch between the step-down operation and the step-up / step-down operation. That is, the duty Duty_d during the step-down operation is expressed by the following equation (3).
Duty_d = Vout / VDD (3)

The on time Ton in one cycle during the step-down operation is expressed by the following equation (4). The on-time Ton is a time during which the transistor Q1 is turned on and the transistor Q2 is turned off during one cycle during the step-down operation. However, the frequency of the step-down clock signal CLKD and the step-up clock signal CLKU is fclk, and the cycle (cycle time) is Tclk.
Ton = Duty_d / fclk = Duty_d × Tclk
= (Vout / VDD) × Tclk (4)

When the threshold value of the input voltage VDD when switching from the step-down operation to the step-up / step-down operation is VDDth, the delay time Td is expressed by the following equation (5).
Td = (Vout / VDDth) × Tclk (5)

  The switching regulator 1 is in a state in which only the step-down operation can be performed during the period from the start time of one cycle to the time point when the delay time Td elapses, and the step-up / step-down operation can be performed after the delay time Td elapses. It will switch to the state.

  The delay time Td may be determined based on the output voltage Vout. Specifically, the delay time Td is preferably set to be longer as the target value of the output voltage Vout is lower. The reason is as follows. That is, when the target value of the output voltage Vout is relatively low, it is difficult to cause a problem even if the boosting capability is low. Therefore, in this case, it is preferable to lengthen the delay time in order to relatively shorten the time allocated to the booster side and relatively increase the time allocated to the booster side. On the other hand, when the target value of the output voltage Vout is relatively high, it is necessary to increase the boosting capability. Therefore, in this case, it is preferable to shorten the delay time in order to relatively lengthen the time allocated to the booster side and relatively shorten the time allocated to the booster side.

  Next, the operation of the above configuration will be described with reference to FIG. Note that the operating states of the transistors Q1 to Q4 during the step-down operation, the step-up / step-down operation, and the step-up operation are the same as those in the first embodiment. Therefore, in the following description, also refer to FIGS. 3 to 5 as appropriate. And

[1] Step-down operation When the input voltage VDD is higher than the output voltage Vout and the on time Ton is less than the delay time Td, the switching regulator 1 executes only the step-down operation. During the step-down operation, the “state A” and “state B” shown in FIG. 3 are alternately repeated as the operation states of the transistors Q1 to Q4.

  In this case, when the step-down clock signal CLKD changes from the L level to the H level, the flip-flop 7 is set. As a result, the drive signal Sg1 becomes H level and the drive signal Sg2 becomes L level. Therefore, as in the “state A” shown in FIG. 3, the transistor Q1 is turned on and the transistor Q2 is turned off.

  In such a state A, as shown in FIG. 8, the voltage at the node Nd is substantially equal to the input voltage VDD. Therefore, a current flows from the power supply terminal Pd to the output terminal Po through the shunt resistor Rs and the inductor L1. The current detection signal Sa rises according to such a current. When the current detection signal Sa rises and reaches the error signal Sb, an L level signal is output from the comparator 5 and the flip-flop 7 is reset.

  As a result, the drive signal Sg1 becomes L level and the drive signal Sg2 becomes H level. Therefore, as in “state B” shown in FIG. 3, the transistor Q1 is turned off and the transistor Q2 is turned on. In such a state B, as shown in FIG. 2, the voltage at the node Nd is substantially equal to the reference potential GND (0 V). In the state B, a reflux current flows from the ground terminal Pg to the output terminal Po through the inductor L1. That is, in the state B, since no current flows through the shunt resistor Rs, the current detection signal Sa becomes L level (0 V).

  After the elapse of the delay time Td from the time when the step-down clock signal CLKD rises, the step-up clock signal CLKU changes from the L level to the H level. However, since the flip-flop 7 is reset at this time, its output signal is at L level. Therefore, the flip-flop 8 is not set, and the state where the drive signal Sg3 is at the H level and the drive signal Sg4 is at the L level is maintained. That is, the driving of the transistors Q3 and Q4 by the boost side driving unit 11 is invalidated. As a result, the transistor Q3 is fixed on and the transistor Q4 is fixed off. As a result, as shown in FIG. 8, the voltage at the node Nu is fixed at a voltage substantially equal to the output voltage Vout.

  As described above, when the input voltage VDD is higher than the output voltage Vout and the on-time Ton is less than the delay time Td, the step-down driving is performed while the driving of the transistors Q3 and Q4 by the step-up driving unit 11 is disabled. As the transistors Q1 and Q2 are switched by the unit 9, only the step-down operation is performed.

[2] Buck-Boost Operation When the input voltage VDD is higher than the output voltage Vout and the on-time Ton is equal to or longer than the delay time Td, the switching regulator 1 executes both the step-up operation and the step-down operation, that is, the step-up / step-down operation. . At the time of the step-up / step-down operation, as the operation states of the transistors Q1 to Q4, “state A”, “state B”, and “state C” shown in FIG. 4 are repeated in the order shown.

  In this case, when the step-down clock signal CLKD changes from the L level to the H level, the flip-flop 7 is set. As a result, the drive signal Sg1 becomes H level and the drive signal Sg2 becomes L level. Therefore, as in the “state A” shown in FIG. 3, the transistor Q1 is turned on and the transistor Q2 is turned off.

  In such a state A, as shown in FIG. 8, the voltage at the node Nd is substantially equal to the input voltage VDD. Therefore, a current flows from the power supply terminal Pd to the output terminal Po through the shunt resistor Rs and the inductor L1. The current detection signal Sa rises according to such a current.

  After the elapse of the delay time Td from the time when the step-down clock signal CLKD rises, the step-up clock signal CLKU changes from the L level to the H level. At this time, the current detection signal Sa has not yet reached the error signal Sb, and the flip-flop 7 has not been reset. Therefore, the flip-flop 8 is set at the rising edge of the step-down clock signal CLKD. As a result, the drive signal Sg3 becomes L level and the drive signal Sg4 becomes H level. Therefore, as in the “state C” shown in FIG. 4, the transistors Q1 and Q4 are turned on, and the transistors Q2 and Q3 are turned off.

  In such a state C, as shown in FIG. 8, the voltage at the node Nd becomes substantially equal to the input voltage VDD, and the voltage at the node Nu becomes substantially equal to 0V. Therefore, a current flows from the power supply terminal Pd to the ground terminal Pg via the shunt resistor Rs and the inductor L1. The current detection signal Sa rises according to such a current. When the current detection signal Sa rises and reaches the error signal Sc, an L level signal is output from the comparator 6 and the flip-flop 8 is reset.

  As a result, the drive signal Sg3 becomes H level and the drive signal Sg4 becomes L level. Therefore, as in the “state A” shown in FIG. 4, the transistors Q1 and Q3 are turned on and the transistors Q2 and Q4 are turned off. In such a state A, as shown in FIG. 8, the voltage at the node Nd becomes substantially equal to the input voltage VDD, and the voltage at the node Nu becomes substantially equal to the output voltage Vout.

  Therefore, a current flows from the power supply terminal Pd to the output terminal Po through the shunt resistor Rs and the inductor L1. The current detection signal Sa rises according to such a current. When the current detection signal Sa rises and reaches the error signal Sb, an L level signal is output from the comparator 5 and the flip-flop 7 is reset. As a result, the drive signal Sg1 becomes L level and the drive signal Sg2 becomes H level. Therefore, as in the “state B” shown in FIG. 4, the transistors Q1 and Q4 are turned off and the transistors Q2 and Q3 are turned on. In such a state B, as shown in FIG. 8, the voltage at the node Nd is substantially equal to 0V. In the state B, a reflux current flows from the ground terminal Pg to the output terminal Po through the inductor L1. That is, in the state B, since no current flows through the shunt resistor Rs, the current detection signal Sa becomes L level.

  As described above, when the input voltage VDD is higher than the output voltage Vout and the on time Ton is equal to or longer than the delay time Td, the step-down operation is performed by switching the transistors Q1 and Q2 by the step-down side drive unit 9. The step-down operation is executed by switching the transistors Q3 and Q4 by the step-up side drive unit 11.

[3] Boosting Operation When the input voltage VDD is equal to or lower than the output voltage Vout, the switching regulator 1 performs only the boosting operation. During the boosting operation, the “state A” and “state C” shown in FIG. 5 are alternately repeated as the operation states of the transistors Q1 to Q4.

  In this case, when the step-down clock signal CLKD changes from the L level to the H level, the flip-flop 7 is set. As a result, the drive signal Sg1 becomes H level and the drive signal Sg2 becomes L level. Thus, after the elapse of the delay time Td from the time when the step-down clock signal CLKD rises, the step-up clock signal CLKU changes from the L level to the H level. As a result, the drive signal Sg3 becomes L level and the drive signal Sg4 becomes H level. Therefore, as in the “state C” shown in FIG. 5, the transistors Q1 and Q4 are turned on and the transistors Q2 and Q3 are turned off.

  In such a state C, as shown in FIG. 8, the voltage at the node Nd becomes substantially equal to the input voltage VDD, and the voltage at the node Nu becomes substantially equal to 0V. Therefore, a current flows from the power supply terminal Pd to the ground terminal Pg via the shunt resistor Rs and the inductor L1. The current detection signal Sa rises according to such a current. When the current detection signal Sa rises and reaches the error signal Sc, an L level signal is output from the comparator 6 and the flip-flop 8 is reset.

  As a result, the drive signal Sg3 becomes H level and the drive signal Sg4 becomes L level. Therefore, as in “state A” shown in FIG. 5, the transistors Q1 and Q3 are turned on, and the transistors Q2 and Q4 are turned off. In this case, the input voltage VDD is equal to or lower than the output voltage Vout. Therefore, in the state A, the current flowing through the inductor L1 changes from rising to lowering.

  For this reason, the flip-flop 7 is not reset in the state A, the drive signal Sg1 is fixed at the H level, and the drive signal Sg2 is fixed at the L level. As a result, the transistor Q1 is fixed on and the transistor Q2 is fixed off. As a result, as shown in FIG. 8, the voltage at the node Nd is fixed at a voltage substantially equal to the input voltage VDD.

  As described above, when the input voltage VDD is equal to or lower than the output voltage Vout, the transistors Q3 and Q4 are switched by the boost side driver 11 while the transistor Q1 is fixed on and the transistor Q2 is fixed off. As a result, only the boosting operation is executed.

According to this embodiment described above, the following effects can be obtained.
As with the switching regulator 1 of the first embodiment, the switching regulator 41 of the present embodiment is provided with separate comparators 5 and 6 on the step-down side and the step-up side, and the error signal Sc is lower than the error signal Sb. An offset is provided. According to such a configuration, the step-up / step-down operation is performed when the input voltage VDD is higher than the output voltage Vout, that is, when the input voltage VDD to be step-up / step-down operation is given, as in the first embodiment. When the input voltage VDD is equal to or lower than the output voltage Vout, that is, when the input voltage VDD to be boosted is given, the boosting operation is executed.

  The switching regulator 41 also includes a delay circuit 42 that delays the boost side clock signal CLKU from the step-down clock signal CLKD by a delay time Td, and a period determined based on the delay time Td, and the transistor Q3 by the boost side driver 11. , Q4 is provided with a second step-up operation limiting unit 43 that disables driving of Q4.

  The short on-time Ton means that the duty during the step-down operation is relatively small, that is, the input voltage VDD is sufficiently higher than the output voltage Vout. Therefore, when the on-time Ton is less than the delay time Td, the input voltage VDD is sufficiently higher than the output voltage Vout, and it can be said that the step-down operation is to be executed. According to the above configuration, when the input voltage VDD is higher than the output voltage Vout and the on-time Ton is less than the delay time Td, that is, when the input voltage VDD for performing the step-down operation is given, the step-down operation is performed. Executed.

  Further, the long on-time Ton means that the duty during the step-down operation is relatively large, that is, the input voltage VDD is not sufficiently high with respect to the output voltage Vout. Therefore, when the on time Ton is equal to or longer than the delay time Td, it can be said that the step-up / step-down operation is to be performed because the input voltage VDD is not sufficiently higher than the output voltage Vout. According to the above configuration, when the input voltage VDD is higher than the output voltage Vout and the on time Ton is equal to or longer than the delay time Td, that is, when the input voltage VDD for performing the step-up / step-down operation is given, the step-up / step-down operation is performed. The action is executed.

  As described above, the switching regulator 41 is provided with the separate comparators 5 and 6 on the step-down side and the step-up side and provides the offset so that the step-up / step-down operation and the step-up operation can be appropriately switched according to the input voltage VDD. It has become. Further, the switching regulator 1 is provided with the delay circuit 42 and the second step-up operation limiting unit 43 so that the step-down operation and the step-up / step-down operation can be appropriately switched according to the input voltage VDD. Therefore, according to the present embodiment, as in the first embodiment, it is possible to switch to an appropriate operation according to the input voltage VDD, thereby suppressing fluctuations in the output voltage Vout and an increase in loss. An excellent effect is obtained.

(Third embodiment)
Hereinafter, a third embodiment will be described with reference to FIGS. 9 and 10.
As shown in FIG. 9, the switching regulator 51 of the present embodiment includes a clock generation circuit 52 and a delay circuit 53 instead of the clock generation circuit 15 and the delay circuit 42 with respect to the switching regulator 41 of the second embodiment. In addition, an OP amplifier 54 is further provided.

  The clock generation circuit 52 generates a clock signal CLK having a frequency (for example, 4 MHz) that is twice the switching frequency (for example, 2 MHz) in the switching regulator 51. The OP amplifier 54 has a voltage follower connection configuration, and an output voltage Vout is applied to its non-inverting input terminal. An output signal Sd corresponding to the output voltage Vout output from the OP amplifier 54 is given to the delay circuit 53.

  The delay circuit 53 divides the input clock signal CLK to output a step-down clock signal CLKD having a frequency that is ½ of the clock signal CLK (2 MHz). Further, the delay circuit 53 outputs a boosted clock signal CLKU delayed by a predetermined delay time Td with respect to the bucked clock signal CLKD. The delay circuit 53 includes a delay time variable unit 55 that varies the delay time Td according to the output voltage Vout.

  As described above, the delay time Td is preferably set to be longer as the output voltage Vout is lower. For this reason, the delay time varying unit 55 of the present embodiment increases the delay time Td as the output voltage Vout decreases, and shortens the delay time Td as the output voltage Vout increases. As a specific configuration of the delay circuit 53 having such a delay time variable unit 55, for example, a configuration as shown in FIG. 10 can be adopted.

  As shown in FIG. 10, the delay circuit 53 includes a D-type flip-flop 56, an inverting buffer 57, a NOR circuit 58, Schmitt trigger type buffers 59 and 60, transistors Q51 to Q54, a resistor R51, and a capacitor C51. . The clock signal CLK is input to the clock terminal CK of the flip-flop 56 and also input to one input terminal of the NOR circuit 58 via the inverting buffer 57.

  The output terminal Q bar of the flip-flop 56 (shown with “−” on Q in FIG. 10) is connected to the input terminal D. A signal output from the output terminal Q of the flip-flop 56 is input to the other input terminal of the NOR circuit 58 and also to the buffer 59.

  The transistors Q51 and Q52 are P-channel MOS transistors, and the transistors Q53 and Q53 are N-channel MOS transistors. Transistors Q51 and Q52 have sources connected to each other and gates connected to each other to form a current mirror circuit. A common source of the transistors Q51 and Q52 is connected to a power supply line 61 to which a power supply voltage Vdd of, for example, 5V is applied. A common gate of the transistors Q51 and Q52 is connected to the drain of the transistor Q51.

  The drain of the transistor Q51 is connected to the drain of the transistor Q53. The source of the transistor Q53 is connected to the ground line 62 via the resistor R61. The drain of the transistor Q52 is connected to the ground line 62 to which the reference potential (0 V) of the circuit is applied via the capacitor C51 and to the input terminal of the buffer 60.

  The input terminal of the buffer 60 is connected to the drain of the transistor Q54. The source of the transistor Q54 is connected to the ground line 62. The output signal of the NOR circuit 58 is given to the gate of the transistor Q54.

  In such a configuration, the output signal of the buffer 59 is a step-down clock signal CLKD having a frequency (2 MHz) that is ½ of the clock signal CLK. A signal obtained by shaping the signal appearing at the terminal of the capacitor C51 by the buffer 60 becomes the boosted clock signal CLKU delayed by the delay time Td with respect to the buck clock signal CLKD.

  In this case, the delay time Td is varied according to the output signal Sd corresponding to the output voltage Vout. That is, according to the level of the output signal Sd, the drain current of the transistor Q52, that is, the current value of the charging current to the capacitor C51 changes. Therefore, the delay time Td of the boost side clock signal CLKU changes according to the output voltage Vout.

  Also by this embodiment described above, the same effect as that of the second embodiment can be obtained. Furthermore, in the present embodiment, the delay circuit 53 includes a delay time variable unit 55 that varies the delay time Td according to the output voltage Vout. The delay time variable unit 55 increases the delay time Td as the output voltage Vout is lower, and shortens the delay time Td as the output voltage Vout is higher. In this way, when the target value of the output voltage Vout, which is unlikely to cause a problem even if the boosting capability is low, is relatively low, the delay time Td becomes long, and the time allocated to the step-down side can be made relatively long. it can. Further, when the target value of the output voltage Vout that needs to increase the boosting capability is relatively high, the delay time Td is shortened, and the time allocated to the boosting side can be relatively long.

(Fourth embodiment)
Hereinafter, a fourth embodiment will be described with reference to FIG.
As a configuration for realizing switching between the step-down operation and the step-up / step-down operation, the VDD monitor 24 and the first boosting operation limiting unit 10 are provided in the first embodiment, and the delay circuit 42 and the second boosting operation limiting unit are configured in the second embodiment. 43 is provided, but these configurations may be combined as in the switching regulator 71 of the present embodiment shown in FIG.

  A switching regulator 71 shown in FIG. 11 is different from the switching regulator 1 of the first embodiment in that a delay circuit 42 is added. The step-up clock signal CLKU output from the delay circuit 42 is input to the set terminal S of the flip-flop 8. Even with such a configuration, since it is possible to perform the same effect as in the first embodiment, that is, switching to an appropriate operation according to the input voltage VDD, the fluctuation of the output voltage Vout and the increase in loss are suppressed. An excellent effect that it can be obtained.

(Other embodiments)
In addition, this invention is not limited to each embodiment described above and described in drawing, In the range which does not deviate from the summary, it can change, combine or expand arbitrarily.
A P-channel MOS transistor may be used as the boost side switching element. The step-down switching element and the step-up switching element are not limited to MOS transistors, and various switching elements such as bipolar transistors and IGBTs can be used. When each switching element is changed, the configurations of the step-down drive unit 9 and the step-up drive unit 11 may be changed so as to correspond to the change.

  The determination method of the offset Vof is not limited to the determination method described above, and can be appropriately changed as long as it can determine the value of the offset Vof that can surely switch between the step-up / step-down operation and the step-up operation. The determination method of the delay time Td is not limited to the determination method described above, and can be appropriately changed as long as it can determine the value of the delay time Td that can surely switch between the step-down operation and the step-up / step-down operation. .

  Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

  DESCRIPTION OF SYMBOLS 1, 41, 51, 71 ... Switching regulator, 2 ... Current detection part, 3 ... Output voltage detection part, 4 ... Error amplification part, 5, 6 ... Comparator, 9 ... Buck side drive part, 10 ... 1st pressure | voltage rise operation restriction | limiting 11, boost side driver, 42, 53 delay circuit, 43 second boost operation limiting unit, 55 delay time variable unit, L 1 inductor, Nd, Nu, interconnection node, Q 1 to Q 4, transistor.

Claims (6)

A switching regulator of a current mode control system that obtains a desired output voltage by switching between a step-down operation for stepping down the input voltage, a step-up / step-down operation for stepping up / down the input voltage, and a step-up operation for stepping up the input voltage (1, 41, 51, 71),
Two step-down switching elements (Q1, Q2) that are switched when performing the step-down operation;
Two boost side switching elements (Q3, Q4) that are switched when performing the boost operation;
An inductor (L1) connected between the interconnection node (Nd) of the two step-down switching elements and the interconnection node (Nu) of the two step-up switching elements;
A current detector (2) for outputting a current detection signal corresponding to the current flowing through the inductor;
An output voltage detector (3) for outputting an output detection voltage corresponding to the output voltage;
An error amplifying unit (4) for outputting an error signal corresponding to a difference between a reference voltage corresponding to a target value of the output voltage and the output detection voltage;
A step-down comparator (5) for comparing the current detection signal and the error signal;
A step-down side drive unit (9) for driving the step-down side switching element based on an output signal of the step-down side comparator and a step-down side clock signal;
A boost side comparator (6) for comparing the current detection signal with a signal obtained by subtracting a predetermined offset from the error signal;
A boost side drive section (11) for driving the boost side switching element based on an output signal of the boost side comparator and a boost side clock signal;
Equipped with a,
The switching regulator further includes a first boosting operation limiting unit (10) that invalidates driving of the boosting side switching element by the boosting side driving unit during a period in which the input voltage is equal to or higher than a predetermined threshold voltage . A switching regulator of a current mode control system that obtains a desired output voltage by switching between a step-down operation for stepping down the input voltage, a step-up / step-down operation for stepping up / down the input voltage, and a step-up operation for stepping up the input voltage (1, 41, 51, 71),
Two step-down switching elements (Q1, Q2) that are switched when performing the step-down operation;
Two boost side switching elements (Q3, Q4) that are switched when performing the boost operation;
An inductor (L1) connected between the interconnection node (Nd) of the two step-down switching elements and the interconnection node (Nu) of the two step-up switching elements;
A current detector (2) for outputting a current detection signal corresponding to the current flowing through the inductor;
An output voltage detector (3) for outputting an output detection voltage corresponding to the output voltage;
An error amplifying unit (4) for outputting an error signal corresponding to a difference between a reference voltage corresponding to a target value of the output voltage and the output detection voltage;
A step-down comparator (5) for comparing the current detection signal and the error signal;
A step-down side drive unit (9) for driving the step-down side switching element based on an output signal of the step-down side comparator and a step-down side clock signal;
A boost side comparator (6) for comparing the current detection signal and a signal obtained by subtracting a predetermined offset from the error signal;
A boost side drive section (11) for driving the boost side switching element based on an output signal of the boost side comparator and a boost side clock signal;
Equipped with a,
further,
A delay circuit (42, 53) for delaying the step-up clock signal by a predetermined delay time with respect to the step-down clock signal;
A second boosting operation limiting unit (43) for invalidating driving of the boosting side switching element by the boosting side driving unit during a period determined based on the delay time;
A switching regulator comprising: 3. The switching according to claim 2 , further comprising a first boosting operation limiting unit (10) that invalidates driving of the boosting side switching element by the boosting side driving unit during a period in which the input voltage is equal to or higher than a predetermined threshold voltage. regulator. The switching regulator according to claim 2 or 3, wherein the delay circuit (53) includes a delay time variable unit (55) that varies the delay time according to the output voltage. The switching regulator according to any one of claims 2 to 4 , wherein the delay time is determined based on a target value of the output voltage.   6. The switching according to claim 1, wherein the offset is determined based on a circuit delay time in the step-down side comparator, the step-down side driving unit, the step-up side comparator, and the step-up side driving unit. regulator.

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