JP6610340B2 - Diodes using group III nitride semiconductors - Google Patents

Description

  The present specification discloses a diode using a laminated structure of a group III nitride semiconductor.

  When a group III nitride semiconductor layer having a large band gap is heterojunctioned to the C plane of the group III nitride semiconductor layer having a small band gap, the range along the C plane in the group III nitride semiconductor layer having a small band gap is A two-dimensional electron gas layer is generated. Patent Document 1 discloses a Schottky diode that uses the two-dimensional electron gas layer. In the technique of Patent Document 1, an anode electrode that is in Schottky contact with a two-dimensional electron gas layer and a cathode electrode that is in ohmic contact with the two-dimensional electron gas layer are used.

When a group III nitride semiconductor layer having a large band gap is heterojunctioned to the C-plane and the minus C-plane of the group III nitride semiconductor layer having a small band gap, the group C nitride is along the C plane in the group III nitride semiconductor layer having a small band gap. A two-dimensional electron gas layer is generated in the range, and a two-dimensional hole gas layer is generated in the range along the minus C plane in the same group III nitride semiconductor layer.
Patent Documents 2 and 3 disclose a technique for forming an FET using a structure in which a layer having a small band gap and a layer having a large band gap are repeatedly stacked.

JP-A-2015-198199 JP 2010-135640 A JP 2013-098284 A

As disclosed in Patent Documents 2 and 3, by repeatedly stacking a layer having a small band gap and a layer having a large band gap, a plurality of two-dimensional electron gas layers and a plurality of two-dimensional hole gas layers can be obtained. It is possible to reduce the resistance.
In Patent Documents 2 and 3, a trench extending deeply from the upper surface of a semiconductor substrate in which a group III nitride semiconductor layer having a small band gap and a group III nitride semiconductor layer having a large band gap are repeatedly stacked is formed. A source electrode and a drain electrode are formed. According to the above structure, the two-dimensional electron gas layer and the two-dimensional hole gas layer generated in the deep part of the semiconductor substrate can be brought into contact with the source electrode and the drain electrode. The resistance of the semiconductor device can be lowered.

  The technology to obtain a plurality of two-dimensional electron gas layers and a plurality of two-dimensional hole gas layers by repeatedly laminating a layer having a small band gap and a layer having a large band gap is also effective for a diode, and can reduce the parasitic resistance of the diode. It becomes possible. In this case, a trench extending deep from the upper surface of the semiconductor substrate is formed, and an anode electrode and a cathode electrode are formed in the trench.

  FIG. 8 attached herewith shows a cross section when a diode is realized using the laminated structure disclosed in Patent Documents 2 and 3. On the upper surface of the support substrate 1 such as a sapphire substrate, a GaN layer having a small band gap and an AlGaN layer having a large band gap are stacked repeatedly. That is, the alternate layer of the GaN layer 2a and the AlGaN layer 3a is laminated on the upper surface of the support substrate 1, the alternate layer of the GaN layer 2b and the AlGaN layer 3b is laminated on the upper surface, and the GaN layer 2c and the AlGaN layer are laminated on the upper surface. 3c of layers are stacked, and a GaN layer 2d is stacked on the top surface. In the following, when describing an event common to the GaN layers 2a, 2b, 2c, and 2d, the alphabet at the end of the reference number is omitted. The same applies to other reference numbers with subscripts. In the case of FIG. 8, the upper surface of the GaN layer 2 is the C plane, and the lower surface is the minus C plane. A two-dimensional electron gas layer 7 is formed in a range along the upper surface of the GaN layer 2 having a small band gap, and a two-dimensional hole gas layer 6 is formed in a range along the lower surface of the GaN layer 2. A trench extending deep from the upper surface of the semiconductor substrate is filled with an anode electrode 26 and a cathode electrode 28. A metal that is in ohmic contact with the two-dimensional hole gas layer 6 is used for the anode electrode 26. According to the structure of FIG. 8, a pn diode formed between the two-dimensional electron gas layer 7a and the two-dimensional hole gas layer 6b, and a pn diode formed between the two-dimensional electron gas layer 7b and the two-dimensional hole gas layer 6b. A diode, a pn diode formed between the two-dimensional electron gas layer 7b and the two-dimensional hole gas layer 6c, a pn diode formed between the two-dimensional electron gas layer 7c and the two-dimensional hole gas layer 6c, A pn diode formed between the two-dimensional electron gas layer 7c and the two-dimensional hole gas layer 6d provides a diode that connects the anode electrode 26 and the cathode electrode 28 in parallel. This reduces the parasitic resistance of the diode.

The structure of FIG. 8 is effective for keeping the parasitic resistance of the diode low, but the two-dimensional electron gas layer 7 is in contact with the anode electrode 26 and the two-dimensional electron hole gas layer 6 is in contact with the cathode electrode 28. As a result, a problem arises in that the reverse leakage current increases.
In this specification, the parasitic resistance can be kept low by repeatedly laminating a group III nitride semiconductor layer having a small band gap and a group III nitride semiconductor layer having a large band gap, and the leakage current in the reverse direction can be reduced. Disclosed is a diode that can be suppressed.

  The diode disclosed in this specification uses a semiconductor substrate in which a group III nitride semiconductor layer having a small band gap and a group III nitride semiconductor layer having a large band gap are repeatedly stacked. The anode electrode of this diode is in contact with each of the two-dimensional hole gas layers and does not contact the two-dimensional electron gas layer, and the cathode electrode is in contact with each of the two-dimensional electron gas layers. The shape is not in contact with the layer.

  According to said structure, the pn diode using a two-dimensional hole gas layer and a two-dimensional electron gas layer is obtained. This diode can suppress the leakage current using a pn barrier. Further, since the anode electrode does not contact the two-dimensional electron gas layer and the cathode electrode does not contact the two-dimensional electron hole gas layer, there is no current path that bypasses the pn barrier. Further, since a plurality of two-dimensional hole gas layers having high carrier mobility and a plurality of two-dimensional electron gas layers having high carrier mobility are used, parasitic resistance can be suppressed to a low level.

  When the anode electrode is formed of a metal that is in Schottky contact with the semiconductor substrate, a diode that uses both a Schottky barrier and a pn barrier can be obtained.

3 is a diagram showing a cross section of the diode of Example 1. FIG. FIG. 6 is a diagram showing a cross section of a diode of Example 2. FIG. 6 is a diagram showing a cross section of a diode of Example 3. FIG. 6 is a diagram showing a cross section of a diode of Example 4; FIG. 6 is a diagram showing a cross section of a diode of Example 5. FIG. 10 is a diagram showing a cross section of a diode of Example 6; FIG. 3 is a diagram showing a manufacturing process of the diode of Example 1. The figure which shows the cross section of the diode obtained by a prior art.

The features of the embodiments described below are listed.
(Feature 1) A stacked structure in which a group III nitride semiconductor layer having a small band gap and a group III nitride semiconductor layer having a large band gap are stacked repeatedly is used.
(Feature 2) The upper surface of each layer forming the layered structure of Feature 1 is exposed.
(Feature 3) An electrode is formed on the exposed surface of Feature 2.
(Feature 4) The distance between the anode electrode and the two-dimensional hole gas layer is less than the distance between the anode electrode and the two-dimensional electron gas layer.
(Feature 5) The distance between the cathode electrode and the two-dimensional hole gas layer is greater than the distance between the cathode electrode and the two-dimensional electron gas layer.
(Feature 6) GaN is used for the group III nitride semiconductor layer having a small band gap, and AlGaN is used for the group III nitride semiconductor layer having a large band gap.
(Feature 7) i-type GaN and i-type AlGaN are used. The i-type here refers to a layer grown without adding a dopant or an acceptor.

Example 1
FIG. 1 shows a cross section of the diode of the first embodiment. Reference numeral 1 denotes a supporting substrate, on which an alternating layer of a group III nitride semiconductor layer 2 having a small band gap and a group III nitride semiconductor layer 3 having a large band gap is laminated repeatedly. That is, the alternate layers of the semiconductor layers 2a and 3a are laminated on the upper surface of the support substrate 1, the alternate layers of the semiconductor layers 2b and 3b are laminated on the upper surface, and the alternate layers of the semiconductor layers 2c and 3c are laminated on the upper surface. A semiconductor layer 2d is laminated on the upper surface.
In this embodiment, a sapphire substrate is used for the support substrate 1, i-type GaN is used for the group III nitride semiconductor layer 2 with a small band gap, and i-type AlGaN is used for the group III nitride semiconductor layer 3 with a large band gap. Use. In this embodiment, the upper surface of the GaN layer 2 is a C plane, and the lower surface is a minus C plane. Alternatively, the upper surface of the GaN layer 2 may be a minus C plane and the lower surface may be a C plane. By selecting the crystal growth method, the upper surface can be the C plane or the upper surface can be the minus C plane. A buffer layer may be provided between the support substrate 1 and the GaN layer 2a.

  In the case of the above laminated structure, the two-dimensional electron gas layer 7 is formed in a range along the C plane (upper surface in this embodiment) of the GaN layer 2 having a small band gap, and the minus C plane (in the embodiment, in the embodiment). A two-dimensional hole gas layer 6 is formed in a range along the lower surface. In the case of FIG. 1, the two-dimensional electron gas layer 7a is generated in the range along the upper surface of the GaN layer 2a, the two-dimensional electron gas layer 7b is generated in the range along the upper surface of the GaN layer 2b, and the upper surface of the GaN layer 2c. The two-dimensional electron gas layer 7c is generated in the range along the GaN layer, the two-dimensional hole gas layer 6b is generated in the range along the lower surface of the GaN layer 2b, and the two-dimensional hole gas layer is formed in the range along the lower surface of the GaN layer 2c. 6c is generated and the two-dimensional hole gas layer 6d is generated in a range along the lower surface of the GaN layer 2d.

  Reference numerals 8b, 8c and 8d denote anode electrodes. The anode electrode 8b is in contact with the exposed upper surface of the GaN layer 2b, the anode electrode 8c is in contact with the exposed upper surface of the GaN layer 2c, and the anode electrode 8d is in contact with the exposed upper surface of the GaN layer 2d. As described above, in this specification, common events will be described by omitting alphabetic suffixes. At the position where the anode electrode 8 is formed, the GaN layer 2 is etched from the upper surface to the vicinity of the lower surface, and the anode electrode 8 is formed on the etched surface. The remaining thickness T1 of the GaN layer 2 is thin, and the two-dimensional electron gas layer 7 is not formed in the remaining thickness range. On the other hand, if the remaining thickness T1 is greater than or equal to a certain distance, the two-dimensional hole gas layer 6 is also formed in the remaining thickness range. If the remaining thickness T1 is too thin, the two-dimensional hole gas layer 6 is depleted. In this embodiment, the thickness T1 is adjusted so that the two-dimensional hole gas layer 6 is not depleted.

  The anode electrode 8 and the two-dimensional hole gas layer 6 are not necessarily in direct contact with each other. In some cases, i-type GaN is interposed between the anode electrode 8 and the two-dimensional hole gas layer 6. Even when i-type GaN is present, the resistance between the anode electrode 8 and the two-dimensional hole gas layer 6 becomes low due to the phenomenon of metal entering the GaN from the anode electrode 8. Even when the anode electrode 8 is formed of a metal that is in Schottky contact with the GaN layer 2, the forward contact resistance between the two is low. In this specification, the anode electrode 8 and the two-dimensional hole gas layer 6 are said to be conducting in a low resistance state. The anode electrode 8b is electrically connected to the two-dimensional hole gas layer 6b, the anode electrode 8c is electrically connected to the two-dimensional hole gas layer 6c, and the anode electrode 8d is electrically connected to the two-dimensional hole gas layer 6d.

The anode electrode 8 and the two-dimensional electron gas layer 7 are insulated. That is, the insulation distance indicated by X1 is ensured between the anode electrode 8b and the two-dimensional electron gas layer 7b, and the insulation distance indicated by X1 is also ensured between the anode electrode 8c and the two-dimensional electron gas layer 7c. The anode electrode 8b and the two-dimensional electron gas layer 7a are insulated by the i-type AlGaN layer 3a. The anode electrode 8c and the two-dimensional electron gas layer 7b are insulated by the i-type AlGaN layer 3b. The anode electrode 8d and the two-dimensional electron gas layer 7c are insulated by the i-type AlGaN layer 3c. In this embodiment, T1 <X1 is established, and the anode electrode 8 and the two-dimensional electron gas layer 7 are in an insulating state with extremely high resistance.
Eventually, the anode electrode 8b is insulated from any of the two-dimensional electron gas layers 7a, 7b, 7c, and is electrically connected to the two-dimensional hole gas layer 6b. The anode electrode 8c is insulated from any of the two-dimensional electron gas layers 7a, 7b, 7c, and is electrically connected to the two-dimensional hole gas layer 6c. The anode electrode 8d is insulated from any of the two-dimensional electron gas layers 7a, 7b, and 7c, and is electrically connected to the two-dimensional hole gas layer 6d.

  Reference numerals 9a, 9b, and 9c denote cathode electrodes. The cathode electrode 9a is in contact with the exposed upper surface of the AlGaN layer 3a, the cathode electrode 9b is in contact with the exposed upper surface of the AlGaN layer 3b, and the cathode electrode 9c is in contact with the exposed upper surface of the AlGaN layer 3c. In the present specification, common events will be described by omitting alphabetic subscripts. At the position where the cathode electrode 9 is formed, the AlGaN layer 3 is etched from the upper surface to the vicinity of the lower surface, and the cathode electrode 9 is formed on the etched surface. The remaining thickness T2 of the AlGaN layer 3 is moderately thin. If the remaining thickness T2 is too thin, the two-dimensional electron gas layer 7 is depleted from the vicinity of the upper surface of the GaN layer 2 in the range where it is heterojunction with the AlGaN layer 3 that is too thin. In this embodiment, the thickness T2 is adjusted so that the two-dimensional electron gas layer 7 is not depleted.

  In this case, the cathode electrode 9 faces the two-dimensional electron gas layer 7 through the AlGaN layer 3 having a thickness T2. Even if the i-type AlGaN layer 3 is interposed between the cathode electrode 9 and the two-dimensional gas layer gas layer 7, the cathode electrode 9 and the two-dimensional electrons are caused by a phenomenon such as a metal entering the AlGaN layer 3 from the cathode electrode 9. The resistance between the gas layers 7 is low. In the present specification, a state where the cathode electrode 9 and the two-dimensional electron gas layer 7 are in a low resistance state is referred to as being conductive.

The cathode electrode 9 and the two-dimensional hole gas layer 6 are not in contact with each other. That is, an insulation distance indicated by X2 is ensured between the cathode electrode 9a and the two-dimensional hole gas layer 6b, and an insulation distance indicated by X2 is also ensured between the cathode electrode 9b and the two-dimensional hole gas layer 6c. An insulation distance indicated by X2 is also secured between 9c and the two-dimensional hole gas layer 6d. In the present embodiment, the relationship of T2 <X2 is satisfied, and the cathode electrode 9 and the two-dimensional electron gas layer 6 are in an insulating state with extremely high resistance.
Eventually, the cathode electrode 9a is insulated from any of the two-dimensional hole gas layers 6b, 6c, 6d and is electrically connected to the two-dimensional electron gas layer 7a. The cathode electrode 9b is insulated from any of the two-dimensional hole gas layers 6b, 6c, 6d and is electrically connected to the two-dimensional electron gas layer 7b. The cathode electrode 9c is insulated from any of the two-dimensional hole gas layers 6b, 6c, 6d and is electrically connected to the two-dimensional electron gas layer 7c.

  Reference numeral 4 indicates a pn diode formed between the GaN layer 2 on the upper surface side of the AlGaN layer 3 and the GaN layer 2 on the lower surface side. That is, reference numeral 4a indicates a pn diode formed between the GaN layer 2b and the GaN layer 2a, reference numeral 4b indicates a pn diode formed between the GaN layer 2c and the GaN layer 2b, and reference numeral 4c indicates A pn diode formed between the GaN layer 2d and the GaN layer 2c is shown. Reference numeral 5 indicates a pn diode formed in the GaN layer 2. That is, reference numeral 5b indicates a pn diode formed in the GaN layer 2b, and reference numeral 5c indicates a pn diode formed in the GaN layer 2c. Each diode is a pn diode that uses the two-dimensional hole gas layer 6 in contact with the anode electrode 8 as an anode and cathodes the two-dimensional electron gas layer 7 in contact with the cathode electrode 9. According to the structure of FIG. 1, it can be seen that a pn diode having the two-dimensional hole gas layer 6 as an anode and the two-dimensional electron gas layer 7 as a cathode is formed.

In the diode of FIG. 8, a total of six carrier paths exist between the anode electrode 26 and the cathode electrode 28. That is, each of the two-dimensional electron gas layers 7a, 7b, 7c and the two-dimensional hole gas layers 6b, 6c, 6d connects between the anode electrode 26 and the cathode electrode 28. Even if the anode electrode 26 is a Schottky electrode, the leakage current is large.
In the diode of FIG. 1, the following carrier path exists between the anode electrode 8 and the cathode electrode 9.
(1) a series circuit of a two-dimensional hole gas layer 6b and a two-dimensional electron gas layer 7a to be the diode 4a;
(2) a series circuit of a two-dimensional hole gas layer 6b and a two-dimensional electron gas layer 7b to be the diode 5b;
(3) a series circuit of a two-dimensional hole gas layer 6c and a two-dimensional electron gas layer 7b to be the diode 4b;
(4) a series circuit of a two-dimensional hole gas layer 6c and a two-dimensional electron gas layer 7c to be the diode 5c;
(5) a series circuit of a two-dimensional hole gas layer 6d and a two-dimensional electron gas layer 7c to be the diode 4c;
Each carrier path has a pn barrier, and the leakage current can be kept low.

  The anode electrode 8 may be in ohmic contact with the GaN layer 2 or may be in Schottky contact with the GaN layer 2. In the latter case, a diode in which a pn diode that cathodes the two-dimensional electron gas layer 7 with the two-dimensional hole gas layer 6 as an anode and a Schottky diode that uses a Schottky contact between the anode electrode and the semiconductor substrate is combined. It becomes.

  The diode shown in FIG. 1 has a structure in which pn diodes 4a, 4b, 4c, 5b, and 5c exist between the anode electrode 8 and the cathode electrode 9. The pn diode keeps the leakage current low. Further, since the plurality of two-dimensional electron gas layers 7a, 7b, and 7c and the plurality of two-dimensional hole gas layers 6b, 6c, and 6d provide a carrier moving path, the parasitic resistance is low.

(Example 2)
In the following, only the differences from the previously described embodiments will be described. The same reference numerals are used for members that are the same as or equivalent to those already described, and redundant descriptions are omitted.
In Example 2 shown in FIG. 2, one continuous anode electrode 8 and cathode electrode 9 common to a plurality of layers are used. Therefore, the insulators 10 and 12 are used in the second embodiment.
The insulator 10a insulates the anode electrode 8 and the two-dimensional electron gas layer 7b, and the insulator 10b insulates the anode electrode 8 and the two-dimensional electron gas layer 7c. The insulator 10c can be omitted. The two-dimensional electron gas layer 7a is insulated from the anode electrode 8 by the i-type AlGaN layer 3a.
The insulator 12a insulates the cathode electrode 9 and the two-dimensional hole gas layer 6b, the insulator 12b insulates the cathode electrode 9 and the two-dimensional hole gas layer 6c, and the insulator 12c includes the cathode electrode 9 and the two-dimensional hole gas layer 6d. Insulate.
Also according to the above, the anode electrode 8 is electrically connected to the two-dimensional hole gas layers 6b, 6c, 6d and insulated from the two-dimensional electron gas layers 7a, 7b, 7c, and the cathode electrode 9 is connected to the two-dimensional electron gas layers 7a, 7b, It is possible to obtain a structure that is electrically connected to 7c and insulated from the two-dimensional hole gas layers 6b, 6c, and 6d.

Example 3
As shown in FIG. 3, in Example 3, the anode electrode 8 is provided in the trench 14, and the cathode electrode 9 is provided in the trench 16. The trench 14b is deep and faces the AlGaN layer 3a through the GaN layer 2b having a thickness T1. The trench 14c is shallow and faces the AlGaN layer 3b through the GaN layer 2c having a thickness T1. The trench 14d is shallower and faces the AlGaN layer 3c through the GaN layer 2d having a thickness T1. The trench 16a is deep and faces the GaN layer 2a through the AlGaN layer 3a having a thickness T2. The trench 16b is shallow and faces the GaN layer 2b through the AlGaN layer 3b having a thickness T2. The trench 16c is shallower and faces the GaN layer 2c through the AlGaN layer 3c having a thickness T2.
The thicknesses T1, T2, X1, and X2 are those described in the first embodiment. The distance X3 is a distance between the anode electrode 8 and the two-dimensional electron gas layer 7 existing outside thereof, and is substantially equal to X1. The distance X4 is a distance between the cathode electrode 9 and the two-dimensional hole gas layer 6 existing outside thereof, and is substantially equal to X2. The embodiment of FIG. 3 has almost the same performance as the embodiment of FIG.

(Example 4)
As shown in FIG. 4, in Example 4, the upper surface of the semiconductor substrate is an inclined upper surface, and a part of each of the GaN layers 2a, 2b, 2c, 2d and the AlGaN layers 3a, 3b, 3c is exposed on the inclined upper surface. It is related.
The anode electrode 8 is in contact with the upper surface side of the AlGaN layer 3 and the lower surface side of the GaN layer 2 on the inclined upper surface. The anode electrode 8 is in contact with the two-dimensional hole gas layer 6 formed along the lower surface of the GaN layer 2. The thickness T3 is the maximum thickness of the GaN layer 2 in the range in contact with the anode electrode 8. The thickness T3 is set to be equal to or greater than the thickness at which the two-dimensional hole gas layer 6 exists in the GaN layer 2 located below the anode electrode 8. The distance L1 is a creeping distance from the two-dimensional electron gas layer 7 positioned above the range where the anode electrode 8 and the inclined upper surface are in contact to the anode electrode 8. T3 <L1, and a sufficient insulation distance is ensured between the range where the anode electrode 8 and the inclined upper surface are in contact with the two-dimensional electron gas layer 7 positioned above the range. The thickness T4 is a thickness at which the anode electrode 8 and the AlGaN layer 3 overlap, and the thickness T5 is a thickness from the lower end of the anode electrode 8 to the two-dimensional electron gas layer 7 existing below the anode electrode 8. If the relationship of thickness T4 <T5 is satisfied, a sufficient insulation distance can be ensured between the lower end of the anode electrode 8 and the two-dimensional electron gas layer 7 located below the anode electrode 8.

In the relationship of FIG. 4, the anode electrode 8 is in contact with the two-dimensional hole gas layer 6, and the upper two-dimensional electron gas layer 7 is separated by a creepage distance L1 necessary for insulation, and the lower two-dimensional electron gas layer 7 is separated. The electron gas layer 7 is separated by a thickness T5 necessary for insulation. The anode electrode 8 is electrically connected to the two-dimensional hole gas layer 6 and is insulated from the two-dimensional electron gas layer 7.
The thickness T4 may be zero. Even if the thickness T4 is zero, the anode electrode 8 and the two-dimensional hole gas layer 6 can be electrically connected.

The cathode electrode 9 is also in contact with the inclined upper surface. The cathode electrode 9 is in contact with the upper surface side of the GaN layer 2 and the lower surface side of the AlGaN layer 3. The thickness T7 is a thickness at which the cathode electrode 9 and the GaN layer 2 overlap, and the two-dimensional electron gas layer 7 exists in the overlapping thickness. The cathode electrode 9 is in contact with the two-dimensional electron gas layer 7 formed along the upper surface of the GaN layer 2. The thickness T6 is the maximum thickness of the AlGaN layer 3 within a range in contact with the cathode electrode 9. The thickness T6 is set to be equal to or greater than the thickness at which the two-dimensional electron gas layer 7 exists in the range along the upper surface of the GaN layer 2 located below the cathode electrode 9. The distance L2 is a creeping distance from the two-dimensional hole gas layer 6 located above the range where the cathode electrode 9 and the inclined upper surface are in contact to the cathode electrode 9. T6 <L2, and a sufficient insulation distance is ensured between the range where the cathode electrode 9 and the inclined upper surface are in contact with the two-dimensional hole gas layer 6 positioned above it. The thickness T8 is a thickness from the lower end of the cathode electrode 9 to the two-dimensional hole gas layer 6 existing below the cathode electrode 9. If the relationship of thickness T7 <T8 is satisfied, a sufficient insulation distance can be ensured between the lower end of the cathode electrode 9 and the two-dimensional hole gas layer 6 positioned therebelow.
The thickness T7 may be zero. Even if the thickness T7 is zero, the cathode electrode 9 and the two-dimensional electron gas layer 7 can be conducted.

  In the relationship of FIG. 4, the cathode electrode 9 is electrically connected to the two-dimensional electron gas layer 7, and the upper two-dimensional hole gas layer 6 is separated by a creepage distance L2 required for insulation, and the lower two-dimensional electron gas layer 6 is separated. The hole gas layer 6 is separated by a thickness T8 necessary for insulation. The cathode electrode 9 is electrically connected to the two-dimensional electron gas layer 7 and is insulated from the two-dimensional hole gas layer 6.

(Example 5)
Example 5 shown in FIG. 5 corresponds to an example in which the inclined upper surface of Example 4 and the insulator of Example 2 are combined. Reference numeral 18 is an insulator (for example, SiO ₂ ) formed on the inclined upper surface, and locally insulates between the inclined upper surface and the anode electrode 8. Reference numeral 20 is also an insulator formed on the inclined upper surface, and locally insulates between the inclined upper surface and the cathode electrode 9.
Also according to the above, the anode electrode 8 is in contact with the two-dimensional hole gas layer 6 and insulated from the two-dimensional electron gas layer 7, and the cathode electrode 9 is in contact with the two-dimensional electron gas layer 7 and insulated from the two-dimensional hole gas layer 6. Can get a relationship. The insulators 18 and 20 may be formed in a local range, or may be formed on the inclined upper surface and then removed locally. The insulators 18d and 20a can be omitted.

(Example 6)
Example 6 shown in FIG. 6 uses regions 22 and 24 in which ions are implanted into a semiconductor substrate. The region 22 is a region where the generation of the two-dimensional electron gas layer 7 is inhibited by the implanted ions. The region 24 is a region where the generation of the two-dimensional hole gas layer 6 is inhibited by the implanted ions. Also according to the above, the anode electrode 8 is in contact with the two-dimensional hole gas layer 6 and insulated from the two-dimensional electron gas layer 7, and the cathode electrode 9 is in contact with the two-dimensional electron gas layer 7 and insulated from the two-dimensional hole gas layer 6. Can get a relationship. The semiconductor may be insulated by implanting ions such as iron into the regions 22 and 24.

(Manufacturing method of Example 1)
FIG. 7 shows a manufacturing method of the diode of the first embodiment.
(1) shows a stage in which the GaN layer 2a, the AlGaN layer 3a, the GaN layer 2b, the AlGaN layer 3b, the GaN layer 2c, the AlGaN layer 3c, and the GaN layer 2d are epitaxially grown in order on the upper surface of the support substrate 1.
(2) shows a state where the etching is finished at a stage where a part of the left side of the GaN layer 2d is etched to leave only the GaN layer 2d having a thickness T1 (see FIG. 1). For the etching, for example, chlorine-based dry etching can be used.
(3) shows a state in which the left side region is further etched, the GaN layer 2d and the AlGaN layer 3c are removed, and the etching is completed when only the GaN layer 2c having the thickness T1 is left.
(4) shows a state in which the left region is further etched, the GaN layer 2c and the AlGaN layer 3b are removed, and the etching is finished at the stage where only the GaN layer 2b having the thickness T1 is left.
(5) shows a state in which the etching is finished at a stage where the right part of the GaN layer 2d is etched, the GaN layer 2d is removed, and only the AlGaN layer 3c having a thickness T2 (see FIG. 1) is left.
(6) shows a state in which the etching is finished at the stage where the right region is further etched, the AlGaN layer 3c and the GaN layer 2c are removed, and only the AlGaN layer 3b having a thickness T2 is left.
(7) shows a state in which the etching is finished when the right region is further etched, the AlGaN layer 3b and the GaN layer 2b are removed, and only the AlGaN layer 3a having a thickness T2 is left.
Although not shown, the anode electrode 8 is formed on the upper surface of the GaN layer 2 having the thickness T1 generated in the step portion formed through the steps (1) to (7), and the AlGaN layer 3 having the thickness T2 generated in the step portion is formed. If the cathode electrode 9 is formed on the upper surface, the diode of Example 1 can be manufactured. When forming the anode electrode 8, an electrode material made of nickel and gold is vapor-deposited and heat-treated in an oxygen atmosphere. As a result, an electrode in ohmic contact with the hole is obtained. The cathode electrode 9 is vapor-deposited with an electrode material made of titanium and aluminum and heat-treated in a nitrogen atmosphere. This provides an electrode that is in ohmic contact with the electrons.

When forming the inclined upper surface shown in FIG. 4, a resist film is formed on the upper surface of the substrate of FIG. At that time, a resist film is formed in which the thickness of the resist film is thick at the center and becomes thinner as it approaches the left and right. A resist film having an inclined upper surface can be manufactured by a known method. In this state, etching is performed from the upper surface of the resist film. Etching is performed under conditions for etching up to the resist film. Then, the etching of the substrate does not proceed at the central portion of the substrate covered with the thick resist film, and the upper surface of the substrate is maintained at a high height. On the other hand, the etching of the substrate proceeds at the left and right portions of the substrate covered with the thin resist film, and the upper surface of the substrate is lowered. In this way, an inclined upper surface can be formed.
In this example, the case of heterojunction of GaN and AlGaN has been described. However, GaN, InN, AlN, or a mixed crystal thereof can be used for a group III nitride semiconductor, and the band gap can be increased or decreased in various combinations. A heterojunction can be realized.

  As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

  The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

1: Support substrate (sapphire substrate in this embodiment)
2: Group III nitride semiconductor layer having a small band gap (i-type GaN layer in this embodiment)
3: Group III nitride semiconductor layer having a large band gap (i-type AlGaN layer in this embodiment)
4: A pn diode formed between the GaN layer on the upper surface side and the GaN layer on the lower surface side of the AlGaN layer.
5: A pn diode formed between the vicinity of the upper surface and the lower surface of the GaN layer.
6: two-dimensional hole gas layer 7: two-dimensional electron gas layer 8: anode electrode 9: cathode electrode 10, 12: insulator 14, 16: trench 18, 20: insulator 22, 24: insulator

Claims (2)

A semiconductor substrate in which a group III nitride semiconductor layer having a small band gap and a group III nitride semiconductor layer having a large band gap are laminated repeatedly;
It has an anode electrode and a cathode electrode in contact with the semiconductor substrate,
The anode electrode is electrically conductive in a range along the minus C plane of the group III nitride semiconductor layer having a small band gap and insulated from the range along the C plane;
The cathode electrode is electrically conductive in a range along the C plane of the group III nitride semiconductor layer having a small band gap and insulated from the range along the negative C plane;
diode.   The diode according to claim 1, wherein the anode electrode is in Schottky contact with the semiconductor substrate.

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