JP6605866B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to inspection and analysis techniques thereof.

  1A to 1C are schematic views showing a semiconductor device 300. FIG. FIG. 1A is an external perspective view of a semiconductor device 300 of a lead frame package. The semiconductor device 300 includes a resin 312 that seals a semiconductor chip (also referred to as a chip or a die) and a plurality of lead terminals (pins) 308 drawn from the resin 312.

  In recent years, a multi-chip package in which a plurality of semiconductor chips are built in one package may be employed as the function of the semiconductor device 300 increases. FIG. 1B is a plan view showing the internal structure of the semiconductor device 300 of the multichip package. Circuit elements such as transistors, wirings, and resistors are integrated in element formation regions of the plurality of semiconductor chips 302a and 302b, and a plurality of I / O pads 304 are provided in an I / O region on the outer periphery of the semiconductor chip 302. Is formed.

  FIG. 1C is a cross-sectional view of a multi-chip package semiconductor device 300. The plurality of semiconductor chips 302a and 302b are mounted on the island 309 (die bonding). Each I / O pad 304 of the semiconductor device 300 is electrically connected to the corresponding lead terminal 308 via a bonding wire 310.

  The pads of the plurality of semiconductor chips 302a and 302b are connected via interchip wires 306. After the wire bonding process, the semiconductor device 300 is sealed with a resin 312. As for the semiconductor device 300, normal products are selected through inspection of electrical characteristics and shipped.

JP 2004-028885 A

  When wire bonding the bonding wires 310 and 306, mechanical stress and damage are applied to the pad 304 and its peripheral circuit elements, which may cause manufacturing defects. Since the bonding wire 310 connected to the lead terminal 308 can be accessed from the outside via the lead terminal 308, a mounting defect of the bonding wire 310 can be detected.

  On the other hand, the inter-chip wire 306 that connects the plurality of semiconductor chips 302 a and 302 b cannot be directly accessed from the turning part via the lead terminal 308. Therefore, when any defect is detected in the semiconductor device 300, it cannot be determined whether the defect is caused by the defect of the inter-chip wire 306 or other defect. Such problems should not be regarded as a general recognition of those skilled in the art. This problem may occur not only in the lead frame package but also in other shapes of multi-chip packages in which chips are connected by wires.

  The present invention has been made in view of such a problem, and one of exemplary objects of an embodiment thereof is to provide a semiconductor device capable of detecting a wiring defect between chips in a multichip package.

  One embodiment of the present invention relates to a semiconductor device of a multichip package. The semiconductor device includes a plurality of input / output pins, a plurality of first pads for interchip connection, a first semiconductor chip configured to be able to supply a test signal to each of the plurality of first pads, and for interchip connection A plurality of second pads, a third pad electrically connected to a test pin that is one of a plurality of input / output pins, and a plurality of signals generated on the plurality of second pads, and one is selected and the third pad is selected. A second semiconductor chip having a first selector that outputs to a pad, each corresponding to one of the plurality of first pads of the first semiconductor chip, and one of the plurality of second pads of the second semiconductor chip; And a plurality of inter-chip wirings connected to each other.

  In the test process, the first selector selects one signal from the plurality of second pads, generates a test signal on the first pad corresponding to the selected second pad, and monitors the state of the test pin. If the chip-to-chip wiring between the selected second pad and the corresponding first pad is normal, a signal corresponding to the test signal is observed on the test pin. If the inter-chip wiring between the selected second pad and the corresponding first pad is abnormal or the peripheral circuit is damaged, a signal corresponding to the test signal is not generated on the test pin. . According to this aspect, it is possible to detect a defect in the interchip wiring.

The second semiconductor chip may further include at least one fourth pad, each connected to a corresponding one of the first pads of the first semiconductor chip via inter-chip wiring. The first selector may be controlled according to the signal of at least one fourth pad.
In this case, the first selector can be controlled in accordance with a control signal supplied to the fourth pad in the first semiconductor chip.

The first semiconductor chip connects a plurality of fifth pads electrically connected to a plurality of input pins included in the plurality of input / output pins, and each of the plurality of first pads to a corresponding one of the plurality of fifth pads. And a second selector capable of selecting a first state to be connected and a second state in which each of the plurality of first pads is connected to a first functional circuit formed in the first semiconductor chip. Good.
In this case, by setting the second selector to the first state, it is possible to input test signals and / or control signals from the outside to the plurality of input pins.

The first semiconductor chip includes a plurality of fifth pads electrically connected to a plurality of input pins included in the plurality of input / output pins, and a selected one of the plurality of first pads as a predetermined number of the fifth pads. A third selector capable of selecting a first state connected to one of the first state and a second state where each of the plurality of first pads is connected to a first functional circuit formed in the first semiconductor chip; You may have.
In this case, a test signal and / or a control signal can be input to an input pin connected to a predetermined one of the fifth pads.

In one aspect, a first semiconductor chip includes a test control circuit that generates a test signal, a first state that supplies a test signal to a selected one of the plurality of first pads, and each of the plurality of first pads. You may further have the 4th selector which can select the 2nd state connected with the 1st functional circuit formed in 1 semiconductor chip.
By incorporating the test control circuit in the first semiconductor chip, it is not necessary to input a test signal / control signal to the input pin, and automatic inspection becomes possible.

  In some embodiments, the plurality of inter-chip wirings may include bonding wires. Thereby, the mounting defect of a bonding wire can be detected.

  In one embodiment, an audio signal processing circuit that processes a digital audio signal and generates a pulse audio signal that is pulse-modulated according to the audio signal is formed in the first semiconductor chip, and the pulse audio signal is amplified in the second semiconductor chip. A class D amplifier may be formed.

In one aspect, the first semiconductor chip sequentially selects a plurality of buffers that generate a high level voltage or a low level voltage on a plurality of first pads, and a plurality of buffers, and selects the high level voltage for the selected one, and the rest A test control circuit that generates a low level voltage and stops the first functional circuit included in the first semiconductor chip and the second functional circuit included in the second semiconductor chip may be further included.
A large leakage current flows when the chip-to-chip wiring connected to the first pad where the high level voltage is generated is short-circuited with the adjacent first pad where the low level voltage is generated. Therefore, a mounting failure can be detected by measuring the current of the power supply pin connected to the power supply terminal of the first semiconductor chip.

  Another embodiment of the present invention is also a semiconductor device. This device is a semiconductor device of a multi-chip package, and a high level voltage or a low level voltage is applied to a plurality of input / output pins, a plurality of first pads for interchip connection, a first functional circuit, and a plurality of first pads. A first semiconductor chip having a plurality of buffers, and a plurality of second pads for inter-chip connection and a second semiconductor chip having a second functional circuit, each of which is a plurality of first semiconductor chips. And a plurality of inter-chip wirings that connect one corresponding pad to one corresponding plurality of second pads of the second semiconductor chip. The first semiconductor chip includes a test control circuit that sequentially selects a plurality of buffers, generates a high level voltage in the selected one, and generates a low level voltage in the remaining one, and stops the first functional circuit and the second functional circuit. Also have.

  A large leakage current flows when the chip-to-chip wiring connected to the first pad where the high level voltage is generated is short-circuited with the adjacent first pad where the low level voltage is generated. Therefore, a mounting failure can be detected by measuring the current of the power supply pin connected to the power supply terminal of the first semiconductor chip.

  It should be noted that any combination of the above-described constituent elements and the expression of the present invention converted between methods, apparatuses, etc. are also effective as an aspect of the present invention.

  According to an aspect of the present invention, it is possible to detect a wiring defect between chips in a multichip package.

1A to 1C are schematic diagrams illustrating a semiconductor device. 1 is a circuit diagram of a semiconductor device according to a first embodiment. It is an equivalent circuit diagram of the semiconductor device in a test mode. FIG. 6 is a circuit diagram of a semiconductor device according to a second embodiment. FIG. 6 is a circuit diagram of a semiconductor device according to a third embodiment. FIG. 6 is a circuit diagram of a semiconductor device according to a fourth embodiment. FIG. 7 is an equivalent circuit diagram in the inspection process of the semiconductor device of FIG. 6. It is a circuit diagram of an audio signal processing circuit including a semiconductor device.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

(First embodiment)
FIG. 2 is a circuit diagram of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 is a multi-chip package, and includes a plurality of input / output pins (I / O pins) 30, a first semiconductor chip 2 and a second semiconductor chip 4, a plurality of inter-chip wirings WI, and a plurality of connection means WE. .

  The first semiconductor chip 2 mainly includes a plurality of fifth pads Pd5, a first functional circuit 20, and a plurality of first pads Pd1 for inter-chip connection. The plurality of fifth pads Pd5 are electrically connected to the plurality of input pins Pe1 among the plurality of I / O pins 30. The connection means WE for the pad Pd and the pin Pe is not particularly limited, and may be a bonding wire, a rewiring, a bump, a via hole, or a combination thereof.

  The first functional circuit 20 inputs / outputs signals from / to the outside via the fifth pad Pd5 and performs predetermined signal processing. The function of the first functional circuit 20 is not particularly limited, and may include an analog circuit, a digital circuit, and an analog / digital mixed circuit depending on the application of the semiconductor device 1.

  The first semiconductor chip 2 is configured to be able to supply a test signal S1 to each of the plurality of first pads Pd1. The first semiconductor chip 2 includes a second selector 22 and a test control circuit 24 in order to generate the test signal S1 at the plurality of first pads Pd1.

The semiconductor device 1 can be switched between a test mode and a normal mode.
The second selector 22 connects each of the plurality of first pads Pd1 to the corresponding one of the plurality of fifth pads Pd5, and connects each of the plurality of first pads Pd1 to the first functional circuit 20. The second state φ2 is configured to be switchable. The test control circuit 24 sets the first semiconductor chip 2 to the first state φ1 in the test mode, and sets the first semiconductor chip 2 to the second state φ2 in the normal mode. The second selector 22 in FIG. 2 indicates the second state φ2. Note that a buffer (also referred to as a transmitter or a level shifter) capable of driving a transmission line including the first pad Pd1, the inter-chip wiring WI, and the second pad Pd2 (fourth pad Pd4) is provided at the output stage or the subsequent stage of the second selector 22. Is provided here, but is omitted here.

  The second semiconductor chip 4 includes a plurality of second pads Pd2, one or more fourth pads Pd4, a second functional circuit 40, a first selector 42, and a third pad Pd3. The plurality of second pads Pd2 and fourth pads Pd4 are provided for interchip connection. The plurality of inter-chip wirings WI electrically connect the second pad Pd2 and the fourth pad Pd4 to the corresponding first pad Pd1. The interchip wiring WI is, for example, a bonding wire.

  The second functional circuit 40 receives a signal from the first semiconductor chip 2 and performs predetermined signal processing in a normal operation state. The function of the second functional circuit 40 is not particularly limited, and may include an analog circuit, a digital circuit, and an analog / digital mixed circuit depending on the application of the semiconductor device 1.

The third pad Pd3 is electrically connected to a test pin (TEST) that is one of the plurality of I / O pins 30. The first selector 42 receives a plurality of test signals generated in the plurality of second pads Pd2 in the test mode, selects one and outputs it to the third pad Pd3. The first selector 42 is controlled according to a control signal for at least one fourth pad Pd4. The fourth pad Pd4 may be provided according to the number of the plurality of second pads Pd2 to be inspected. For example, if there are two second pads Pd2, one fourth pad Pd4, four second pads Pd2, two fourth pads Pd4, and eight second pads Pd2, the second pad Pd2 fourth pad Pd4 when ^{the 2 N} is N pieces required.

  In addition, a power supply voltage is supplied to a power supply pin (VDD) that is one of the I / O pins 30, and a ground voltage is supplied to another power supply pin (VSS) and a ground pin (GND). Further, another output pin (OUT) is provided for outputting a signal generated by the second functional circuit 40.

  The above is the configuration of the semiconductor device 1. Next, the operation in the inspection process will be described. In the inspection process, the test control circuit 24 sets the second selector 22 to the first state φ1. Accordingly, the test signal S1 can be input to the first selector 42 from a part of the plurality of input pins Pe1 via the first pad Pd1 and the second pad Pd2. Further, the first selector 42 can be controlled according to the control signal S2 input to a part of the input pin Pe1.

FIG. 3 is an equivalent circuit diagram of the semiconductor device 1 in the test mode. When inspecting whether or not the i-th (i = 1, 2,... N) inter-chip wiring WI is mounted, the first selector 42 is controlled by the control signal S2, and the i-th second pad Pd2 _i and the third pad Connect Pd3. In this state, with respect to the input pin Pe1 _i corresponding to the second pad Pd2 _i, inputting a test signal S1. At this time, if the inter-chip wiring WI _i is normal, a signal corresponding to the test signal S1 is observed on the TEST pin, and if the inter-chip wiring WI _i has a mounting failure, the test signal S1 is observed on the TEST pin. Not. By repeating the same process while switching the inter-chip wire WI of the test object, it is possible to inspect the mounting failure between the plurality of chip line WI ₁ ~WI _N.

In addition, it is possible to detect mounting defects for the inter-chip wiring WI connected to the fourth pad Pd4. For example, a plurality of test signals S1 are supplied to the plurality of input pins Pe1 _{1 to} Pe1 _N , and the control signal S2 is changed in this state. Based on the combination of the control signal S2 and the signal observed at the TEST pin, it can be determined whether the first selector 42 is operating normally according to the control signal S2. That is, it is possible to detect a mounting failure of the inter-chip wiring WI connected to the fourth pad Pd4.

(Second Embodiment)
FIG. 4 is a circuit diagram of the semiconductor device 1a according to the second embodiment. The first semiconductor chip 2 a includes a third selector 26 instead of the second selector 22. The third selector 26 can switch between the first state φ1 and the second state φ2. The second state φ2 is the same as the second state φ2 of the second selector 22.

The third selector 26, among the plurality of first pads Pd1 in the first state .phi.1, selects one indicated by the test control circuit 24 is connected to a predetermined one Pd5 _N of the plurality of fifth pad Pd5.

The above is the configuration of the semiconductor device 1a. In the second embodiment, for one fifth pad Pd5 _N, and inputs a test signal S1. Then, the test signal S1 is supplied to one of the plurality of first pads Pd1 _{1 to} Pd1 _N by the third selector 26. Also by this semiconductor device 1a, the same effect as in the first embodiment can be obtained.

(Third embodiment)
FIG. 5 is a circuit diagram of the semiconductor device 1b according to the third embodiment. The first semiconductor chip 2 b includes a fourth selector 28 instead of the second selector 22 or the third selector 26. The test control circuit 24 generates a test signal and a control signal for the first selector 42 in the test mode.

  The fourth selector 28 includes a first state φ1 for supplying the test signal S1 to a selected one of the plurality of first pads Pd1, and a plurality of first pads Pd1 formed on the first semiconductor chip 2 respectively. The second state φ2 connected to the one-function circuit 20 can be selected.

  That is, in the third embodiment, instead of inputting the test signal S1 and the control signal S2 from the outside, the test control circuit 24 generates the test signal S1 and the control signal S2. Thereby, it is not necessary to input the test signal S1 and the control signal S2 to the input pin Pe1, and an automatic inspection can be performed.

(Fourth embodiment)
FIG. 6 is a circuit diagram of a semiconductor device 1c according to the fourth embodiment. The features described in the fourth embodiment may be used in combination with the first to third embodiments, or may be used alone.

The first semiconductor chip 2c includes a plurality of buffers B1 in addition to the first functional circuit 20. Each buffer B1 generates a high level voltage V _H or a low level voltage V _L at the corresponding first pad Pd1 according to the input test signal S1. The method of supplying the test signal S1 to the buffer B1 can take any of the forms shown in the first to third embodiments.

  The circuit format of the buffer B1 is not particularly limited, and can be composed of a CMOS inverter circuit, a level shifter, a transmitter, and the like.

The test control circuit 24 sequentially selects a plurality of buffers B1 _{1 to} B1 _N , generates a high level voltage V _H (= V _DD ) in the selected one, and generates a low level voltage V _L (= V _SS ) in the remaining one. Let The test control circuit 24 stops the first functional circuit 20 included in the first semiconductor chip 2 and the second functional circuit 40 included in the second semiconductor chip 4.

  The above is the configuration of the semiconductor device 1c. Next, the operation will be described.

FIG. 7 is an equivalent circuit diagram in the inspection process of the semiconductor device 1c of FIG. In the inspection process, the semiconductor device 1 is supplied with the power supply voltage V _DD and the ground voltage V _SS . The i-th inter-chip wiring WI _i is an inspection target. At this time, the high-side transistor MH of the i-th buffer B1 _i is turned on and the low-side transistor ML is turned off, and a high level voltage V _H (= V _DD ) is generated at the first pad Pd1 _i . On the other hand, the high-side transistor MH of the adjacent (i + 1) th buffer B1 _{i + 1} is turned off and the low-side transistor ML is turned on, so that a low level voltage V _L (= V _SS ) is generated at the first pad Pd1 _{i + 1} . The first function circuit 20 and the second function circuit 40 are stopped, and the consumption currents I _DD1 and I _DD2 are set to zero.

(Normal state)
First, the case where the first semiconductor chip 2 and the second semiconductor chip 4 are normal and the inter-chip wiring WI _i is normal will be described. At this time, the input impedance of the receiving circuit RX _i on the second semiconductor chip 4 side is very high. If the inter-chip wiring WI _i is normal, the first pad Pd1 _i is high impedance, and _{therefore the} current I _Bi1 flowing through the buffer B1 _i is substantially zero. For the other buffers B1 _j (j ≠ i), the current IB1 _j is substantially zero because the high-side transistor MH is off. Therefore, at the normal time, the current I _TOTAL flowing through the semiconductor device 1 is substantially zero.

(Wire mounting failure)
Subsequently, although the first semiconductor chip 2 and the second semiconductor chip 4 are normal, the inter-chip wiring WI _i is connected to the adjacent first pads Pd1 _{i + 1} (or alternatively, as shown by a dashed line (i) in FIG. A case where the second pad Pd2 _{i + 1} and the inter-chip wiring WI _{i + 1} ) are short-circuited will be described.

In this case, the power supply line 50 and the ground line 52 of the first semiconductor chip 2 are short-circuited via the high-side transistor MH of the buffer B1 _i , the path (i), and the low-side transistor ML of the buffer B1 _{i + 1} . As a result, the current I _TOTAL flowing through the semiconductor device 1 increases.

(Defects due to element destruction)
Next, a description will be given of a failure in which an element included in the buffer B1 _i of the first semiconductor chip 2 or the reception circuit RX _i of the second semiconductor chip 4 is destroyed although the inter-chip wiring WI _i is normal.

For example, if the buffer B1 _i of the low-side transistor ML (or protection diode D1) is destroyed in short mode, a current flows through the path (ii) comprising a high-side transistor MH and the low-side transistor ML of buffer B1 _i, thereby, The current I _TOTAL flowing through the semiconductor device 1 increases.

Alternatively, when the protection diode D2 of the reception circuit RX _i or the reception buffer B2 _i and the pull-down transistor M3 are destroyed in the short mode, the path (iii) including the high-side transistor MH of the buffer B1 _i and the reception circuit RX _i As a result, current I _TOTAL flowing in the semiconductor device 1 increases.

The above is the description of the inspection process of the semiconductor device 1c. As described above, according to the semiconductor device 1c, the mounting current of the inter-chip wiring WI or the short-mode breakdown of the peripheral circuit can be detected by measuring the operating current I _TOTAL of the semiconductor device 1c.

  Finally, the use of the semiconductor device 1 (1a to 1c) will be described. FIG. 8 is a circuit diagram of an audio signal processing circuit including the semiconductor device 1. The audio signal processing circuit 100 includes a DSP (Digital Signal Processor or Digital Sound Processor) chip 102 corresponding to the first semiconductor chip 2 and a class D amplifier chip 104 corresponding to the second semiconductor chip 4.

The DSP chip 102 (first semiconductor chip 2) is formed with an audio signal processing circuit that processes a digital audio signal and generates a pulse audio signal that is pulse-modulated in accordance with the audio signal. The input pin Pe1 includes SCL, SDA, ADDR, SDATA, LRCK, BCLK, MUTEX, and RSTX. The SCL and SDA pins are provided for I ² C communication. ADDR is a pin for addressing, SDATA is a pin for receiving audio data, LRCK and BCLK are pins for receiving a clock for audio data, MUTEX is a pin for receiving a mute control signal, RSTX is a pin for receiving a mute control signal It is. The DSP chip 102 receives 2-channel (Lch / Rch) audio data SDATA, performs predetermined signal processing, and generates an Lch / Rch pulse audio signal.

  The plurality of first pads Pd1 include SCLO, SDAO, OUT2N, OUT2P, OUT1N, OUT1P, MUTEXO, and RSTXO. The clock and data input to the SCL and SDA pins are transmitted to the class D amplifier chip 104 via the SCLO and SDAO pads. OUT1P / OUT1N transmits the pulse audio signal of the L channel to the class D amplifier chip 104 in a differential format. OUT2P / OUT2N transmits the R-channel pulse audio signal to the class D amplifier chip 104 in a differential format. MUTEXO and RSTXO transmit a signal input to the MUTEX pin and the RSTX pin to the class D amplifier chip 104.

  In the class D amplifier chip 104, a class D amplifier 106 for the R channel and a class D amplifier 108 for the L channel are formed. The class D amplifier 106 converts the differential pulse signal OUT2P / OUT2N into a single-ended format, amplifies it, and outputs it from the OUTR pin. The class D amplifier 108 converts the differential pulse signal OUT1P / OUT1N into a single-ended format, amplifies it, and outputs it from the OUTL pin.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
The type of package of the semiconductor device 1 is not particularly limited. In addition to DIP (Dual Inline Package) shown in FIG. 1A, SIP (Single Inline Package), PGA (Pin Grid Array), QFP (Quad Flat Package), It can be applied to various packages such as a BGA (Ball Grid Array) package.

(Second modification)
In the embodiment, the case where a plurality of semiconductor chips are mounted on the same plane has been described, but they may be mounted three-dimensionally. Further, the interchip wiring WI is not limited to the bonding wire, and may be a rewiring, a bump, a via hole, or a combination thereof. Further, the number of chips may be three or more.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... 1st semiconductor chip, 4 ... 2nd semiconductor chip, 20 ... 1st functional circuit, 22 ... 2nd selector, 24 ... Test control circuit, 26 ... 3rd selector, 40 ... 2nd functional circuit 42 ... 1st selector, B1 ... buffer, 30 ... I / O pin, S1 ... test signal, S2 ... control signal, Pd1 ... 1st pad, Pd2 ... 2nd pad, Pd3 ... 3rd pad, Pd4 ... 4th. Pad, Pd5 ... Fifth pad, Pe1 ... Input pin, WI ... Interchip wiring, 300 ... Semiconductor integrated circuit, 302 ... Semiconductor substrate, 304 ... I / O pad, 306 ... Interchip wire, 308 ... Lead terminal, 310 ... Bonding wire, 312 ... resin, 100 ... audio signal processing circuit, 102 ... DSP chip, 104 ... D class amplifier chip.

Claims (9)

A multi-chip package semiconductor device,
Multiple input / output pins;
A first semiconductor chip having a plurality of first pads for interchip connection and configured to be able to supply a test signal to each of the plurality of first pads;
Receiving a plurality of second pads for inter-chip connection, a third pad electrically connected to a test pin which is one of the plurality of input / output pins, and a plurality of signals generated on the plurality of second pads; A first selector that selects and outputs to the third pad; and
A plurality of inter-chip wirings each connecting a corresponding one of the plurality of first pads of the first semiconductor chip to a corresponding one of the plurality of second pads of the second semiconductor chip;
Bei to give a,
The first semiconductor chip is
A plurality of fifth pads electrically connected to a plurality of input pins included in the plurality of input / output pins;
A first state in which a selected one of the plurality of first pads is connected to a predetermined one of the plurality of fifth pads, and each of the plurality of first pads is formed on the first semiconductor chip. A third selector capable of selecting a second state connected to one functional circuit;
The semiconductor device further comprising: A multi-chip package semiconductor device,
Multiple input / output pins;
A first semiconductor chip having a plurality of first pads for interchip connection and configured to be able to supply a test signal to each of the plurality of first pads;
Receiving a plurality of second pads for inter-chip connection, a third pad electrically connected to a test pin which is one of the plurality of input / output pins, and a plurality of signals generated on the plurality of second pads; A first selector that selects and outputs to the third pad; and
A plurality of inter-chip wirings each connecting a corresponding one of the plurality of first pads of the first semiconductor chip to a corresponding one of the plurality of second pads of the second semiconductor chip;
Bei to give a,
The first semiconductor chip is
A test control circuit for generating the test signal;
A first state in which the test signal is supplied to a selected one of the plurality of first pads, and a first function circuit that connects each of the plurality of first pads to a first functional circuit formed in the first semiconductor chip. A fourth selector capable of selecting two states;
The semiconductor device further comprising: A multi-chip package semiconductor device,
Multiple input / output pins;
A first semiconductor chip having a plurality of first pads for interchip connection and configured to be able to supply a test signal to each of the plurality of first pads;
Receiving a plurality of second pads for inter-chip connection, a third pad electrically connected to a test pin which is one of the plurality of input / output pins, and a plurality of signals generated on the plurality of second pads; A first selector that selects and outputs to the third pad; and
A plurality of inter-chip wirings each connecting a corresponding one of the plurality of first pads of the first semiconductor chip to a corresponding one of the plurality of second pads of the second semiconductor chip;
Bei to give a,
The first semiconductor chip is
A plurality of buffers for generating a high level voltage or a low level voltage on the plurality of first pads;
The plurality of buffers are sequentially selected, a high level voltage is generated in the selected one, and a low level voltage is generated in the remaining one, and the first functional circuit included in the first semiconductor chip and the second semiconductor chip include A test control circuit for stopping the second function circuit;
The semiconductor device further comprising: The second semiconductor chip is
Each further comprising at least one fourth pad connected to a corresponding one of the first pads of the first semiconductor chip via an interchip interconnect;
Wherein the first selector, the semiconductor device according to any one of claims 1 to 3, characterized in that said controlled in accordance with at least one signal of the fourth pad. The first semiconductor chip is
A plurality of fifth pads electrically connected to a plurality of input pins included in the plurality of input / output pins;
A first state in which each of the plurality of first pads is connected to a corresponding one of the plurality of fifth pads; and a first functional circuit formed on the first semiconductor chip, each of the plurality of first pads. A second selector that can be selected from the second state to be connected;
The semiconductor device according to claim 3 , further comprising:   The semiconductor device according to claim 1, wherein the plurality of inter-chip wirings include bonding wires. An audio signal processing circuit for processing a digital audio signal and generating a pulse audio signal pulse-modulated according to the audio signal is formed in the first semiconductor chip,
7. The semiconductor device according to claim 1, wherein a class D amplifier that amplifies the pulse audio signal is formed in the second semiconductor chip. The first semiconductor chip is
A plurality of buffers for generating a high level voltage or a low level voltage on the plurality of first pads;
The plurality of buffers are sequentially selected, a high level voltage is generated in the selected one, and a low level voltage is generated in the remaining one, and the first functional circuit included in the first semiconductor chip and the second semiconductor chip include A test control circuit for stopping the second function circuit;
The semiconductor device according to claim 1 or 2, characterized in that it further comprises a. A multi-chip package semiconductor device,
Multiple input / output pins;
A first semiconductor chip having a plurality of first pads for inter-chip connection, a power supply terminal, a first functional circuit, and a plurality of buffers for generating a high level voltage or a low level voltage in the plurality of first pads;
A second semiconductor chip having a plurality of second pads for inter-chip connection and a second functional circuit;
A plurality of inter-chip wirings each connecting a corresponding one of the plurality of first pads of the first semiconductor chip to a corresponding one of the plurality of second pads of the second semiconductor chip;
A power supply pin connected to a power supply terminal of the first semiconductor chip;
With
The first semiconductor chip sequentially selects the plurality of buffers, generates a high level voltage in the selected one, and generates a low level voltage in the remaining one, and stops the first function circuit and the second function circuit. A semiconductor device further comprising a test control circuit.

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