JP6605573B2 - 並列ディシジョン・ツリー・プロセッサー・アーキテクチャ - Google Patents

並列ディシジョン・ツリー・プロセッサー・アーキテクチャ Download PDF

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JP6605573B2
JP6605573B2 JP2017501068A JP2017501068A JP6605573B2 JP 6605573 B2 JP6605573 B2 JP 6605573B2 JP 2017501068 A JP2017501068 A JP 2017501068A JP 2017501068 A JP2017501068 A JP 2017501068A JP 6605573 B2 JP6605573 B2 JP 6605573B2
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decision tree
decision
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processors
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バーガー,ダグラス・シー
ラルス,ジェームズ・アール
パットナム,アンドリュー
グレイ,ジャン
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00Computing arrangements using knowledge-based models
    • G06N5/02Knowledge representation; Symbolic representation
    • G06N5/022Knowledge engineering; Knowledge acquisition
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90Details of database functions independent of the retrieved data types
    • G06F16/901Indexing; Data structures therefor; Storage structures
    • G06F16/9027Trees
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90Details of database functions independent of the retrieved data types
    • G06F16/903Querying
    • G06F16/90335Query processing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00Machine learning
    • G06N20/20Ensemble learning

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JP2017501068A 2014-03-17 2015-03-12 並列ディシジョン・ツリー・プロセッサー・アーキテクチャ Active JP6605573B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/216,990 US10332008B2 (en) 2014-03-17 2014-03-17 Parallel decision tree processor architecture
US14/216,990 2014-03-17
PCT/US2015/020050 WO2015142595A1 (en) 2014-03-17 2015-03-12 Parallel decision tree processor architecture

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JP2017517082A JP2017517082A (ja) 2017-06-22
JP2017517082A5 JP2017517082A5 (enExample) 2018-04-19
JP6605573B2 true JP6605573B2 (ja) 2019-11-13

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US (1) US10332008B2 (enExample)
EP (1) EP3120262A1 (enExample)
JP (1) JP6605573B2 (enExample)
KR (1) KR102376117B1 (enExample)
CN (1) CN106133721B (enExample)
AU (1) AU2015231828A1 (enExample)
CA (1) CA2939959A1 (enExample)
CL (1) CL2016002294A1 (enExample)
IL (1) IL247166A0 (enExample)
MX (1) MX2016011670A (enExample)
PH (1) PH12016501639A1 (enExample)
RU (1) RU2016136985A (enExample)
SG (1) SG11201607431XA (enExample)
WO (1) WO2015142595A1 (enExample)

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CN109376590A (zh) * 2018-09-07 2019-02-22 百度在线网络技术(北京)有限公司 基于无人车的障碍物分类方法、装置、设备以及存储介质
JP7176359B2 (ja) * 2018-11-05 2022-11-22 株式会社リコー 学習装置および学習方法
JP7196542B2 (ja) * 2018-11-05 2022-12-27 株式会社リコー 学習装置および学習方法
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US10998047B1 (en) 2020-01-15 2021-05-04 Hewlett Packard Enterprise Development Lp Methods and systems for an analog CAM with fuzzy search
US20230237387A1 (en) * 2020-06-19 2023-07-27 Albert-Ludwigs-Universität Freiburg Architecture for Classification of a Decision Tree Ensemble and Method
US11615827B2 (en) * 2020-10-15 2023-03-28 Hewlett Packard Enterprise Development Lp Hardware accelerator with analog-content addressable memory (a-CAM) for decision tree computation
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CN117851399A (zh) * 2022-09-30 2024-04-09 戴尔产品有限公司 数据读取方法、数据更新方法、电子设备和程序产品

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Publication number Publication date
WO2015142595A1 (en) 2015-09-24
RU2016136985A3 (enExample) 2018-10-24
KR20160132853A (ko) 2016-11-21
KR102376117B1 (ko) 2022-03-17
IL247166A0 (en) 2016-09-29
US10332008B2 (en) 2019-06-25
RU2016136985A (ru) 2018-03-20
CN106133721B (zh) 2019-10-01
SG11201607431XA (en) 2016-10-28
CL2016002294A1 (es) 2017-03-24
AU2015231828A1 (en) 2016-09-08
CN106133721A (zh) 2016-11-16
CA2939959A1 (en) 2015-09-24
MX2016011670A (es) 2016-11-07
EP3120262A1 (en) 2017-01-25
PH12016501639A1 (en) 2016-10-03
US20150262064A1 (en) 2015-09-17
JP2017517082A (ja) 2017-06-22

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