JP6596908B2 - Digital filter - Google Patents

Description

  The present invention relates to a digital filter.

  An adaptive filter (adaptive equalizer) that includes a tapped delay line and updates a tap coefficient using an LMS (Least Mean Square) algorithm is known (for example, see Patent Document 1).

JP 2002-259116 A

  A general adaptive filter compensates for the average impulse response, so if the rising and falling edges of the signal transition are asymmetrical in the waveform of the signal before equalization, compensation is made for one of the rising and falling transitions. Insufficient compensation on the other transition may be excessive. As a result, the error after equalization (deviation from the ideal symbol) becomes large, and the noise margin related to the determination of the symbol value may be reduced.

  One embodiment of the present invention provides a digital filter capable of expanding a noise margin.

  A digital filter according to one embodiment of the present invention is a digital filter that outputs an output signal with respect to an input signal. The digital filter includes: a first filter unit that outputs a signal obtained by performing signal processing on an input signal using a first tap coefficient as a determination signal; a transition state detection unit that detects a transition state of the determination signal; Depending on the transition state, either the second tap coefficient that is the rising tap coefficient or the third tap coefficient that is the falling tap coefficient is selected, and signal processing is performed on the input signal using the selected tap coefficient. And a second filter unit that outputs a signal obtained by performing as an output signal.

  According to one aspect of the present invention, it is possible to expand a noise margin related to determination of a symbol value.

It is a block diagram which shows typically the digital filter which concerns on one Embodiment. FIG. 2 is a partially enlarged view of the digital filter of FIG. 1. It is a figure which shows the eye pattern of a PAM4 signal. It is a figure for demonstrating the output signal in the digital filter of a comparative example. It is a figure for demonstrating the output signal in the digital filter of FIG. It is a figure which shows an example of the time change of the error in the digital filter of a comparative example, and an example of the time change of the error in the digital filter of FIG.

[Description of Embodiment of Present Invention]
First, the contents of the embodiment of the present invention will be listed and described.

  A digital filter according to one embodiment of the present invention is a digital filter that outputs an output signal with respect to an input signal. The digital filter includes: a first filter unit that outputs a signal obtained by performing signal processing on an input signal using a first tap coefficient as a determination signal; a transition state detection unit that detects a transition state of the determination signal; Depending on the transition state, either the second tap coefficient that is the rising tap coefficient or the third tap coefficient that is the falling tap coefficient is selected, and signal processing is performed on the input signal using the selected tap coefficient. And a second filter unit that outputs a signal obtained by performing as an output signal.

  According to this digital filter, the transition state of the output signal is detected based on the determination signal from the first filter unit. Then, the rising second tap coefficient and the falling third tap coefficient are selected according to the detected transition state, and signal processing of the input signal is performed using the selected tap coefficient. For this reason, even if the rise and fall of the input signal are asymmetric, the second tap coefficient for rise is used at the rise and the third tap coefficient for fall is used at the fall. Thus, appropriate compensation according to the transition state can be performed. As a result, the error of the output signal can be reduced, and the noise margin related to the determination of the symbol value can be increased.

  The digital filter according to another aspect of the present invention may further include a first update unit that updates the first tap coefficient. In this case, the first tap coefficient can be finely corrected and converged, and the first tap coefficient can be optimized.

  The digital filter according to still another aspect of the present invention may further include a second update unit that updates the second tap coefficient and a third update unit that updates the third tap coefficient. The second updating unit may update the second tap coefficient when the transition state indicates rising, and the third updating unit updates the third tap coefficient when the transition state indicates falling. Also good. In this case, since the tap coefficient corresponding to the transition state is updated, the second tap coefficient and the third tap coefficient can be finely corrected and converged, and the second tap coefficient and the third tap coefficient can be optimized. It becomes.

  The second update unit may further update the second tap coefficient when the transition state indicates no transition, and the third update unit further indicates that the transition state indicates that there is no transition. The third tap coefficient may be updated. In this case, even if the modulation signal to be equalized has a portion where the same symbol value continues, the tap coefficient can be updated so as to reduce the error of the DC amplitude value.

  The input signal may have a plurality of symbols generated by multi-level modulation, and in the digital filter according to still another aspect of the present invention, the determination signal is assigned to any one of the plurality of symbols. It may further include a first determination unit that performs a symbol determination and outputs a first symbol determination value according to the determined symbol. The transition state detection unit may detect the transition state of the determination signal using the first symbol determination value. The determination signal may have an error with respect to the first symbol determination value. For this reason, even if the signals are assigned to the same symbol, they may be different judgment signals. Therefore, when the transition state is detected using the judgment signal, either the rising state or the falling state is detected. As a result, the transition state may be erroneously detected. On the other hand, since signals assigned to the same symbol are likely to have the same first symbol determination value, the transition state detection accuracy can be improved by using the first symbol determination value.

  The transition state detection unit may detect the transition state of the determination signal after delaying the first symbol determination value by a predetermined delay amount, and the second filter unit delays the input signal by the delay amount described above. A signal obtained by performing signal processing on the obtained signal may be output as an output signal. In this case, the time slot of the signal to be detected for the state transition can be matched with the time slot of the signal processed in the second filter unit. Therefore, more appropriate compensation can be performed on the input signal according to the transition state. As a result, the error of the output signal can be further reduced, and the noise margin related to the determination of the symbol value can be further expanded.

  A digital filter according to still another aspect of the present invention performs symbol determination as to which symbol an output signal is assigned to among a plurality of symbols, and outputs a second symbol determination value according to the determined symbol. An error calculator for calculating an error between the second determination unit, the second symbol determination value, and the output signal; and a first error statistic obtained by performing statistical processing on the error when the second tap coefficient is selected. An error statistic calculator that calculates a value and a second error statistic obtained by performing statistical processing on the error when the third tap coefficient is selected may be further provided. The second filter unit may select the second tap coefficient when the transition state indicates that there is no transition and the first error statistic value is smaller than the second error statistic value. If the second error statistic value is smaller than the first error statistic value, the third tap coefficient may be selected. According to this configuration, when there is no transition, the tap coefficient corresponding to the smaller one of the first error statistical value and the second error statistical value is used. For this reason, even when there is no transition, the error of the output signal can be reduced, and the noise margin related to the determination of the symbol value can be further expanded.

  The digital filter according to still another aspect of the present invention further includes a switching unit that outputs a selection signal for causing the second filter unit to select either the second tap coefficient or the third tap coefficient according to the transition state. You may prepare. The second filter unit may select either the second tap coefficient or the third tap coefficient according to the selection signal. In this case, the second filter unit may select either the second tap coefficient or the third tap coefficient in accordance with the selection signal, so that the configuration of the second filter unit can be simplified.

  The first filter unit may be a first finite impulse response filter including a first delay line in which a plurality of delay circuits are connected in series, and the second filter unit has a plurality of delay circuits connected in series. A second finite impulse response filter including a second delay line may be used. A part of the plurality of delay circuits of the first delay line may be used as a part of the plurality of delay circuits of the second delay line. In this case, the number of delay circuits can be reduced.

[Details of the embodiment of the present invention]
Specific examples of the digital filter according to the embodiment of the present invention will be described below with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to a claim are included.

  FIG. 1 is a configuration diagram schematically illustrating a digital filter according to an embodiment. FIG. 2 is a partially enlarged view of the digital filter of FIG. A digital filter 1 shown in FIGS. 1 and 2 is a digital filter that is mounted on a receiver and used for demodulation of a signal that has been subjected to multi-level (M-value) modulation in the transmitter. The digital filter 1 is a digital filter that outputs an output signal y with respect to an input signal x, and is, for example, an adaptive filter (adaptive equalizer). The digital filter 1 includes a finite impulse response (FIR) filter. The input signal x input to the digital filter 1 has a plurality of symbols generated by multilevel modulation, and for example, a signal modulated by pulse amplitude modulation (PAM) or the like can be used. . In the following description, when indicating a time slot of a signal, a number indicating a time slot is added in parentheses after a code indicating the signal. For example, for an input signal x, when the number of a certain time slot is n (n is a positive integer value), the value of the input signal x in that time slot is represented as x (n), and the time immediately before that The value of the input signal x in the slot is represented as x (n-1), and the value of the input signal x in the time slot immediately after the time slot number n is represented as x (n + 1). As for the time slot number, a smaller value indicates that it is earlier in time, and a larger value indicates that it is later in time. That is, the above example represents that the value of the input signal x changes in the order of x (n−1), x (n), and x (n + 1) for each time slot as time passes.

  FIG. 3 is a diagram showing an eye pattern of the PAM4 signal. The PAM4 signal is, for example, a symbol value corresponding to each of four predetermined voltage values (for example, “0”, “1”, “2”, “3”, respectively, in order from the smallest voltage value to the largest voltage value). Information is transmitted by repeating the transition from the previous symbol value to the next symbol value at regular time intervals (symbol periods). However, transitions between symbol values do not necessarily occur every cycle. For example, the transition is caused by the same symbol value continuing so that the symbol value is “0” and the next symbol value is also “0”. If not, it can happen frequently. The eye pattern shown in FIG. 3 is an eye pattern of an analog input signal before being sampled for digital signal processing. The horizontal axis of FIG. 3 represents time normalized with 1/10 of the symbol period as one unit. Specifically, in the case of 100 Gbps DP-QPSK (Dual Polarization-Quadrature Phase Shift Keying), the symbol period is 30 to 40 ps. The vertical axis in FIG. 3 represents the value of the input signal normalized with the distance between adjacent symbols as one unit (more specifically, the voltage difference between adjacent symbols is normalized as one unit. It may be considered that it represents a normalized voltage).

  For example, a PAM4 signal, which is a quaternary PAM signal, ideally has a symbol value (for example, “1”) to another symbol value (for example, “3”) as shown in FIG. The rise time when transitioning to) and the fall time when transitioning from another symbol value (“3”) to a certain symbol value (“1”) are the same, and 2 in the signal waveform. The eye pattern is graphically symmetric when a straight line extending in the vertical direction at a certain time with respect to the transition between two different symbol values is taken as the axis of symmetry. However, actually, as shown in FIG. 3B, the rise time and the fall time are different with respect to the transition between two different symbol values, and the rise and fall are asymmetric in the signal waveform. Sometimes. In FIG. 3B, the rise time is longer than the fall time, but the rise time may be shorter than the fall time.

  As shown in FIGS. 1 and 2, the digital filter 1 includes a first filter unit 11, a temporary determination unit 12 (first determination unit), an error calculation unit 13, and an update unit 14 (first update unit). A second filter unit 15, a main determination unit 16 (second determination unit), an error calculation unit 17, an update unit 18 (second update unit), an update unit 19 (third update unit), and an error A statistical value calculation unit 21, a transition state detection unit 22, and a switching unit 23 are provided.

  The first filter unit 11 is an FIR filter including a first delay line, and outputs a signal obtained by performing signal processing (compensation) on the input signal x (n) using the tap coefficient h0 (first tap coefficient). Output as signal y0 (n) (determination signal). The tap coefficient h0 is a tap coefficient vector including tap coefficients h0 (0) to h0 (6). The first filter unit 11 includes a part of the delay unit 111, a multiplication unit 112, and an addition unit 113. A part of the delay unit 111 includes delay circuits 111a to 111f connected in series to form a first delay line. The multiplier 112 includes the input signal x (n), the input signal sequence of the signals x (n−0.5) to x (n−3) output from the delay unit 111, and the tap coefficient output from the update unit 14. The product of h0 (0) to h0 (6) is calculated, and the calculation result is output. The multiplication unit 112 includes multipliers 112a to 112g. The adder 113 calculates the sum of the calculation results output from the multiplier 112 and outputs the calculation result as an output signal y0 (n). The adding unit 113 includes adders 113a to 113f. As a feature of the FIR filter, the first filter unit 11 does not have a signal feedback loop in the filter configuration, and performs signal processing by a finite impulse response. Note that the length of the first delay line (the number of delay circuits) need not be limited to this embodiment, and may be shortened or lengthened according to the required signal processing characteristics. Further, the number of multipliers and adders may be changed as appropriate according to the length of the first delay line.

  Hereinafter, the first filter unit 11 will be described in detail. Each delay circuit 111a to 111f delays the input signal by a half period (T / 2) of the symbol period T, and outputs the delayed signal. The delay circuit 111a delays the input signal x (n) of the digital filter 1 by a half period (T / 2) of the symbol period T and multiplies the delayed signal x (n−0.5) by the delay circuit 111b. Output to the device 112 b and the updating unit 14. The delay circuit 111b delays the signal x (n−0.5) output from the delay circuit 111a by a half period (T / 2) of the symbol period T, and delays the delayed signal x (n−1). The data is output to the circuit 111c, the multiplier 112c, the updating unit 14, the later-described multiplier 152a, the updating unit 18, and the updating unit 19.

  The delay circuit 111c delays the signal x (n−1) output from the delay circuit 111b by a half period (T / 2) of the symbol period T, and delays the delayed signal x (n−1.5). 111d, multiplier 112d, update unit 14, multiplier 152b, update unit 18 and update unit 19 to be described later. The delay circuit 111d delays the signal x (n−1.5) output from the delay circuit 111c by a half period (T / 2) of the symbol period T, and delays the delayed signal x (n−2). The data is output to the circuit 111e, the multiplier 112e, the updating unit 14, the multiplier 152c described later, the updating unit 18 and the updating unit 19.

  The delay circuit 111e delays the signal x (n−2) output from the delay circuit 111d by a half period (T / 2) of the symbol period T, and delays the delayed signal x (n−2.5). The data is output to the circuit 111f, the multiplier 112f, the updating unit 14, the multiplier 152d, the updating unit 18 and the updating unit 19 which will be described later. The delay circuit 111f delays the signal x (n−2.5) output from the delay circuit 111e by a half period (T / 2) of the symbol period T, and delays the delayed signal x (n−3). The data is output to the circuit 111g, the multiplier 112g, the updating unit 14, the multiplier 152e, the updating unit 18, and the updating unit 19 described later.

  The multiplier 112a calculates the product of the input signal x (n) of the digital filter 1 and the tap coefficient h0 (0) output from the updating unit 14, and outputs the calculation result to the adder 113a. The multiplier 112b calculates the product of the signal x (n−0.5) output from the delay circuit 111a and the tap coefficient h0 (1) output from the updating unit 14, and outputs the calculation result to the adder 113a. To do. The multiplier 112c calculates the product of the signal x (n-1) output from the delay circuit 111b and the tap coefficient h0 (2) output from the updating unit 14, and outputs the calculation result to the adder 113b.

  The multiplier 112d calculates the product of the signal x (n−1.5) output from the delay circuit 111c and the tap coefficient h0 (3) output from the updating unit 14, and outputs the calculation result to the adder 113c. To do. The multiplier 112e calculates the product of the signal x (n−2) output from the delay circuit 111d and the tap coefficient h0 (4) output from the updating unit 14, and outputs the calculation result to the adder 113d. The multiplier 112f calculates the product of the signal x (n−2.5) output from the delay circuit 111e and the tap coefficient h0 (5) output from the updating unit 14, and outputs the calculation result to the adder 113e. To do. The multiplier 112g calculates the product of the signal x (n−3) output from the delay circuit 111f and the tap coefficient h0 (6) output from the updating unit 14, and outputs the calculation result to the adder 113f.

  The adder 113a adds the calculation result of the multiplier 112a and the calculation result of the multiplier 112b, and outputs the addition result to the adder 113b. The adder 113b adds the operation result of the multiplier 112c and the addition result of the adder 113a, and outputs the addition result to the adder 113c. The adder 113c adds the operation result of the multiplier 112d and the addition result of the adder 113b, and outputs the addition result to the adder 113d. The adder 113d adds the operation result of the multiplier 112e and the addition result of the adder 113c, and outputs the addition result to the adder 113e. The adder 113e adds the operation result of the multiplier 112f and the addition result of the adder 113d, and outputs the addition result to the adder 113f. The adder 113f adds the operation result of the multiplier 112g and the addition result of the adder 113e, and outputs the addition result to the provisional determination unit 12 and the error calculation unit 13 as an output signal y0 (n).

  The temporary determination unit 12 performs symbol determination as to which symbol of the plurality of symbols the output signal y0 (n) output from the first filter unit 11 is assigned, and performs symbol determination according to the determined symbol The value d0 (n) (first symbol determination value) is output. When the input signal x (n) is a PAM4 signal, the tentative determination unit 12 performs quaternary symbol determination (for example, in the above example, four symbols according to the voltage value of the input signal x (n)). It is determined which of the values “0”, “1”, “2”, “3” corresponds). When the input signal x (n) is a PAM8 signal that is an 8-level PAM signal, the provisional determination unit 12 performs 8-level symbol determination. The temporary determination unit 12 outputs the symbol determination value d0 (n) to the error calculation unit 13 and the transition state detection unit 22.

The error calculation unit 13 calculates an error e0 (n) between the symbol determination value d0 (n) output from the temporary determination unit 12 and the output signal y0 (n) output from the first filter unit 11. The error calculation unit 13 is, for example, a subtracter, and an output output from the first filter unit 11 from the symbol determination value d0 (n) output from the temporary determination unit 12 as shown in Expression (1). The error e0 (n) is calculated by subtracting the signal y0 (n). The error calculation unit 13 outputs the calculated error e0 (n) to the update unit 14.

  The updating unit 14 updates the tap coefficient h0. Based on the error e0 (n), the updating unit 14 updates the tap coefficient h0 using, for example, an existing LMS algorithm. The update unit 14 includes a tap coefficient update unit 141 and a delay circuit 142. The delay circuit 142 delays the tap coefficient h0 output from the tap coefficient updating unit 141 by one symbol period T, and outputs the delayed tap coefficient h0 'to the tap coefficient updating unit 141 and the first filter unit 11. The tap coefficient h0 'indicates a tap coefficient vector before update, and the tap coefficient h0 indicates a tap coefficient vector after update.

For example, in the case of a modulation signal that generally involves not only amplitude but also phase modulation, the tap coefficient updating unit 141 may include a tap coefficient h0 ′, an error e0 (n), And tap coefficient h0 is calculated using the conjugate complex number of signal x (n)-x (n-3). That is, the tap coefficient updating unit 141 calculates the product of the step size μ, the error e0 (n), and the conjugate complex number of the signal x (nm−2) using the LMS algorithm, The tap coefficient h0 (m) is calculated by adding the tap coefficient h0 ′ (m). The tap coefficient updating unit 141 outputs the updated tap coefficient h0 to the delay circuit 142. In this embodiment, m is an integer value of 0-6. For example, in the case of a PAM4 signal, since phase modulation is not involved, as an actual calculation, the imaginary part of each conjugate complex number may be set to 0 and only the real part may be calculated (that is, the real number).

  The second filter unit 15 is configured as a basic form of an FIR filter including a second delay line, and outputs a signal obtained by performing signal processing on a signal obtained by delaying the input signal x (n) by a predetermined delay amount. Output as signal y (n-1) (output signal). In this example, the predetermined delay amount is one symbol period T. The second filter unit 15 selects and selects either the tap coefficient hr (second tap coefficient) or the tap coefficient hf (third tap coefficient) according to the transition state detected by the transition state detection unit 22 A signal obtained by performing signal processing (compensation) on the signal x (n−1) using the tap coefficient is output as an output signal y (n−1). The tap coefficient hr is a tap coefficient for rising, and is a tap coefficient vector including tap coefficients hr (0) to hr (6). The tap coefficient hf is a tap coefficient for falling, and is a tap coefficient vector including tap coefficients hf (0) to hf (6). As a feature of the FIR filter, the second filter unit 15 does not have a signal feedback loop in the filter configuration, and performs signal processing by a finite impulse response. Note that the length of the second delay line (the number of delay circuits) need not be limited to this embodiment, and may be shortened or lengthened according to the required signal processing characteristics. Further, the number of multipliers and adders may be changed as appropriate according to the length of the second delay line.

  By the way, in the present embodiment, the length of the first delay line of the first filter unit 11 is the same as the length of the second delay line of the second filter unit 15, but the length of the first delay line of the first filter unit 11 is the same. The length may be shorter than the length of the second delay line of the second filter unit 15. As the length of the delay line is increased, the number of tap coefficients is increased accordingly, and as the length of the delay line is increased, the calculation amount, circuit scale, and power consumption of the FIR filter are increased. Since the first filter unit 11 is intended for provisional determination and transition detection, it is preferable to reduce the length of the first delay line in order to reduce the calculation amount, circuit scale, and power consumption of the entire digital filter 1. There is a case. However, if the length of the first delay line of the first filter unit 11 is extremely shorter than the length of the second delay line of the second filter unit 15, the output signal of the first filter unit 11 (determination signal) ) Of the provisional determination result is relatively unlikely to coincide with the determination result of the output signal of the second filter unit 15, and the reliability of the provisional determination result may be reduced.

  The second filter unit 15 selects the tap coefficient hr when the transition state detected by the transition state detection unit 22 indicates rising, and when the transition state detected by the transition state detection unit 22 indicates falling , The tap coefficient hf is selected. The second filter unit 15 indicates that the transition state detected by the transition state detection unit 22 has no transition, and an error statistic sr (first error statistic) described later is an error statistic sf (first error statistic) described later. 2), the tap coefficient hr is selected, the transition state detected by the transition state detection unit 22 indicates no transition, and the error statistic sf is smaller than the error statistic sr. If it is smaller, the tap coefficient hf is selected. Specifically, the second filter unit 15 selects either the tap coefficient hr or the tap coefficient hf based on the selection signal SEL output from the switching unit 23. The selection signal SEL is a signal for causing the second filter unit 15 to select either the tap coefficient hr or the tap coefficient hf. The second filter unit 15 includes a part of the delay unit 111, a selector unit 151, a multiplier unit 152, and an adder unit 153.

  A part of the delay unit 111 includes delay circuits 111c to 111h connected in series to form a second delay line. As described above, a part of the delay circuits 111a to 111f forming the first delay line is used as a part of the delay circuits 111c to 111h forming the second delay line. The selector unit 151 selects one of the tap coefficients hr (0) to hr (6) and the tap coefficients hf (0) to hf (6) according to the selection signal SEL output from the switching unit 23. And output as tap coefficients h (0) to h (6). The selector unit 151 includes selectors 151a to 151g. The multiplication unit 152 includes input signal sequences of signals x (n−1) to x (n−4) output from the first filter unit 11 and tap coefficients h (0) to h ( 6) and the product of each and calculate the result. The multiplication unit 152 includes multipliers 152a to 152g. The adder 153 calculates the sum of the calculation results output from the multiplier 152 and outputs the calculation result as an output signal y (n−1). The adder 153 includes adders 153a to 153f.

  Hereinafter, the second filter unit 15 will be described in detail. The delay circuit 111g delays the signal x (n−3) output from the delay circuit 111f by a half period (T / 2) of the symbol period T, and delays the delayed signal x (n−3.5). The data is output to the circuit 111h, the multiplier 152f, the updating unit 18, and the updating unit 19. The delay circuit 111h delays the signal x (n−3.5) output from the delay circuit 111g by a half period (T / 2) of the symbol period T, and multiplies the delayed signal x (n−4). Output to the update unit 152g, the update unit 18, and the update unit 19.

  The selectors 151 a to 151 g are, for example, 2-input 1-output demultiplexers, and switch inputs according to the selection signal SEL output from the switching unit 23. The selector 151a receives the tap coefficient hr (0) and the tap coefficient hf (0), and either the tap coefficient hr (0) or the tap coefficient hf (0) according to the selection signal SEL output from the switching unit 23. Is selected and output to the multiplier 152a as a tap coefficient h (0). The selector 151b receives the tap coefficient hr (1) and the tap coefficient hf (1), and selects either the tap coefficient hr (1) or the tap coefficient hf (1) according to the selection signal SEL output from the switching unit 23. Is selected and output to the multiplier 152b as a tap coefficient h (1).

  The selector 151c receives the tap coefficient hr (2) and the tap coefficient hf (2), and selects either the tap coefficient hr (2) or the tap coefficient hf (2) according to the selection signal SEL output from the switching unit 23. Is selected and output to the multiplier 152c as a tap coefficient h (2). The selector 151d receives the tap coefficient hr (3) and the tap coefficient hf (3), and either the tap coefficient hr (3) or the tap coefficient hf (3) according to the selection signal SEL output from the switching unit 23. Is selected and output to the multiplier 152d as a tap coefficient h (3). The selector 151e receives the tap coefficient hr (4) and the tap coefficient hf (4), and selects either the tap coefficient hr (4) or the tap coefficient hf (4) according to the selection signal SEL output from the switching unit 23. Is selected and output to the multiplier 152e as a tap coefficient h (4).

  The selector 151f receives the tap coefficient hr (5) and the tap coefficient hf (5), and either the tap coefficient hr (5) or the tap coefficient hf (5) according to the selection signal SEL output from the switching unit 23. Is selected and output to the multiplier 152f as a tap coefficient h (5). The selector 151g receives the tap coefficient hr (6) and the tap coefficient hf (6), and selects either the tap coefficient hr (6) or the tap coefficient hf (6) according to the selection signal SEL output from the switching unit 23. Is selected and output to the multiplier 152g as a tap coefficient h (6). For example, when the selection signal SEL is at the low level, the selectors 151a to 151g select the tap coefficients hr (0) to hr (6), respectively, and when the selection signal SEL is at the high level, the tap coefficients hf (0) to hf. Select (6) respectively.

  The multiplier 152a calculates the product of the tap coefficient h (0) output from the selector 151a and the signal x (n-1) output from the delay circuit 111b, and outputs the calculation result to the adder 153a. The multiplier 152b calculates the product of the tap coefficient h (1) output from the selector 151b and the signal x (n−1.5) output from the delay circuit 111c, and outputs the calculation result to the adder 153a. . The multiplier 152c calculates the product of the tap coefficient h (2) output from the selector 151c and the signal x (n-2) output from the delay circuit 111d, and outputs the calculation result to the adder 153b.

  The multiplier 152d calculates the product of the tap coefficient h (3) output from the selector 151d and the signal x (n−2.5) output from the delay circuit 111e, and outputs the calculation result to the adder 153c. . The multiplier 152e calculates the product of the tap coefficient h (4) output from the selector 151e and the signal x (n-3) output from the delay circuit 111f, and outputs the calculation result to the adder 153d. The multiplier 152f calculates the product of the tap coefficient h (5) output from the selector 151f and the signal x (n−3.5) output from the delay circuit 111g, and outputs the calculation result to the adder 153e. . Multiplier 152g calculates the product of tap coefficient h (6) output from selector 151g and signal x (n-4) output from delay circuit 111h, and outputs the calculation result to adder 153f.

  The adder 153a adds the calculation result of the multiplier 152a and the calculation result of the multiplier 152b, and outputs the addition result to the adder 153b. The adder 153b adds the calculation result of the multiplier 152c and the addition result of the adder 153a, and outputs the addition result to the adder 153c. The adder 153c adds the calculation result of the multiplier 152d and the addition result of the adder 153b, and outputs the addition result to the adder 153d. The adder 153d adds the operation result of the multiplier 152e and the addition result of the adder 153c, and outputs the addition result to the adder 153e. The adder 153e adds the operation result of the multiplier 152f and the addition result of the adder 153d, and outputs the addition result to the adder 153f. The adder 153f adds the calculation result of the multiplier 152g and the addition result of the adder 153e, and outputs the addition result to the main determination unit 16 and the error calculation unit 17 as an output signal y (n-1). The output signal y (n−1) is also used as an equalizer output of the digital filter 1.

  The determination unit 16 performs symbol determination as to which symbol of the plurality of symbols the output signal y (n−1) output from the second filter unit 15 is assigned, and according to the determined symbol The symbol determination value d (n−1) (second symbol determination value) is output. When the input signal x (n) is a PAM4 signal, the determination unit 16 performs quaternary symbol determination. When the input signal x (n) is a PAM8 signal that is an 8-level PAM signal, the determination unit 16 performs 8-level symbol determination. The main determination unit 16 outputs the symbol determination value d (n−1) to the error calculation unit 17. The symbol determination value d (n−1) is also used as the symbol determination result of the digital filter 1.

The error calculator 17 calculates an error e (n−) between the symbol determination value d (n−1) output from the main determination unit 16 and the output signal y (n−1) output from the second filter unit 15. 1) is calculated. The error calculation unit 17 is, for example, a subtracter, and is output from the second filter unit 15 from the symbol determination value d (n−1) output from the main determination unit 16 as shown in Expression (3). The error e (n-1) is calculated by subtracting the output signal y (n-1). The error calculation unit 17 outputs the calculated error e (n−1) to the update unit 18, the update unit 19, and the error statistic value calculation unit 21.

  The update unit 18 updates the tap coefficient hr. Here, the tap coefficient hr is a vector including the tap coefficients hr (0) to hr (6). Based on the error e (n−1), the update unit 18 updates the tap coefficient hr using, for example, an existing LMS algorithm. The update unit 18 updates the tap coefficient hr when the transition state detected by the transition state detection unit 22 indicates rising and when the transition state detected by the transition state detection unit 22 indicates that there is no transition. To do. Specifically, the update unit 18 updates the tap coefficient hr based on the disable signal disr output from the switching unit 23. The disable signal disr is a signal for invalidating the function of the update unit 18 (specifically, the tap coefficient update unit 181) so that the update unit 18 does not update the tap coefficient hr. For example, the disable signal disr becomes active when the disable signal disr is at a high level, the function of the updating unit 18 is disabled, and the disable signal disr is inactive when the disable signal disr is at a low level. Thus, the function of the updating unit 18 is validated. The update unit 18 includes a tap coefficient update unit 181 and a delay circuit 182.

  The delay circuit 182 delays the tap coefficient hr output from the tap coefficient updating unit 181 by one symbol period T, and outputs the delayed tap coefficient hr ′ to the tap coefficient updating unit 181 and the second filter unit 15. The tap coefficient hr ′ indicates a tap coefficient vector before update, and the tap coefficient hr indicates a tap coefficient vector after update.

When the disable signal disr is inactive, the tap coefficient update unit 181 performs tap coefficient hr ′, error e (n−1), and signal x (n−1) as shown in, for example, Expression (4). ) To x (n-4) are used to calculate the tap coefficient hr. That is, the tap coefficient updating unit 181 calculates the product of the step size μ, the error e (n−1), and the conjugate complex number of the signal x (nm−2-1) using the LMS algorithm. The tap coefficient hr (m) is calculated by adding the calculation result and the tap coefficient hr ′ (m). The tap coefficient updating unit 181 outputs the updated tap coefficient hr to the delay circuit 182. In this embodiment, m is an integer value of 0-6. Here, the description has been made assuming that signal processing is generally performed on a modulated signal that involves not only amplitude but also phase modulation. For example, in the case of a PAM4 signal, phase modulation is not involved. As an actual calculation, the imaginary part of each conjugate complex number is set to 0 and only the real part is calculated (that is, the real number is calculated).

  The updating unit 19 updates the tap coefficient hf. Here, the tap coefficient hf is a vector including the tap coefficients hf (0) to hf (6). Based on the error e (n−1), the updating unit 19 updates the tap coefficient hf using, for example, an existing LMS algorithm. The update unit 19 sets the tap coefficient hf when the transition state detected by the transition state detection unit 22 indicates a falling edge and when the transition state detected by the transition state detection unit 22 indicates that there is no transition. Update. Specifically, the updating unit 19 updates the tap coefficient hf based on the disable signal disf output from the switching unit 23. The disable signal disf is a signal for invalidating the function of the updating unit 19 (specifically, the tap coefficient updating unit 191) so that the updating unit 19 does not update the tap coefficient hf. For example, the disable signal disf becomes active when the disable signal disf is at a high level, the function of the updating unit 19 is disabled, and the disable signal disf is inactive when the disable signal disf is at a low level. Thus, the function of the updating unit 19 is validated. The update unit 19 includes a tap coefficient update unit 191 and a delay circuit 192.

  The delay circuit 192 delays the tap coefficient hf output from the tap coefficient update unit 191 by one symbol period T, and outputs the delayed tap coefficient hf ′ to the tap coefficient update unit 191 and the second filter unit 15. The tap coefficient hf 'indicates a tap coefficient vector before update, and the tap coefficient hf indicates a tap coefficient vector after update.

When the disable signal disf is inactive, the tap coefficient updating unit 191, for example, as shown in Equation (5), tap coefficient hf ′, error e (n−1), and signal x (n−1) ) To x (n−4) are used to calculate the tap coefficient hf. That is, the tap coefficient updating unit 191 calculates the product of the step size μ, the error e (n−1), and the conjugate complex number of the signal x (nm−2-1) using the LMS algorithm. The tap coefficient hf (m) is calculated by adding the calculation result and the tap coefficient hf ′ (m). The tap coefficient updating unit 191 outputs the updated tap coefficient hf to the delay circuit 192. In this embodiment, m is an integer value of 0-6. Here, the description has been made assuming that signal processing is generally performed on a modulated signal that involves not only amplitude but also phase modulation. For example, in the case of a PAM4 signal, phase modulation is not involved. As an actual calculation, the imaginary part of each conjugate complex number is set to 0 and only the real part is calculated (that is, the real number is calculated).

  The error statistic calculator 21 calculates an error statistic sr and an error statistic sf. The error statistical value sr is a statistical value obtained by performing statistical processing on the error e when the tap coefficient hr is selected in the second filter unit 15. The error statistical value sf is a statistical value obtained by performing statistical processing on the error e when the tap coefficient hf is selected in the second filter unit 15. The error statistic value calculation unit 21 includes a selector 211, an error statistic unit 212, and an error statistic unit 213.

  The selector 211 receives the error e output from the error calculation unit 17 and outputs the input error e to either the error statistical unit 212 or the error statistical unit 213. The selector 211 is, for example, a 1-input 2-output switch, and switches the output destination according to the selection signal SEL output from the switching unit 23. For example, the selector 211 outputs the error e to the error statistics unit 212 when the selection signal SEL is at the low level, and outputs the error e to the error statistics unit 213 when the selection signal SEL is at the high level.

  The error statistic unit 212 calculates the error statistic value sr and outputs the calculated error statistic value sr to the switching unit 23. For example, the error statistic unit 212 recalculates the error statistic value sr every time the error e is input via the selector 211. The error statistic unit 212 calculates the error statistic value sr by, for example, the moving average of the absolute value of the input error e, the moving average of the square value of the input error e, or the like. The error statistic unit 212 may include a storage device such as a first-in first-out (FIFO) memory for storing the calculated error statistic sr, for example.

  The error statistic unit 213 calculates the error statistic value sf, and outputs the calculated error statistic value sf to the switching unit 23. The error statistic unit 213 recalculates the error statistic value sf every time the error e is input via the selector 211, for example. The error statistic unit 213 calculates the error statistic value sf by, for example, the moving average of the absolute value of the input error e, the moving average of the square value of the input error e, or the like. The error statistic unit 213 may include a storage device such as a FIFO memory for storing the calculated error statistic value sf, for example.

  The transition state detection unit 22 detects the transition state of the output signal y0 based on the output signal y0 output from the first filter unit 11. The transition state detected by the transition state detection unit 22 is one of a rising state, a falling state, and a state where there is no transition. The transition state detection unit 22 detects the transition state of the output signal y0 using, for example, the symbol determination value d0 output from the temporary determination unit 12. The transition state detection unit 22 detects the transition state of the output signal y0 after delaying the symbol determination value d0 by a predetermined delay amount. In this example, the predetermined delay amount is one symbol period T. The transition state detection unit 22 includes a delay circuit 221, a delay circuit 222, and a subtracter 223.

  The delay circuit 221 delays the symbol determination value d0 (n) output from the provisional determination unit 12 by one symbol period T, and sends the delayed symbol determination value d0 (n−1) to the delay circuit 222 and the subtractor 223. Output. In order to match the time slot between the symbol determination value d0 used for detecting the transition state by the transition state detection unit 22 and the output signal y that is the detection target of the transition state, the delay amount of the delay circuit 221 is the second filter. The value is set equal to the delay amount of the signal x (n−1) input to the multiplier 152a of the unit 15 with respect to the input signal x (n). That is, when the delay amount of the signal input to the multiplier 152a of the second filter unit 15 with respect to the input signal x (n) is 2T, for example, the delay amount of the delay circuit 221 is set to 2T.

  The delay circuit 222 delays the symbol determination value d0 (n−1) output from the delay circuit 221 by one symbol period T, and outputs the delayed symbol determination value d0 (n−2) to the subtractor 223. The subtracter 223 subtracts the symbol determination value d0 (n−2) output from the delay circuit 222 from the symbol determination value d0 (n−1) output from the delay circuit 221 and switches the subtraction result as a transition state value. To the unit 23. A positive transition state value indicates that the transition of the output signal y0 is in the rising direction (positive direction), and a negative transition state value indicates that the transition of the output signal y0 is Indicates the falling direction (negative direction). A transition state value of 0 indicates that there is no transition of the output signal y0.

  The switching unit 23 outputs a selection signal SEL, a disable signal disr, and a disable signal disf according to the transition state detected by the transition state detection unit 22. For example, the switching unit 23 selects the selection signal SEL, based on the error statistical value sr and the error statistical value sf output from the error statistical value calculation unit 21 and the transition state value output from the transition state detection unit 22. A disable signal disr and a disable signal disf are output. Specifically, when the transition state value is a positive value, the switching unit 23 selects the selector unit 151 to select the tap coefficient hr and the selector 211 to select the error statistic unit 212 as the output destination. In addition to outputting the signal SEL, in order to cause the updating unit 18 to update the tap coefficient hr, the disable signal disr is deactivated (also referred to as “deasserting”), and the updating unit 19 updates the tap coefficient hf. Therefore, the disable signal disf is activated (also referred to as “asserted”). When the transition state value is a negative value, the switching unit 23 outputs the selection signal SEL so that the selector unit 151 selects the tap coefficient hf and the selector 211 selects the error statistics unit 213 as the output destination. The disable signal disr is activated to prevent the updating unit 18 from updating the tap coefficient hr, and the disable signal disf is deactivated to cause the updating unit 19 to update the tap coefficient hf.

  When the transition state value is 0, the switching unit 23 determines which of the error statistical value sr and the error statistical value sf is smaller. When the switching unit 23 determines that the error statistical value sr is small, the switching unit 23 outputs the selection signal SEL so that the selector unit 151 selects the tap coefficient hr and the selector 211 selects the error statistical unit 212 as an output destination. To do. When determining that the error statistic value sf is small, the switching unit 23 outputs the selection signal SEL so that the selector unit 151 selects the tap coefficient hf and the selector 211 selects the error statistic unit 213 as the output destination. To do. When the transition state value is 0, the switching unit 23 does not activate the disable signal disr and the disable signal disf. When the selector unit 151 selects the tap coefficient hr and the selector 211 selects the error statistic unit 212 as an output destination, the selection signal SEL is set to a high level, for example, and the selector unit 151 selects the tap coefficient hf. When causing the selector 211 to select the error statistic unit 213 as an output destination, the selection signal SEL is set to a low level, for example.

  Next, the operation of the digital filter 1 will be described. In the digital filter 1, when an input signal x (n) is input from the outside (for example, a signal processing unit in the previous stage), the input signal x (n) is a symbol period T in the delay unit 111 of the first filter unit 11. Signal (n−0.5) to signal x (n−4) are generated with a delay of half a cycle. Then, the multiplication unit 112 multiplies the signals x (n) to x (n−3) by the tap coefficients h0 (0) to h0 (6), respectively. The calculation result of the adding unit 113 is output as the output signal y0 (n).

  Subsequently, the provisional determination unit 12 performs symbol determination on the output signal y0 (n) output from the first filter unit 11, and outputs a symbol determination value d0 (n). Then, the error calculation unit 13 calculates an error e0 (n) between the symbol determination value d0 (n) output from the temporary determination unit 12 and the output signal y0 (n) output from the first filter unit 11. Is output. Then, the updating unit 14 updates the tap coefficient h0 based on the error e0 (n), and outputs the updated tap coefficient h0 to the first filter unit 11. The tap coefficient h0 is updated using, for example, an LMS algorithm.

  Further, the transition state detection unit 22 detects the transition state of the output signal y0 using the symbol determination value d0 output from the temporary determination unit 12. Specifically, the symbol determination in which the symbol determination value d0 (n) is delayed by two symbol periods T from the symbol determination value d0 (n−1) in which the symbol determination value d0 (n) is delayed by one symbol period T. A subtraction result obtained by subtracting the value d0 (n−2) is output to the switching unit 23 as a transition state value.

  In the switching unit 23, the selection signal SEL, the disable signal disr, and the disable signal disf are output according to the transition state. More specifically, when the transition state value indicates a rising edge, that is, when the transition state value is a positive value, the selector 151 is caused to select the tap coefficient hr, and the selector 211 is configured to output the error statistics unit 212. The selection signal SEL is output so that the updating unit 18 updates the tap coefficient hr, and the disable signal disr is deactivated so that the updating unit 19 does not update the tap coefficient hf. The disable signal disf is activated at the same time. On the other hand, when the transition state value indicates a fall, that is, when the transition state value is a negative value, the selector unit 151 is made to select the tap coefficient hf, and the selector 211 is made to select the error statistic unit 213 as the output destination. In addition, the selection signal SEL is output, the disable signal disr is activated to prevent the update unit 18 from updating the tap coefficient hr, and the disable signal disf is updated to cause the update unit 19 to update the tap coefficient hf. Deactivated.

  When the transition state value indicates that there is no transition, that is, when the transition state value is 0, it is determined which of the error statistical value sr and the error statistical value sf is smaller. When the error statistical value sr is small, the selection signal SEL is output so that the selector 151 selects the tap coefficient hr and the selector 211 selects the error statistical unit 212 as an output destination. On the other hand, when the error statistic value sf is small, the selection signal SEL is output so that the selector unit 151 selects the tap coefficient hf and the selector 211 selects the error statistic unit 213 as the output destination. If the transition state value is 0, the disable signal disr and the disable signal disf are deactivated.

  Subsequently, in the selector unit 151 of the second filter unit 15, any one of tap coefficient vectors of tap coefficients hr (0) to hr (6) and tap coefficients hf (0) to hf (6) according to the selection signal SEL. Is selected. Then, in the multiplication unit 152, the tap coefficient vector selected by the selector unit 151 is used as the tap coefficients h (0) to h (6), and the signals x (n−1) to x (n−4), respectively. Is multiplied. Then, the sum of the multiplication results of the multiplication unit 152 is calculated in the addition unit 153, and the calculation result of the addition unit 153 is output as an output signal y (n-1). The output signal y (n−1) is output to the outside (for example, a signal processing unit at the subsequent stage) as an equalizer output of the digital filter 1.

  Subsequently, the main determination unit 16 performs symbol determination on the output signal y (n−1) output from the second filter unit 15 and outputs a symbol determination value d (n−1). The symbol determination value d (n−1) is output to the outside (for example, a signal processing unit at the subsequent stage) as a symbol determination result of the digital filter 1. Then, in the error calculation unit 17, an error e () between the symbol determination value d (n−1) output from the main determination unit 16 and the output signal y (n−1) output from the second filter unit 15. n-1) is calculated and output.

  Subsequently, when the disable signal disr is inactive, the updating unit 18 updates the tap coefficient hr based on the error e (n−1), and the updated tap coefficient hr is used as the second filter unit 15. Is output. On the other hand, when the disable signal disf is inactive, the updating unit 19 updates the tap coefficient hf based on the error e (n−1), and the updated tap coefficient hf is sent to the second filter unit 15. Is output. The tap coefficient hr and the tap coefficient hf are updated using, for example, an LMS algorithm.

  Further, in the error statistic value calculation unit 21, the output destination of the selector 211 is switched according to the selection signal SEL, and the error e (n−1) is output to either the error statistic unit 212 or the error statistic unit 213. When the error e (n−1) is output to the error statistic unit 212, the error statistic value sr is recalculated, and the recalculated error statistic value sr is output to the switching unit 23. On the other hand, when the error e (n−1) is output to the error statistic unit 213, the error statistic value sf is recalculated, and the recalculated error statistic value sf is output to the switching unit 23. The error statistic value sr and the error statistic value sf are calculated by, for example, a moving average of absolute values of input errors, a moving average of square values of input errors, or the like.

  The series of processes described above is repeated each time the input signal x (n) is input. In this case, when a signal sequence obtained by sampling a certain signal z at an appropriate sampling period is z (k) (k is a positive integer) and equalization is performed, for example, z of a certain period k is used. If (k) is input to the digital filter 1 as x (n) in FIGS. 1 and 2, z (k + 1) is also input to the digital filter 1 as x (n) in the next period k + 1. Become. However, since n-0.5, n-1 and the like in FIGS. 1 and 2 indicate relative delays based on n, x (n), x (n-0.5), x ( The actual value such as n−1) sequentially changes according to the input signal (for example, z (k), z (k + 1)) every time the signal sequence z is input.

  Next, with reference to FIGS. 4-6, the effect of the digital filter 1 is demonstrated. FIG. 4 is a diagram for explaining an output signal in the digital filter of the comparative example. FIG. 4A shows an example of a time change of the output signal in the digital filter of the comparative example, and FIG. Shows an example of the distribution of output signals in the digital filter of the comparative example. FIG. 5 is a diagram for explaining an output signal in the digital filter 1. FIG. 5A shows an example of a time change of the output signal in the digital filter 1, and FIG. An example of the distribution of output signals in FIG. FIG. 6 is a diagram illustrating an example of the time variation of the error in the digital filter of the comparative example and an example of the time variation of the error in the digital filter 1. FIG. 6A illustrates the time of the error in the digital filter of the comparative example. An example of the change is shown, and FIG. 6B shows an example of the time change of the error in the digital filter 1. 4 (a) and FIG. 5 (a), the horizontal axis indicates the time normalized by 10000 symbol periods as one unit, and the vertical axis is normalized by the distance between two adjacent symbols as one unit. The output value of the digital filter is shown. 4 (b) and FIG. 5 (b), the horizontal axis indicates the number of symbols existing in the histogram section, and the vertical axis is normalized in the same manner as in FIG. 4 (a) and FIG. 5 (b). The output value of the digital filter is shown. 6 (a) and 6 (b), the horizontal axis indicates the time normalized with a unit of 10000 symbol periods as one unit, and the vertical axis is calculated with the distance between two adjacent symbols as one unit. Indicates the value of the error signal.

  As the digital filter of the comparative example, a digital filter having the same configuration as that of the first filter unit 11, the temporary determination unit 12, the error calculation unit 13, and the update unit 14 of the digital filter 1 was used. The output signal of the digital filter of the comparative example corresponds to the output signal y0 output from the first filter unit 11, and the error of the digital filter of the comparative example corresponds to the error e0 output from the error calculation unit 13. As the input signal, an input signal having asymmetric rising and falling edges with respect to the transition between two different symbol values as shown in FIG. 3B is used. The black graph in FIG. 6B shows the time change of the error at the rising edge, and the gray graph shows the time change of the error at the falling edge. Each graph was obtained by using the selection signal SEL and separately observing the error e output from the error calculation unit 17 into a rising error and a falling error. FIG. 6B shows a state in which a gray graph is overwritten on a black graph, and a black graph value may exist even in a portion where only the gray graph is actually visible.

  As shown in FIGS. 4 and 5, it can be seen that the digital filter 1 has less variation in voltage value for each symbol than the digital filter of the comparative example. Further, as shown in FIG. 6, the error at the rise and the error at the fall have the same magnitude, and it can be seen that both errors are significantly smaller than the error of the comparative example.

  As described above, in the digital filter 1, the transition state of the output signal y0 is detected based on the output signal y0 from the first filter unit 11. Then, when the detected transition state indicates rising, the tap coefficient hr is selected, and when the detected transition state indicates falling, the tap coefficient hf is selected, and the selected tap coefficient is used to input the input signal. Signal processing of x is performed. For this reason, even if the rising edge and the falling edge of the input signal x are asymmetric, the rising tap coefficient hr is used at the rising edge, and the falling tap coefficient hf is used at the falling edge. Thus, appropriate compensation according to the transition state can be performed. As a result, the error e of the output signal y can be reduced, and the noise margin related to the determination of the symbol value can be increased.

  Further, the digital filter 1 includes the update unit 14 that updates the tap coefficient h0, so that the tap coefficient h0 can be finely corrected and converged, and the tap coefficient h0 can be optimized.

  In the digital filter 1, the update unit 18 updates the tap coefficient hr when the transition state detected by the transition state detection unit 22 indicates a rising edge, and the update unit 19 is detected by the transition state detection unit 22. When the transition state indicates a falling edge, the tap coefficient hf is updated. For this reason, since the tap coefficient corresponding to the transition state is updated among the tap coefficient hr and the tap coefficient hf, the tap coefficient hr and the tap coefficient hf can be finely corrected and converged, and the tap coefficient hr and the tap coefficient hf can be converged. Can be optimized.

  In the digital filter 1, the update unit 18 updates the tap coefficient hr when the transition state detected by the transition state detection unit 22 indicates that there is no transition, and the update unit 19 updates the transition state detection unit 22. The tap coefficient hf is updated when the transition state detected by indicates that there is no transition. As a result, even if the modulation signal to be equalized has a portion where the same symbol value continues, the tap coefficient can be updated so as to reduce the error of the DC amplitude value.

  In the digital filter 1, the transition state detection unit 22 detects the transition state of the output signal y 0 using the symbol determination value d 0 output from the temporary determination unit 12. The output signal y0 may have an error with respect to the symbol determination value d0. For this reason, even if two output signals y0 assigned to the same symbol may have different values, when a transition state is detected using the output signal y0, a rising state or a falling state is detected. In some cases, the transition state may be erroneously detected. On the other hand, since signals assigned to the same symbol are likely to have the same symbol determination value d0, the detection accuracy of the transition state can be improved by using the symbol determination value d0.

  In the digital filter 1, the transition state detection unit 22 detects the transition state of the output signal y0 by delaying the symbol determination value d0 by a predetermined delay amount, and the second filter unit 15 outputs the input signal x as described above. The signal delayed by the delay amount is subjected to signal processing to output an output signal y. As a result, the time slot of the signal to be detected as the state transition can be matched with the time slot of the signal processed in the second filter unit 15. For this reason, more appropriate compensation can be performed on the input signal x in accordance with the transition state. As a result, the error e of the output signal y can be further reduced, and the noise margin relating to the determination of the symbol value can be further expanded.

  In the digital filter 1, the second filter unit 15 indicates that the transition state detected by the transition state detection unit 22 has no transition, and the error statistic sr is smaller than the error statistic sf. The tap coefficient hr is selected, and the tap coefficient hf is selected when the transition state detected by the transition state detection unit 22 indicates that there is no transition and the error statistical value sf is smaller than the error statistical value sr. As described above, when there is no transition, a tap coefficient corresponding to the error statistical value which is smaller of the error statistical value sr and the error statistical value sf is used. For this reason, even when there is no transition, the error e of the output signal y can be reduced, and the noise margin can be further expanded.

  In the digital filter 1, the second filter unit 15 selects either the tap coefficient hr or the tap coefficient hf based on the selection signal SEL output from the switching unit 23. For this reason, the configuration of the second filter unit 15 can be simplified.

  As described above, the digital filter 1 is an adaptive equalizer having three types of tap coefficient vectors of the tap coefficient h0, the tap coefficient hr, and the tap coefficient hf. The tap coefficient vector of one system (tap coefficient h0) operates the first filter unit 11 as a general adaptive equalizer and detects the transition state of the output signal y based on the output signal y0 of the first filter unit 11. Used for. The tap positions of the remaining two systems of tap coefficient vectors are input signal sequences delayed by one symbol period T with respect to signals x (n) to x (n−3) which are input signal sequences of the first filter unit 11. Corresponding to certain signals x (n−1) to x (n−4), the remaining two systems based on the presence / absence and transition direction of the equalizer output (output signal y) detected by the transition state detection unit 22 Whether or not the tap coefficient is updated is switched. That is, the tap coefficient hr is not updated when the equalizer output transition is in the falling direction (negative direction), and is updated only when there is no equalizer output transition and when the equalizer output transition is in the rising direction (positive direction). Is done. The tap coefficient hf is not updated when the equalizer output transition is in the rising direction, and is updated only when there is no equalizer output transition and when the equalizer output transition is in the falling direction. Then, when there is a transition of the equalizer output, the second filter unit 15 calculates the equalizer output by using the tap coefficient that is one symbol period T before the updated one of the tap coefficient hr and the tap coefficient hf. If there is no transition, the equalizer output is obtained by using the tap coefficient one symbol period T before the tap coefficient corresponding to the smaller error statistical value of the past error statistical value sr and error statistical value sf. Calculated.

  The digital filter according to the present invention is not limited to the above embodiment. For example, the digital filter 1 does not need to include the update unit 14, the update unit 18, and the update unit 19. That is, the tap coefficient h0, the tap coefficient hr, and the tap coefficient hf may be set in advance, and the tap coefficient h0, the tap coefficient hr, and the tap coefficient hf need not be updated.

  Moreover, although the transition state detection part 22 has detected the transition state based on the symbol determination value d0, you may detect a transition state based on the output signal y0.

  The second filter unit 15 is not limited to the signal x (n−1), and may perform signal processing on a signal obtained by delaying the input signal x by a predetermined delay amount and output the output signal y. . At this time, the transition state detection unit 22 detects the transition state of the output signal y by delaying the symbol determination value d0 by the delay amount described above. That is, the time slot of the symbol determination value d0 that is the detection target of the transition state and the time slot of the signal that is the signal processing target in the second filter unit 15 are the same.

  The delay amounts of the delay circuits 111a to 111h correspond to the time resolution of the impulse response of the digital filter 1, and the tap coefficient h0, the tap coefficient hr, and the tap coefficient hf form an impulse response profile. For this reason, the delay amount of the delay circuits 111a to 111h is not limited to half the symbol period T (T / 2).

  In general, the tap coefficient vector is adaptively updated so that the error between the symbol determination value and the output signal is minimized. The delay amount of the delay circuit 142, the delay amount of the delay circuit 182 and the delay The delay amount of the circuit 192 is not limited to one symbol period T.

  DESCRIPTION OF SYMBOLS 1 ... Digital filter, 11 ... 1st filter part, 12 ... Temporary determination part (1st determination part), 14 ... Update part (1st update part), 15 ... 2nd filter part, 16 ... This determination part (2nd Determination unit), 17 ... error calculation unit, 18 ... update unit (second update unit), 19 ... update unit (third update unit), 21 ... error statistic value calculation unit, 22 ... transition state detection unit, 23 ... switching Part, d ... symbol judgment value (second symbol judgment value), d0 ... symbol judgment value (first symbol judgment value), e ... error, h0 ... tap coefficient (first tap coefficient), hf ... tap coefficient (third Tap coefficient), hr ... tap coefficient (second tap coefficient), SEL ... selection signal, sf ... error statistical value (second error statistical value), sr ... error statistical value (first error statistical value), x ... input signal , Y... Output signal, y0... Output signal (determination signal).

Claims (7)

A digital filter that outputs an output signal with respect to an input signal,
A first filter unit that outputs a signal obtained by performing signal processing on the input signal using a first tap coefficient as a determination signal;
A transition state detection unit for detecting a transition state of the determination signal;
According to the transition state, either a second tap coefficient that is a rising tap coefficient or a third tap coefficient that is a falling tap coefficient is selected, and a signal is transmitted to the input signal using the selected tap coefficient. A second filter unit that outputs a signal obtained by performing processing as the output signal;
A second updating unit for updating the second tap coefficient;
A third updating unit for updating the third tap coefficient;
Equipped with a,
The second update unit updates the second tap coefficient when the transition state indicates rising and when the transition state indicates no transition,
The third updating unit, indicating down the transition state stood, and to indicate that the transition state without transition, to update the third tap coefficients, the digital filter.   The digital filter according to claim 1, further comprising a first updating unit that updates the first tap coefficient. The input signal has a plurality of symbols generated by multi-level modulation,
The digital filter includes a first determination unit that performs symbol determination as to which symbol of the plurality of symbols the determination signal is assigned, and outputs a first symbol determination value according to the determined symbol. In addition,
The digital filter according to claim 1 , wherein the transition state detection unit detects a transition state of the determination signal using the first symbol determination value. The transition state detection unit detects the transition state of the determination signal after delaying the first symbol determination value by a predetermined delay amount,
The digital filter according to claim 3 , wherein the second filter unit outputs, as the output signal, a signal obtained by performing the signal processing on a signal obtained by delaying the input signal by the delay amount. A second determination unit that performs symbol determination as to which of the plurality of symbols the output signal is assigned to, and outputs a second symbol determination value according to the determined symbol;
An error calculator that calculates an error between the second symbol determination value and the output signal;
A first error statistical value obtained by performing statistical processing on the error when the second tap coefficient is selected, and a first error statistical value obtained by performing statistical processing on the error when the third tap coefficient is selected. 2 error statistic values, and an error statistic calculation unit for calculating
Further comprising
The second filter unit selects the second tap coefficient when the transition state indicates no transition and the first error statistic value is smaller than the second error statistic value, and the transition It indicates that the state does not transition, and when the second error statistic is less than the first error statistic, selects the third tap coefficient, digital claim 3 or claim 4 filter. A switching unit that outputs a selection signal for causing the second filter unit to select one of the second tap coefficient and the third tap coefficient according to the transition state;
The digital filter according to any one of claims 1 to 5 , wherein the second filter unit selects one of the second tap coefficient and the third tap coefficient in accordance with the selection signal. The first filter unit is a first finite impulse response filter including a first delay line in which a plurality of delay circuits are connected in series.
The second filter unit is a second finite impulse response filter including a second delay line in which a plurality of delay circuits are connected in series.
Said portion of said plurality of delay circuits of the first delay line, the second is used as a part of said plurality of delay circuits of the delay line, digital according to any one of claims 1 to 6 filter.