JP2013153313A - Equalization device and equalization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a feedback time margin while suppressing a reduction in setup time.SOLUTION: An equalization device 5 comprises: a clock output section 50 for outputting a data clock notifying a sampling timing such that an interval between the sampling timing and the preceding edge timing is shorter than an interval between the sampling timing and the following edge timing; a data sampling section 52 for sampling a value of an input signal at the sampling timing; and an equalization section 51 for feeding back the value of the input signal to the edge timing. The data sampling section 52 includes: a first determination section 520 for determining the value of the input signal on a plus threshold voltage value higher than a reference voltage value; a second determination section 521 for determining the value of the input signal on a minus threshold voltage value lower than the reference voltage value; and a selection section 522 for selecting the value of the input signal determined by the determination section whose reference voltage value is the voltage value on the voltage value side corresponding to the preceding sampled value of the input signal.

Description

  The present invention relates to an equalization apparatus and an equalization method, and more particularly to a technique for equalizing an input signal having a deteriorated signal waveform.

  In recent years, a shortage of transmission line bandwidth has become apparent as the communication speed increases. Due to the insufficient bandwidth of the transmission line, the signal waveform is distorted, causing intersymbol interference. Intersymbol interference means that one symbol in a signal interferes with another symbol. This intersymbol interference reduces the eye opening and makes it difficult to determine the bit value of the input signal input to the receiving side. As a method for solving this intersymbol interference, waveform equalization can be mentioned.

  Waveform equalization is a technique for intentionally changing a part of a signal waveform to remove the influence of intersymbol interference. As one of the waveform equalization techniques, there is a decision feedback type equalization that is processed only on the receiving side. In decision feedback equalization, the bit value indicated by the input signal is determined from the waveform of the input signal. Then, based on the determination result, the influence of deterioration due to the waveform of the already received input signal is removed from the input signal input to the receiving side next.

  FIG. 9 shows an example of an input signal degraded by intersymbol interference. This input signal indicates a signal determined as a bit value of 0 or 1 depending on the voltage value. FIG. 9 shows an example of an input signal whose expected value is that the bit value of the symbol in the main tap is 1 and the bit value of the symbol in the other tap is 0. This input signal has received the interference of the voltage value in a main tap, and the voltage value of each of the 1st-3rd post tap has not fallen completely. Therefore, for example, if the voltage value of the first post-tap is higher than the reference voltage value that defines the bit value of 0 or 1, the bit value of the symbol in the first post-tap is erroneously determined as 1. Will be.

  In contrast, in decision feedback equalization, intersymbol interference after the first post-tap can be removed. Specifically, the intersymbol interference at each post tap can be removed by feeding back the bit value determination result at the main tap to each post tap.

  On the other hand, with an increase in communication speed, there is a demand for faster decision feedback equalization. However, in the decision feedback equalizer, it is necessary to feed back the decision result by the decision timing of the next bit value. Therefore, due to the performance limitation of the circuit, it is difficult to increase the communication speed because the feedback time is not in time for 1 UI of the margin. Note that 1 UI means one symbol length.

  In order to solve this problem, it has been proposed to use, for example, a loop unroll method disclosed in Non-Patent Document 1 as a speed-up technique for decision feedback equalization. The loop unroll method is a method of equalizing an input signal while performing speculative execution without returning the first post tap. Therefore, by using the loop unroll method, the feedback time margin that was 1 UI is not until the next bit value determination timing, but until the next bit value determination timing as shown in FIG. 10A. be able to. For example, in FIG. 10A, the determination timing of the bit value “d1” corresponds to the main tap, and the determination timing of the bit value “d3” corresponds to the second post-tap. Therefore, the feedback time margin is relaxed to 2 UI, and the communication speed can be increased.

John F. Bulzacchelli, et al., "A 10-Gb / s 5-Tap DFE / 4-Tap FFE Transceiver in 90-nm CMOS Technology," IEEE Journal of Solid-State Circuit, vol.41, no.12, pp.2885-2900, Dec., 2006.

  In recent communication systems, clock data recovery (CDR) for recovering clock timing from an input signal is generally performed on the receiving side. In order to perform this CDR, it is necessary to sample the bit value of the input signal even at the edge timing which is the switching timing of the bit value of the input signal. Therefore, when performing CDR, it is preferable to feed back the determination result to this edge timing. In this case, the feedback time margin is reduced by 0.5 UI as compared with the case where the edge timing is not considered. That is, even when the loop unroll method is implemented, the feedback time margin is 1.5 UI as shown in FIG. 10B. For this reason, expansion of a feedback time margin becomes a subject for further increase in communication speed.

  On the other hand, a fixed setup time is required to determine the bit value of the input signal. The setup time is the time from the edge timing to the next determination timing. That is, the setup time is the time from when the bit value of the input signal is switched to when the bit value is determined. When the setup time cannot be required, there is a problem that the bit value of the input signal cannot be normally determined. That is, the error rate in determining the bit value is deteriorated.

  An object of the present invention is to provide an equalization apparatus and an equalization method capable of increasing a feedback time margin while suppressing a decrease in setup time in order to solve the above-described problem.

  An equalization apparatus according to a first aspect of the present invention is an equalization apparatus that equalizes an input signal that shows a different value depending on whether a voltage value is higher or lower than a predetermined reference voltage value. A clock output unit that outputs a data clock that notifies data sampling timing between edge timings, a data sampling unit that samples the value of the input signal at the data sampling timing based on the data clock, and sampling by the data sampling unit An equalization unit that equalizes the input signal by feeding back the value of the input signal to the input signal at the edge timing after the data sampling timing obtained by sampling the value of the input signal. The output unit immediately before the data sampling timing The data clock is output so that the period until the edge timing becomes shorter than the period from the data sampling timing to the edge timing immediately after the data sampling timing, and the data sampling unit has a first predetermined value higher than the reference voltage value. A first determination unit that determines the value of the input signal at the data sampling timing, with a positive threshold voltage value that is higher by a voltage value as the reference voltage value, and a second predetermined voltage value lower than the reference voltage value Of the second determination unit that determines the value of the input signal at the data sampling timing, the first determination unit, and the second determination unit, with the negative threshold voltage value as the reference voltage value, the previous sampling is performed. The input signal determined by the determination unit using the voltage value on the voltage side corresponding to the input signal value as the reference voltage value. The values, a selection unit for selecting as a value of the input signal the sampling, is intended to include.

  An equalization method according to a second aspect of the present invention is an equalization method for equalizing an input signal indicating a different value depending on whether a voltage value is higher or lower than a predetermined reference voltage value. A clock output step for outputting a data clock for notifying a data sampling timing between edge timings; a data sampling step for sampling the value of the input signal at the data sampling timing based on the data clock; and the sampled input signal An equalization step of equalizing the input signal by feeding back the value of the input signal to the input signal at the edge timing after the data sampling timing at which the value of the input signal is sampled, and in the clock output step, From the data sampling timing, the previous error The data clock is output so that the period until the timing is shorter than the period from the data sampling timing to the immediately following edge timing, and the data sampling step includes the reference voltage value at the data sampling timing. A determination of the value of the input signal with a positive threshold voltage value higher by a first predetermined voltage value than the reference voltage value, and a negative threshold voltage lower by a second predetermined voltage value than the reference voltage value. A step of determining the value of the input signal with the value as the reference voltage value, and the value of the input signal determined with the voltage value on the voltage value side corresponding to the value of the input signal sampled last time as the reference voltage value Selecting as the value of the sampled input signal.

  According to each aspect of the present invention described above, it is possible to provide an equalization apparatus and an equalization method capable of increasing a feedback time margin while suppressing a decrease in setup time.

It is a block diagram which shows the structure of the equalization apparatus concerning embodiment of this invention. It is a block diagram which shows the structure of the decision feedback type | mold equalization apparatus concerning embodiment of this invention. It is a figure which shows the eye pattern of the input signal waveform concerning embodiment of this invention. It is a figure which shows the eye pattern of the input signal waveform concerning embodiment of this invention. It is a figure which shows the eye pattern of the input signal waveform concerning embodiment of this invention. It is a flowchart which shows operation | movement of the decision feedback type | mold equalization part concerning embodiment of this invention. It is the figure which showed the feedback time margin when the phase difference of an edge clock and a data clock is 90 degree | times. It is the figure which showed the feedback time margin when the phase difference of an edge clock and a data clock is 45 degree | times. It is the figure which showed the feedback time margin when the phase difference of an edge clock and a data clock is 0 degree. It is the figure which showed the setup time and hold time in case the phase difference of an edge clock and a data clock is 90 degree | times by making a zero threshold value into the criterion of bit value. In the embodiment of the present invention, it is a diagram showing a setup time and a hold time when the phase difference between the edge clock and the data clock is 45 degrees. In the embodiment of the present invention, it is a diagram showing the setup time and hold time when the phase difference between the edge clock and the data clock is 0 degree. It is a figure which shows an example of the input signal degraded by intersymbol interference. It is a figure for demonstrating the subject of this invention. It is a figure for demonstrating the subject of this invention.

  First, with reference to FIG. 1, the structure of the equalization apparatus 5 used as the outline | summary of the decision feedback type | mold equalization apparatus 1 concerning embodiment of this invention is demonstrated. FIG. 1 is a block diagram showing a configuration of an equalization apparatus 5 according to an embodiment of the present invention.

  The equalization apparatus 5 includes a clock output unit 50, an equalization unit 51, and a data sampling unit 52. The data sampling unit 52 includes a first determination unit 520, a second determination unit 521, and a selection unit 522. The equalizer 5 equalizes input signals that show different values depending on whether the voltage value is higher or lower than a predetermined reference voltage value.

  The clock output unit 50 outputs a data clock clkd that notifies the data sampling timing between the edge timings of the input signal. Here, the clock output unit 50 outputs the data clock so that the period from the data sampling timing to the immediately preceding edge timing is shorter than the period from the data sampling timing to the immediately following edge timing.

  The equalization unit 51 feeds back the value of the input signal sampled by the data sampling unit 52 to the input signal at the edge timing one bit after the data sampling timing at which the value of the input signal is sampled. This equalizes the input signal.

  The data sampling unit 52 samples the value of the input signal at the data sampling timing based on the data clock clkd.

  The first determination unit 520 determines the value of the input signal at the data sampling timing using a positive threshold voltage value that is higher than the reference voltage value by a first predetermined voltage value as a reference voltage value. The second determination unit 521 determines the value of the input signal at the data sampling timing using a minus threshold voltage value lower than the reference voltage value by a second predetermined voltage value as the reference voltage value. The selection unit 522 is determined by the determination unit using the voltage value on the voltage value side corresponding to the value of the input signal sampled last time as the reference voltage value among the first determination unit 520 and the second determination unit 521. The value of the input signal is selected as the value of the sampled input signal.

  Next, processing of the equalization apparatus 5 according to the embodiment of the present invention will be described.

  The clock output unit 50 outputs a data clock that notifies the data sampling timing between the edge timings of the input signal. At this time, the clock output unit 50 outputs the data clock so that the period from the data sampling timing to the immediately preceding edge timing is shorter than the period from the data sampling timing to the immediately following edge timing.

  The data sampling unit 52 samples the value of the input signal at the data sampling timing based on the data clock clkd. At this time, the first determination unit 520 determines the value of the input signal at the data sampling timing with a plus threshold voltage value that is higher than the reference voltage value by a first predetermined voltage value as the reference voltage value. In addition, the second determination unit 521 determines the value of the input signal at the data sampling timing with a negative threshold voltage value lower than the reference voltage value by a second predetermined voltage value as the reference voltage value. Then, the selection unit 522 is determined by the determination unit using the voltage value on the voltage value side corresponding to the value of the input signal sampled last time as the reference voltage value among the first determination unit 520 and the second determination unit 521. The value of the input signal thus selected is selected as the value of the sampled input signal.

  The equalization unit 51 feeds back the value of the input signal sampled by the data sampling unit 52 to the input signal at the edge timing 1 bit after the data sampling timing at which the value of the input signal is sampled.

  As described above, in the equalization apparatus 5 according to the present embodiment, the period from the data sampling timing to the immediately preceding edge timing is shorter than the period from the data sampling timing to the immediately following edge timing. Thus, the data clock is output. According to this, it is possible to lengthen the period from the data sampling timing for acquiring the value of the input signal to the edge timing for feeding back the value of the input signal. Therefore, the feedback time margin can be increased.

  At this time, since the period from the edge timing to the data sampling timing is shortened, it seems that the setup time is shortened. However, in this embodiment, the first determination unit that determines the value of the input signal with the positive threshold voltage value and the second determination unit that determines the value of the input signal with the negative threshold voltage value are sampled last time. The value of the input signal determined by the determination unit using the voltage value on the voltage value side corresponding to the input signal value as the reference voltage value is selected as the value of the sampled input signal. According to this, when the bit value of the input signal changes, the timing for recognizing the bit value after the transition can be advanced. Therefore, even if the period from the edge timing to the data sampling timing is shortened, a decrease in the setup time can be suppressed.

  Then, with reference to FIG. 2, the structure of the decision feedback type | mold equalization apparatus 1 concerning embodiment of this invention is demonstrated. FIG. 2 is a block diagram showing the configuration of the decision feedback equalizer 1 according to the embodiment of the present invention.

  The decision feedback equalization apparatus 1 includes a decision feedback equalization unit 10 and a CDR unit 20. The decision feedback equalization unit 10 includes addition units 101 to 103, calculation units 104 and 105, threshold offset units 106 to 108, determination units 109 to 111, a selection unit 112, and a data holding unit 113. The CDR unit 20 includes a clock output unit 201, a clock phase detection unit 202, and a clock phase adjustment unit 203. Each of the decision feedback equalization unit 10 and the CDR unit 20 is configured by, for example, a circuit that realizes each function described later.

  Here, the input signal shown in FIG. 3 is input to the decision feedback equalizer 1. FIG. 3 is a diagram showing an eye pattern after equalization of the input signal waveform. In the present embodiment, as illustrated in FIG. 3, a case where a binary signal is input as an input signal is illustrated. When the input signal is determined by binary values of 0 and 1, the bit value is determined as 1 if the voltage value of the input signal is higher than the zero threshold, and the bit value is 0 if the voltage value of the input signal is lower than the zero threshold. It is determined. In the present embodiment, a case where the zero threshold is 0V will be described. In FIG. 3, “edge clock timing” corresponds to edge timing, and “data clock timing” corresponds to determination timing. The input signal is, for example, a signal received from another device.

  The addition unit 101 adds the addition signal output from the calculation unit 104 to the input signal, and outputs the input signal to the threshold value offset unit 106. Each of the addition units 102 and 103 adds the addition signal output from the calculation unit 105 to the input signal, and outputs the input signal to each of the threshold value offset units 107 and 108.

  Each of arithmetic units 104 and 105 calculates an added voltage value for removing intersymbol interference at the edge timing after the first post-tap based on the retained bit value signal output from data retaining unit 113. The held bit value signal is a signal indicating the bit value of the input signal determined in the past, held in the data holding unit 113. Each of the calculation units 104 and 105 outputs an addition signal that takes the calculated addition voltage value to the addition units 102 and 103.

  Here, a method of calculating the added voltage value by the arithmetic units 104 and 105 will be described with reference to FIG. In the input signal shown in FIG. 9, for example, when the voltage value at the edge timing between the first post-tap and the second post-tap is 0.4 V due to intersymbol interference, each of the arithmetic units 104 and 105 is -0.4V which removes the voltage value is calculated as an additional voltage value. This added voltage value is calculated by, for example, multiplying the voltage value at the main tap by a predetermined weight. Different weights may be prepared for each edge timing.

  Then, the calculation unit 104 outputs an addition signal that takes the calculated addition voltage value to the addition unit 101 before the edge timing between the first post-tap and the second post-tap. Thereby, the adder 101 can generate an input signal from which intersymbol interference is removed at the edge timing between the first post-tap and the second post-tap. In addition, the calculation unit 105 also outputs an addition signal that takes the calculated addition voltage value to the addition units 102 and 103 before the second post-tap timing (determination timing). As a result, the adders 102 and 103 can generate an input signal from which intersymbol interference is removed at the second post-tap.

  However, as shown in FIG. 9, the voltage value due to intersymbol interference at the edge timing between the first and second post taps and the voltage value due to intersymbol interference at the second post tap are close to each other. Strictly different values of things. Therefore, as described above, when the intersymbol interference is removed based on only the voltage value at the edge timing, the accuracy of removing the intersymbol interference at the post-tap is lowered. However, in this way, the processing contents in the arithmetic units 104 and 105 can be made the same logic, so that development costs can be reduced. A method of removing intersymbol interference at the edge timing based on the voltage value of the edge timing as described above is called “edge equalization”. Conversely, a method of removing intersymbol interference at the determination timing with reference to the voltage value at the determination timing is referred to as “center equalization”. Here, since the arithmetic units 104 and 105 perform the same processing, the arithmetic units 104 and 105 may be configured by one circuit and output the addition signal to the addition units 101 to 103. By doing so, the circuit scale can be reduced.

  Here, the method of removing intersymbol interference is not limited to edge equalization. That is, the calculation unit 105 may calculate an addition voltage value that eliminates a voltage value due to intersymbol interference at the post-tap, and output an addition signal that takes the calculated addition voltage value to the addition units 102 and 103. . In this case, a weight for calculating the added voltage value is also prepared for each post-tap. By doing so, intersymbol interference can be removed more accurately. That is, an intersymbol interference removal method combining edge equalization and center equalization may be performed.

  It should be noted that the intersymbol interference is removed at the edge timing between the first post-tap and the second post-tap and also at the determination timing other than the timing of the second post-tap. Since it becomes the same, description is abbreviate | omitted. For example, as shown in FIG. 9, when intersymbol interference occurs before the fourth post-tap, the intersymbol interference is removed at each of the edge timing and the determination timing before the fourth post-tap. Note that the addition units 101 to 103 and the calculation units 104 and 105 correspond to the equalization unit 51.

  The threshold offset unit 106 adds the offset voltage to the input signal from the addition unit 101 and outputs the input signal to the determination unit 109. Here, since it is not necessary to offset the input signal in the threshold offset unit 106, 0V is used as the offset voltage. Therefore, a configuration without the threshold offset unit 106 may be employed.

  The threshold offset unit 107 adds an offset voltage that is a positive threshold (+ α) to the input signal output from the addition unit 102 and outputs the added signal to the determination unit 110. The threshold value offset unit 108 adds an offset voltage that is a minus threshold value (−α) to the input signal output from the addition unit 103 and outputs the result to the determination unit 111. That is, the plus threshold (+ α) is a voltage value obtained by adding an offset voltage to the zero threshold, and the minus threshold (−α) is a voltage value obtained by subtracting the offset voltage from the zero threshold.

  Arbitrary voltage values can be determined in advance as the positive threshold value (+ α) and the negative threshold value (−α). The positive threshold value (+ α) and the negative threshold value (−α) are determined in advance as voltage values located in the middle of the line segment surrounded by the eye opening, for example, in the voltage pattern at the data clock timing in the eye pattern. . Specifically, as shown in FIG. 4, the positive threshold (+ α) is an eye opening of the straight line in the voltage direction at the data clock timing in the eye pattern of the input signal waveform determined by the positive threshold (+ α). The negative threshold value (−α) is defined as a voltage value located in the middle of the enclosed line segment, and the voltage pattern straight line at the data clock timing in the eye pattern of the input signal waveform determined by the negative threshold value (−α). Is determined as a voltage value located in the middle of the line segment surrounded by the eye opening. The input signal waveform to be determined in each of the plus threshold (+ α) and the minus threshold (−α) will be described in detail later.

  The determination unit 109 determines the bit value of the input signal output from the threshold offset unit 106 at the rising timing of the edge clock clke with reference to the zero threshold. The determination unit 109 outputs the determined bit value to the clock phase detection unit 202. Here, the edge clock clke is a clock signal in which a rising edge occurs at the edge timing.

  The determination unit 110 determines the bit value of the input signal output from the threshold offset unit 107 at the rising timing of the data clock clkd with reference to the zero threshold. The determination unit 110 outputs the determined bit value to the selection unit 112. Here, an input signal to which an offset voltage that is a positive threshold is added by the threshold offset unit 107 is input to the determination unit 110. Therefore, the determination unit 110 substantially determines the bit value of the input signal by regarding the minus threshold as the zero threshold. The data clock clkd is a clock signal that generates a rising edge at the determination timing. The threshold offset unit 107 and the determination unit 110 correspond to the second determination unit 521.

  The determination unit 111 determines the bit value of the input signal output from the threshold offset unit 108 at the rising timing of the data clock clkd with reference to the zero threshold. The determination unit 111 outputs the determined bit value to the selection unit 112. Here, an input signal to which an offset voltage that is a negative threshold is added by the threshold offset unit 108 is input to the determination unit 111. Therefore, the determination unit 111 substantially determines the bit value of the input signal by regarding the plus threshold as the zero threshold. The threshold offset unit 108 and the determination unit 111 correspond to the first determination unit 520.

  The selection unit 112 selects a bit value output from one of the determination unit 110 and the determination unit 111 based on the stored bit value signal output from the data storage unit 113, and inputs the input signal to the data storage unit 113. Output as the bit value of. As shown in the input signal waveforms 70 and 71 shown in FIG. 5, when a bit value of 1 is taken at the next data clock timing after taking a bit value of 1 at the data clock timing, the input signal is caused by intersymbol interference. In some cases, the voltage value does not fall below the zero threshold. Therefore, when the bit value of the input signal at the previous data clock timing is 1 in the held bit value, the selection unit 112 selects the bit value output from the determination unit 111 and outputs it to the data holding unit 113. In other words, the bit value of the input signal is determined by regarding the plus threshold as the zero threshold. According to this, even if the voltage value of the input signal does not fall to a voltage value lower than the zero threshold value due to intersymbol interference and slightly exceeds the zero threshold value, the bit value is erroneously 1 It is possible to prevent erroneous determination. That is, in FIG. 9, the bit value is not erroneously determined even when the voltage value of the first post-tap has not fallen below the zero threshold due to the interference of the voltage value at the main tap. Can do. Therefore, it is possible to correctly determine the bit value at the first post-tap without feeding back the bit value at the main tap to the first post-tap, so that loop unrolling can be performed.

  In addition, when the bit value 81 of 1 is taken at the next data clock timing after taking the bit value of 0 at the data clock timing as shown in the input signal waveforms 72 and 73 shown in FIG. In some cases, interference does not allow the voltage value to rise higher than the zero threshold. Therefore, when the bit value of the input signal at the previous data clock timing is 0 in the held bit value, the selection unit 112 selects the bit value output from the determination unit 110 and outputs the selected bit value to the data holding unit 113. In other words, the bit value of the input signal is determined by regarding the minus threshold as the zero threshold. According to this, even when the voltage value of the input signal does not rise to a voltage value higher than the zero threshold value due to intersymbol interference and is slightly below the zero threshold value, the bit value is erroneously 0. It is possible to prevent erroneous determination. The selection unit 112 corresponds to the selection unit 522.

  The data holding unit 113 holds the bit value output from the selection unit 112. Further, the data holding unit 113 outputs a held bit value signal indicating the held bit value to the selection unit 112 and the calculation units 104 and 105. For example, as shown in FIG. 9, when the interference due to the voltage value in the main tap extends to the third post tap, the bit values up to at least three before are held. By doing so, the bit value in the main tap can be fed back to the third post tap. The number of previous bit values may be arbitrarily determined in advance according to the influence of intersymbol interference. In this embodiment, in order to perform loop unrolling, the bit value at the main tap may be fed back to the input signal at the edge timing and determination timing after the first post tap.

  The clock output unit 201 outputs a data clock clkd and an edge clock clke. The phase of the data clock clkd is arbitrarily determined in advance so as to take a phase difference between 0 degrees and less than 90 degrees with the edge clock clke as a reference. The clock output unit 201 corresponds to the clock output unit 50.

  Whether the phase of the data clock and the edge clock is advanced with respect to the symbol of the input signal based on the bit values at the edge clock timing and the data clock timing output from the determination unit 109 and the selection unit 112 Or determine if you are late. The clock phase detection unit 202 outputs a determination result signal indicating the determination result to the clock phase adjustment unit 203.

  Based on the determination result signal output from the clock phase detection unit 202, the clock phase adjustment unit 203 outputs a phase adjustment signal for adjusting the phases of the data clock clkd and the edge clock clke to be appropriate phases. Output to. Thus, the phases of the data clock clkd and the edge clock clke output from the clock output unit 204 are adjusted to appropriate phases. That is, CDR is performed by the clock phase detection unit 202, the clock phase adjustment unit 203, and the clock output unit 204.

  Next, the operation of the decision feedback equalizer 10 according to the embodiment of the present invention will be described with reference to FIG. FIG. 6 is a flowchart showing the operation of the decision feedback equalizer 10 according to the embodiment of the present invention.

  The input signal input to the decision feedback equalizer 1 is input to each of the adders 101 to 103. The addition unit 102 adds the addition signal output from the calculation unit 105 to the input signal, and outputs the input signal to the threshold offset unit 107 (S1). The addition unit 103 adds the addition signal output from the calculation unit 105 to the input signal, and outputs the input signal to the threshold value offset unit 108 (S2). The addition unit 101 adds the addition signal output from the calculation unit 104 to the input signal, and outputs the input signal to the threshold value offset unit 106 (S3).

  The threshold offset unit 107 adds an offset voltage corresponding to the plus threshold to the input signal, and outputs the input signal to the determination unit 110 (S4). The threshold offset unit 108 adds an offset voltage corresponding to the plus threshold to the input signal and outputs the input signal to the determination unit 111 (S5). The threshold value offset unit 106 adds an offset voltage of 0 V to the input signal and outputs the input signal to the determination unit 109 (S6).

  When the rising edge of the data clock from the clock output unit 201 is input, the determination unit 110 determines the bit value of the input signal output from the threshold offset unit 107 (S7). The determination unit 109 outputs the determined bit value to the selection unit 112. When the rising edge of the data clock from the clock output unit 201 is input, the determination unit 111 determines the bit value of the input signal output from the threshold offset unit 108 (S8). The determination unit 111 outputs the determined bit value to the selection unit 112. When the rising edge of the edge clock from the clock output unit 201 is input, the determination unit 109 determines the bit value of the input signal output from the threshold offset unit 106 (S9). The determination unit 109 outputs the determined bit value to the clock phase detection unit 202.

  The selection unit 112 determines whether or not the bit value determined last time is 1 among the holding bit values output from the data holding unit 113 (S10). When the bit value determined last time is 1 (S10: Yes), the selection unit 112 selects the bit value output from the determination unit 111 and outputs it to the data holding unit 113. When the previously determined bit value is 0 (S10: No), the selection unit 112 selects the bit value output from the determination unit 110 and outputs the selected bit value to the data holding unit 113.

  The data holding unit 113 holds the bit value output from the selection unit 112. The data holding unit 113 outputs the held bit value to the calculation units 104 and 105. Each of the arithmetic units 104 and 105 calculates an addition signal based on the bit value output from the data holding unit 113 (S14 and S13). Operation unit 104 outputs the calculated addition signal to addition unit 101. This addition signal is added to the input signal by the addition unit 101 (S3). The calculation unit 105 outputs the calculated addition signal to each of the addition units 102 and 103. This addition signal is added to the input signal by each of the addition units 102 and 103 (S1, S2).

  Next, effects of the embodiment of the present invention will be described with reference to FIGS.

  When the phase difference between the edge clock clkd and the data clock clke is 90 degrees, the feedback time margin when the main tap is fed back to the edge timing between the first post tap and the second post tap is 1 as shown in FIG. 7A. .5 UI. This is the same as FIG. 10B. On the other hand, the feedback time margin can be increased by setting the phase difference between the edge clock clkd and the data clock clke to a phase difference of 0 to less than 90 degrees as in the present embodiment. .

  For example, when the phase difference between the edge clock clkd and the data clock clke is 45 degrees, as shown in FIG. 7B, the feedback time margin when the main tap is fed back to the edge timing between the first post tap and the second post tap. Is 1.75 UI. When the phase difference between the edge clock clkd and the data clock clke is 0 degree, as shown in FIG. 7C, a feedback time margin when the main tap is fed back to the edge timing between the first post tap and the second post tap. Is 2.0 UI.

  As described above, in this embodiment, the phase difference between the edge clock clkd and the data clock clke is set to a phase difference of 0 degree to less than 90 degrees, so that the feedback time is smaller than that in the case where the phase difference is 90 degrees. The margin can be increased. As a result, the communication speed can be increased. Among them, the feedback time margin can be maximized by setting the phase difference to 0 degree.

  Here, as described above, when the bit value of the input signal is determined by the circuit, a certain setup time is required. However, as shown in FIGS. 7A to 7C, the setup time generally decreases as the phase difference between the edge clock clkd and the data clock clke decreases.

  On the other hand, as in this embodiment, the phase difference between the edge clock clkd and the data clock clke is set from 0 degrees to less than 90 degrees, and the input signal varies depending on different threshold values for enabling loop unrolling. By combining with the configuration for determining the bit value, it is possible to increase the feedback time margin while suppressing a decrease in the setup time. The reason will be described below.

  In general, since the bit value is determined based on the zero threshold, the bit value after the transition from the edge clock timing can be recognized as shown in FIG. 8A. FIG. 8A shows a case where the phase difference between the edge clock and the data clock is 90 degrees. In this case, the setup time 90 is from the edge clock timing to the next data clock timing. The hold time 91 is from the data clock timing to the next edge clock timing. Therefore, when the phase difference between the edge clock clkd and the data clock clke is simply set to 0 degrees to less than 90 degrees, there is a problem that the setup time is reduced. That is, the feedback time margin and the setup time are in a trade-off relationship. Note that the setup time 90 and the hold time 91 are the minimum setup time and hold time.

  FIG. 8B shows a case where the phase difference between the edge clock clkd and the data clock clke is 45 degrees. Here, in the present embodiment, for example, as shown in FIG. 8B, when the input signals indicated by the input signal waveforms 70 and 74 are input, the bit value is determined at the data clock timing shown in the figure. The bit value is determined by the unit 111 on the basis of the plus threshold. According to this, the bit value after the transition can be recognized from the timing before the edge clock timing. Therefore, even when the phase difference between the edge clock clkd and the data clock clke is 0 degree to less than 90 degrees, it is possible to suppress a decrease in setup time.

  However, as shown in FIG. 8C, when the phase difference between the edge clock clkd and the data clock clke is further reduced, the hold time 91 increases, but the setup time 90 decreases. FIG. 8C illustrates the case where the plus threshold is the same as that in FIG. 8B and the phase difference is 0 degree. That is, as described above, since the feedback margin and the setup time are in a trade-off relationship, an optimal phase difference may be selected.

  Here, also in the case shown in FIG. 8C, the setup time can be increased if the positive threshold value is set to a higher voltage value. However, if the positive threshold value is set too high, the voltage value of the input signal falls below the positive threshold value due to jitter or the like, and the bit value that should be determined as 1 may be erroneously determined as 0. Therefore, preferably, the phase difference is set to 45 degrees. Further, as described above, in the eye pattern, the voltage value positioned in the middle of the line segment surrounded by the eye opening in the voltage direction straight line at the data clock timing is set. It may be determined as a positive threshold. By doing so, almost the center of the eye opening 60 surrounded by the input signal waveforms 70 and 74 having the same inclination can be set as the timing for switching from the setup time to the hold time. Therefore, as shown in FIG. 8B, the setup time 90 and the hold time 91 can be set to substantially the same time. Further, since the positive threshold value can be prevented from being too high as compared with the case where the phase difference is set to 0 degree, the erroneous determination as described above can be suppressed. Since the same can be said for the minus threshold side, the description thereof is omitted.

  Furthermore, in the loop unroll method, since the first post-tap is equalized without feedback, there is a problem that the jitter of the input signal slightly increases. However, CDR requires that edges be detected correctly. On the other hand, in the present embodiment, edge equalization is performed. By performing edge equalization, the intersymbol interference at the edge timing can be accurately removed, so that the jitter at the edge timing can be further reduced.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

  In the present embodiment, the case of having one decision feedback type equalization unit is illustrated, but an n-phase (n is a natural number) configuration including a plurality of decision feedback type equalization units may be employed. Further, the circuits constituting the decision feedback equalization unit 10 and the CDR unit 20 are not limited to the configuration of the present embodiment as long as the circuit satisfies the above-described operation of the present embodiment.

  In the present embodiment, the offset voltage from the zero threshold value to the plus threshold value and the offset voltage from the zero threshold value to the minus threshold value are set to the same voltage value, but each offset voltage may be a different voltage value. Also, the zero threshold value is not limited to 0 V, and may be another voltage value.

  In the present embodiment, loop unrolling is performed, but loop unrolling may not be performed according to the input speed of the input signal. In other words, loop unrolling may not be performed on an input signal having a speed in which feedback from the main tap to the first post tap and each of the edge timings between the main tap and the first post tap is in time.

  In the present embodiment, as a preferred example, the phase difference is 45 degrees, and in the eye pattern, the voltage positioned in the middle of the line segment surrounded by the eye opening in the voltage direction straight line at the data clock timing. Although cases have been described in which values are defined as positive threshold values or negative threshold values, the values are not necessarily limited to those values. That is, the phase difference may be approximately 45 degrees, and each of the positive threshold value and the negative threshold value may be a voltage value positioned approximately in the middle of the line segment surrounded by the eye opening. That is, the phase difference may be shifted from 45 degrees to several degrees. In other words, the ratio of the period until the edge clock timing immediately before the data clock timing and the period until the edge clock timing immediately after the data clock timing may be approximately 1: 3. Further, the voltage value set as the positive threshold value or the negative threshold value may be shifted by several percent from the middle of the line segment surrounded by the eye opening with respect to the entire length of the line segment.

DESCRIPTION OF SYMBOLS 1 Decision feedback type | mold equalization apparatus 5 Equalization apparatus 10 Decision feedback type | mold equalization part 20 CDR part 50 Clock output part 51 Equalization part 52 Data sampling part 101,102,103 Addition part 104,105 Operation part 106,107,108 Threshold offset unit 109, 110, 111 Determination unit 112 Selection unit 113 Data holding unit 201 Clock output unit 202 Clock phase detection unit 203 Clock phase adjustment unit 520 First determination unit 521 Second determination unit 522 Selection unit

Claims (9)

An equalizer for equalizing an input signal showing different values depending on whether the voltage value is higher or lower than a predetermined reference voltage value,
A clock output unit for outputting a data clock for notifying a data sampling timing between edge timings of the input signal;
A data sampling unit that samples the value of the input signal at the data sampling timing based on the data clock;
An equalization unit for equalizing the input signal by feeding back the value of the input signal sampled by the data sampling unit to the input signal at the edge timing after the data sampling timing of sampling the value of the input signal; With
The clock output unit outputs the data clock so that a period from the data sampling timing to the immediately preceding edge timing is shorter than a period from the data sampling timing to the immediately following edge timing;
The data sampling unit
A first determination unit that determines a value of the input signal at the data sampling timing with a positive threshold voltage value that is higher than the reference voltage value by a first predetermined voltage value as the reference voltage value;
A second determination unit that determines a value of the input signal at the data sampling timing with a negative threshold voltage value lower than the reference voltage value by a second predetermined voltage value as the reference voltage value;
Among the first determination unit and the second determination unit, the value of the input signal determined by the determination unit using the voltage value side voltage value corresponding to the value of the input signal sampled last time as the reference voltage value And a selection unit that selects as a value of the sampled input signal,
Equalizer. The equalization unit feeds back the value of the sampled input signal to an input signal at an edge timing subsequent to the data sampling timing after sampling the value of the input signal,
The equalization unit
An edge calculation unit that calculates an edge addition voltage value for correcting the voltage value of the input signal at the edge timing to the reference voltage value based on the value of the input signal;
An edge addition unit that adds an edge addition voltage value calculated by the edge calculation unit to the input signal;
The equalization apparatus according to claim 1.   The equalization apparatus according to claim 1 or 2, wherein the first predetermined voltage value and the second predetermined voltage value are the same voltage value. The clock output unit outputs the data clock so that a ratio between a period until the edge timing immediately before the data sampling timing and a period until the edge timing immediately after the data sampling timing is approximately 1: 3. And
In the eye pattern of the signal waveform of the input signal determined by the positive threshold voltage value, the positive threshold voltage value is approximately in the middle of the line segment surrounded by the eye opening among the straight lines in the voltage direction at the data sampling timing. Is the voltage value located,
The negative threshold voltage value is approximately in the middle of a line segment surrounded by an eye opening among straight lines in the voltage direction at the data sampling timing in the eye pattern of the signal waveform of the input signal determined by the negative threshold voltage value. The voltage value that is located,
The equalization apparatus according to claim 3. The clock output unit further outputs an edge clock notifying the edge timing,
The equalizer further includes an edge sampling unit that samples the value of the input signal at the edge timing based on the edge clock,
The clock output unit is configured to perform clock data recovery based on the value of the input signal sampled by the edge sampling unit and the value of the input signal sampled by the data sampling unit. Generate clock,
The equalization apparatus of any one of Claims 1 thru | or 4. The equalization device further includes:
A first offset unit for subtracting and outputting the first predetermined voltage value from the input signal;
A second offset unit that outputs the input signal by adding the second predetermined voltage value, and
The first determination unit determines the value of the input signal by using the plus threshold voltage value as the reference voltage value by comparing the input signal output from the first offset unit with the reference voltage value. ,
The second determination unit determines the value of the input signal using the negative threshold voltage value as the reference voltage value by comparing the input signal output from the second offset unit with the reference voltage value. ,
The equalization apparatus according to any one of claims 1 to 5. The equalization unit further feeds back the value of the sampled input signal to an input signal at a data sampling timing subsequent to the data sampling timing after sampling the value of the input signal,
The equalization unit
Based on the value of the input signal, a data calculation unit that calculates a data addition voltage value for correcting the voltage value of the input signal at the data sampling timing to the reference voltage value;
A data addition unit that adds the data addition voltage value calculated by the data operation unit to the input signal,
The equalization apparatus according to claim 2. The input signal is a signal that indicates 1 when it is higher than the reference voltage value, and indicates 0 when it is lower than the reference voltage value,
The selection unit selects the value of the input signal determined by the first determination unit when the value of the input signal sampled last time is 1, and the value of the input signal sampled last time is 0 In some cases, the value of the input signal determined by the second determination unit is selected.
The equalization apparatus according to any one of claims 1 to 7. An equalization method for equalizing an input signal showing different values depending on whether a voltage value is higher or lower than a predetermined reference voltage value,
A clock output step of outputting a data clock for notifying a data sampling timing between edge timings of the input signal;
A data sampling step of sampling the value of the input signal at the data sampling timing based on the data clock;
An equalization step of equalizing the input signal by feeding back the value of the sampled input signal to the input signal at the edge timing after the data sampling timing at which the value of the input signal is sampled, and
In the clock output step, the data clock is output so that a period from the data sampling timing to the immediately preceding edge timing is shorter than a period from the data sampling timing to the immediately following edge timing,
The data sampling step includes
At the data sampling timing, determination of the value of the input signal using a positive threshold voltage value that is higher than the reference voltage value by a first predetermined voltage value as the reference voltage value, and second than the reference voltage value. Determining a value of the input signal with a negative threshold voltage value that is lower by a predetermined voltage value as the reference voltage value;
Selecting the value of the input signal determined as the reference voltage value as the voltage value on the voltage value side corresponding to the value of the input signal sampled last time, as the value of the sampled input signal,
Equalization method.

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