JP6595256B2 - Volume control device - Google Patents

Description

  The present invention relates to a volume control device that controls an electronic volume of an audio device, and more particularly to a volume control device that reduces the gain switching noise (zipper noise) of the electronic volume and shortens the switching time.

  In the electronic volume, the gain is adjusted based on a command from a volume control device such as a microcomputer provided in the audio device, but zipper noise may occur at the time of switching for the adjustment.

  That is, when the gain of the input audio signal Vin is switched by a control signal at an arbitrary time point, as shown in FIG. 8A, a large inflection point C is formed in the output audio signal Vout and zipper noise is generated. .

  Therefore, as a method for improving zipper noise, (1) a method of switching gains at a time when zero-crossing detection of an input audio signal Vin is performed, (2) a method of switching gains in multiple steps at an arbitrary timing, ( 3) A method of switching gains in multiple steps by one step at each zero crossing time point (Patent Document 1), (4) A plurality of transition times at the start and end of switching of gains in a period from the start of switching to the end of switching A method of making the transition time longer than the stage transition time (Patent Document 2) has been proposed.

JP 2008-103877 A JP 2007-325057 A

  In the method (1) of switching the gains at a time when the zero crossing is detected, as shown in FIG. 8B, the potential variation of the output signal Vout at the time of the gain switching is small, and the generation of the inflection point is suppressed. In some cases, the gain is switched by the potential of the output signal Vout deviated from the zero-crossing point due to variations in the accuracy of the circuit that performs the zero-crossing detection or variations in the response speed of the entire device. In such a case, an inflection point is generated, Zipper noise occurs.

  In the method (2) in which the gain is switched step by step at an arbitrary point of time, since the potential change of the output signal Vout is small and the generation of the inflection point is suppressed because the step is switched step by step, the peak value of the input audio signal Vin When the gain is switched in the vicinity, the potential fluctuation of the output signal Vout increases as shown in FIG. As a result, the generation of inflection points is not suppressed and zipper noise occurs. In addition, by increasing the gain switching interval for each step, zipper noise caused by gain switching can be moved outside the audible frequency range (low frequency range). In this case, however, the switching time becomes longer and the control delay is delayed. Is a conspicuous problem in hearing.

  The method of switching the gain by one step at each zero crossing time point in (3) is the switching of the gain when the number of steps until the gain reaches the target value is large in addition to the problem described in the method of (1). The time required to complete the process becomes longer, and the delay may become noticeable in hearing. The audio signal in the general voice band has a high frequency of detection at the time of zero-crossing. However, in the case of professional equipment, the above-mentioned problem is serious because the frequency of detection of the zero-crossing time is low when handling low-frequency signals. It becomes.

  The method (4) of making the transition time at the start of the gain switching and the end of the switching larger than the transition time of a plurality of stages in the period from the start of the switching to the end of the switching is the same as in FIG. When switching around the peak value, even if the gain is switched gently, the potential difference that fluctuates becomes large, and the zipper noise may not be suppressed.

  An object of the present invention is to provide a volume control device that solves the above problems and realizes the suppression of the occurrence of zipper noise at the time of gain switching and the shortening of the switching time.

In order to achieve the above object, a volume control device according to a first aspect of the present invention is a volume control device for controlling the gain of an input audio signal by means of an electronic volume, and a volume setting circuit for setting the gain of the electronic volume, A clock generation circuit for generating a clock signal for performing stepwise switching of the gain of the electronic volume, and the volume setting circuit includes a first register in which a target value of the gain of the electronic volume is set; A second register in which the current value of the gain is set; an analysis circuit that compares the target value of the first register with the current value of the second register; and the second register according to a comparison result of the analysis circuit The current value of the first register is updated stepwise for each pulse of the clock signal toward the target value of the first register And a control circuit,
The clock generation circuit switches the frequency of the clock signal based on the magnitude of the output signal of the electronic volume.

  According to a second aspect of the present invention, in the volume control device according to the first aspect, the clock generation circuit sets the frequency of the clock signal high when the output signal of the electronic volume is small, and the output signal of the electronic volume When the frequency is large, the frequency of the clock signal is set low.

  According to a third aspect of the present invention, there is provided a volume control device for controlling a gain of an input audio signal by an electronic volume, a volume setting circuit for setting the gain of the electronic volume, and a clock for performing stepwise switching of the gain of the electronic volume. A clock generation circuit for generating a signal, wherein the volume setting circuit includes a first register in which a target value of the gain of the electronic volume is set, and a second register in which a current value of the gain of the electronic volume is set; An analysis circuit for comparing the target value of the first register with the current value of the second register, and the current value of the second register according to a comparison result of the analysis circuit. A control circuit that updates the clock signal step by step for each pulse of the clock signal. Serial and switches the frequency of the clock signal based on said current value of the magnitude and the second register of the output signal of the electronic volume.

  According to a fourth aspect of the present invention, there is provided the volume control device according to the third aspect, wherein the clock generation circuit has a frequency of the clock signal when the output signal of the electronic volume is small and the current value of the second register is small. Is set high, and when the output signal of the electronic volume is large and the current value of the second register is large, the frequency of the clock signal is set low.

  According to a fifth aspect of the present invention, there is provided a volume control device for controlling a gain of an input audio signal by an electronic volume, a volume setting circuit for setting the gain of the electronic volume, and a clock for performing stepwise switching of the gain of the electronic volume. A clock generation circuit for generating a signal, wherein the volume setting circuit includes a first register in which a target value of the gain of the electronic volume is set, and a second register in which a current value of the gain of the electronic volume is set; An analysis circuit for comparing the target value of the first register with the current value of the second register, and the current value of the second register according to a comparison result of the analysis circuit. A control circuit that updates the clock signal step by step for each pulse of the clock signal. Serial and switches the frequency of the clock signal on the basis of said target value of the magnitude and the first register of the output signal of the electronic volume.

  According to a sixth aspect of the present invention, in the volume control device according to the fifth aspect, the clock generation circuit has a small output signal of the electronic volume and a small difference between the target value of the first register and the output signal. When the frequency of the clock signal is set high, the frequency of the clock signal is set low when the output signal of the electronic volume is large and the difference between the target value of the first register and the output signal is large. To do.

  According to the present invention, the frequency of the clock signal for performing stepwise switching of the gain of the electronic volume is switched based on the output signal, the current value of the gain of the second register, the target value of the gain of the first register, etc. When the frequency of the clock signal increases, the time for switching one step at a time is shortened, and the gain can be shifted to the target value in a short time. When the frequency of the clock signal decreases, the time for switching one step at a time increases. Zipper noise can be suppressed without causing a delay that causes a sense of incongruity due to switching of the gain by moving the noise out of the audible range (low frequency range).

It is a block diagram which shows the structure of the volume control apparatus of 1st Example of this invention. It is an operation | movement waveform diagram of the volume control apparatus of 1st Example. It is explanatory drawing of the example 1 of a table of the volume control apparatus of 1st Example, and Example 2. FIG. It is explanatory drawing of the example 3 of the table of the volume control apparatus of 1st Example. It is a block diagram which shows the structure of the volume control apparatus of 2nd Example of this invention. It is a block diagram which shows the structure of the volume control apparatus of the 3rd Example of this invention. It is explanatory drawing of the table of the volume control apparatus of a 3rd Example. It is a waveform at the time of conventional volume switching.

<First embodiment>
FIG. 1 shows a circuit of a volume control apparatus according to the first embodiment of the present invention. Reference numeral 10 denotes an electronic volume, 20 denotes a volume setting circuit for setting the gain of the electronic volume 10, and 30 denotes a clock generation circuit for generating a clock for generating a gain switching timing of the electronic volume 10.

  The volume setting circuit 20 includes a first register 21 that sets a value of a target gain Gv21 input from the outside, a second register 22 that sets a value of a current gain Gv22 to be set in the electronic volume 10, and a first register 21. The target gain Gv21 and the current gain Gv22 value of the second register 22 are compared, and the current gain Gv22 value of the second register 22 is gradually increased according to the comparison result of the analysis circuit 23. And a control circuit 24 for updating toward the value of Gv21.

  The analysis circuit 23 compares the value of the target gain Gv21 in the first register 21 with the value of the current gain Gv22 in the second register 22, and gives a command of “attenuation” to the control circuit 24 when Gv21 <Gv22. When Gv21> GV22, an “amplification” command is issued. When Gv21 = Gv22, a “maintenance” command is issued.

  The control circuit 24 takes in the clock signal Vclk output from the clock generation circuit 30. When the command input from the analysis circuit 23 is “amplification”, one step per pulse of the clock signal Vclk, a control signal for increasing the value of the current gain Gv22 is output to the second register 22, Thus, the gain of the electronic volume 10 is increased by one step. Further, when “Attenuation” is set, a control signal for decreasing the value of the current gain Gv22 is output to the second register 22, thereby reducing the gain of the electronic volume 10 by one step. Further, when “maintain”, the second register 22 is not instructed to change the value of the current gain Gv22. The control circuit 24 issues a “mismatch” command to the clock generation circuit 30 when “amplification” and “attenuation” are input, and issues a “match” command when “maintain” is input. The amount by which the value of the current gain Gv22 of the second register 22 changes per step is constant (fixed value) ΔGv.

  The clock generation circuit 30 includes a clock generator 31 that generates a variable frequency clock signal Vclk, a table 32 that stores data for setting the frequency of the clock signal Vclk of the clock generator 31, and an output voltage Vout of the electronic volume 10. And a level detection circuit 33 for detecting the level (absolute value). The level detection circuit 33 is composed of, for example, a window comparator. Then, based on the absolute value level of the output audio signal Vout detected by the level detection circuit 33 and the value of the current gain Gv22 set in the second register 22, the potential per step of the output signal is described later. The fluctuation amount ΔVout is calculated. When the potential fluctuation amount ΔVout is obtained, frequency data corresponding to the potential fluctuation amount ΔVout is read from the table 32, and the frequency of the clock signal Vclk generated by the clock generator 31 is determined. An example of the table 32 is shown by a characteristic curve A in FIG.

で表される。 Here, calculation of the potential fluctuation amount ΔVout per step of the output signal Vout will be described. Assuming that the setting value Gv22 of the second register 22 is Gv22 (n) at the nth step and Gv22 (n + 1) at the n + 1 step, the output voltage Vout (n) at the nth step and n + 1 The output voltage Vout (n + 1) of the step is

It is represented by

で表される。 The potential fluctuation amount ΔVout is

It is represented by

  In this way, the clock generator 31 takes in the output voltage Vout (n) of the nth step detected by the level detection circuit 33, takes in the current gain Gv22 (n) of the nth step from the second register 22, Furthermore, by predicting the gain Gv22 (n + 1) of the (n + 1) th step from the current gain Gv22 (n), the potential fluctuation amount ΔVout per step can be detected. The prediction of the gain Gv22 (n + 1) at the (n + 1) th step is obtained by a value obtained by adding or subtracting the above-described fixed value ΔGv to the current gain Gv22.

  From the state where the level of the input audio signal Vin is constant and the value of the target gain Gv21 of the first register 21 and the value of the current gain Gv21 of the second register 22 are the same gain Gv (1), FIG. As shown in a), it is assumed that a gain Gv (2) larger than Gv (1) by Gv is set as the value of the target gain Gv21 in the first register 21 at a certain timing. At this time, since there is a relationship of Gv (1) <Gv (2), the analysis circuit 23 gives an “amplification” command to the control circuit 24. Therefore, the value of the current gain Gv22 of the second register 22 increases by ΔGv per clock of the clock signal Vclk input from the clock generation circuit 30, as shown in FIG. When the value of the current gain Gv22 of the second register 22 becomes Gv (2), a command “match” is given to the clock generation circuit 30 from the control circuit 24, and the clock signal Vclk stops. The gain ΔGv increasing per step is constant as described above, and as shown in FIG. 2B, ΔGv (n−1) = ΔGv (n) = ΔGv (n + 1).

  On the other hand, although the gain of the electronic volume 10 is set by the value of the current gain Gv22 of the register 22, the amount of change per step (potential fluctuation amount ΔVout) is large when the set gain is large. Small when the set gain is small. For example, in the case of “amplification”, when the value of the gain Gv22 changes by 1 dB from −1 dB to 0 dB, ΔVout = 109 mV, but when the value changes from −2 dB to −1 dB by 1 dB, the potential fluctuation amount ΔVout = 97 mV. ... -21 dB → −20 dB, and when it changes by 1 dB, ΔVout = 11 mV.

  Accordingly, the potential fluctuation amount ΔVout when the “amplification” command is issued from the analysis circuit 23 as described above, the value of the gain Gv22 increases every time the pulse of the clock signal Vclk is input. It becomes an increasing change. That is, as shown in FIG. 2 (c), ΔVout (n−1) <ΔVout (n) <ΔVout (n + 1).

  Since the data indicated by the characteristic curve A (example 1) in FIG. 3 is stored in the table 32, the higher frequency data is read and the higher frequency is set in the clock generator 31 as the potential fluctuation amount ΔVout is smaller. As the potential fluctuation amount ΔVout is larger, lower frequency data is read and a lower frequency is set in the clock generator 31. FIG. 2D shows the potential fluctuation amount ΔVout, and FIG. 2E shows the frequency change of the clock signal Vclk.

  In this way, when the potential fluctuation amount ΔVout is small, zipper noise caused by the volume gain switching is not a problem. Therefore, by increasing the frequency of the clock signal Vclk to shorten the switching time per step. The gain change of the electronic volume 10 is completed in a short time. On the contrary, when the potential fluctuation amount ΔVout is large, the problem of zipper noise caused by the volume gain switching becomes large. Therefore, by reducing the frequency of the clock signal Vclk and increasing the switching time per step, The zipper noise generated when the gain of the volume 10 is changed is moved outside the audible frequency range (low frequency) to suppress the zipper noise. As a result, zipper noise can be suppressed without causing a delay in which the volume gain switching time is uncomfortable in terms of hearing.

  In the above operation example, since the value of the current gain Gv22 of the second register 22 is changed from the small gain Gv (1) to the large gain Gv (2), the frequency of the clock signal Vclk sequentially decreases for each step. However, when changing from the large gain Gv (2) to the small gain Gv (1), the frequency of the clock signal Vclk is sequentially increased for each step. In either case, when the value of the current gain Gv22 in the second register 22 reaches the value of the target gain Gv21 in the first register 21, a command “match” is output from the control circuit 24 to the clock generator 31. The generation of the clock signal Vclk is stopped.

  In the above embodiment, the example in which the frequency of the clock signal Vclk is switched to five stages of f1, f2, f3, f4, and f5 has been described. However, as shown in the characteristic curve B (example 2) in FIG. The frequency of the signal Vclk may be continuously switched according to the change in the potential fluctuation amount ΔVout.

  FIG. 4 shows another example of the table (Example 3). As shown in Expression (2), the above-described potential fluctuation amount ΔVout increases as the output voltage Vout increases and decreases as the output voltage Vout decreases. The potential fluctuation amount ΔVout is larger as the value of the current gain Gv22 (equivalent to Gv22 (n) in the expression (2)) of the second register 22 is larger and smaller as it is smaller. Therefore, in the table of FIG. 4, as the level of the output voltage Vout decreases, the frequency of the clock signal Vclk increases in the order of f1 → f2 → f3, f2 → f3 → f4, or f3 → f4 → f5. Further, as the current gain Gv22 of the second register 22 decreases, the frequency of the clock signal Vclk increases in the order of f1 → f2 → f3, f2 → f3 → f4, or f3 → f4 → f5.

  As described above, the same result can be obtained even if the frequency of the clock signal Vclk is switched according to the magnitude of the value of the output voltage Vout and the current gain Gv22 of the second register 22 in addition to the magnitude of the potential fluctuation amount ΔVout. .

<Second embodiment>
FIG. 5 shows a circuit of a volume control apparatus according to the second embodiment of the present invention. The same components as those described with reference to FIG. In this embodiment, the value of the target gain Gv21 of the first register 21 is taken into the clock generator 31, and the potential fluctuation amount ΔVout is calculated based on the value of the target gain Gv21 and the output signal Vout detected by the level detection circuit 33. By estimation, the frequency of the clock signal Vclk generated by the clock generator 31 is determined by the table 32.

  In this embodiment, when the value of the target gain Gv21 of the first register 21 is changed from Gv (1) to Gv (2), as in the case of the first embodiment, the current gain Gv22 of the second register 22 is changed. The value is sequentially updated from Gv (1) to Gv (2), and the output voltage Vout is also sequentially updated. Since the output voltage Vout is initially small, the difference between the value corresponding to the output voltage obtained from the value of the target gain Gv21 of the first register 21 and the output voltage Vout detected by the level detection circuit 33 becomes large, and the output Since the voltage Vout is small, it is estimated that the potential fluctuation amount ΔVout per step is small, and the frequency of the clock signal Vclk generated by the clock generator 31 is high. However, when the output voltage Vout increases, the difference between the value corresponding to the output voltage obtained from the value of the target gain Gv21 of the first register 21 and the output voltage Vout detected by the level detection circuit 33 decreases, and the output voltage Vout Is large, the potential fluctuation amount ΔVout per step is estimated to be large, and the frequency of the clock signal Vclk is sequentially lowered. When the value of the current gain Gv22 reaches Gv (2), a “match” command is output from the control circuit 24 to the clock generator 31, and the clock signal Vclk is stopped.

  In the above operation example, since the value of the current gain Gv22 of the second register 22 is changed from the small gain Gv (1) to the large gain Gv (2), the frequency of the clock signal Vclk sequentially decreases for each step. When changing from a large gain Gv (2) to a small gain Gv (1), the frequency of the clock signal Vclk is sequentially increased for each step. In either case, when the value of the current gain Gv22 in the second register 22 reaches the value of the target gain Gv21 in the first register 21, a command “match” is output from the control circuit 24 to the clock generator 31. The generation of the clock signal Vclk is stopped.

  In this way, in the volume control device of the second embodiment, as in the volume control device of the first embodiment, when the output voltage Vout is small, the frequency of the clock signal Vclk is increased and the switching per step is performed. By shortening the time, the volume setting value is changed in a short time. Further, when the output voltage Vout is large, the frequency of the clock signal Vclk is lowered and the switching time per step is lengthened to move the zipper noise generated by the volume setting switching out of the audible range (low frequency). , Suppress zipper noise.

<Third embodiment>
FIG. 6 shows a circuit of a volume control apparatus according to the third embodiment of the present invention. The same components as those described with reference to FIG. In this embodiment, the value of the target gain Gv21 of the first register 21 and the value of the current gain Gv22 of the second register 22 are taken into the clock generator 31. Based on the value of the target gain Gv21 and the value of the current gain Gv22 of the second register 22, the frequency of the clock signal Vclk generated by the clock generator 31 is determined by the table 32.

  In the present embodiment, since the output voltage Vout is not detected, the value of the current gain Gv22 of the second register 22 is used as the equivalent. When the value of the current gain Gv22 is small, the output voltage Vout is also small. Therefore, the frequency of the clock signal Vclk is increased. Conversely, when the value of the current gain Gv22 is large, the output voltage Vout is also large. Data that lowers the frequency of the frequency is stored in the table 32.

Further, the difference between the value of the target gain Gv21 of the first register 21 and the value of the current gain Gv22 of the second register 22 is expressed as ΔGv1 = | Gv21−Gv22 | (3)
As the difference ΔGv1 is larger, the frequency of the clock signal Vclk may be increased, and the smaller the data, the lower the data may be stored in the table 32.

  The contents of the table 32 in this case are as shown in FIG. In this case, the frequency of the clock signal Vclk increases as the value of the current gain Gv22 of the second register 22 decreases, and the frequency of the clock signal Vclk increases as the value of the difference ΔGv1 increases.

  In this manner, in the volume control device of the third embodiment, the smaller the current gain Gv22 value of the second register 22 (estimated that the output voltage Vout is smaller) and the larger the difference ΔGv1, the more the clock signal Vclk becomes. By increasing the frequency and shortening the switching time per step, the volume setting value is changed in a short time. Further, as the value of the current gain Gv22 of the second register 22 is larger (estimated that the output voltage Vout is larger) and the difference ΔGv1 is smaller, the frequency of the clock signal Vclk is lowered and the switching time per step is lengthened. By doing so, zipper noise caused by switching the volume setting is moved outside the audible range (low frequency), and zipper noise is suppressed.

10: Electronic volume 20: Volume setting circuit, 21: First register, 22: Second register, 23: Analysis circuit, 24: Control circuit, 30: Clock generation circuit, 31: Clock generator, 32: Table, 33: Level Detection circuit

Claims (6)

In a volume control apparatus that controls the gain of an input audio signal by means of an electronic volume, a volume setting circuit that sets the gain of the electronic volume, and a clock generation circuit that generates a clock signal that performs stepwise switching of the gain of the electronic volume, With
The volume setting circuit includes a first register in which a target value of the gain of the electronic volume is set, a second register in which a current value of the gain of the electronic volume is set, the target value of the first register, and the An analysis circuit for comparing the current value of the second register, and the current value of the second register for each pulse of the clock signal toward the target value of the first register according to the comparison result of the analysis circuit A control circuit for updating in stages,
The volume control device, wherein the clock generation circuit switches the frequency of the clock signal based on the magnitude of the output signal of the electronic volume. The volume control device according to claim 1,
The clock generation circuit sets the frequency of the clock signal to be high when the output signal of the electronic volume is small, and sets the frequency of the clock signal to be low when the output signal of the electronic volume is large. apparatus. In a volume control apparatus that controls the gain of an input audio signal by means of an electronic volume, a volume setting circuit that sets the gain of the electronic volume, and a clock generation circuit that generates a clock signal that performs stepwise switching of the gain of the electronic volume, With
The volume setting circuit includes a first register in which a target value of the gain of the electronic volume is set, a second register in which a current value of the gain of the electronic volume is set, the target value of the first register, and the An analysis circuit for comparing the current value of the second register, and the current value of the second register for each pulse of the clock signal toward the target value of the first register according to the comparison result of the analysis circuit A control circuit for updating in stages,
The volume control device, wherein the clock generation circuit switches the frequency of the clock signal based on the magnitude of the output signal of the electronic volume and the current value of the second register. The volume control device according to claim 3,
The clock generation circuit sets the frequency of the clock signal high when the output signal of the electronic volume is small and the current value of the second register is small, and the output signal of the electronic volume is large and the output of the second register The volume control device, wherein the frequency of the clock signal is set low when the current value is large. In a volume control device that controls the gain of an input audio signal by means of an electronic volume, a volume setting circuit that sets the gain of the electronic volume, and a clock generation circuit that generates a clock signal that performs stepwise switching of the gain of the electronic volume, With
The volume setting circuit includes a first register in which a target value of the gain of the electronic volume is set, a second register in which a current value of the gain of the electronic volume is set, the target value of the first register, and the An analysis circuit for comparing the current value of the second register, and the current value of the second register for each pulse of the clock signal toward the target value of the first register according to the comparison result of the analysis circuit A control circuit for updating in stages,
The volume control device, wherein the clock generation circuit switches the frequency of the clock signal based on the magnitude of the output signal of the electronic volume and the target value of the first register. The volume control device according to claim 5,
The clock generation circuit sets the frequency of the clock signal high when the output signal of the electronic volume is small and the difference between the target value of the first register and the output signal is small, and the output signal of the electronic volume is large. The volume control device is characterized in that the frequency of the clock signal is set low when the difference between the target value of the first register and the output signal is large.

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