JP6587891B2 - Printed wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a printed wiring board including a covering insulating layer having an opening for exposing a conductor pad, and a bump formed on the exposed conductor pad, and a method for manufacturing the same.

  Patent Document 1 discloses a build-up multilayer printed wiring board having a multilayer structure in which resin insulating layers 34, 36, and 38 and wiring patterns 33, 35, and 37 are alternately laminated as shown in FIG. Yes. A via hole 44 that exposes the wiring pattern 37 is formed in the resin insulating layer 38 that is located closest to the surface layer among the plurality of resin insulating layers 34, 36, and 38, and the via hole 44 is filled with copper plating and externally filled. A post-like conductive pad 40 as a connection terminal is formed. Solder bumps 41 are formed on the upper surface of each conductive pad 40. The upper end portion of the conductive pad 40 has a diameter larger than that of the via hole 44 and projects outwardly in the radial direction on the upper surface of the resin insulating layer 38.

JP 2004-63907 A

  However, in the build-up multilayer printed wiring board disclosed in Patent Document 1, copper diffuses into the solder bump 41 at the boundary between the copper conductive pad 40 and the solder bump 41 to generate a Cu—Sn alloy layer. Since the conductive pads 40 and the solder bumps 41 are formed on the surface of the resin insulating layer 38 so as to protrude in a flange shape, Cu—Sn alloy is generated as a residue around the protruding portion of the bump 41, There is a problem that causes migration.

  Further, in the build-up multilayer printed wiring board disclosed in Patent Document 1, since the conductive pad 40 is formed in a post shape to serve as a support layer for the solder bump 41, there is a problem that the amount of copper used is large and the cost is high. .

  The present invention has been made to solve the above problems, and a printed wiring board according to the present invention includes a base insulating layer made of an insulating material, and a conductor layer including conductor pads formed on the base insulating layer. A printed wiring board comprising: a covering insulating layer formed on the base insulating layer and the conductor layer and having an opening exposing the conductor pad; and a bump formed on the exposed conductor pad. The bump includes an electroless plating metal layer formed on the exposed conductor pad, a barrier metal layer formed on the electroless plating metal layer and covering the electroless plating metal layer, and the barrier metal layer And the electroless plating metal layer and the barrier metal layer are formed along the periphery of the opening on the upper surface of the insulating coating layer.

  The printed wiring board of the present invention is formed on a base insulating layer made of an insulating material, a conductor layer including a conductor pad formed on the base insulating layer, the base insulating layer, and the conductor layer. A printed wiring board comprising: a covering insulating layer having an opening exposing the conductor pad; and a bump precursor formed on the exposed conductor pad, wherein the bump precursor is the exposed conductor pad. An electroless plating metal layer formed thereon, a barrier metal layer formed on the electroless plating metal layer and covering the electroless plating metal layer, and a solder layer formed on the barrier metal layer. The electroless plating metal layer and the barrier metal layer are formed along the periphery of the opening on the upper surface of the covering insulating layer.

  The printed wiring board manufacturing method of the present invention includes a base insulating layer made of an insulating material, a conductor layer including conductor pads formed on the base insulating layer, the base insulating layer, and the conductor layer. In a method of manufacturing a printed wiring board, comprising: a covering insulating layer having an opening exposing the conductive pad formed on the exposed conductive pad; and a bump formed on the exposed conductive pad. Preparing a printed wiring board in which a conductor layer is formed and having a base insulating layer and a covering insulating layer formed on the conductor layer, and forming an opening extending through the covering insulating layer to the conductor pad; Forming an electroless plating metal layer electrically connected to the conductor pad along the upper surface of the exposed conductor pad, the upper surface of the covering insulating layer, and the inner wall surface of the opening; Forming a plating resist on the electroless plating metal layer so that the opening position of the layer has an opening larger than the opening of the covering insulating layer; and exposing the electroless plating metal layer from the opening of the plating resist. Forming a barrier metal layer on the portion to be plated by plating and forming a solder layer in the opening of the coating insulating layer and in the opening of the plating resist by electrolytic plating using the electroless plating metal layer as a power feeding layer Removing the plating resist; removing the electroless plating layer on the upper surface of the covering insulating layer exposed by the removal of the plating resist; and reflowing the solder layer by heating to form bumps. Forming.

  According to the embodiment of the present invention, the bump is formed so that the upper surface of the conductor pad and the inner wall surface of the opening are covered, and the opening of the coating insulating layer is filled on the electroless plating metal layer. Therefore, the amount of copper used can be reduced and the cost can be reduced as compared with the case where bumps are formed on a copper post as disclosed in Patent Document 1. Can do. Also, the barrier metal layer formed between the electroless plating metal layer and the solder layer bumps the metal of the electroless plating metal layer (for example, copper when the electroless plating metal layer is an electroless copper plating layer). Diffusion between the solder layer and the electroless plating metal layer and the solder layer between the metal of the electroless plating metal layer (for example, copper) and the metal constituting the solder layer (for example, tin). An alloy is not formed. Therefore, it is possible to prevent the alloy residue from being generated around the opening on the covering insulating layer and causing migration.

It is a fragmentary sectional view which expands and partially shows one Embodiment of the printed wiring board with a bump of this invention. (A)-(H) are partial sectional drawings which show an example of the manufacturing method of the printed wiring board with a bump shown by FIG. It is sectional drawing which shows one application example of the printed wiring board with a bump of embodiment of this invention. It is sectional drawing which shows the other application example of the printed wiring board with a bump of embodiment of this invention. It is sectional drawing of the conventional printed wiring board.

  FIG. 1 is a partial cross-sectional view showing a partially enlarged printed wiring board with bumps according to an embodiment of the present invention. The printed wiring board with bumps of this embodiment is formed on the base insulating layer 1 made of an insulating material, the conductor layer 2 including the conductor pads 2a formed on the base insulating layer 1, and the base insulating layer 1. A covering insulating layer 3 having an opening 3a exposing the conductor pad 2a and a bump 4 formed on the conductor pad 2a exposed from the opening 3a are provided. The base insulating layer 1 may be a single layer as shown in the figure, but may have a laminated structure of a plurality of layers, and a conductor layer 2 may be formed between these insulating layers. In this description, “upper” means the side where the conductor layer 2 is present in the relationship between the base insulating layer 1 and the conductor layer 2 or the side where the covering insulating layer 3 is present in the relationship between the conductor layer 2 and the covering insulating layer 3. Point to. Further, “below” refers to the side where the base insulating layer 1 is present in the relationship between the base insulating layer 1 and the conductor layer 2 or the side where the conductive layer 2 is present in the relationship between the conductor layer 2 and the covering insulating layer 3. Thus, for example, the upper surface of the covering insulating layer 3 refers to the surface of the both sides of the covering insulating layer 3 opposite to the side facing the conductor layer 2 or the base insulating layer 1. Similarly, the upper surface of the conductor pad 2a refers to the surface of the both sides of the conductor pad 2a opposite to the side facing the base insulating layer 1. Although one conductor pad 2a, one opening 3a, and one bump 4 are shown in FIG. 1, a plurality of each may be provided.

  The insulating material forming the base insulating layer 1 may be an organic resin material such as epoxy or polyimide, but may be an inorganic material such as ceramic or glass. The conductor layer 2 may be a conductive metal, but is preferably copper. The material for forming the covering insulating layer 3 may be a commercially available build-up film as an insulating resin film, but may also be a normal solder resist. The upper end diameter of the openings 3a is preferably 20% or more and 70% or less of the pitch (center distance) between the openings 3a. The minimum pitch between the openings 3a is preferably 30 μm or more and 90 μm or less. As a result, for example, a package substrate can be formed in which mounted semiconductor elements are connected by ultra-high density wiring.

  The bump 4 has a thin electroless plated metal layer 5 and a solder layer 6 that fills the opening 3 a of the covering insulating layer 3 and has an upper portion protruding from the upper surface of the covering insulating layer 3. The electroless plating metal layer 5 covers the upper surface of the conductor pad 2a exposed from the opening 3a of the covering insulating layer 3, the inner wall surface of the opening 3a of the covering insulating layer 3, and the upper surface surrounding the opening 3a of the covering insulating layer 3. Formed as follows.

  Further, a barrier metal layer 7 is formed between the electroless plating metal layer 5 and the solder layer 6. The barrier metal layer 7 is formed along the upper surface of the conductor pad 2a exposed from the opening 3a of the covering insulating layer 3, the inner wall surface of the opening 3a of the covering insulating layer 3, and the peripheral upper surface of the covering insulating layer 3 around the opening 3a. It is formed so as to cover the electroplated metal layer 5. Therefore, the electroless plating metal layer 5 and the barrier metal layer 7 have overhanging portions 5a and 7a projecting radially outward from the opening 3a along the upper surface of the covering insulating layer 3 at the upper ends thereof. By providing such overhang portions 5a and 7a, it is possible to improve the adhesion between the bump 4 and the coating insulating layer 3 and increase the strength of the bump 4. The overhang length of the overhang portions 5a and 7a (the length along the radial direction from the upper edge of the opening 3a to the outer peripheral edge of the overhang portions 5a and 7a) is 10% or more with respect to the inner diameter of the opening 3a of the covering insulating layer 3 And preferably 30% or less. If the length of the overhang portions 5a and 7a is less than 10% with respect to the inner diameter of the opening 3a, the effect of improving the adhesion between the bump 4 and the coating insulating layer 3 and increasing the strength of the bump 4 may not be obtained. Because there is sex. In addition, if the length of the overhang portions 5a and 7a exceeds 30% with respect to the inner diameter of the opening 3a, the distance to the adjacent bump 4 becomes too small, and it may be difficult to ensure insulation. is there.

  The solder layer 6 is preferably an electrolytic plating layer. In this case, the solder layer 6 is formed on the electroless plating metal layer 5 by an electrolytic plating method using the electroless plating metal layer 5 as a power feeding layer. The solder layer 6 is made of, for example, Sn / Pb. However, the present invention is not limited to this, and the solder layer 6 may be formed of Sn / Sb, Sn / Ag, Sn / Ag / Cu, Sn / Cu, Sn / Zn, or the like. The solder layer 6 is also formed on the overhang portions 5 a and 7 a of the electroless plating metal layer 5 and the barrier metal layer 7, and the outer diameter of the solder layer 6 is the edge of the opening 3 a on the upper surface of the insulating coating layer 3. It is larger than the inner diameter of (upper edge).

  The electroless plating metal layer 5 is preferably an electroless copper plating layer. The thickness of the electroless plating metal layer 5 is preferably 0.1 μm or more and 3 μm or less. When the thickness of the electroless plating metal layer 5 is less than 0.1 μm, there is a possibility that the formation of the solder layer 6 may be uneven when the solder layer 6 is formed using the electroless plating metal layer 5 as a power feeding layer. If it exceeds 3 μm, it takes time to form the electroless plating metal layer 5 by the electroless plating method, and the amount of metal (for example, copper) constituting the electroless plating metal layer 5 increases, resulting in an increase in cost.

  The barrier metal layer 7 is preferably a nickel plating layer, and more preferably an electrolytic nickel plating layer formed by an electrolytic plating method using the electroless plating metal layer 5 as a power feeding layer. When the barrier metal layer 7 is a nickel plating layer, the thickness is preferably 1 μm or more and 3 μm or less. If nickel has a thickness of 1 μm or more, it is possible to effectively prevent the metal (for example, copper) of the electroless plating metal layer 5 from diffusing into the solder layer 6. Moreover, even if the thickness is made larger than 3 μm, the effect of preventing diffusion of the metal (for example, copper) of the electroless plating metal layer 5 into the solder layer 6 is saturated.

  According to the printed wiring board with bumps of the present embodiment, the bumps 4 are formed by covering the upper surface of the conductor pad 2a and the inner wall surface of the opening 3a with the electroless plated metal layer 5 and covering the electroless plated metal layer 5 Since it is formed from the solder layer 6 formed so as to fill the opening 3a of the layer 3, as disclosed in Patent Document 1, the amount of copper used is reduced compared to the case where the bump is formed on the copper post. This can be reduced and the cost can be reduced. Further, the barrier metal layer 7 formed between the electroless plating metal layer 5 and the solder layer 6 allows the metal of the electroless plating metal layer 5 (for example, when the electroless plating metal layer 5 is an electroless copper plating layer). Is prevented from diffusing into the solder layer 6 of the bump 4, so that the metal (for example, copper) and the solder layer of the electroless plating metal layer 5 are interposed between the electroless plating metal layer 5 and the solder layer 6. An alloy with the metal constituting the metal 6 (for example, tin) is not formed. Therefore, it is possible to prevent the alloy residue from being generated around the opening 3a on the covering insulating layer 3.

  The printed wiring with bumps having the above-described configuration can be manufactured by the method for manufacturing a printed wiring board with bumps according to an embodiment of the present invention shown in FIGS.

  In the manufacturing method of this embodiment, as shown in FIG. 2A, a base insulating layer 1 made of an insulating material, a conductor layer 2 formed on the base insulating layer 1, the base insulating layer 1 and a conductor An intermediate substrate having a coating insulating layer 3 formed on the layer 2 is prepared. The base insulating layer 1 is made of, for example, an organic resin material such as epoxy or polyimide, or an inorganic material such as ceramic or glass. The conductor layer 2 is formed by, for example, an additive method, a semi-additive method, a subtractive method, or the like. The conductor layer 2 is made of, for example, copper. The conductor layer 2 includes a conductor pad 2a for mounting an electronic component such as a semiconductor element, and wiring (not shown) such as a signal line and a power source. The covering insulating layer 3 is formed of a commercially available build-up film as an insulating resin film or a solder resist made of an insulating resin such as epoxy.

  First, as shown in FIG. 2A, an opening 3a is formed in the covering insulating layer 3 so as to penetrate the covering insulating layer 3 and reach the conductor pad 2a. When the plurality of openings 3a are formed, the minimum opening pitch (center-to-center distance) is preferably 30 μm or more and 90 μm or less. The opening diameter is preferably 20% or more and 70% or less of the opening pitch. For example, the opening diameter is 25 μm with respect to the opening pitch of 55 μm. The upper surface of the covering insulating layer 3 and the inner wall surface of the opening 3a are preferably subjected to a rough surface treatment.

  The opening 3a of the covering insulating layer 3 is formed by, for example, a laser, preferably a UV laser suitable for forming a small diameter hole. By increasing the output of the laser, the coating insulating layer 3 is sufficiently melted, and the inner wall surface of the opening 3a has an inverted truncated conical shape that linearly intersects the surface of the conductor pad 2a. By narrowing the laser beam, the crossing angle of the inner wall surface of the opening 3a with respect to the surface of the conductor pad 2a covered with the covering insulating layer 3 is 45 ° or more and less than 90 °.

  The inner wall surface of the opening 3a may have a cylindrical shape with a constant inner diameter that intersects the surface of the conductor pad 2a at a right angle. In that case, the opening 3a is formed by performing etching such as dry etching, plasma etching, light etching, or the like instead of the laser, and then performing alkali degreasing.

  Alternatively, the opening 3 a of the covering insulating layer 3 may be formed by exposure and development processing when a photosensitive solder resist is used as the covering insulating layer 3.

  Next, as shown in FIG. 2B, the electroless plating metal layer 5 is formed on the upper surface of the covering insulating layer 3 and the inner wall surface of the opening 3a. The electroless plating metal layer 5 is preferably formed by copper plating. The electroless plating metal layer 5 adheres firmly to the covering insulating layer 3 when the upper surface of the covering insulating layer 3 and the inner wall surface of the opening 3a are roughened. The thickness of the electroless plating metal layer 5 is preferably 0.1 μm or more and 3 μm or less.

  Next, as shown in FIG. 2C, for example, an ultraviolet curable thick plating resist (dry film resist) 9 is laminated on the electroless plating metal layer 5 on the upper surface of the covering insulating layer 3. An opening 9 a is formed in the plating resist 9 by arranging a mask on the plating resist 9 and exposing the mask so as to cover a position corresponding to the opening 3 a of the covering insulating layer 3 and developing the mask. The lower end diameter of the opening 9 a of the plating resist 9 is larger than the upper end diameter of the opening 3 a of the coating insulating layer 3. The lower end diameter of the opening 9 a of the plating resist 9 is preferably 110% or more and 130% or less of the upper end diameter of the opening 3 a of the coating insulating layer 3.

  Next, as shown in FIG. 2D, the barrier metal layer 7 is formed in the opening 3a of the coating insulating layer 3 and the opening 9a of the plating resist 9 by an electrolytic plating method using the electroless plating metal 5 as a power feeding layer. It is formed. The barrier metal layer 7 may be formed not only by the electrolytic plating method but also by the electroless plating method. The barrier metal layer 7 is preferably formed with a thickness of 1 μm or more and 3 μm or less.

  Next, as shown in FIG. 2 (E), the solder layer 6 is formed in the opening 3a of the coating insulating layer 3 and in the opening 9a of the plating resist 9 by an electrolytic plating method using the electroless plating metal layer 5 as a power feeding layer. Is formed. In addition, since the film thickness varies when the solder layer 6 is formed by filling plating, the solder layer 6 is preferably formed by conformal plating having a concave shape at the center of the surface as illustrated.

  Next, as shown in FIG. 2F, the plating resist 9 is peeled off, for example, manually by an operator, and the outer peripheral surface (side surface) of the solder layer 6 is exposed and covers the upper surface of the coating insulating layer 3. The electroless plating metal layer 5 is exposed.

  Next, as shown in FIG. 2G, a portion of the electroless plated metal layer 5 that is exposed without being covered with the solder layer is removed by etching, and the printed wiring including the bump precursor 4 ′ A board is obtained. In the present specification, the “bump precursor” refers to a material before a bump 4 described later is subjected to a reflow process. The bump precursor 4 ′ includes an electroless plating metal layer 5 formed on the conductor pad 2 a, a barrier metal layer 7 covering the electroless plating metal layer 5, and a solder layer formed on the barrier metal layer 7. 6. The barrier metal layer 7 in the bump precursor 4 ′ is formed along the periphery of the opening 3 a on the upper surface of the covering insulating layer 3. Further, in the bump precursor 4 ′, the solder layer 6 has a concave portion whose depth increases toward the center on the upper surface.

  Then, as shown in FIG. 2H, the solder layer 6 in the bump precursor 4 ′ is reflowed to form a bump 4 having a substantially hemispherical portion protruding from the upper surface of the covering insulating layer 3. .

  FIG. 3 is a cross-sectional view showing an application example of the printed wiring board with bumps according to the embodiment of the present invention. In this application example, a package-on-package (POP) type in which an upper package substrate P2 on which a semiconductor element E3 is mounted is stacked and electrically connected on a lower package substrate P1 on which semiconductor elements E1 and E2 are mounted. The printed wiring board with bumps of the embodiment manufactured in the same manner as the previous embodiment is applied to the lower package substrate P1 of the printed wiring board. The lower package substrate P1 is a semiconductor through the solder layer 6 of the bump 4 formed according to the present invention on the conductor pad 2a in the central region of the pitch corresponding to the refined terminal pitch of the semiconductor elements E1 and E2. The upper package substrate is connected to the terminals of the elements E1 and E2 through the solder layer 6 of the bump 4 formed according to the present invention on the conductor pad 2a in the peripheral region corresponding to the large terminal pitch of the upper package substrate P2. It is connected to the terminal on the lower surface of P2.

  FIG. 4 is a sectional view showing another application example of the printed wiring board with bumps according to the embodiment of the present invention. In this application example, the printed wiring board P4 with bumps of the embodiment manufactured in the same manner as the previous embodiment is embedded in the recess formed in the two outer layers of the multilayer printed wiring board P3. The wiring board P4 is based on the present invention on the conductor pads 2a having pitches corresponding to the respective finer terminal pitches of, for example, the memory chip C1 and the CPU chip C2 as semiconductor elements mounted on the multilayer printed wiring board P3. The terminals of the memory chip C1 and the CPU chip C2 are connected to each other through the solder layer 6 of the bump 4 formed in this manner, thereby constituting a (internal) broadband signal transmission path on the substrate. Note that the printed wiring board P4 with bumps of the embodiment may be mounted on two outer layers of the multilayer printed wiring board P3, and for example, connect the memory chip C1 and the CPU chip C2.

  Thus, according to the present invention, it is possible to reduce the cost of the printed wiring board and to prevent the generation of alloy residues around the bumps.

DESCRIPTION OF SYMBOLS 1 Base insulation layer 2 Conductor layer 2a Conductive pad 3 Cover insulation layer 3a Opening 4 Bump 4 'Bump precursor 5 Electroless plating metal layer 5a Overhang part 6 Solder layer 7 Barrier metal layer 7a Overhang part 9 Plating resist (dry film resist)
9a Opening C1 Memory chip C2 CPU chip E1, E2, E3 Semiconductor element P1 Lower package substrate P2 Upper package substrate P3 Multilayer printed wiring board P4 Bumped printed wiring board

Claims (11)

A base insulating layer made of an insulating material;
A conductor layer including a conductor pad formed on the base insulating layer;
A covering insulating layer formed on the base insulating layer and the conductor layer and having an opening exposing the conductor pad;
Bumps formed on the exposed conductor pads;
In a printed wiring board comprising
The bump includes an electroless plating metal layer formed on the exposed conductor pad, a barrier metal layer formed on the electroless plating metal layer and covering the electroless plating metal layer, and the barrier metal layer. A solder layer formed, and
The electroless plating metal layer and the barrier metal layer are projected along the periphery of the opening on the upper surface of the covering insulating layer to form a protruding portion, and the protruding length of the protruding portion is determined by the covering insulation. It is 10% or more and 30% or less with respect to the inner diameter of the opening of the layer .   The printed wiring board according to claim 1, wherein the solder layer is an electrolytic plating layer.   3. The printed wiring board according to claim 1, wherein the electroless plating metal layer is an electroless copper plating layer.   4. The printed wiring board according to claim 1, wherein the barrier metal layer is a nickel plating layer. 5.   It is a printed wiring board as described in any one of Claim 1 to 4, Comprising: The thickness of the said electroless-plating layer is 0.1 micrometer or more and 3 micrometers or less. 6. The printed wiring board according to claim 1, wherein the solder layer has an outer diameter larger than an inner diameter of an edge of an opening on an upper surface of the covering insulating layer . 7. The printed wiring board according to claim 1, wherein the insulating coating layer has a plurality of openings, and an inner diameter at an edge of each opening is 20 of a pitch between adjacent openings. % To 70%. 8. The printed wiring board according to claim 1, wherein the covering insulating layer has a plurality of the openings, and a minimum pitch between adjacent openings is not less than 30 μm and not more than 90 μm. A base insulating layer made of an insulating material;
A conductor layer including a conductor pad formed on the base insulating layer;
A covering insulating layer formed on the base insulating layer and the conductor layer and having an opening exposing the conductor pad;
A bump precursor formed on the exposed conductor pad;
In a printed wiring board comprising
The bump precursor includes an electroless plating metal layer formed on the exposed conductor pad, a barrier metal layer formed on the electroless plating metal layer and covering the electroless plating metal layer, and the barrier metal layer A solder layer formed thereon,
The electroless plating metal layer and the barrier metal layer are projected along the periphery of the opening on the upper surface of the covering insulating layer to form a protruding portion, and the protruding length of the protruding portion is determined by the covering insulation. It is 10% or more and 30% or less with respect to the inner diameter of the opening of the layer .   10. The printed wiring board according to claim 9, wherein the solder layer has a concave portion whose depth increases toward the center on the upper surface. A base insulating layer made of an insulating material; a conductor layer including a conductor pad formed on the base insulating layer; and an opening formed on the base insulating layer and on the conductor layer to expose the conductor pad. In a manufacturing method of a printed wiring board comprising a covering insulating layer having, and a bump formed on the exposed conductor pad,
Preparing a printed wiring board in which the conductor layer is formed on the base insulating layer and a covering insulating layer is formed on the base insulating layer and the conductor layer;
Forming an opening extending through the covering insulating layer to the conductor pad;
Forming an electroless plating metal layer electrically connected to the conductor pad along the upper surface of the exposed conductor pad, the upper surface of the covering insulating layer, and the inner wall surface of the opening;
Forming a plating resist on the electroless plating metal layer so that the opening position of the covering insulating layer has an opening larger by 10% or more and 30% or less than the opening of the covering insulating layer;
Forming a barrier metal layer by plating on a portion of the electroless plating metal layer exposed from the opening of the plating resist;
Forming a solder layer in the opening of the coating insulating layer and in the opening of the plating resist by electrolytic plating using the electroless plating metal layer as a power supply layer;
Removing the plating resist;
Removing the electroless plating layer on the upper surface of the covering insulating layer exposed by removing the plating resist;
Reflowing the solder layer by heating to form bumps.

Images